一种任意波形发生器高速标记信号生成系统及方法

By combining modules such as FPGA, parallel-to-serial conversion, digital delay, analog phase shifting, and temperature compensation, a high-speed marker signal generation system was achieved with high data rate, accurate delay, and large offset range. This solves the problems of limited signal rate and range in existing technologies and improves the system's delay and offset accuracy and stability.

CN116069121BActive Publication Date: 2026-07-17CHINA ELECTRONIS TECH INSTR CO LTD

Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
CHINA ELECTRONIS TECH INSTR CO LTD
Filing Date
2023-01-30
Publication Date
2026-07-17

AI Technical Summary

Technical Problem

In the prior art, the signal rate of the marker signal generation device is limited, the delay resolution is low, the output marker signal range is limited, and there is a lack of effective temperature compensation and analog phase shifting circuit.

Method used

A combination of FPGA module, parallel-to-serial conversion module, digital delay module, analog phase shifting module, digitally controlled gain amplifier module, bias module, memory module, synchronous clock module, temperature compensation module and analog control module is used to achieve high-speed marking signal generation through buffering, parallel-to-serial conversion, digital delay, analog phase shifting, temperature compensation and analog control.

Benefits of technology

It achieves high data rate, accurate delay, and large offset range for high-speed marker signals, improves the accuracy and stability of delay and offset, and solves the problems of limited signal rate and range.

✦ Generated by Eureka AI based on patent content.

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Abstract

本发明提供了一种任意波形发生器高速标记信号生成系统及方法,系统包括:依次连接的FPGA模块、并串转换模块、数字延时模块、模拟移相模块、数控增益放大器模块以及偏置器模块,FPGA模块还分别与数字延时模块和数控增益放大器模块相连,还包括:与FPGA模块互相连接的存储器模块,与FPGA模块连接、并串转换模块连接的同步时钟模块,分别与数字延时模块、模拟移相模块和模拟控制模块相连接的温度补偿模块,以及与模拟移相模块和偏置器模块相连接的模拟控制模块。本发明的技术方案克服现有技术中信号速率受限、延时分辨率低、输出标记信号范围受限的问题。
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