Power supply control circuit and solid state drive

Abstract

This invention discloses a power supply control circuit and a solid-state drive (SSD). The power supply control circuit includes a delay unit, a control unit, at least two voltage conversion units, and at least one resistance adjustment unit. The input terminal of the delay unit is electrically connected to a power supply, and its output terminal is electrically connected to the control unit. The delay unit is used to slow down the rate of voltage change at its output terminal. The control unit is electrically connected to the enable terminals of each voltage conversion unit, and is used to sequentially control the start (or stop) of each voltage conversion unit during the rise (or fall) of the output voltage of the delay unit. The input terminals of each voltage conversion unit are electrically connected to a power supply, and their output terminals are respectively electrically connected to different power supply output terminals. The sampling terminal of at least one voltage conversion unit is electrically connected to the resistance adjustment unit, which is used to adjust the voltage division ratio at the sampling terminal. This invention can achieve power-on / off timing control for multiple power supply output terminals and can realize bias voltage testing functions for each power supply circuit.

Description

Technical Field

[0001] This invention relates to the field of chip power supply technology, and in particular to a power supply control circuit and a solid-state drive. Background Technology

[0002] Existing processing chips have multiple operating voltages. To ensure reliable operation, the power-on and power-off of each operating voltage must follow a specific timing sequence. Otherwise, excessive current during power-on, abnormal device startup, and irreversible damage to the chip may occur during product use.

[0003] In the prior art, PMIC (Power Management IC) power chips are usually used to drive the power-on and power-off timing. However, these power chips usually only meet the power-on requirements of the chip and cannot perform pull-off tests on the chip when aging verification is required, so their functions are relatively simple. Summary of the Invention

[0004] This invention provides a power supply control circuit and a solid-state drive, aiming to solve the problem that the existing technology cannot simultaneously meet the requirements of voltage bias and power-on / off timing control.

[0005] To achieve the above objectives, the first aspect of the present invention provides a power supply control circuit, comprising a delay unit, a control unit, at least two voltage conversion units, and at least one resistance adjustment unit; wherein,

[0006] The input terminal of the delay unit is electrically connected to the power supply, and the output terminal is electrically connected to the control unit. The delay unit is used to slow down the rate of change of the voltage at its output terminal.

[0007] The control unit is electrically connected to the enable terminal of each voltage conversion unit, and is used to sequentially control each voltage conversion unit to start working during the rise of the output voltage of the delay unit, and sequentially control each voltage conversion unit to stop working during the fall of the output voltage of the delay unit.

[0008] The input terminal of each voltage conversion unit is electrically connected to a power supply, and the output terminal of each voltage conversion unit is electrically connected to a different power supply output terminal. The sampling terminal of at least one voltage conversion unit is electrically connected to the resistance adjustment unit, which is used to adjust the voltage division ratio of the sampling terminal.

[0009] In some embodiments, the control unit includes a plurality of sub-control units, each sub-control unit corresponding to each voltage conversion unit. The sub-control unit is electrically connected between the enable terminal of the corresponding voltage conversion unit and the output terminal of the delay unit. When the output voltage of the delay unit reaches its respective voltage threshold, each sub-control unit outputs a signal to control the corresponding voltage conversion unit to start working. The voltage threshold values ​​of each sub-control unit are different.

[0010] In some embodiments, each of the sub-control units includes a voltage comparator. The V+ pin of the voltage comparator is electrically connected to the output terminal of the delay unit, the V- pin receives a reference voltage provided by the power supply, and the output pin is electrically connected to the enable terminal of the corresponding voltage conversion unit. The reference voltage of the V- pin of each voltage comparator is different.

[0011] In some embodiments, the resistance adjustment unit includes a range switch and a pull-down unit. The pull-down unit has multiple ranges with different pull-down resistance values. The range switch is electrically connected between the sampling terminal and the pull-down unit and is used to switch between the ranges of the pull-down unit.

[0012] In some embodiments, the pull-down unit includes at least a standard range resistor, a pull-down resistor, and a pull-up resistor; the range switching switch is a jumper adjustment switch, including a first jumper pin, a second jumper pin, a third jumper pin, and a jumper cap electrically connected to the sampling terminal, wherein the first jumper pin is grounded through the standard range resistor, the second jumper pin is grounded through the pull-down resistor, and the third jumper pin is grounded through the pull-up resistor.

[0013] In some embodiments, the delay unit includes a first resistor and a first capacitor, one end of the first resistor is the input terminal of the delay unit, the other end of the first resistor is the output terminal of the delay unit, and the other end of the first resistor is grounded through the first capacitor.

[0014] In some embodiments, the at least two voltage conversion units include a first voltage conversion unit and a second voltage conversion unit, wherein the sampling terminal of the second voltage conversion unit is electrically connected to the resistance adjustment unit;

[0015] The first voltage conversion unit includes an LDO chip, a first pull-up resistor, a first voltage divider resistor, and a second voltage divider resistor. The enable pin of the LDO chip is the enable terminal of the first voltage conversion unit. The input pin of the LDO chip is electrically connected to the power supply via the first pull-up resistor. The output pin of the LDO chip is electrically connected to the output terminal of the first voltage conversion unit. The sampling pin of the LDO chip is the sampling terminal of the first voltage conversion unit. The output pin of the LDO chip is electrically connected to its sampling pin via the first voltage divider resistor. The sampling pin of the LDO chip is grounded via the second voltage divider resistor.

[0016] The second voltage conversion unit includes a DC-DC chip, a second pull-up resistor, and a third voltage divider resistor. The enable pin of the DC-DC chip is the enable terminal of the second voltage conversion unit. The input pin of the DC-DC chip is electrically connected to the power supply via the second pull-up resistor. The output pin of the DC-DC chip is electrically connected to the output terminal of the second voltage conversion unit. The sampling pin of the DC-DC chip is the sampling terminal of the second voltage conversion unit, and the output pin of the DC-DC chip is electrically connected to its sampling pin via the third voltage divider resistor.

[0017] In some embodiments, the second voltage conversion unit further includes a filter inductor and a filter capacitor. One end of the filter inductor is electrically connected to the output pin of the DC-DC chip, and the other end is electrically connected to the power supply output terminal. The filter capacitor is connected in parallel with the third voltage divider resistor.

[0018] In some embodiments, the output terminal of the voltage conversion unit is connected to a filter circuit for filtering out noise.

[0019] A second aspect of the present invention provides a solid-state drive, the solid-state drive including the power supply control circuit described above.

[0020] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0021] (1) The power supply control circuit provided by the present invention includes a delay unit, which is used to slow down the rate of voltage change at its output terminal. That is, the control unit electrically connected to the output terminal of the delay unit will receive different input voltages at different time points. Therefore, in the control unit, when the input voltage rises to a certain voltage threshold, the control unit can enable the corresponding voltage conversion unit to start working and output the power supply voltage; or when the input voltage drops below the voltage threshold, the enable is cut off and the corresponding voltage conversion unit stops working. In this way, the power-on and power-off timing control of different power supply circuits is achieved through a simple circuit design.

[0022] (2) The power supply control circuit provided by the present invention further includes at least one resistance adjustment unit, which is used to adjust the voltage division ratio at the sampling terminal of the voltage conversion unit. The voltage conversion unit can further adjust its output voltage based on different voltage division ratios. This forms a closed-loop adjustment of the output power supply voltage. In practical applications, the user can adjust the resistance value connected to the resistance adjustment unit and ultimately adjust the power supply voltage. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a power supply control circuit module in one embodiment of the present invention. Figure 1 ;

[0024] Figure 2 This is a schematic diagram of a power supply control circuit module in one embodiment of the present invention. Figure 2 ;

[0025] Figure 3 This is a schematic diagram of the power supply control circuit in one embodiment of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0027] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0028] It should also be noted that when a component is described as "fixed to" or "set on" another component, it can be directly on the other component or there may be an intervening component present. When a component is described as "connected to" another component, it can be directly connected to the other component or there may be an intervening component present.

[0029] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0030] See Figures 1-3 As shown, the present invention proposes a power supply control circuit, including a delay unit 10, a control unit 20, at least two voltage conversion units (shown in the figures as a first voltage conversion unit 310 and a second voltage conversion unit 320), and at least one resistance adjustment unit 40; wherein,

[0031] The input terminal of the delay unit 10 is electrically connected to the power supply, and the output terminal is electrically connected to the control unit 20. The delay unit 10 is used to slow down the rate of change of the voltage at its output terminal.

[0032] The control unit 20 is electrically connected to the enable terminal of each voltage conversion unit, and is used to sequentially control each voltage conversion unit to start working during the rise of the output voltage of the delay unit 10, and sequentially control each voltage conversion unit to stop working during the fall of the output voltage of the delay unit 10.

[0033] The input terminals of each voltage conversion unit are electrically connected to the power supply, and the output terminals of each voltage conversion unit are electrically connected to different power supply output terminals. The sampling terminal of at least one voltage conversion unit is electrically connected to the resistance adjustment unit 40, which is used to adjust the voltage division ratio of the sampling terminal.

[0034] The technical solution provided by this invention includes a voltage conversion unit electrically connected to a power supply for converting and generating the supply voltage. One voltage conversion unit represents one power supply circuit. Given that processing chips in the prior art typically have multiple operating voltages, the technical solution of this invention provides at least two voltage conversion units to provide two different sets of supply voltages.

[0035] Secondly, a delay unit 10 and a control unit 20 electrically connected to the output of the delay unit 10 are provided. The output of the control unit 20 is connected to the enable terminal of the voltage conversion unit. The delay unit 10 has the function of slowing down the rate of change of the voltage at its output terminal. That is, the control unit 20, which is electrically connected to the output of the delay unit 10, will receive different input voltages at different time points. Therefore, the control unit 20 can control the different voltage conversion units to start or stop working based on the different input voltages at different time points, thereby achieving the power-on and power-off sequence control of multiple power supply circuits.

[0036] In addition, a resistance adjustment unit 40 is provided. As the name suggests, the resistance adjustment unit 40 can change the resistance value to different values, which users can freely choose according to their actual needs. The resistance adjustment unit 40 adjusts the voltage division ratio at the sampling terminal of the voltage conversion unit by adjusting the resistance value, and then further adjusts the output voltage of the voltage conversion unit in the closed-loop adjustment to meet the actual use requirements, such as bias test operations that require different supply voltages.

[0037] In summary, the power supply control circuit provided in this application can not only meet the power-on and power-off timing control of different power supply circuits, but also, through circuit structure design, control different voltage outputs of different power supply circuits, thus meeting the actual usage needs of power supply control circuits such as bias voltage testing.

[0038] See Figure 2 , Figure 3 As shown, in some embodiments, the control unit 20 includes multiple sub-control units (the figures show a first sub-control unit 210 and a second sub-control unit 220), each sub-control unit corresponds to a voltage conversion unit, and the sub-control unit is electrically connected between the enable terminal of the corresponding voltage conversion unit and the output terminal of the delay unit 10. When the output voltage of the delay unit 10 reaches its respective voltage threshold, each sub-control unit outputs a signal to control the corresponding voltage conversion unit to start working; the voltage threshold values ​​of each sub-control unit are different.

[0039] In this embodiment, the sub-control unit is electrically connected between the enable terminal of the corresponding voltage conversion unit and the output terminal of the delay unit 10, so that the input voltage received by each sub-control unit at the same time point is the same. Each sub-control unit is set with a different voltage threshold. After the input voltage of each sub-control unit is compared with each voltage threshold, if the preset conditions are met, the working state of the corresponding voltage conversion unit can be controlled accordingly.

[0040] In some embodiments, each sub-control unit includes a voltage comparator. The V+ pin of the voltage comparator is electrically connected to the output of the delay unit 10, the V- pin receives a reference voltage provided by the power supply, and the output pin is electrically connected to the enable terminal of the corresponding voltage conversion unit. The reference voltage of the V- pin of each voltage comparator is different.

[0041] In this embodiment, the power supply provides a reference voltage to the V-pin of the voltage comparator. In some implementations, the V-pins of each voltage comparator are electrically connected to the same output terminal of the power supply. Different voltage divider modules are set between the V-pin of each voltage comparator and the output terminal of the power supply so that the V-pin of each voltage comparator can receive different magnitudes of reference voltage (i.e., provide a voltage threshold through the V-pin).

[0042] For example, at least two voltage conversion units include a first voltage conversion unit 310 and a second voltage conversion unit 320. The sub-control unit includes a first voltage comparator U1 whose output terminal is electrically connected to the first voltage conversion unit 310, and a second voltage comparator U3 whose output terminal is electrically connected to the second voltage conversion unit 320. The V-pin of the first voltage comparator U1 provides a first voltage threshold, and the V-pin of the second voltage comparator U3 provides a second voltage threshold. During power-up, the voltage at the output terminal of the delay unit 10 rises from 0. When it reaches the first voltage threshold, the first voltage comparator U1 enables the first voltage conversion unit 310 to start operating and output a first supply voltage. The voltage at the output terminal of the delay unit 10 continues to rise, and when it reaches the second voltage threshold, the second voltage comparator U3 enables the second voltage conversion unit 320 to start operating and output a second supply voltage. Because there is a certain time interval between the voltage at the output terminal of the delay unit 10 changing from the first voltage threshold to the second voltage threshold, different power-up timing controls are formed. Furthermore, during power-down, the voltage at the output of delay unit 10 gradually decreases from its maximum value to 0. When the voltage at the output of delay unit 10 drops to the second voltage threshold, the second voltage comparator U3 stops enabling the second voltage conversion unit 320, and the second voltage conversion unit 320 stops working. When the voltage at the output of delay unit 10 continues to drop below the first voltage threshold, the first voltage comparator U1 stops enabling the first voltage conversion unit 310, and the first voltage conversion unit 310 stops working, thus forming different power-down timing control.

[0043] In some embodiments, the resistance adjustment unit 40 includes a range switch K and a pull-down unit. The pull-down unit has multiple ranges with different pull-down resistance values. The range switch K is electrically connected between the sampling terminal and the pull-down unit and is used to switch the range of the pull-down unit.

[0044] Furthermore, the pull-down unit includes at least a standard range resistor R8, a low range resistor R7, and a high range resistor R9; the range switching switch K is a jumper adjustment switch, including a first jumper pin, a second jumper pin, a third jumper pin, and a jumper cap electrically connected to the sampling terminal. The first jumper pin is grounded through the standard range resistor R8, the second jumper pin is grounded through the low range resistor R7, and the third jumper pin is grounded through the high range resistor R9.

[0045] In this embodiment, the circuit path between the sampling end and different resistor levels is achieved by connecting jumper caps to different jumper pins, thereby adjusting the voltage division ratio at the sampling end. It can be understood that when the standard resistor R8 is connected, the output voltage of the voltage conversion unit is the normal operating voltage; when the pull-down resistor R7 is connected, the output voltage of the voltage conversion unit is lower than the normal operating voltage; and when the pull-up resistor R9 is connected, the output voltage of the voltage conversion unit is higher than the normal operating voltage. Thus, the resistance adjustment unit 40 meets the practical application requirements for tasks such as pull-off testing.

[0046] In some embodiments, the delay unit 10 includes a first resistor R1 and a first capacitor C1. One end of the first resistor R1 is the input terminal of the delay unit 10, and the other end of the first resistor R1 is the output terminal of the delay unit 10. The other end of the first resistor R1 is grounded through the first capacitor C1.

[0047] In this embodiment, a simple RC delay circuit is constructed using the first resistor R1 and the first capacitor C1. The RC delay process is the charging and discharging process of the first capacitor C1, according to the capacitor charging and discharging formula:

[0048] Vt=V0+(V1-V0)*[1-exp(-t / R*C)]

[0049] Where V0 is the initial voltage value across the capacitor, V1 is the final voltage value that the capacitor can be charged to or discharged from, Vt is the voltage value across the capacitor at time t, and R*C is the time constant of the RC delay circuit. The parameters of the other variable in the RC delay circuit can be calculated by configuring any two of the three variables: the input voltage of the RC delay circuit, the first resistor R1, and the first capacitor C1.

[0050] In some embodiments, at least two voltage conversion units include a first voltage conversion unit 310 and a second voltage conversion unit 320, and the sampling terminal of the second voltage conversion unit 320 is electrically connected to the resistance adjustment unit 40.

[0051] The first voltage conversion unit 310 includes an LDO chip U2, a first pull-up resistor R2, a first voltage divider resistor R3, and a second voltage divider resistor R4. The enable pin of the LDO chip U2 is the enable terminal of the first voltage conversion unit 310. The input pin of the LDO chip U2 is electrically connected to the power supply through the first pull-up resistor R2. The output pin of the LDO chip U2 is electrically connected to the output terminal of the first voltage conversion unit 310. The sampling pin of the LDO chip U2 is the sampling terminal of the first voltage conversion unit 310. The output pin of the LDO chip U2 is electrically connected to its sampling pin through the first voltage divider resistor R3. The sampling pin of the LDO chip U2 is grounded through the second voltage divider resistor R4.

[0052] The second voltage conversion unit 320 includes a DC-DC chip U4, a second pull-up resistor R5, and a third voltage divider resistor R6. The enable pin of the DC-DC chip U4 is the enable terminal of the second voltage conversion unit 320. The input pin of the DC-DC chip U4 is electrically connected to the power supply via the second pull-up resistor R5. The output pin of the DC-DC chip U4 is electrically connected to the output terminal of the second voltage conversion unit 320. The sampling pin of the DC-DC chip U4 is the sampling terminal of the second voltage conversion unit 320, and the output pin of the DC-DC chip U4 is electrically connected to its sampling pin via the third voltage divider resistor R6.

[0053] In this embodiment, the resistance adjustment unit 40 is electrically connected only to the sampling terminal of the second voltage conversion unit 320, and the first voltage conversion unit 310 uses an LDO chip U2, while the second voltage conversion unit 320 uses a DC-DC chip U4. The LDO chip U2 is typically used in circuits with small input-output voltage differences. Combined with the feedback adjustment of the first voltage divider resistor R3 and the second voltage divider resistor R4, the first voltage conversion unit 310 outputs a stable voltage.

[0054] Based on the circuit structure design, the working process of the first voltage conversion unit 310 is as follows: the first voltage comparator U1 enables the LDO chip U2, the LDO chip U2 starts working, the power supply voltage is input through the input pin of the LDO chip U2, and after being converted by the LDO chip U2, it is output to the output terminal of the first voltage conversion unit 310 through the output pin. Furthermore, the sampling pin of the LDO chip U2 can sample the voltage of the second voltage divider resistor R4, and can provide feedback to adjust the output of the LDO chip U2.

[0055] Similarly, the working process of the second voltage conversion unit 320 is as follows: the second voltage comparator U3 enables the DC-DC chip U4, the DC-DC chip U4 starts working, the power supply voltage is input through the input pin of the DC-DC chip U4, and after being converted by the DC-DC chip U4, it is output to the output terminal of the first voltage conversion unit 310 through the output pin. Furthermore, the sampling pin of the DC-DC chip U4 can sample the voltage of the resistance adjustment unit 40 and adjust the output of the DC-DC chip U4 accordingly.

[0056] In some embodiments, the second voltage conversion unit 320 further includes a filter inductor L1 and a filter capacitor C2. One end of the filter inductor L1 is electrically connected to the output pin of the DC-DC chip U4, and the other end is electrically connected to the output terminal of the second voltage conversion unit 320. The filter capacitor C2 is connected in parallel with the third voltage divider resistor R6.

[0057] In some embodiments, the output terminal of the voltage conversion unit is connected to a filter circuit, including a capacitor provided at its output terminal. The capacitor has multiple capacitors for filtering output noise to form a stable output.

[0058] The following section provides a detailed explanation of the power supply control for LPDDR5 chips.

[0059] LPDDR, short for Low Power Double Data Rate, is a communication standard developed by the JEDEC Solid State Technology Association for low-power memory. It is known for its low power consumption and small size, and is specifically designed for mobile electronic products, often simply referred to as "low-power memory." LPDDR5 is the latest standard. LPDDR5 internally has three voltage groups: VDD1, VDD2, and VDDQ. During the aging verification of LPDDR5 chips, the VDDQ voltage is primarily tested. Based on specific requirements, a power-on / off timing circuit suitable for LPDDR5 chip voltage testing is proposed, mainly targeting the VDD2 and VDDQ power supply circuits. For its specific structure, please refer to [reference needed]. Figure 3 The following are included:

[0060] The RC delay unit 10 includes a first resistor R1 and a first capacitor C1, wherein the resistance of the first resistor R1 is 1kΩ and the capacitance of the capacitor C1 is 10µF. Its connection structure can be configured as described above for the RC delay unit 10. The input voltage at one end of the first resistor R1 is 1.8V.

[0061] R*C=R2*C1=1000×0.01=10ms

[0062] That is, the RC delay unit 10 requires 10ms for the subsequent circuit to rise from 0V to 1.8V.

[0063] The control unit 20 includes a first voltage comparator U1 and a second voltage comparator U3. The V+ pins of both the first voltage comparator U1 and the second voltage comparator U3 are connected to the output terminal of the RC delay unit 10, and the V- pins of both are connected to the power supply. The output voltage of the power supply is 3.3V. A voltage divider module is connected between the power supply and the V- pin of each voltage comparator so that the V- pin of the first voltage comparator U1 can provide a reference voltage of 1.1V and the V- pin of the second voltage comparator U3 can provide a reference voltage of 1.7V.

[0064] The voltage conversion unit includes a first voltage conversion unit 310 and a second voltage conversion unit 320. The circuit structure of the first voltage conversion unit 310 and the second voltage conversion unit 320 is set with reference to the circuit structure described above, and will not be repeated here. The input voltage of the LDO chip U2 and the DC-DC chip U4 is 3.3V. The sampling pin of the DC-DC chip U4 is connected to the resistance adjustment unit 40. The resistance of the first voltage divider resistor R3 is 30Ω, the resistance of the second voltage divider resistor R4 is 100Ω, the resistance of the third voltage divider resistor R6 is 300Ω, the resistance of the standard range resistor R8 is 1.5kΩ, the resistance of the low range resistor R7 is 1.2kΩ, and the resistance of the high range resistor R9 is 1kΩ.

[0065] Understandably, the power supply circuit for the first voltage conversion unit 310 is the VDD2 power supply circuit, and the power supply circuit for the second voltage conversion unit 320 is the VDDQ power supply circuit.

[0066] Based on the voltage output formula Vout=K*(1+RA / RB), the supply voltage of VDD2 can be calculated as follows:

[0067]

[0068] K = 0.8 is a constant value determined based on the LDO stable chip U2, and VDD2 = 1.05V is the normal power supply voltage of the VDD2 power supply circuit in the LPDDR5 chip.

[0069] Based on the voltage output formula Vout=K*(1+RA / RB), the supply voltages of the three VDDQ sets can be calculated:

[0070]

[0071]

[0072]

[0073] Where K = 0.4 is a constant value determined based on the DC-DC chip U4; VDDQ1 = 0.48V is the pull-down test voltage, VDDQ2 = 0.5V is the normal operating voltage, and VDDQ3 = 0.52V is the pull-up test voltage.

[0074] Therefore, the working principle of power supply control for the LPDDR5 chip is as follows: First, upon power-on, the 1.8V voltage is provided by the power supply. This 1.8V is charged through the RC delay unit 10. When the V+ terminal voltage in the first voltage comparator U1 and the second voltage comparator U3 reaches 1.1V, the enable pin of the LDO chip U2 is pulled high, and VDD2 normally outputs 1.05V to power VDD2. The magnitude of this 1.05V voltage is determined by the first voltage divider resistor R3 and the second voltage divider resistor R4. When the V+ terminal in the first voltage comparator U1 and the second voltage comparator U3 reaches 1.7V, the enable pin of the DC-DC chip U4 is pulled high. When the sampling pin of the DC-DC chip U4 is connected to the standard range resistor R8, it normally outputs 0.5V to power VDDQ, thus achieving sequential power-on. Similarly, the sampling pin of the DC-DC chip U4 can also be connected to a low-range resistor R7 and a high-range resistor R9, and the voltage can be switched by a jumper cap, pulling it up to a voltage output of 0.52V or pulling it down to a voltage output of 0.48V respectively.

[0075] When the chip is powered down, the output voltage of the RC delay unit 10 drops below 1.7V first. The voltage at the V+ terminal of the second voltage comparator U3 is lower than the voltage at the V- terminal, the DC-DC chip U4 stops working, and VDDQ is powered off first. The output voltage of the RC delay circuit continues to decrease. When it drops below 1.1V, the voltage at the V+ terminal of the first voltage comparator U1 is lower than the voltage at the V- terminal, the LDO chip U2 stops working, and VDD2 is powered off, thus achieving sequential power-down.

[0076] The present invention further proposes a solid-state drive (SSD) including a power supply control circuit. The specific structure of the power supply control circuit is as described in the above embodiments. Since the SSD adopts all the technical solutions of all the embodiments of the power supply control circuit described above, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0077] The above description is only a part or preferred embodiment of the present invention. Neither the text nor the drawings should limit the scope of protection of the present invention. All equivalent structural transformations made using the content of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect applications in other related technical fields, are included within the scope of protection of the present invention.

Claims

1. A power supply control circuit, characterized in that, It includes a delay unit, a control unit, at least two voltage conversion units, and at least one resistance adjustment unit; wherein, The input terminal of the delay unit is electrically connected to the power supply, and the output terminal is electrically connected to the control unit. The delay unit is used to slow down the rate of change of the voltage at its output terminal. The control unit is electrically connected to the enable terminal of each voltage conversion unit, and is used to sequentially control each voltage conversion unit to start working during the rise of the output voltage of the delay unit, and sequentially control each voltage conversion unit to stop working during the fall of the output voltage of the delay unit. The input terminal of each voltage conversion unit is electrically connected to a power supply, and the output terminal of each voltage conversion unit is electrically connected to a different power supply output terminal. The sampling terminal of at least one voltage conversion unit is electrically connected to the resistance adjustment unit. The resistance adjustment unit is used to adjust the voltage division ratio of the sampling terminal. The resistance adjustment unit includes a range switch and a pull-down unit. The pull-down unit has multiple ranges with different pull-down resistance values. The range switch is electrically connected between the sampling terminal and the pull-down unit and is used to switch between the ranges of the pull-down unit. The control unit includes multiple sub-control units, each of which corresponds one-to-one with each of the voltage conversion units. Each sub-control unit is electrically connected between the enable terminal of the corresponding voltage conversion unit and the output terminal of the delay unit. When the output voltage of the delay unit reaches its respective voltage threshold, each sub-control unit outputs a signal to control the corresponding voltage conversion unit to start working. The voltage threshold values ​​of each sub-control unit are different.

2. The power supply control circuit according to claim 1, characterized in that, Each of the sub-control units includes a voltage comparator. The V+ pin of the voltage comparator is electrically connected to the output terminal of the delay unit, the V- pin receives the reference voltage provided by the power supply, and the output pin is electrically connected to the enable terminal of the corresponding voltage conversion unit. The reference voltage of the V- pin of each voltage comparator is different.

3. The power supply control circuit according to claim 1, characterized in that, The pull-down unit includes at least a standard range resistor, a low range resistor, and a high range resistor; the range switching switch is a jumper adjustment switch, including a first jumper pin, a second jumper pin, a third jumper pin, and a jumper cap electrically connected to the sampling terminal. The first jumper pin is grounded through the standard range resistor, the second jumper pin is grounded through the low range resistor, and the third jumper pin is grounded through the high range resistor.

4. The power supply control circuit according to claim 1, characterized in that, The delay unit includes a first resistor and a first capacitor. One end of the first resistor is the input terminal of the delay unit, and the other end of the first resistor is the output terminal of the delay unit. The other end of the first resistor is grounded through the first capacitor.

5. The power supply control circuit according to claim 1, characterized in that, The at least two voltage conversion units include a first voltage conversion unit and a second voltage conversion unit, wherein the sampling terminal of the second voltage conversion unit is electrically connected to the resistance adjustment unit; The first voltage conversion unit includes an LDO chip, a first pull-up resistor, a first voltage divider resistor, and a second voltage divider resistor. The enable pin of the LDO chip is the enable terminal of the first voltage conversion unit. The input pin of the LDO chip is electrically connected to the power supply via the first pull-up resistor. The output pin of the LDO chip is electrically connected to the output terminal of the first voltage conversion unit. The sampling pin of the LDO chip is the sampling terminal of the first voltage conversion unit. The output pin of the LDO chip is electrically connected to its sampling pin via the first voltage divider resistor. The sampling pin of the LDO chip is grounded via the second voltage divider resistor. The second voltage conversion unit includes a DC-DC chip, a second pull-up resistor, and a third voltage divider resistor. The enable pin of the DC-DC chip is the enable terminal of the second voltage conversion unit. The input pin of the DC-DC chip is electrically connected to the power supply via the second pull-up resistor. The output pin of the DC-DC chip is electrically connected to the output terminal of the second voltage conversion unit. The sampling pin of the DC-DC chip is the sampling terminal of the second voltage conversion unit, and the output pin of the DC-DC chip is electrically connected to its sampling pin via the third voltage divider resistor.

6. The power supply control circuit according to claim 5, characterized in that, The second voltage conversion unit further includes a filter inductor and a filter capacitor. One end of the filter inductor is electrically connected to the output pin of the DC-DC chip, and the other end is electrically connected to the power supply output terminal. The filter capacitor is connected in parallel with the third voltage divider resistor.

7. The power supply control circuit according to claim 1, characterized in that, The output of the voltage conversion unit is connected to a filter circuit to filter out noise.

8. A solid-state drive, characterized in that, The solid-state drive includes the power supply control circuit as described in any one of claims 1-7.

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