计算装置、计算装置的操作方法、电子设备和存储介质
By pre-storing the on-chip addresses of unbound resource descriptors in the instruction scheduler circuit, the processor latency problem caused by frequent interactions of unbound resource descriptors is solved, thereby improving the processor's performance and efficiency.
CN116069392BActive Publication Date: 2026-07-17SHANGHAI BIREN TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2023-01-13
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
Existing processors frequently interact with dedicated caches when using unbound resource descriptors, resulting in processing delays and impacting processor performance.
Method used
The on-chip address of the unbound resource descriptor is pre-stored in the instruction scheduler circuit, and the on-chip address is pre-allocated before the memory access instruction through the pre-allocation instruction. The instruction is directly read from the on-chip address register of the descriptor and sent to the execution unit circuit to execute the instruction.
Benefits of technology
It reduces instruction wait time, improves processor performance and execution efficiency, and reduces operational complexity.
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Figure CN116069392B_ABST
Abstract
本公开提供了一种计算装置、计算装置的操作方法、电子设备和计算机可读存储介质。该计算装置包括：多个执行单元，每个所述执行单元包括指令调度器电路以及执行单元电路，其中所述指令调度器电路包括描述符片上地址寄存器，所述描述符片上地址寄存器用于保存通过预分配指令获取的至少一个非绑定资源描述符的片上地址，其中所述指令调度器电路被配置为：在接收到存储访问指令时，直接从所述描述符片上地址寄存器读取与所述存储访问指令相对应的非绑定资源描述符的片上地址，并且将所述非绑定资源描述符的片上地址发送给所述执行单元电路以执行所述存储访问指令。
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