Instruction fetching method, instruction fetching device, and storage medium

Abstract

The present disclosure provides a fetch instruction method, a fetch instruction device and a computer readable storage medium. The fetch instruction method is used for fetching instructions for a thread bundle, the thread bundle corresponds to an instruction temporary storage area, the instruction temporary storage area includes a first sub-area, and the fetch instruction method includes: obtaining a first group of instructions; pre-parsing the first group of instructions to determine a first branch instruction, wherein the first group of instructions includes the first branch instruction; in response to the first sub-area being empty or storing invalid instructions, fetching instructions from a target address of the first branch instruction to obtain a second group of instructions; and storing the second group of instructions to the first sub-area.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an instruction fetching method, an instruction fetching apparatus, and a computer-readable storage medium. Background Technology

[0002] Branch instructions are common in both CPU (central processing unit) and GPU (graphics processing unit) instruction sets. They represent instructions that change the program flow, causing the program counter (PC) of a GPGPU (general purpose graphics processing unit) to jump. Based on whether a jump occurs, branch instructions can be divided into immediate jump instructions and conditional jump instructions; based on the jump address, they can be divided into direct jump instructions and indirect jump instructions. An immediate jump instruction means that when the branch instruction is executed, the PC pointer points to the target address specified by the branch instruction, instead of the address it was originally pointing to. A conditional jump instruction means that when the jump condition specified by the branch instruction is met, the PC pointer points to the target address specified by the branch instruction; otherwise, the PC pointer does not jump and points to the address it was originally pointing to. A direct jump instruction means that the target address of the branch instruction is obtained by adding an immediate offset from the current PC value to the address specified in the instruction. An indirect jump branch instruction means that the target address of the branch instruction is provided by a register, so it is necessary to read the register to obtain the target address. Summary of the Invention

[0003] This disclosure provides at least one embodiment of an instruction fetching method for fetching instructions for a thread bundle, wherein the thread bundle corresponds to an instruction temporary storage area, the instruction temporary storage area includes a first sub-region, and the instruction fetching method includes: obtaining a first set of instructions; pre-parsing the first set of instructions to determine a first branch instruction, wherein the first set of instructions includes the first branch instruction; in response to the first sub-region being empty or storing an invalid instruction, fetching instructions from the target address of the first branch instruction to obtain a second set of instructions; and storing the second set of instructions into the first sub-region.

[0004] For example, in the instruction fetching method provided in at least one embodiment of this disclosure, the instruction temporary storage area further includes a second sub-region and a third sub-region, the first group of instructions is stored in the second sub-region or the third sub-region, and the instruction fetching method further includes: determining the instruction execution result obtained by executing the first branch instruction; and, in response to the instruction execution result indicating that a jump is needed, jumping to execute the second group of instructions stored in the first sub-region.

[0005] For example, at least one embodiment of the present disclosure provides an instruction fetching method that further includes: after jumping to execute the second set of instructions stored in the first sub-region, obtaining a third set of instructions, wherein the addresses of the instructions in the second set of instructions and the addresses of the instructions in the third set of instructions are contiguous; and storing the third set of instructions in the second sub-region or the third sub-region.

[0006] For example, at least one embodiment of the instruction fetching method provided in this disclosure further includes: after storing the third set of instructions to the second sub-region or the third sub-region, in response to the second set of instructions not including branch instructions and the first sub-region storing at least one valid unexecuted instruction, suspending the instruction fetching operation.

[0007] For example, at least one embodiment of the present disclosure provides an instruction fetching method that further includes: after jumping to execute the second set of instructions stored in the first sub-region, pre-parsing the second set of instructions to determine a second branch instruction, wherein the second set of instructions includes the second branch instruction; fetching instructions from the target address of the second branch instruction to obtain a fifth set of instructions; and storing the fifth set of instructions in the second sub-region or the third sub-region.

[0008] For example, at least one embodiment of the instruction fetching method provided in this disclosure further includes: after jumping to execute the second set of instructions stored in the first sub-region, setting all unexecuted instructions in the second sub-region and the third sub-region as invalid instructions.

[0009] For example, at least one embodiment of the instruction fetching method provided in this disclosure further includes: in response to the instruction execution result indicating that no jump is required, executing the instruction after the first branch instruction, and setting all unexecuted instructions in the first sub-region as invalid instructions.

[0010] For example, in the instruction fetching method provided in at least one embodiment of this disclosure, the instruction temporary storage area further includes a second sub-region, and obtaining the first set of instructions includes: in response to the second sub-region being empty or storing invalid instructions, obtaining the first set of instructions, and the instruction fetching method further includes: storing the first set of instructions in the second sub-region.

[0011] For example, in the instruction fetching method provided in at least one embodiment of this disclosure, the instruction temporary storage area further includes a third sub-region, and the instruction fetching method further includes: in response to the third sub-region being empty or storing invalid instructions, obtaining a fourth set of instructions, wherein the addresses of the instructions in the fourth set of instructions and the addresses of the instructions in the first set of instructions are consecutive; and storing the fourth set of instructions in the third sub-region.

[0012] For example, in the instruction fetching method provided in at least one embodiment of this disclosure, the number of instructions in the first group of instructions is the same as the number of instructions in the fourth group of instructions.

[0013] For example, in the instruction fetching method provided in at least one embodiment of this disclosure, pre-parsing the first group of instructions to determine the first branch instruction includes: pre-parsing all instructions in the first group of instructions; determining that the first group of instructions includes at least one branch instruction, and taking the branch instruction that is executed first in the execution order among the at least one branch instruction as the first branch instruction.

[0014] For example, in the instruction fetching method provided in at least one embodiment of this disclosure, the instruction temporary storage area further includes a fourth sub-region, and the instruction fetching method further includes: pre-parsing the first group of instructions to determine a third branch instruction, wherein the first group of instructions further includes the third branch instruction; in response to the fourth sub-region being empty or storing an invalid instruction, fetching instructions from the target address of the third branch instruction to obtain a sixth group of instructions; and storing the sixth group of instructions in the fourth sub-region.

[0015] At least one embodiment of this disclosure provides an instruction fetching device for fetching instructions for a thread bundle, wherein the thread bundle corresponds to an instruction temporary storage area, the instruction temporary storage area includes a first sub-region, and the instruction fetching device includes: an instruction fetching unit configured to acquire a first set of instructions; a branch instruction determination unit configured to pre-parse the first set of instructions to determine a first branch instruction, wherein the first set of instructions includes the first branch instruction; the instruction fetching unit is further configured to, in response to the first sub-region being empty or storing invalid instructions, fetch instructions from the target address of the first branch instruction to acquire a second set of instructions; and store the second set of instructions in the first sub-region.

[0016] At least one embodiment of this disclosure provides an instruction fetching apparatus, including a memory and a processor, wherein the memory stores computer-executable instructions suitable for execution by the processor, the computer-executable instructions being executed by the processor to perform one or more steps of the instruction fetching method according to any embodiment of this disclosure.

[0017] At least one embodiment of this disclosure provides a computer-readable storage medium that non-transitoryly stores computer-executable instructions, wherein the computer-executable instructions are executed by a computer at runtime, performing one or more steps of the instruction fetching method according to any embodiment of this disclosure. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0019] Figure 1 This is a schematic diagram of a finger-fetching process;

[0020] Figure 2 A schematic flowchart illustrating an instruction fetching method provided for at least one embodiment of this disclosure;

[0021] Figure 3 A schematic diagram of a temporary instruction storage area provided for at least one embodiment of this disclosure;

[0022] Figure 4 A schematic flowchart illustrating the storage of instructions in a temporary instruction storage area provided for at least one embodiment of this disclosure;

[0023] Figure 5 A schematic diagram illustrating the jump of the instruction read pointer in the instruction temporary storage area during instruction execution, provided for at least one embodiment of this disclosure;

[0024] Figure 6 A schematic flowchart illustrating the storage of instructions in a temporary instruction storage area provided for at least one embodiment of this disclosure;

[0025] Figure 7 A schematic diagram of an indexing device provided for at least one embodiment of this disclosure;

[0026] Figure 8 A schematic block diagram of an instruction fetching device provided for at least one embodiment of this disclosure; and

[0027] Figure 9 This is a schematic diagram of a computer-readable storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0030] In the description of this disclosure, the instruction execution result of a branch instruction indicating that a jump is required is called "taken", and the instruction execution result of a branch instruction indicating that a jump is not required is called "not-taken".

[0031] Instruction fetching in GPGPU is based on a single warp. Before the GPGPU executes a piece of code, the corresponding instructions are pre-stored in an allocated instruction segment. A single warp needs to fetch instructions one by one, then decode and execute them. However, due to the bandwidth capabilities of the GPGPU cache system design, in general, fetching instructions for a single warp can retrieve multiple instructions at once.

[0032] Instructions for recurring addresses are stored locally to satisfy subsequent execution. Each thread bundle has a temporary buffer space to store multiple fetched instructions, i.e., the instruction temporary storage area. Typically, this temporary storage area stores...

[0033] The size of the instruction fetch area can cover the number of instructions fetched multiple times. Therefore, when the instruction temporary storage area is not full, the instruction fetch unit corresponding to the thread bundle can continue to fetch multiple instructions in advance for the thread bundle, maximizing the execution bandwidth of subsequent execution units.

[0034] Figure 1 A schematic diagram of an instruction fetch process is shown. During each fetch process, the 0th fetch unit corresponding to the thread bundle can fetch multiple instructions at once; assuming the number of instructions fetched at one time is 8...

[0035] Each instruction has a dword (double word, each word is 2 bytes long), and assuming each instruction is 1 dword wide, then 8 instructions can be retrieved at once. For example... Figure 1As shown, the instruction temporary storage area is a storage array that can hold 16 dwords. The storage array consists of 4 rows L00 to L03, each row can hold 4 dwords (i.e., Figure 1 Each rectangular block in the array can hold 5 bytes of dword. During the first instruction fetch operation, the 8 instructions fetched by the instruction fetch unit can be stored...

[0036] In lines L00 and L01, the eight instructions fetched by the instruction fetch unit in the second instruction fetch operation will be stored in lines L02 and L03. While the fetched instructions are stored in the instruction temporary storage area, the instruction pre-parse unit will pre-parse these temporarily stored instructions, analyzing whether they contain any...

[0037] If the instruction contains branch instructions, then instruction prefetching will no longer be performed. In this case, the instruction pre-parsing unit can send an abort instruction prefetch to the instruction fetch unit to instruct the instruction fetch unit to abort the instruction.

[0038] Instruction prefetching. After aborting instruction prefetching, all branch instructions stored in the instruction temporary storage area are executed. If the execution result of all branch instructions stored in the instruction temporary storage area is "not-taken", then the instruction fetching operation for that thread bundle is resumed. At this time, the instruction preparing unit can send a resume instruction prefetch to the instruction fetching unit to instruct the instruction fetching unit to restart instruction prefetching.

[0039] 5 such as Figure 1 As shown, the instruction execution unit can retrieve and execute branch instructions from the instruction temporary storage area.

[0040] If the execution result of a branch instruction stored in the instruction temporary storage area is "taken", then the instruction execution unit can invalidate all the remaining unexecuted instructions in the instruction temporary storage area. At the same time, the instruction execution unit will send an instruction prefetch to the instruction fetch unit to notify the instruction fetch unit to fetch the instruction from the target address of that branch instruction.

[0041] The above instruction fetching process has the following problems: First, when the fetched instruction contains a branch instruction,

[0042] The instruction fetch unit will pause prefetching instructions for the thread bundle. If the execution results of these branch instructions are all "not taken," meaning the PC does not need to jump, then the time the instruction fetch unit pauses to prefetch instructions for the thread bundle is wasted, which will affect the overall GPGPU IPC (instructions per clock, which measures the speed at which the processor executes instructions; IPC represents the average number of instructions the processor can execute in a single machine cycle). Secondly, when there are branch instructions among the fetched instructions, the instruction fetch unit will pause prefetching instructions for the thread bundle. If there are branch instructions whose execution result is "taken" and that branch instruction is not currently in the execution cycle, then when the branch instruction is executed, the thread bundle will find that the PC needs to jump and invalidate the unexecuted instructions in the instruction temporary storage area before notifying the instruction fetch unit to fetch the instruction at the target address of the branch instruction. Therefore, the thread bundle is in an idle state until the instruction at the target address of the branch instruction is fetched, which will also affect the overall GPGPU IPC.

[0043] To address the shortcomings of the aforementioned solutions, at least one embodiment of this disclosure provides an instruction fetching method for fetching instructions for a thread bundle. The thread bundle corresponds to a temporary instruction storage area, which includes a first sub-region. The instruction fetching method includes: obtaining a first set of instructions; pre-parsed the first set of instructions to determine a first branch instruction, wherein the first set of instructions includes a first branch instruction; in response to the first sub-region being empty or storing an invalid instruction, fetching instructions from the target address of the first branch instruction to obtain a second set of instructions; and storing the second set of instructions in the first sub-region.

[0044] In the instruction fetching method provided in the embodiments of this disclosure, when pre-parsing instructions and determining that there are branch instructions, a set of instructions is fetched in advance from the target address of the branch instructions that have not yet been executed and stored in the instruction temporary storage area. When the instruction execution result of the branch instruction is "taken", the PC jumps and can immediately read the instruction at the target address of the branch instruction from the instruction temporary storage area for execution without stopping the thread bundle. This reduces the time overhead of the PC jumping to execute due to the branch instruction to a certain extent, thereby improving the IPC of the GPGPU to a certain extent, reducing the idle time of the thread bundle, and improving the efficiency of instruction execution.

[0045] At least one embodiment of this disclosure also provides an instruction fetching device and a computer-readable storage medium.

[0046] The instruction fetching method provided in this disclosure can be applied to the instruction fetching device provided in this disclosure, which can be configured on an electronic device. The electronic device can be a personal computer, a mobile terminal, etc., and the mobile terminal can be a smartphone, tablet computer, or other hardware device.

[0047] In this disclosure, "branch fetch operation" means that the fetch unit performs an instruction fetch operation from the target address of the branch instruction, and "normal fetch operation" means that the fetch unit performs an instruction fetch operation from the address corresponding to the normal instruction flow. Both branch fetch operation and normal fetch operation are performed by the fetch unit.

[0048] In this disclosure, "valid unexecuted instructions" refers to instructions that belong to the current instruction sequence being executed by the processor, but have not yet been executed by the processor and need to be executed by the processor later. "Invalid instructions" can be divided into two types: the first type is instructions that have already been executed by the processor, in which case the instructions will be considered invalid; the second type is instructions that have not yet been executed by the processor, but due to some specific events, these instructions do not need to be executed by the processor later.

[0049] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings; however, this disclosure is not limited to these specific embodiments. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted.

[0050] Figure 2 This is a schematic flowchart illustrating an instruction fetching method provided for at least one embodiment of the present disclosure. Figure 3 This is a schematic diagram of a temporary instruction storage area provided for at least one embodiment of the present disclosure.

[0051] For example, the instruction fetch method is applied to thread bundles, specifically for fetching instructions for thread bundles. A thread bundle is a group of threads executing on a single PC (a group of threads includes multiple threads), and is also the smallest unit of instruction scheduling in a GPGPU. Multiple threads within each thread bundle can execute in parallel. In some examples, each thread bundle may include 32 threads, 64 threads, etc. It should be noted that the number of threads included in a thread bundle can be set according to the actual hardware circuitry, and the embodiments disclosed herein do not impose specific limitations on this.

[0052] For example, each thread bundle corresponds to a temporary instruction storage area to store instructions retrieved in advance for that thread bundle. This temporary instruction storage area can consist of multiple rows and columns of storage units, such as... Figure 3 As shown, the temporary instruction storage area can include 6 rows and 4 columns of storage units. Figure 3In this diagram, each rectangular block Su represents a memory cell. In some examples, each memory cell can store at least one instruction. It should be noted that, for clarity and brevity, this description uses the example of each memory cell storing one instruction.

[0053] It is worth noting that, Figure 3 The temporary instruction storage area shown is for illustrative purposes only. Figure 3 The positions of the rows of memory cells in the instruction temporary storage area shown are not arranged in order of their addresses.

[0054] For example, the instruction temporary storage area may include multiple sub-regions, each of which can store all instructions retrieved in a single instruction fetch operation (normal instruction fetch or branch instruction fetch). It should be noted that, for clarity and brevity, the embodiments of this disclosure are described using the example of each sub-region storing all instructions retrieved in only one instruction fetch operation. However, this disclosure is not limited to this; the division of sub-regions can be set according to actual circumstances. For example, each sub-region may also be configured to store all instructions retrieved in at least two instruction fetch operations. In the embodiments of this disclosure, the sub-regions are merely set up for descriptive convenience; in actual scenarios, the instruction temporary storage area does not have an actual division of sub-regions.

[0055] For example, such as Figure 3 As shown, the instruction temporary storage area includes the first sub-region R1. Figure 2 As shown, the finger fetching method includes the following steps S10 to S40.

[0056] Step S10: Obtain the first set of instructions.

[0057] Step S20: Pre-parse the first group of instructions to determine the first branch instruction, wherein the first group of instructions includes the first branch instruction.

[0058] Step S30: In response to the first sub-region being empty or containing invalid instructions, fetch instructions from the target address of the first branch instruction to obtain the second set of instructions.

[0059] Step S40: Store the second set of instructions to the first sub-region.

[0060] For example, the first sub-region R1 may include at least one row of storage cells, and each row of storage cells includes at least one storage cell. Figure 3 In the example shown, the first sub-region R1 may include storage cell line L0 and storage cell line L1. The first sub-region R1 may store at least all instructions fetched in one branch fetch operation for a branch instruction. The first sub-region R1 may also be used to store a second set of instructions pre-fetched from the target address of the first branch instruction.

[0061] In this disclosure, for the prefetching of branch instructions (e.g., the first unexecuted branch instruction), a separate space can be allocated in the instruction temporary storage area of ​​the thread bundle to store the instruction prefetched from the target address of the branch instruction. This avoids the problem that when the result of the branch instruction execution is "taken", the remaining unexecuted instructions in the instruction temporary storage area are invalidated, and the instruction fetching unit has to start fetching instructions from the target address of the branch instruction. It also avoids the thread bundle being idle when the result of the branch instruction execution is "taken", improving the IPC of the GPGPU and enhancing the performance of instruction execution and fetching.

[0062] For example, such as Figure 3 As shown, in one embodiment, the instruction temporary storage area further includes a second sub-region R2, which may include storage cell row L2 and storage cell row L3.

[0063] For example, in step S10, the PC of the main process executing instructions can retrieve the first set of instructions from external storage. Step S10 may include: retrieving the first set of instructions in response to the second sub-region being empty or storing invalid instructions. In embodiments of this disclosure, when retrieving instructions, it is first necessary to determine whether there is free storage space in the instruction temporary storage area to store the retrieved instructions; if it is determined that there is free storage space in the instruction temporary storage area, then an instruction fetch operation is performed to retrieve the instructions, and the retrieved instructions are stored in the corresponding storage space.

[0064] For example, in some embodiments, the instruction fetching method further includes storing a first set of instructions into a second sub-region.

[0065] For example, the first set of instructions is the set of instructions retrieved in a normal instruction fetch operation. In some embodiments, the first set of instructions may include eight instructions. If the memory cells in the second sub-region are all empty or contain invalid instructions, a normal instruction fetch operation can be performed to retrieve the first set of instructions. Then, the first set of instructions can be stored in memory cell rows L2 and L3 in the second sub-region.

[0066] For example, such as Figure 3 As shown, in one embodiment, the instruction temporary storage area further includes a third sub-region R3, which may include storage cell row L4 and storage cell row L5.

[0067] For example, in some embodiments, the instruction fetching method further includes: in response to the third sub-region being empty or containing invalid instructions, fetching a fourth set of instructions, wherein the addresses of the instructions in the fourth set of instructions are contiguous with the addresses of the instructions in the first set of instructions; and storing the fourth set of instructions in the third sub-region.

[0068] In the embodiments of this disclosure, the number of instructions fetched by the instruction fetch unit in each instruction fetch operation (normal instruction fetch operation or branch instruction fetch operation) can be a fixed value. For example, each instruction fetch operation can fetch 8 instructions, 16 instructions, etc. For example, the number of instructions in the first group of instructions, the number of instructions in the second group of instructions, and the number of instructions in the fourth group of instructions can all be the same. For example, in one example, they are all 8 instructions.

[0069] It should be noted that in some embodiments, the first set of instructions can be stored in the third sub-region R3, while the fourth set of instructions is stored in the second sub-region R2. The embodiments of this disclosure do not impose specific restrictions on the storage locations of the first set of instructions and the fourth set of instructions.

[0070] For example, in some embodiments, the first set of instructions is fetched earlier than the fourth set of instructions. In this case, after storing the first set of instructions in storage cell rows L2 and L3 in the second sub-region R2, it can be determined whether storage cell rows L4 and L5 in the third sub-region R3 are both empty or contain invalid instructions. When storage cell rows L4 and L5 are both empty or contain invalid instructions, regardless of whether the first set of instructions includes branch instructions, the normal instruction fetch operation can be performed again, that is, the fourth set of instructions is fetched and stored in storage cell rows L4 and L5.

[0071] For example, in some other embodiments, the time for fetching the first set of instructions is later than the time for fetching the fourth set of instructions. In this case, after fetching the fourth set of instructions and storing it in storage cell rows L4 and L5 in the third sub-region R3, it can be determined whether storage cell rows L2 and L3 in the second sub-region R2 are both empty or contain invalid instructions. If storage cell rows L2 and L3 are both empty or contain invalid instructions, regardless of whether the fourth set of instructions includes branch instructions, the normal instruction fetch operation can be performed again, that is, the first set of instructions is fetched and stored in storage cell rows L2 and L3.

[0072] The above description uses the example of a temporary instruction storage area comprising a first sub-region R1, a second sub-region R2, and a third sub-region R3. However, this disclosure is not limited to this. If the first set of instructions is fetched earlier than the fourth set of instructions, after retrieving the first set of instructions and storing it in storage cell lines L2 and L3 of the second sub-region, other sub-regions in the temporary instruction storage area used to store instructions fetched during normal instruction fetching operations can be evaluated to determine whether each sub-region stores at least one valid, unexecuted instruction. If each sub-region stores at least one valid, unexecuted instruction, the normal instruction fetching operation is aborted. If the temporary instruction storage area also includes at least one free storage space for storing all instructions fetched in one normal instruction fetching operation, the normal instruction fetching operation continues. For example, free storage space refers to the space in the temporary instruction storage area used to store instructions fetched during normal instruction fetching operations, and may include space occupied by unstored instructions and / or invalid instructions.

[0073] In the embodiments of this disclosure, even if the instructions stored in the second sub-region R2 or the third sub-region R3 include branch instructions, the normal instruction fetch operation will not be interrupted. Instead, the normal instruction fetch operation will continue to be executed until each sub-region in the instruction temporary storage area used to store the instructions retrieved by the normal instruction fetch operation stores at least one valid unexecuted instruction or the free storage space in the instruction temporary storage area used to store the instructions retrieved by the normal instruction fetch operation is insufficient to store the instructions retrieved by a normal instruction fetch operation, thereby maximizing the execution bandwidth of subsequent execution units.

[0074] For example, in some embodiments, step S20 may include: pre-parse all instructions in the first group of instructions; determine that the first group of instructions includes at least one branch instruction, and select the branch instruction that is executed first in the execution order from the at least one branch instruction in the first group of instructions as the first branch instruction.

[0075] For example, in step S20, when the second set of instructions is fetched, the first branch instruction has not yet been executed. Therefore, the instruction fetching method provided by the embodiments of this disclosure can be used to prefetch instructions for branch instructions. When the instruction execution result of the branch instruction is "taken", the PC jumps and can immediately read the instruction at the target address of the branch instruction from the instruction temporary storage area for execution without stopping the thread bundle. This reduces the time overhead of the PC jumping to execute the branch instruction to a certain extent, thereby improving the IPC of the GPGPU to a certain extent, reducing the idle time of the thread bundle, and improving the efficiency of instruction execution.

[0076] For example, in steps S30 and S40, when pre-parsing and determining that the first set of instructions includes at least one branch instruction, if the storage cell line L0 and storage cell line L1 of the first sub-region R1 are both empty or contain only invalid instructions, a branch fetch operation can be performed on the branch instruction that is executed first in the execution order (i.e., the first branch instruction). That is, the instruction is fetched from the target address of the first branch instruction to obtain the second set of instructions, and then the fetched second set of instructions is stored in the first sub-region R1. If the storage cell line L0 and storage cell line L1 of the first sub-region R1 contain at least one valid unexecuted instruction, and the second sub-region R2 and the third sub-region R3 also contain at least one valid unexecuted instruction, then no pre-fetch operation is performed on the first branch instruction until the instruction temporary storage area contains free storage space capable of storing the instructions fetched by one branch fetch operation.

[0077] The following explanation uses an example where the instruction temporary storage area only includes the first sub-region R1, the second sub-region R2, and the third sub-region R3. If the first set of instructions is fetched earlier than the fourth set of instructions, in the embodiments of this disclosure, after fetching and storing the first set of instructions, the first set of instructions can be pre-parsed to determine whether the first set of instructions includes at least one branch instruction. If the first set of instructions does not include a branch instruction or includes at least one branch instruction (not yet executed), and storage cell line L4 and storage cell line L5 are both empty or contain invalid instructions, then the next normal instruction fetch operation will be executed, that is, the fourth set of instructions will be fetched, and the pre-fetched fourth set of instructions will be stored in storage cell line L4 and storage cell line L5. If storage cell line L4 and storage cell line L5 are not both empty or do not contain all invalid instructions, then each sub-region in the instruction temporary access area used to store instructions fetched in the normal instruction fetch operation stores at least one valid unexecuted instruction, or the free storage space in the instruction temporary access area used to store instructions fetched in the normal instruction fetch operation is insufficient to store instructions fetched in one normal instruction fetch operation, then the normal instruction fetch operation can be aborted. Furthermore, if the first set of instructions includes at least one branch instruction (not yet executed), when memory cell line L0 and memory cell line L1 are both empty or both contain invalid instructions, a branch fetch operation will also be performed for the first branch instruction (e.g., the first branch instruction) included in the first set of instructions. That is, the instruction will be fetched from the target address of the first branch instruction to obtain the second set of instructions, and then the second set of instructions to be fetched will be stored in memory cell line L0 and memory cell line L1.

[0078] In the embodiments of this disclosure, when pre-parsing instructions and determining that a branch instruction exists, a branch instruction fetch operation can be performed without interrupting the instruction prefetching of the thread bundle. For example, when pre-parsing and determining that a first branch instruction exists in the first group of instructions, the normal instruction fetch operation can continue to obtain the fourth group of instructions. Therefore, when the execution result of the branch instruction is "not taken," the instructions following the branch instruction can continue to be executed. This can, to some extent, reduce the idle time of subsequent execution units due to the lack of instructions in the instruction temporary storage area, thereby improving the IPC of the GPGPU to a certain extent.

[0079] If the time to obtain the first group of instructions is later than the time to obtain the fourth group of instructions, the fourth group of instructions can be pre-parsed and it can be determined whether the fourth group of instructions includes at least one branch instruction. The subsequent operations are similar to the above operations of pre-parsed the first group of instructions and determining whether the first group of instructions includes at least one branch instruction. The repeated parts will not be described again.

[0080] Unless otherwise specified, the following description will use the example of obtaining the first set of instructions earlier than obtaining the fourth set of instructions.

[0081] For example, in some embodiments, the instruction fetching method further includes: determining the instruction execution result obtained by executing the first branch instruction; and, in response to the instruction execution result indicating that a jump is required, jumping to execute the second set of instructions stored in the first sub-region.

[0082] When executing the first branch instruction, the result of the branch instruction can be obtained. If the instruction execution result indicates that a jump is required (i.e., "taken"), the PC of the thread bundle jumps, thereby jumping to execute the second set of instructions stored in the first sub-region. Therefore, the next instruction to be executed will be the first instruction in the instructions previously prefetched for the first branch instruction, that is, the first instruction stored in the first sub-region.

[0083] For example, in some embodiments, the instruction fetching method further includes: after jumping to execute the second set of instructions stored in the first sub-region, setting all unexecuted instructions in the second and third sub-regions as invalid instructions.

[0084] It should be noted that in this disclosure, if the instruction execution result obtained from executing the first branch instruction indicates that a jump instruction is required, then all other instructions in the instruction temporary storage area, except for the instruction pre-fetched for the first branch instruction, can be set to invalid.

[0085] For example, if the execution result of the first branch instruction indicates that a jump (i.e., "taken") is required, then the remaining unexecuted instructions in the second sub-region are invalidated, as are the previously fetched instructions in the third sub-region. It should be noted that if there are no unexecuted instructions in the second sub-region and / or no stored instructions in the third sub-region (i.e., all instructions in the instruction temporary storage area except those fetched for the first branch instruction have been executed, or there are no instructions in the instruction temporary storage area except those fetched for the first branch instruction), then the operation of invalidating the instructions is not necessary.

[0086] For example, in some embodiments, the instruction fetching method further includes: after jumping to execute the second set of instructions stored in the first sub-region, pre-parsing the second set of instructions to determine the second branch instructions, wherein the second set of instructions includes the second branch instructions; fetching instructions from the target address of the second branch instructions to obtain the fifth set of instructions; and storing the fifth set of instructions to the second sub-region or the third sub-region.

[0087] For example, pre-parse the second set of instructions to determine the second branch instruction may include: pre-parse all instructions in the second set of instructions; in response to determining that the second set of instructions includes at least one branch instruction; and selecting the branch instruction that is executed first in the execution order from the at least one branch instruction included in the second set of instructions as the second branch instruction.

[0088] For example, storing the fifth set of instructions to the second or third sub-region may include: storing the fifth set of instructions to the third sub-region in response to storing the third set of instructions to the second sub-region; or storing the fifth set of instructions to the fourth sub-region in response to storing the third set of instructions to the third sub-region.

[0089] In embodiments of this disclosure, at least one sub-region needs to be reserved in the instruction temporary storage area to store the instructions retrieved by the branch instruction fetch operation, thereby ensuring that the branch instruction can be executed after pre-parsing. For example, in some embodiments, the instruction fetching method further includes: after storing the third set of instructions to the second or third sub-region, in response to the second set of instructions not including a branch instruction and the first sub-region storing at least one valid unexecuted instruction, the instruction fetching operation is aborted.

[0090] For example, in some embodiments, the instruction fetching method further includes: after jumping to execute the second set of instructions stored in the first sub-region, fetching a third set of instructions, wherein the addresses of the instructions in the second set of instructions and the addresses of the instructions in the third set of instructions are contiguous; and storing the third set of instructions in the second sub-region or the third sub-region.

[0091] For example, when fetching the third set of instructions, the second branch instructions have not yet been executed.

[0092] For example, the number of instructions in the second group and the number of instructions in the third group can both be the same; for example, in one example, both are 8 instructions.

[0093] It should be noted that, in the embodiments of this disclosure, "after jumping to execute the second set of instructions stored in the first sub-region" means jumping and starting to execute the second set of instructions stored in the first sub-region. It does not mean that all instructions in the second set have been executed; it only indicates that a jump has occurred on the PC. After the PC jumps, the second set of instructions can be pre-parsed to determine whether it includes branch instructions.

[0094] For example, in the embodiments of this disclosure, after the jump to execute the second set of instructions stored in the first sub-region, that is, after the PC jumps, since all instructions in the second and third sub-regions are invalidated, it is equivalent to the second and third sub-regions storing invalid instructions or being empty. Both the second and third sub-regions can receive and store the instructions fetched by the instruction fetch unit. Therefore, instruction prefetching can be triggered at this time, and the subsequent process will be similar to the above. It should be noted that after the PC jumps, the instruction execution flow corresponding to the second set of instructions becomes the main (non-branch) instruction execution flow. At this time, the instruction prefetching operation for the third set of instructions is a normal instruction fetching operation. If the second set of instructions includes branch instructions, then the instruction prefetching operation for the branch instructions in the second set of instructions is a branch instruction fetching operation. At this time, when the instructions stored in the first sub-region (i.e., the second set of instructions) include branch instructions (e.g., the second branch instruction), the instructions fetched in the normal instruction fetching operation are stored in the second or third sub-region. Correspondingly, the instructions fetched in the branch instruction fetching operation for the second branch instruction are stored in the third or second sub-region.

[0095] In the above description, the number of normal instruction fetch operations can be 2, and the number of branch instruction fetch operations can be 1. It should be noted that this disclosure is not limited to this; depending on the size of the instruction temporary storage area, the branch instruction fetch operation can also be performed multiple times.

[0096] For example, in some embodiments, the instruction fetching method further includes: in response to an instruction execution result indicating that no jump is required, executing the instruction following the first branch instruction, and setting all unexecuted instructions in the first sub-region as invalid instructions.

[0097] For example, if the execution result of the first branch instruction is "not-taken," then the remaining unexecuted instructions in the second sub-region will continue to be executed. Simultaneously, all instructions prefetched for the first branch instruction will be invalidated; for example, all instructions prefetched for the first branch instruction in the first sub-region will be invalidated. In this case, the program counter (PC) of the thread bundle will not jump. If there are other branch instructions subsequently, they will continue to be prefetched, and the prefetched instructions can still be stored in the first sub-region, and so on. For example, if the first group of instructions includes a next branch instruction different from the first branch instruction, and it is determined that the execution result of the first branch instruction is "not-taken," then a branch fetch operation can be performed for that next branch instruction, and the fetched instructions can be stored in the first sub-region.

[0098] For example, in embodiments of this disclosure, corresponding instruction storage spaces can be set up for multiple branch instructions in the instruction temporary storage area to meet different needs, further improve the IPC of the GPGPU, and reduce the idle time of the thread bundle. For example, in some embodiments, the instruction temporary storage area also includes a fourth sub-region, and the instruction fetching method further includes: pre-parsing the first group of instructions to determine the third branch instruction, wherein the first group of instructions also includes the third branch instruction; in response to the fourth sub-region being empty or storing invalid instructions, fetching instructions from the target address of the third branch instruction to obtain the sixth group of instructions; and storing the sixth group of instructions in the fourth sub-region.

[0099] In the above description, taking the instruction temporary storage area as an example, which includes a sub-region for storing instructions retrieved by a branch fetch operation, the number of branch fetch operations is 1. However, this disclosure is not limited to this. In the embodiments of this disclosure, multiple branch fetch operations can be performed for a branch instruction. For example, in some embodiments, the instruction temporary storage area may include two sub-regions, which are used to store instructions retrieved by a branch fetch operation performed for a branch instruction. In this case, two branch fetch operations can be performed for each branch instruction.

[0100] Figure 4 A schematic flowchart illustrating the storage of instructions in a temporary instruction storage area provided for at least one embodiment of this disclosure.

[0101] like Figure 4 As shown in ①, a normal instruction fetch operation is performed (i.e. Figure 4 The first normal instruction fetch operation in memory (e.g., fetching the first set of instructions and storing it in memory cell lines L2-L3). Figure 4 As shown in ②, in response to the fact that all memory cell lines L4 to L5 are empty or all store invalid instructions, the next normal instruction fetch operation can be executed (i.e., Figure 4The second normal instruction fetch operation (e.g., fetching the fourth instruction set and storing the first instruction set in memory locations L2-L3). For example, during the second normal instruction fetch operation, pre-parsing and instruction execution operations can be performed: pre-parsing the first instruction set and executing the instructions within it. If it's determined that the first instruction set does not include branch instructions, then after executing all instructions in the first set, execution of the fourth instruction set can continue. For example, after storing the first instruction set in memory locations L2-L3 and the fourth instruction set in memory locations L4-L5, the instruction fetch operation can be aborted because there is no free storage space in the instruction temporary storage area to store the instructions fetched in the next normal instruction fetch operation. For example, as... Figure 4 As shown in ③, the first group of instructions and the fourth group of instructions can be pre-parsed sequentially. When the pre-parsed instructions of the first group and / or the fourth group of instructions determine that the first group and / or the fourth group of instructions includes a branch instruction, for example, the first group of instructions includes a first branch instruction, then a branch fetch operation can be performed on the first branch instruction (i.e., ... Figure 4 The first branch fetch operation in the memory (e.g., fetching the second set of instructions and storing it in memory cell lines L0 to L1). Figure 4 As shown in ④, if the execution result of the first branch instruction is "taken", then the second group of instructions in memory cell lines L0 to L1 will begin execution, and all instructions in memory cell lines L2 to L5 will be set as invalid instructions. Figure 4 As shown in ⑤, after jumping to execute the second group of instructions in memory cell line L0~L1, the next normal instruction fetch operation can continue. Figure 4 The third normal instruction fetch operation (as shown) involves, for example, fetching the third set of instructions and storing it in memory cell lines L2-L3. At this time, memory cell lines L4-L5 can store the instructions fetched during the branch instruction fetch operation. For example... Figure 4 As shown in ⑥, after jumping to execute the second group of instructions in memory cell line L0~L1, after pre-parsing the second group of instructions and / or the third group of instructions and determining that the second group of instructions and / or the third group of instructions includes a branch instruction, for example, the second group of instructions includes a second branch instruction, then a branch fetch operation can be performed on the second branch instruction (i.e., Figure 4 The second branch fetch operation in the memory (e.g., fetching the fifth instruction group and storing it in memory cell lines L4-L5). Figure 4 As shown in ⑦, if the execution result of the second branch instruction is "taken", then the fifth group of instructions in memory cell lines L4 to L5 will begin execution, and all instructions in memory cell lines L0 to L3 will be set as invalid instructions. Figure 4As shown in ⑧, after jumping to execute the fifth group of instructions in memory cell line L4-L5, the next normal instruction fetch operation can continue. Figure 4 The fourth normal instruction fetch operation shown in the diagram is used to store the fetched instruction in memory cell lines L2 to L3. At this time, memory cell lines L0 to L1 can store the instructions fetched by the branch instruction fetch operation, and so on.

[0102] It should be noted that if the instruction temporary storage area contains no instructions or all stored instructions are invalid when fetching instructions, the operation of fetching that instruction is called an instruction fetch operation; if the instruction temporary storage area contains at least one valid unexecuted instruction when fetching instructions, the operation of fetching that instruction is called an instruction prefetch operation; in addition, branch instruction fetching operations are usually also instruction prefetch operations. Figure 4 As shown, the first normal instruction fetch operation is an instruction fetch operation, while the second, third, and fourth normal instruction fetch operations are all instruction pre-fetch operations. The first branch instruction fetch operation and the second branch instruction fetch operation are both instruction pre-fetch operations for branch.

[0103] Figure 5 This is a schematic diagram illustrating the jump of the instruction read pointer in the instruction temporary storage area during instruction execution, provided for at least one embodiment of the present disclosure.

[0104] Normally, the value of the instruction read pointer rd_ptr increments sequentially. The instruction read pointer rd_ptr follows a wraparound mechanism; that is, when the value of the instruction read pointer rd_ptr reaches its maximum value, its value becomes 0, meaning it starts from the beginning again. If a branch instruction of the type "taken" occurs, the instruction read pointer rd_ptr will jump to the first memory location of memory location line L0 or the first memory location of memory location line L4.

[0105] like Figure 5 As shown, storage cell row L2 includes storage cells S0 to S3, storage cell row L3 includes storage cells S4 to S7, storage cell row L3 includes storage cells S8 to S11, storage cell row L4 includes storage cells S12 to S15, storage cell row L0 includes storage cells S16 to S19, and storage cell row L2 includes storage cells S20 to S23.

[0106] When all memory rows L2 through L5 contain instructions, the thread can begin execution from the first instruction stored in memory row L2. This first instruction is stored in memory cell S0 of memory row L2, and the instruction read pointer rd_ptr points to memory cell S0. After executing the instructions stored in memory cell S0, the instructions stored in memory cell S1 are executed, and the instruction read pointer rd_ptr points to memory cell S1, and so on, until the instruction stored in memory cell S15 is executed. The next instruction after the instruction stored in memory cell S15 is stored in memory cell S0. After executing the instructions stored in memory cell S15, if it is determined that the instructions stored in memory rows L2 through L5 do not include branch instructions, or if the execution result of a branch instruction in memory rows L2 through L5 is "not taken," then the program counter (PC) does not jump. The instructions stored in memory cell S0 are then executed, and the instruction read pointer rd_ptr points to memory cell S0, and this process continues.

[0107] like Figure 5 As shown, when the instructions stored in storage cell lines L2 to L3 include branch instructions, for example, if storage cell S5 stores a branch instruction, when the execution of the branch instruction stored in storage cell S5 is reached, if the instruction execution result of the branch instruction stored in storage cell S5 is "taken", then the instruction read pointer rd_ptr jumps to storage cell S16 and begins to execute the instruction stored in storage cell S16. At this time, normal instruction fetching operations can continue, and the fetched instruction is stored in storage cell lines L2 to L3. That is, the next instruction after the instruction stored in storage cell S23 is stored in storage cell S0.

[0108] like Figure 5 As shown, when the instructions stored in storage cell lines L4 to L5 include branch instructions, for example, if storage cell S12 stores a branch instruction, when the execution of the branch instruction stored in storage cell S12 is reached, if the instruction execution result of the branch instruction stored in storage cell S12 is "taken", then the instruction read pointer rd_ptr jumps to storage cell S16 and begins to execute the instruction stored in storage cell S16. At this time, normal instruction fetching operations can continue to be performed, and the fetched instruction is stored in storage cell lines L2 to L3. That is, the next instruction after the instruction stored in storage cell S23 is stored in storage cell S0.

[0109] After the instruction read pointer rd_ptr jumps to memory location S16, if it is determined that the instructions stored in memory locations L0 to L1 do not include branch instructions, or if it is determined that the instruction execution result of the branch instructions stored in memory locations L0 to L1 is "not-taken", then the PC does not jump. At this time, after the instructions stored in memory location S23 are executed, the instructions stored in memory location S0 are executed. That is, the instruction read pointer rd_ptr jumps to memory location S0 and begins to execute the instructions stored in memory location S0 until the instructions stored in memory location S7 are executed. Then the instructions stored in memory location S16 are executed. At this time, the instruction read pointer rd_ptr jumps to memory location S0, and so on.

[0110] After the instruction read pointer rd_ptr jumps to memory unit S16, if it is determined that the instructions stored in memory unit lines L0 to L1 include branch instructions, then a branch instruction fetch operation is performed for the branch instruction, and the fetched instruction is stored in memory unit lines L4 to L5. For example, if memory unit S20 stores branch instructions, when the execution of the branch instruction stored in memory unit S20 is reached, if the instruction execution result of the branch instruction stored in memory unit S20 is "taken", then the instruction read pointer rd_ptr jumps to memory unit S8, and the instruction stored in memory unit S8 begins to be executed. At this time, normal instruction fetch operation can continue, and the fetched instruction is stored in memory unit lines L2 to L3.

[0111] Therefore, it can be concluded that in Figure 4 and Figure 5 In the example shown, instructions fetched during a branch fetch operation can only be stored in the first sub-region (store cell lines L0 to L1) and the third sub-region (store cell lines L4 to L5). The second sub-region (store cell lines L2 to L3) is only used to store instructions fetched during a normal fetch operation.

[0112] In the embodiments of this disclosure, by controlling the read pointer of the instruction temporary storage area, the memory cell lines L2 to L3 can also store instructions to be fetched for branch fetch operations, thus enabling more flexible use of the resources of the entire instruction temporary storage area.

[0113] Figure 6 A schematic flowchart illustrating the storage of instructions in a temporary instruction storage area provided for at least one embodiment of this disclosure.

[0114] Figure 6 ①~⑦ and Figure 4 The operation processes ① to ⑦ are the same, and the repeated parts will not be repeated. Figure 6 and Figure 4 The difference is that, in Figure 6In step ⑧, after jumping to execute the fifth group of instructions in memory cell line L4-L5, the next normal instruction fetch operation can continue. Figure 4 The fourth normal instruction fetch operation shown in the diagram is used to store the fetched instruction in memory cell lines L0 to L1. At this time, memory cell lines L2 to L3 can store the instructions fetched by the branch instruction fetch operation, and so on.

[0115] exist Figure 6 In the example shown, the first sub-region (memory cell rows L0 to L1) to the third sub-region (memory cell rows L4 to L5) can all be used to store instructions retrieved during normal instruction fetch operations, or they can be used to store instructions retrieved during branch instruction fetch operations.

[0116] The instruction fetching method provided in this disclosure adds a small amount of storage space to the instruction temporary storage area of ​​the thread bundle, pre-fetching multiple instructions from the target address of branch instructions that have not yet been executed and storing them in the instruction temporary storage area. When the branch instruction is "taken", the PC jumps, and the instruction at the target address of the branch instruction can be immediately read from the instruction temporary storage area for execution without stopping the thread bundle. This can reduce the time overhead of PC jump execution caused by branch instructions to a certain extent, thereby improving the IPC of the GPGPU to a certain extent.

[0117] Meanwhile, when the instructions stored in the instruction temporary storage area include branch instructions, the normal instruction fetching operation of the thread bundle is not interrupted. When the branch instruction is "not-taken", the instructions after the branch instruction can continue to be executed. In this way, there are enough instructions in the instruction temporary storage area for the subsequent execution units to execute. To a certain extent, this can also reduce the idle time of the subsequent execution units due to the lack of instructions available for execution in the instruction temporary storage area, thereby improving the IPC of the GPGPU to a certain extent.

[0118] Furthermore, the instruction fetching method provided in the embodiments of this disclosure can also statically control whether the current thread bundle supports instruction prefetching for branch instructions by means of register configuration. That is, in the hardware implementation process, a switch register can be added to control whether the thread bundle needs to support the prefetching of target addresses for unexecuted branch instructions.

[0119] The instruction fetching method provided in the embodiments of this disclosure is mainly for direct jump branch instructions, that is, the first branch instructions to the third branch instructions mentioned above are all direct jump branch instructions.

[0120] Figure 7 This is a schematic diagram of a finger-fetching device provided for at least one embodiment of the present disclosure.

[0121] At least one embodiment of this disclosure also provides an instruction fetching device, which can be used to fetch instructions for a thread bundle, the thread bundle corresponding to an instruction temporary storage area, the instruction temporary storage area including a first sub-region. For example, as Figure 7 As shown, the instruction fetching device 700 includes an instruction fetching unit 701 and a branch instruction determination unit 702.

[0122] Instruction fetch unit 701 is configured to fetch the first set of instructions.

[0123] The branch instruction determination unit 702 is configured to pre-parse a first group of instructions to determine a first branch instruction, for example, the first group of instructions includes a first branch instruction.

[0124] The instruction fetch unit 701 is also configured to fetch instructions from the target address of the first branch instruction in response to the first sub-region being empty or containing invalid instructions, so as to fetch a second set of instructions; and store the second set of instructions into the first sub-region.

[0125] Instruction fetch unit 701 is used to execute Figure 2 Steps S10, S30, and S40 in the instruction fetch method shown are executed by the branch instruction determination unit 702. Figure 2 Step S20 in the finger fetching method shown.

[0126] For example, in some embodiments, the instruction temporary storage area further includes a second sub-region. When the instruction fetch unit 701 performs the operation of fetching the first set of instructions, it includes performing the following operations: in response to the second sub-region being empty or storing invalid instructions, fetching the first set of instructions. The instruction fetch unit 701 is also configured to store the first set of instructions into the second sub-region.

[0127] For example, in some embodiments, the instruction temporary storage area further includes a third sub-region, and the instruction fetch unit 701 is further configured to: in response to the third sub-region being empty or storing invalid instructions, fetch a fourth set of instructions, wherein the addresses of the instructions in the fourth set of instructions and the addresses of the instructions in the first set of instructions are contiguous; and store the fourth set of instructions in the third sub-region.

[0128] For example, the number of instructions in the first group of instructions is the same as the number of instructions in the fourth group of instructions.

[0129] For example, in some embodiments, the instruction temporary storage area further includes a second sub-region and a third sub-region, and the first set of instructions is stored in the second sub-region or the third sub-region. The instruction fetching device 700 also includes an instruction execution unit, which is configured to: execute a first branch instruction; determine the instruction execution result obtained by executing the first branch instruction; and, in response to an instruction execution result indicating that a jump is required, jump to execute the second set of instructions stored in the first sub-region.

[0130] For example, in some embodiments, the instruction fetch unit 701 is further configured to: after jumping to execute the second set of instructions stored in the first sub-region, fetch a third set of instructions, wherein the addresses of the instructions in the second set of instructions and the addresses of the instructions in the third set of instructions are contiguous; and store the third set of instructions in the second sub-region or the third sub-region.

[0131] For example, in some embodiments, the instruction fetch unit 701 is further configured to: after storing the third set of instructions to the second sub-region or the third sub-region, in response to the second set of instructions not including branch instructions and the first sub-region storing at least one valid unexecuted instruction, suspend the instruction fetch operation.

[0132] For example, in some embodiments, the branch instruction determination unit 702 is further configured to: after jumping to execute the second set of instructions stored in the first sub-region, pre-parse the second set of instructions to determine the second branch instruction, wherein the second set of instructions includes the second branch instruction. The instruction fetch unit 701 is further configured to: fetch instructions from the target address of the second branch instruction to obtain the fifth set of instructions; and store the fifth set of instructions in the second sub-region or the third sub-region.

[0133] For example, in some embodiments, the instruction execution unit is further configured to: after jumping to execute the second set of instructions stored in the first sub-region, set all unexecuted instructions in the second and third sub-regions as invalid instructions.

[0134] For example, in some embodiments, the branch instruction determination unit 702 is further configured to: execute instructions following the first branch instruction in response to an instruction execution result indicating that a jump is not required. The instruction execution unit is further configured to: set all unexecuted instructions in the first sub-region as invalid instructions in response to an instruction execution result indicating that a jump is not required.

[0135] For example, when the branch instruction determination unit 702 performs the operation of pre-parsing the first group of instructions to determine the first branch instruction, it includes performing the following operations: pre-parsing all instructions in the first group of instructions; determining that the first group of instructions includes at least one branch instruction, and selecting the branch instruction that is executed first in the execution order from the at least one branch instruction as the first branch instruction.

[0136] For example, in some embodiments, the instruction temporary storage area further includes a fourth sub-region, and the branch instruction determination unit 702 is further configured to: pre-parse the first group of instructions to determine the third branch instruction, wherein the first group of instructions further includes the third branch instruction. The instruction fetch unit 701 is further configured to: in response to the fourth sub-region being empty or storing an invalid instruction, fetch instructions from the target address of the third branch instruction to obtain a sixth group of instructions; and store the sixth group of instructions in the fourth sub-region.

[0137] At least one embodiment of this disclosure also provides an instruction fetching device for fetching instructions for a thread bundle. Figure 8 This is a schematic block diagram of an instruction fetching device provided for at least one embodiment of the present disclosure.

[0138] For example, such as Figure 8 As shown, the instruction fetching device 80 may include a memory 805 and a processor 810. The memory 805 is used to non-temporarily store computer-executable instructions suitable for execution by the processor 810; the processor 810 is used to execute the computer-executable instructions, which, when executed by the processor 810, cause the processor 810 to perform one or more steps of the instruction fetching method according to any embodiment of this disclosure. For specific implementations and related explanations of the various steps of the instruction fetching method, please refer to the embodiments of the instruction fetching method described above, and will not be repeated here.

[0139] It should be noted that Figure 8 The components of the finger fetching device 80 shown are merely exemplary and not limiting. The finger fetching device 80 may have other components depending on the actual application requirements.

[0140] For example, the processor 810 and the memory 805 can communicate with each other directly or indirectly.

[0141] For example, the processor 810 and memory 805 can communicate via a network connection. The network can include a wireless network, a wired network, and / or any combination of wireless and wired networks; this disclosure does not limit the type and function of the network. As another example, the processor 810 and memory 805 can also communicate via a bus connection. The bus can be a Peripheral Component Interconnect Standard (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc.

[0142] For example, the processor 810 and memory 805 can be located on the server side (or in the cloud) or on the client side (e.g., mobile devices such as mobile phones).

[0143] For example, processor 810 can be a central processing unit (CPU), tensor processor (TPU), or graphics processing unit (GPU) with data processing and / or instruction execution capabilities, and can control other components in instruction fetch device 80 to perform desired functions. The central processing unit (CPU) can be an x86 or ARM architecture, etc.

[0144] For example, memory 805 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer-executable instructions may be stored on the computer-readable storage medium, and processor 810 may execute these computer-executable instructions to implement various functions of instruction fetching device 80. Memory 805 may also store various application programs and various data, as well as various data used and / or generated by the application programs.

[0145] It should be noted that the finger-grabbing device 80 can achieve similar technical effects to the aforementioned finger-grabbing method, and the repetitive parts will not be described again.

[0146] At least one embodiment of this disclosure also provides a computer-readable storage medium. Figure 9 This is a schematic diagram of a computer-readable storage medium provided for at least one embodiment of the present disclosure.

[0147] For example, such as Figure 9 As shown, one or more computer-executable instructions 1001 may be stored non-transitory on the computer-readable storage medium 1000.

[0148] For example, when the computer-executable instructions 1001 are executed by a computer, one or more steps of the instruction fetching method according to any embodiment of this disclosure can be performed. The computer-readable storage medium 1000 can achieve similar technical effects to the aforementioned instruction fetching method, and the details will not be repeated.

[0149] For example, the computer-readable storage medium 1000 can be applied to the instruction fetching device 80 described above, for example, it can be the memory 805 in the instruction fetching device 80.

[0150] For example, the computer-readable storage medium 1000 can be a non-transitory computer-readable storage medium.

[0151] For example, the description of the computer-readable storage medium 1000 can be found in the embodiment of the instruction fetching device 80. The details of the memory 805 will not be repeated here.

[0152] The following points should be noted regarding this disclosure:

[0153] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0154] (2) For clarity, the thickness and dimensions of layers or structures are enlarged in the accompanying drawings used to describe embodiments of the invention. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0155] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0156] The above description is only a specific embodiment of this disclosure, but the protection scope of this disclosure is not limited thereto. The protection scope of this disclosure should be determined by the protection scope of the claims.

Claims

1. An instruction fetching method for fetching instructions for a thread bundle, wherein, The thread bundle corresponds to a temporary instruction storage area, which includes a first sub-region and a third sub-region. The instruction fetching method includes: Obtain the first set of instructions; The first group of instructions is pre-parsed to determine the first branch instruction, wherein the first group of instructions includes the first branch instruction; In response to the first sub-region being empty or containing invalid instructions, an instruction is fetched from the target address of the first branch instruction to obtain a second set of instructions and store the second set of instructions into the first sub-region. In response to the third sub-region being empty or containing invalid instructions, a fourth set of instructions is obtained and stored in the third sub-region, wherein the addresses of the instructions in the fourth set of instructions and the addresses of the instructions in the first set of instructions are consecutive.

2. The finger-fetching method according to claim 1, wherein, The temporary instruction storage area also includes a second sub-area, where the first group of instructions is stored in either the second or the third sub-area. The instruction fetching method further includes: Determine the instruction execution result obtained by executing the first branch instruction; In response to the instruction execution result indicating that a jump is required, the jump is executed to execute the second set of instructions stored in the first sub-region.

3. The finger-fetching method according to claim 2 further includes: After jumping to execute the second set of instructions stored in the first sub-region, the third set of instructions is obtained, wherein the addresses of the instructions in the second set of instructions and the addresses of the instructions in the third set of instructions are consecutive; Store the third set of instructions to the second sub-region or the third sub-region.

4. The finger-fetching method according to claim 3 further includes: After storing the third set of instructions to the second sub-region or the third sub-region, in response to the second set of instructions not including branch instructions and the first sub-region storing at least one valid unexecuted instruction, the instruction fetch operation is aborted.

5. The finger-fetching method according to claim 2 further includes: After jumping to execute the second set of instructions stored in the first sub-region, the second set of instructions is pre-parsed to determine the second branch instruction, wherein the second set of instructions includes the second branch instruction; Fetch instructions from the target address of the second branch instruction to obtain the fifth set of instructions; Store the fifth set of instructions to the second sub-region or the third sub-region.

6. The finger fetching method according to claim 2 further includes: After jumping to execute the second set of instructions stored in the first sub-region, all unexecuted instructions in the second and third sub-regions are set to invalid instructions.

7. The finger-fetching method according to claim 2 further includes: In response to the instruction execution result indicating that no jump is required, the instructions following the first branch instruction are executed, and all unexecuted instructions in the first sub-region are set as invalid instructions.

8. The finger fetching method according to claim 1, wherein, The temporary instruction storage area also includes a second sub-area. Retrieving the first set of instructions includes: in response to the second sub-region being empty or containing invalid instructions, retrieving the first set of instructions. The instruction fetching method further includes: Store the first set of instructions in the second sub-region.

9. The finger-fetching method according to claim 1, wherein, The number of instructions in the first group of instructions is the same as the number of instructions in the fourth group of instructions.

10. The finger-fetching method according to any one of claims 1 to 9, wherein, Pre-parse the first group of instructions to determine that the first branch instructions include: Pre-parse all instructions in the first group of instructions; The first group of instructions is determined to include at least one branch instruction, and the branch instruction that is executed first in the execution order among the at least one branch instruction is taken as the first branch instruction.

11. The finger-fetching method according to any one of claims 1 to 9, wherein, The temporary instruction storage area also includes a fourth sub-area. The instruction fetching method further includes: The first group of instructions is pre-parsed to determine the third branch instruction, wherein the first group of instructions further includes the third branch instruction; In response to the fourth sub-region being empty or containing an invalid instruction, an instruction fetch is performed from the target address of the third branch instruction to obtain the sixth group of instructions; Store the sixth set of instructions in the fourth sub-region.

12. An instruction fetching device for fetching instructions for a thread bundle, wherein, The thread bundle corresponds to a temporary instruction storage area, which includes a first sub-region and a third sub-region. The finger-fetching device includes: The instruction fetch unit is configured to fetch the first set of instructions; A branch instruction determination unit is configured to pre-parse the first group of instructions to determine a first branch instruction, wherein the first group of instructions includes the first branch instruction; The instruction fetching unit is further configured to fetch instructions from the target address of the first branch instruction in response to the first sub-region being empty or containing invalid instructions, so as to obtain a second set of instructions and store the second set of instructions into the first sub-region. The instruction fetch unit is further configured to fetch a fourth set of instructions and store the fourth set of instructions into the third sub-region in response to the third sub-region being empty or containing invalid instructions, wherein the addresses of the instructions in the fourth set of instructions and the addresses of the instructions in the first set of instructions are contiguous.

13. An instruction fetching device, comprising a memory and a processor, in, The memory stores computer-executable instructions suitable for execution by the processor, which, when executed by the processor, perform one or more steps of the instruction fetch method according to any one of claims 1 to 11.

14. A computer-readable storage medium that stores computer-executable instructions non-transitoryly. in, The computer-executable instructions are executed by a computer at runtime, performing one or more steps of the instruction fetching method according to any one of claims 1 to 11.

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