A data processing method, device, apparatus, and readable storage medium

Abstract

The application discloses a data processing method, device and equipment and a readable storage medium. The method comprises the following steps: receiving a first memory allocation request sent by a first process, and obtaining a memory domain set according to the first memory allocation request. Each memory domain in the memory domain set is composed of one or more memory blocks. A to-be-allocated memory domain corresponding to the first process is determined according to the memory domain set, a first target memory block corresponding to the first process is determined in the one or more memory blocks included in the to-be-allocated memory domain according to the first memory allocation request, and the first target memory block is allocated to the first process. The to-be-allocated memory domain in the memory domain set is updated to an updated memory domain according to the first target memory block. The memory domain set containing the updated memory domain is used to allocate a second target memory block to a second process when a second memory allocation request of the second process is received. By using the application, the memory allocation efficiency of the system can be improved, and the resource utilization rate is improved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data processing method, apparatus, device, and readable storage medium. Background Technology

[0002] In operating systems (such as Linux), memory management and allocation are crucial factors affecting system stability. The main function of memory management is to organize free memory blocks in the system and respond to application memory allocation and reclamation requests.

[0003] Currently, the buddy system management algorithm is the primary memory management method, designed for small-scale single-core operating systems. Based on this algorithm, all memory requests must be executed serially. However, because it is primarily designed for small-scale single-core operating systems, in multi-core operating systems, the buddy system management algorithm cannot respond to memory requests in a timely manner. If multiple processes issue memory requests, the buddy system management algorithm will cause severe memory allocation latency, significantly impacting memory allocation efficiency. Summary of the Invention

[0004] This application provides a data processing method, apparatus, device, and readable storage medium, which can improve the memory allocation efficiency of the system and enhance resource utilization.

[0005] One embodiment of this application provides a data processing method, including: Receive the first memory allocation request sent by the first process, and obtain a set of memory domains according to the first memory allocation request; each memory domain in the set of memory domains consists of one or more memory blocks; The memory domain to be allocated for the first process is determined based on the set of memory domains. Based on the first memory allocation request, the first target memory block corresponding to the first process is determined from one or more memory blocks included in the memory domain to be allocated, and the first target memory block is allocated to the first process. Based on the first target memory block, the memory domain to be allocated in the memory domain set is updated to the updated memory domain; the memory domain set containing the updated memory domain is used to allocate the second target memory block for the second process when a second memory allocation request from the second process is received.

[0006] One embodiment of this application provides a data processing apparatus, including: The request processing module is used to receive the first memory allocation request sent by the first process and obtain a set of memory domains according to the first memory allocation request; each memory domain in the set of memory domains consists of one or more memory blocks; The memory domain determination module is used to determine the memory domain to be allocated for the first process based on the set of memory domains. The memory block allocation module is used to determine the first target memory block corresponding to the first process from one or more memory blocks included in the memory domain to be allocated, based on the first memory allocation request, and allocate the first target memory block to the first process; The memory domain update module is used to update the memory domain to be allocated in the memory domain set to the updated memory domain according to the first target memory block; the memory domain set containing the updated memory domain is used to allocate the second target memory block for the second process when the second memory allocation request of the second process is received.

[0007] In one embodiment, the memory domain determination module includes: The first domain detection unit is used to detect memory domains in the memory domain set; The first domain acquisition unit is used to acquire the memory domain to be allocated corresponding to the first process from the allocable memory domain if an allocable memory domain is detected in the memory domain set, and switch the memory domain to be allocated from the idle state to the locked state; each memory block in the allocable memory domain is in the idle state; there are no memory blocks in the locked memory domain that are in the idle state.

[0008] In one embodiment, the memory domain determination module includes: The second domain detection unit is used to detect memory domains in the memory domain set; The second domain acquisition unit is used to set the first process to a waiting state if no allocatable memory domain is detected in the memory domain set, and to switch the first process from the waiting state to the allocation state when an allocatable memory domain reappears in the memory domain set. The unit then acquires the memory domain to be allocated corresponding to the first process in the allocation state from the allocatable memory domains and switches the memory domain to be allocated from the idle state to the locked state. Each memory block in the allocatable memory domain is in an idle state. There are no memory blocks in the locked memory domain that are in an idle state.

[0009] In one embodiment, the memory domain update module includes: The block determination unit is used to identify memory blocks in the memory domain to be allocated, excluding the first target memory block, as the first remaining memory block. A domain composition unit is used to compose an updated memory domain based on the first remaining memory block; the updated memory domain in the memory domain set belongs to the allocatable memory domain.

[0010] In one embodiment, the memory domain update module includes: The domain partitioning unit is used to partition the memory domain to be allocated according to the first target memory block, so as to obtain the first partitioned memory domain and the second partitioned memory domain. The update domain determination unit is used to determine the first partitioned memory domain and the second partitioned memory domain as the update memory domain; the update memory domain in the memory domain set belongs to the allocatable memory domain.

[0011] In one embodiment, the domain partitioning unit includes: The sub-unit for determining the blocks to be partitioned is used to determine the memory blocks to be partitioned in the memory domain to be allocated based on the first target memory block; the number of blocks to be partitioned is greater than the number of blocks in the first target memory block; The difference block acquisition subunit is used to acquire the difference memory block between the memory block to be divided and the first target memory block; The partitioning domain is composed of sub-units, which are used to form a first partitioned memory domain based on the difference memory blocks and a second partitioned memory domain based on the second remaining memory blocks; the second remaining memory blocks refer to the memory blocks in the memory domain to be allocated, excluding the memory blocks to be partitioned.

[0012] In one embodiment, the memory domain determination module further includes: The domain number determination unit is used to obtain the remaining memory domains in the allocable memory domains excluding the memory domains to be allocated, and the number of domains in the remaining memory domains; The domain merging unit is used to merge the remaining memory domains when the number of domains exceeds a threshold, resulting in a merged memory domain; the merged memory domain in the memory domain set belongs to the allocatable memory domain.

[0013] In one embodiment, the data processing apparatus further includes: The status detection module is used to receive the memory release request for the first target memory block sent by the first process; The status detection module is also used to detect the storage status of the memory buffer based on the memory release request; The first memory block release module is used to add the first target memory block to the memory buffer if the storage state of the memory buffer is the first storage state. The first memory block release module is also used to release the first target memory block in the memory buffer to the memory domain set when the memory block release condition is met; The second memory block release module is used to adjust the storage capacity of the memory buffer according to the first target memory block if the storage state of the memory buffer is the second storage state, so as to obtain the adjusted memory buffer. The second memory block release module is also used to add the first target memory block to the adjustment memory buffer, and release the first target memory block in the adjustment memory buffer to the memory domain set when the memory block release condition is met.

[0014] In one embodiment, the state detection module includes: The process information acquisition unit is used to acquire historical memory release behavior information and virtual address space of the first process. The prediction quantity determination unit is used to determine the predicted memory release request quantity of the first process within the target time period based on historical memory release behavior information and virtual address space. The status detection unit is used to obtain the number of target blocks of the first target memory block and the number of predicted blocks corresponding to the predicted memory release request volume, and to detect the storage status of the memory buffer based on the number of target blocks and the number of predicted blocks.

[0015] In one embodiment, the state detection unit includes: The operation subunit is used to perform calculations on the number of target blocks and the number of predicted blocks to obtain the total number; The capacity acquisition subunit is used to obtain the remaining storage capacity of the memory buffer; The state determination subunit is used to determine the storage state of the memory buffer as the first storage state if the remaining storage capacity of the memory buffer is greater than the total number. The state determination subunit is also used to determine the storage state of the memory buffer as the second storage state if the remaining storage capacity of the memory buffer is less than the total number.

[0016] In one embodiment, the first memory block release module includes: The existing memory block acquisition unit is used to acquire the existing memory blocks included in the memory buffer when the memory block release time is reached; the existing memory blocks include the first target memory block; The pre-determining unit is used to obtain the allocatable memory domains from the memory domain set when the memory block is released, and to use the allocatable memory domains as memory domains to be added; each memory block in the allocatable memory domain is in an idle state. The block addition unit is used to release an existing memory block to the memory domain to be added.

[0017] In one embodiment, the second memory block release module includes: The quantity determination unit is used to obtain the predicted memory release request quantity of the first process within the target time period, and the predicted number of blocks corresponding to the predicted memory release request quantity; The quantity determination unit is also used to obtain the target block quantity of the first target memory block and determine the total quantity corresponding to the target block quantity and the predicted block quantity; The capacity adjustment unit is used to obtain the remaining storage capacity corresponding to the memory buffer, and adjust the storage capacity of the memory buffer according to the remaining storage capacity and the total quantity to obtain the adjusted memory buffer; the updated remaining storage capacity of the adjusted memory buffer is greater than the total quantity.

[0018] One embodiment of this application provides a computer device, including: a processor and a memory; The memory stores a computer program, which, when executed by a processor, causes the processor to perform the methods described in the embodiments of this application.

[0019] One aspect of this application provides a computer-readable storage medium storing a computer program, which includes program instructions. When executed by a processor, the program instructions perform the methods described in this application.

[0020] One aspect of this application provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method provided in one aspect of the embodiments of this application.

[0021] In this embodiment, a set of memory domains (comprising one or more memory domains, each consisting of one or more memory blocks) can be provided. When a concurrent memory allocation request from a process is received, one or more memory domains included in the set can concurrently respond to the process's memory allocation request. For example, when a first memory allocation request from a first process is received, the first process does not need to queue and wait for previous processes (such as processes that issued memory allocation requests before the first process) to complete their requests. Instead, it can directly and quickly determine the memory domain to be allocated for the first process based on multiple memory domains in the set, and allocate the first target memory block to the first process using that memory domain. It is understood that by grouping different memory blocks into different memory domains, memory fragmentation can be reduced, thereby improving memory resource utilization. At the same time, in multi-process concurrent memory request scenarios, memory allocation latency can be reduced, and memory request response efficiency can be improved. Furthermore, after allocating the first target memory block to the first process, the memory domain to be allocated can be updated in a timely manner based on the first target memory block. This means the memory domain to be allocated can be updated to the updated memory domain. This allows for dynamic updating and adjustment of the memory domain set in real time based on the memory block allocation status. This enables more accurate and timely allocation of memory blocks to subsequent processes based on their memory allocation requests (such as the second memory allocation request from the second process), further improving memory request response efficiency. In summary, this application can improve the system's memory allocation efficiency and enhance resource utilization. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a network architecture diagram provided in an embodiment of this application; Figure 2 This is a flowchart illustrating a data processing method provided in an embodiment of this application; Figure 3a This is a schematic diagram illustrating how a memory domain provides services in a high-concurrency scenario, as provided in an embodiment of this application. Figure 3b This is a schematic diagram illustrating how a memory domain provides services in a low-concurrency scenario, as provided in an embodiment of this application. Figure 4a This is a schematic diagram illustrating a scenario of splitting memory domains according to an embodiment of this application; Figure 4b This is a schematic diagram of a scenario of merging memory domains provided in an embodiment of this application; Figure 5 This is a flowchart illustrating a data processing method provided in an embodiment of this application; Figure 6 This is a system structure diagram provided in an embodiment of this application; Figure 7 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application; Figure 8 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] Please see Figure 1 , Figure 1 This is a network architecture diagram provided in an embodiment of this application. For example... Figure 1 As shown, this network architecture may include a service server 1000 and a terminal device cluster. The terminal device cluster may include one or more terminal devices; the number of terminal devices is not limited here. Figure 1As shown, multiple terminal devices may include terminal device 100a, terminal device 100b, terminal device 100c, ..., terminal device 100n; as Figure 1 As shown, terminal devices 100a, 100b, 100c, ..., 100n can each connect to the business server 1000 via a network, so that each terminal device can interact with the business server 1000 through the network connection.

[0026] Each terminal device can have a target application installed. When this target application runs on each terminal device, it can interact with the above-mentioned... Figure 1 The business servers 1000 shown interact with each other. The target application can include applications with the ability to display text, images, audio, and video data. For example, the application can be an entertainment application (such as a game or video application), used for users to upload and view data (such as watching videos); or a shopping application (such as an e-commerce application), used for users to upload and purchase items. Of course, the application can also be other applications with data display capabilities, which will not be listed here. It is understood that when a terminal device runs an application, the business server 1000 can provide services to it. When the application on the terminal device is started and running, its corresponding Central Processing Unit (CPU) will also run accordingly. The running CPU, after requesting memory, will provide the corresponding computing power services to the application on the terminal device.

[0027] Understandably, to improve the response efficiency of CPU memory allocation requests and enable each CPU to allocate memory promptly and efficiently, this application proposes a data processing method (i.e., a memory management method). This method can group idle memory blocks (which can be understood as unoccupied or unused blocks) into multiple different memory domains (i.e., a memory domain consists of one or more memory blocks), and these multiple different memory domains can form a memory domain set. When multiple CPUs run concurrently and issue memory allocation requests concurrently, a memory domain can be determined for each CPU using the memory domain set to allocate memory blocks. Compared to executing CPU memory allocation requests serially, this application can support concurrent responses to memory allocation requests from multiple CPUs, significantly reducing memory response latency and improving memory allocation efficiency. For details on the specific implementation of dividing memory domains into memory domain sets and allocating memory to different CPUs based on these sets, please refer to subsequent sections. Figure 2 The description in the corresponding embodiments.

[0028] This application embodiment can select one terminal device from multiple terminal devices as the target terminal device. This terminal device may include: smartphones, tablets, laptops, desktop computers, smartwatches, smart in-vehicle terminals, smart home appliances (such as smart TVs, smart speakers, etc.), smart voice interaction devices, and other smart terminals with multimedia data processing functions (e.g., video data playback functions, music data playback functions), but is not limited to these. For example, this application embodiment can... Figure 1 The terminal device 100a shown is the target terminal device. The target terminal device may integrate the aforementioned target application. At this time, the target terminal device can interact with the business server 1000 through the target application.

[0029] It is understood that the methods provided in this application embodiment can be executed by computer devices, including but not limited to terminal devices or business servers. The business server can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms.

[0030] The terminal equipment and the business server can be connected directly or indirectly through wired or wireless communication, and this application does not impose any restrictions on this.

[0031] Optionally, and understandably, the aforementioned computer devices (such as the aforementioned business server 1000, terminal device 100a, terminal device 100b, etc.) can be nodes in a distributed system. This distributed system can be a blockchain system, formed by connecting multiple nodes through network communication. The nodes can form a peer-to-peer (P2P) network, where the P2P protocol is an application layer protocol running on top of the Transmission Control Protocol (TCP). In this distributed system, any type of computer device, such as a business server or terminal device, can become a node in the blockchain system by joining this peer-to-peer network. For ease of understanding, the concept of blockchain is explained below: Blockchain is a new application model of computer technologies such as distributed data storage, peer-to-peer transmission, consensus mechanisms, and encryption algorithms. It is mainly used to organize data in chronological order and encrypt it into a ledger, making it tamper-proof and forgery-proof, while also enabling data verification, storage, and updating. When a computer device is a blockchain node, the immutability and anti-counterfeiting characteristics of the blockchain ensure that the data in this application (such as application operation-related data) is authentic and secure, thereby making the results obtained after data processing based on this data more reliable.

[0032] Furthermore, for ease of understanding, please refer to Figure 2 , Figure 2 This is a flowchart illustrating a data processing method provided in an embodiment of this application. The method can be implemented by a terminal device (e.g., the one described above). Figure 1 The execution can be performed by any terminal device in the terminal device cluster shown, such as terminal device 100a, or by a service server (as described above). Figure 1 The method can be executed by the business server 1000 in the corresponding embodiment, or it can be jointly executed by the terminal device and the business server. For ease of understanding, this embodiment will be described using the execution of the above-mentioned business server as an example. The data processing method may include at least the following steps S101-S103: Step S101: Receive the first memory allocation request sent by the first process, and obtain a set of memory domains according to the first memory allocation request; each memory domain in the set of memory domains consists of one or more memory blocks.

[0033] In this application, a process can refer to a single running activity of a program with independent functionality on a certain data set. Each process can request and own system resources (such as memory resources). Generally, one application corresponds to one process. For example, when an application installed on a terminal device is launched and run, a corresponding process is generated. This process can request system resources from the system, and the system allocates different memory spaces to each process during operation. It is understood that the first process in this application can refer to any process. For multi-core operating systems (multi-CPU operating systems), multiple processes can perform calculations in parallel on multiple CPUs. In this application, it can be understood that one process corresponds to one CPU (i.e., one process performs calculations on one CPU, and the CPU requests memory resources for its corresponding process).

[0034] Understandably, the memory allocation request issued by the first process can be referred to as the first memory allocation request. After receiving the first memory allocation request, the application server can obtain a set of memory domains. This set of memory domains can consist of one or more memory domains, and each memory domain consists of one or more memory blocks. The memory blocks that make up a memory domain can refer to memory blocks in a free state (unoccupied or unused) in the system. It should be understood that in an operating system, physical memory can be divided into blocks of a certain size (e.g., 4KB), and a 4KB block is the smallest unit of management, which can be called a page frame. Therefore, a memory block here can refer to a page frame, and a memory domain can be composed of one or more free page frames.

[0035] It is understood that the memory domain set in this application can be adjusted and updated in real time according to the concurrency of memory allocation requests from processes (that is, the memory domain set is adjusted and updated by adjusting memory domains). Therefore, the memory domain set at the moment when the first process issues the first memory allocation request can refer to the set dynamically updated and adjusted based on the concurrency of historical processes (that is, processes that issued memory allocation requests before the first process) (including high concurrency and low concurrency scenarios). For the specific implementation of dynamically adjusting memory domains, please refer to the following sections. Figure 2 The description in the corresponding embodiments.

[0036] Step S102: Determine the memory domain to be allocated corresponding to the first process based on the memory domain set; determine the first target memory block corresponding to the first process from one or more memory blocks included in the memory domain to be allocated based on the first memory allocation request; and allocate the first target memory block to the first process.

[0037] In this application, upon obtaining a set of memory domains, the current set of memory domains can be detected, and the memory domain to be allocated for the first process can be determined based on the detection result. In one embodiment, the specific implementation of determining the memory domain to be allocated for the first process based on the set of memory domains can be as follows: the memory domains in the set of memory domains can be detected; if an allocable memory domain is detected in the set of memory domains, the memory domain to be allocated for the first process can be obtained from the allocable memory domain, and the memory domain to be allocated can be switched from an idle state to a locked state; wherein, each memory block in the allocable memory domain is in an idle state; there are no memory blocks in an idle state in the locked memory domain to be allocated.

[0038] It's understandable that when a CPU (which can correspond to a process) issues a memory allocation request, a memory domain can provide service to it. A memory domain that is providing service cannot provide service to other CPUs; this memory domain can be considered locked. Each memory block in a locked memory domain cannot be allocated to another CPU. The state of memory blocks that can be allocated to other CPUs can be called the idle state. Therefore, when memory blocks cannot be allocated to other CPUs, each memory block in that memory domain can be considered locked (i.e., there are no idle memory blocks that can be allocated to other CPUs). Conversely, when a memory domain is not providing service to any CPU but is waiting to provide service to a CPU, it can be called an allocatable memory domain. Each memory block in this waiting-to-be-provided memory domain can be allocated to any CPU that issues a memory allocation request; that is, each memory block in this memory domain is in an idle state.

[0039] It should be understood that when a first memory allocation request is received from the first process, if an allocatable memory domain is detected in the set of memory domains, then a memory domain can be directly obtained from these allocatable memory domains as the memory domain to be allocated for the first process. This memory domain to be allocated provides services to the first process. When the memory domain to be allocated is providing services to the first process, the state of the memory domain to be allocated can be switched from an idle state to a locked state.

[0040] In one feasible embodiment, the specific implementation of determining the memory domain to be allocated corresponding to the first process based on the memory domain set can also be as follows: the memory domains in the memory domain set can be detected; if no allocable memory domain is detected in the memory domain set, the first process can be set to a waiting state; when an allocable memory domain is detected to reappear in the memory domain set, the first process can be switched from the waiting state to the allocation state, the memory domain to be allocated corresponding to the first process in the allocation state can be obtained from the allocable memory domains, and the memory domain to be allocated can be switched from an idle state to a locked state; each memory block in the allocable memory domain is in an idle state; there are no memory blocks in the locked memory domain that are in an idle state.

[0041] It should be understood that when the first memory allocation request from the first process is received, if no allocatable memory domain is detected in the current memory domain set, it indicates that all existing memory domains are serving different CPUs, and no memory domain can serve the first process. In this case, the application server can set the first process to a waiting state, forcing it to wait. During the first process's waiting process, when a process (CPU) completes its memory request (which can be understood as the process having completed the allocation of memory blocks), the memory domain serving it will be released. The released memory domain can then provide corresponding services (returning to an idle state). This released memory domain can be understood as a newly reappearing allocatable memory domain in the memory domain set. At this point, the first process can obtain its own allocatable memory domain from the released memory domain without waiting, and this allocatable memory domain will serve the first process. When the allocatable memory domain serves the first process, its state can be switched from idle to locked.

[0042] Furthermore, it can be understood that after obtaining the memory domain to be allocated corresponding to the first process, the first target memory block corresponding to the first process can be obtained from one or more memory blocks included in the memory domain to be allocated, and the first target memory block can be allocated to the first process. It can be understood that when each process sends a memory allocation request, it can also send a block request amount for the memory block (which can be called the memory request amount or memory block request amount). The application server can then allocate memory to the process based on this memory block request amount. For example, the first memory allocation request of the first process can carry a memory block request amount of 8. Then the application server can obtain 8 memory blocks from the memory domain to be allocated, use them as the first target memory block, and allocate the first target memory block to the first process.

[0043] Specifically, the method by which the business server obtains the first target memory block from the memory blocks to be allocated can be random acquisition or acquisition according to the order of memory block identifiers (for example, acquisition in ascending order according to the memory block sequence number). Other methods are also possible for obtaining the process's target memory block within the memory domain, and this application will not impose any restrictions.

[0044] Step S103: Based on the first target memory block, update the memory domain to be allocated in the memory domain set to the updated memory domain; the memory domain set containing the updated memory domain is used to allocate the second target memory block for the second process when the second memory allocation request of the second process is received.

[0045] In this application, the memory domain to be allocated in the memory domain set can be updated to the updated memory domain based on the first target memory block.

[0046] Understandably, when a first memory allocation request is received from the first process, if an allocatable memory domain is detected in the memory domain set, a memory domain can be directly acquired from these allocatable memory domains as the first process's memory domain to be allocated. After acquiring the first target memory block in the memory domain to be allocated and allocating the first target memory block to the first process, the memory blocks in the memory domain to be allocated, excluding the first target memory block, can be considered as the first remaining memory block. Subsequently, an updated memory domain can be formed based on the first remaining memory block. The updated memory domain in the memory domain set belongs to the allocatable memory domains. Understandably, when the memory domain to be allocated is providing services to the first process, it is in a locked state. When the first process completes its memory request (i.e., allocates the first target memory block to the first process), it can release the memory domain to be allocated. In fact, after the first target memory block in the memory domain to be allocated is allocated to the first process, the remaining memory blocks in the memory domain to be allocated can form a new memory domain (called the updated memory domain). The release of the first integrated memory domain can be understood as the updated memory domain. After the updated memory domain is released, it is in an idle state. Each memory block in the updated memory domain is in an idle state. In other words, the updated memory domain is an allocatable memory domain.

[0047] Understandably, when the first memory allocation request from the first process is received, if no allocatable memory domain is detected in the current memory domain set, the application server can set the first process to a waiting state, forcing it to wait. During the first process's waiting period, when a historical process (CPU) completes its memory request (which can be understood as the process having completed the allocation of a memory block), the memory domain providing services to it will be released. This released memory domain can then provide the corresponding services (returning to an idle state). This released memory domain can then be understood as a newly reappearing allocatable memory domain in the memory domain set. At this point, the first process can obtain its own allocatable memory domain from the released memory domain without waiting. Subsequently, based on the first target memory block, the allocatable memory domain can be partitioned into a first partitioned memory domain and a second partitioned memory domain. The first and second partitioned memory domains can be identified as updated memory domains; among them, the updated memory domains in the memory domain set belong to the allocatable memory domains.

[0048] The specific implementation of dividing the memory domain to be allocated based on the first target memory block to obtain the first and second partitioned memory domains can be as follows: Based on the first target memory block, determine the memory blocks to be partitioned within the memory domain to be allocated; wherein the number of blocks to be partitioned is greater than the number of blocks in the first target memory block; subsequently, obtain the difference memory blocks between the memory blocks to be partitioned and the first target memory block; the first partitioned memory domain can be formed based on the difference memory blocks, and the second partitioned memory domain can be formed based on the second remaining memory blocks; wherein the second remaining memory blocks refer to the memory blocks in the memory domain to be allocated other than the memory blocks to be partitioned.

[0049] It should be understood that when the first memory allocation request from the first process is received, if no allocatable memory domain is detected in the current memory domain set, it can be assumed that the memory domain is serving different memory allocation requests. However, if another memory allocation request from the first process is received at this time, it can be considered a high-concurrency memory request scenario. To meet the system's concurrent requests, reduce request latency, and improve allocation efficiency, the memory domain can be split, that is, the memory domain can be fragmented. This allows multiple CPUs to be served by different memory domains simultaneously, achieving concurrency in memory request processing. When the system's concurrency demand decreases, due to the continuous splitting of memory domains, many memory domains may not be used. Therefore, to avoid resource fragmentation, the memory domains can be merged to achieve resource consolidation.

[0050] One specific method for merging memory domains is as follows: obtain the remaining memory domains in the allocatable memory domains excluding the memory domain to be allocated, and the number of domains in the remaining memory domains; when the number of domains is greater than the number threshold, merge the remaining memory domains to obtain the merged memory domain; the merged memory domain in the memory domain set belongs to the allocatable memory domains.

[0051] In other words, after determining the memory domain to be allocated for the first process, the number of memory domains in the current memory domain set that are in a free state can be obtained (that is, the number of remaining memory domains in the currently allocable memory domains, excluding the memory domain to be allocated). When this number of domains exceeds a threshold, the remaining memory domains can be merged. This threshold can be a manually defined value, such as 2, 3, 4, etc., which will not be listed here. It should be noted that the merging of remaining memory domains can be done by directly merging all remaining memory domains, or by selecting a portion of the remaining memory domains (such as two memory domains) for merging. This application does not restrict the merging method for memory domains.

[0052] It should be understood that after the memory domain to be allocated is updated to the updated memory domain, when a second memory allocation request is received from the second process, the memory domain to be allocated corresponding to the second process can be determined based on the memory domain set containing the updated memory domain. The second target memory block can then be obtained from the second process's memory domain to be allocated and allocated to the second process. The specific implementation process can be found in the description of allocating the first target memory block to the first process, and will not be repeated here. It should be noted that the second process's memory allocation request can be sent when the memory domain set has not been updated (i.e., when it does not contain the updated memory domain). In other words, after determining the memory domain to be allocated corresponding to the first process in the current memory domain set, but before the memory domain set has been updated, when a memory allocation request is received from the second process, the memory domain to be allocated for the second process can be determined from the current memory domain set.

[0053] In this embodiment, memory domains can be dynamically adjusted according to the concurrency requirements of processes. For example, under high concurrency memory requests, memory domains can be divided, thereby providing multiple memory domains to simultaneously respond to the memory request needs of multiple processes. For instance, when a first memory allocation request is received from a first process, the first process does not need to queue and wait for previous processes (such as processes that issued memory allocation requests before the first process) to complete their requests. Instead, it can directly and quickly determine the memory domain to be allocated for the first process based on multiple memory domains in the memory domain set, and allocate the first target memory block to the first process using that memory domain. This can reduce memory allocation latency and improve memory request response efficiency. Under low concurrency memory requests, memory domains can be merged and integrated, consolidating fragmented memory domains into a large resource pool to reduce fragmentation. In summary, this application can dynamically expand or merge memory domains according to the system's concurrency status. Under high concurrency, multiple memory domains can be provided to simultaneously respond to the memory allocation requests of multiple processes, reducing request response latency and improving memory allocation efficiency; under low concurrency, memory domains can be integrated to reduce fragmentation and improve resource utilization.

[0054] Furthermore, for a better understanding of the method of dynamically adjusting memory domains, please refer to [link to relevant documentation]. Figure 3a , Figure 3a This is a schematic diagram illustrating how a memory domain provides services in a high-concurrency scenario, as provided in an embodiment of this application. Figure 3a As shown, when the system generates high-concurrency memory requests, meeting system concurrency requirements becomes the primary focus. Memory can be dynamically divided into memory domain 0, memory domain 1, and memory domain 2. Memory domain 0 can consist of physical page frames (i.e., free memory blocks) 0 and 3; memory domain 1 can consist of physical page frames 1 and 5; and memory domain 2 can consist of physical page frames 2 and 4. In this case, multiple CPUs can be served simultaneously by different memory domains, for example... Figure 3a As shown, CPU0 can be served by memory domain 0, CPU1 can be served by memory domain 1, and CPU2 can be served by memory domain 2.

[0055] Currently, aggregation between memory domains is not possible, and cross-domain aggregation is not possible. It should be understood that when the system is under high concurrency and requests are being made, dynamic partitioning of memory domains can provide multiple memory domains to serve different CPUs simultaneously. This allows CPU requests to be processed concurrently, reduces memory response latency, and improves memory allocation efficiency.

[0056] Similarly, for a better understanding of the method of dynamically adjusting memory domains, please refer to [link to relevant documentation]. Figure 3b , Figure 3bThis is a schematic diagram illustrating how a memory domain provides services in a low-concurrency scenario, as provided in an embodiment of this application. Figure 3b As shown, when the system's concurrent memory requests decrease (e.g., as... Figure 3b As shown, among CPU0, CPU1, and CPU2, only CPU0 sends memory requests; CPU1 and CPU2 do not send memory allocation requests. In this case, reducing fragmentation is the primary focus, and there is no need to divide the memory into multiple domains. Multiple memory domains can be merged. For example, as... Figure 3b As shown, physical page frames 1 and 3 from memory domain 0, physical page frames 1 and 5 from memory domain 1, and physical page frames 2 and 4 from memory domain 2 can be merged and integrated to obtain a new memory domain (such as...). Figure 3b Memory domain 3 is shown.

[0057] In this context, memory domains can be aggregated, including cross-domain aggregation. This means that merging can consolidate page frames distributed across multiple memory domains into higher-order pages, reducing resource fragmentation and improving resource utilization.

[0058] To further understand the dynamic adjustment process of memory domains, please refer to [link / reference]. Figure 4a , Figure 4a This is a schematic diagram illustrating a scenario of splitting memory domains according to an embodiment of this application. For example... Figure 4a As shown, the process of splitting memory domains can be divided into three stages: concurrency detection, resource partitioning, and memory domain expansion. For ease of understanding, these three stages will be explained below.

[0059] like Figure 4a The concurrency detection phase shown can detect concurrent request issues in the system. For example, such as... Figure 4aThe CPU0 shown can correspond to process 0. The current memory domain set includes only memory domain 0 (i.e., the memory domain set consists of only one memory domain 0). This memory domain 0 can consist of all free memory blocks (all free page frames) in the current system. At this time, memory domain 0 is serving CPU0; that is, CPU0 is requesting memory domain 0 to allocate a memory block. Memory domain 0 cannot serve other CPUs at this time (i.e., memory domain 0 is not idle and is not an allocable memory domain). When CPU1 (which can correspond to process 1) issues a memory allocation request, because the only memory domain 0 is serving CPU0, the application server cannot allocate a memory block for it due to insufficient system resources. The application server can allocate a waiting space for CPU1, and CPU1 will be in a waiting state, waiting for the application server to allocate a memory block. It is understandable that when multiple CPUs (such as CPU0 and CPU1) concurrently issue memory requests, the memory domain cannot concurrently serve multiple CPUs, resulting in large request-response latency and severely impacting memory allocation efficiency. In order to reduce memory request response latency and improve memory allocation efficiency, this application embodiment can divide system resources (i.e., memory domains), that is, divide memory domains and expand the number of memory domains so that they can provide services to multiple CPUs concurrently.

[0060] like Figure 4a As shown, during the resource partitioning phase, after CPU0 completes its memory request (which can be understood as CPU0 having been allocated memory blocks), CPU0 releases memory domain 0. It's understood that each CPU's memory allocation request can carry the number of memory blocks requested (referred to as the memory block request quantity). When memory domain 0 provides services to CPU0, the application server can allocate corresponding memory blocks to CPU0 based on the memory block request quantity carried in CPU0's memory allocation request. In other words, the application server can obtain the corresponding memory blocks from memory domain 0 and allocate them to CPU0. Therefore, when CPU0 releases memory domain 0, the memory blocks included in memory domain 0 do not actually include those already allocated to CPU0. For clarity, the memory domain released by CPU0 can be referred to as memory domain 0'. Furthermore, after memory domain 0' is released, the application server can detect the existence of waiting space and can partition memory domain 0'.

[0061] The specific process of partitioning memory domain 0' can be as follows: First, the business server can obtain the memory block request amount carried in the memory allocation request of CPU1. The business server can obtain a memory block in memory domain 0' that is larger than the requested amount, which will be used as the memory block to be partitioned. This memory block to be partitioned can form memory domain 1, which can serve as the memory domain to be allocated for CPU1, providing services to CPU1 (e.g., obtaining the target memory block from memory domain 1 and allocating it to CPU1). At the same time, the remaining memory blocks in memory domain 0' (that is, the memory blocks other than the memory block to be partitioned) can form a new memory domain (e.g., ... Figure 4a If we consider memory domain 0'', then by dividing memory domain 0', we can obtain memory domain 0'' and memory domain 1. The set of memory domains can include memory domain 0'' and memory domain 1.

[0062] Furthermore, such as Figure 4a As shown, during the memory domain expansion phase, after CPU1 completes its request (which can be understood as CPU1 having already been allocated memory blocks), CPU1 releases memory domain 1. It's understood that each CPU's memory allocation request can carry the number of memory blocks requested (referred to as the memory block request quantity). When memory domain 1 provides services to CPU1, the application server can allocate corresponding memory blocks to CPU1 based on the memory block request quantity carried in CPU1's memory allocation request. In other words, the application server can obtain the corresponding memory blocks from memory domain 1 and allocate them to CPU1. Therefore, when CPU1 releases memory domain 1, the memory blocks included in memory domain 1 do not actually include the memory blocks already allocated to CPU1. For clarity, the memory domain released by CPU1 can be referred to as memory domain 1'. At this point, after CPU1 completes its request, the memory domain set includes memory domain 0'' and memory domain 1'. As can be seen, the memory domain has expanded from a single memory domain 0 to multiple memory domains (memory domain 0'' and memory domain 1'). The set of memory domains containing memory domain 0'' and memory domain 1' can directly satisfy the subsequent concurrent access of the CPU (such as the concurrent access of CPU2 and CPU1).

[0063] It should be noted that when memory domain 0'' and memory domain 1' are providing services to CPU0 and CPU1 respectively, if CPU2 initiates a memory allocation request, then, as described above with CPU1, CPU2 can first wait for a CPU to complete the request and release the memory domain, and then divide the memory domain before allocating memory blocks to it.

[0064] Understandably, for scenarios with high concurrency memory request requirements, this application can dynamically divide memory domains, thereby providing multiple memory domains to serve multiple CPUs simultaneously, which can reduce request response latency and improve memory allocation efficiency.

[0065] Furthermore, for a better understanding of the dynamic adjustment process of memory domains, please refer to [link to relevant documentation]. Figure 4b , Figure 4b This is a schematic diagram illustrating a scenario of merging memory domains provided in an embodiment of this application. For example... Figure 4b As shown, the process of merging memory domains can be divided into three stages: redundant resource detection, resource merging, and memory domain compression. For ease of understanding, these three stages will be explained below.

[0066] like Figure 4b The redundancy resource stage shown can detect redundant resources in the system. For example, as... Figure 4b The CPU0 shown can correspond to process 0. The current memory domain set can include memory domain 0, memory domain 1, and memory domain 2. Memory domain 0 is currently providing services to CPU0, while memory domains 1 and 2 are not providing services to any CPU and are in an idle state (also called a free state; memory domains 1 and 2 are both allocatable memory domains). When CPU0 completes its request, that is, after memory domain 0 finishes its service, CPU0 will release memory domain 0. When CPU0 releases memory domain 0, the memory blocks included in memory domain 0 do not actually include the memory blocks that have already been allocated to CPU0. For ease of distinction, the memory domain released by CPU0 can be called memory domain 0'. At this time, the memory domains in the system can be detected. It is found that memory domains 0, 1, and 2 are all in an idle state, and memory domains 1 and 2 have been in an idle state for a long time. At this time, the memory request concurrency of the system can be considered to be low concurrency (i.e., the number of allocatable memory domains in the system is relatively large). Resource merging can then be performed.

[0067] Furthermore, such as Figure 4b As shown, during the resource merging phase, idle memory domains can be merged. For example, ... Figure 4bAs shown, memory domain 1 and memory domain 2 can be merged to obtain memory domain 3. It should be noted that merging memory domains can involve merging all idle memory domains or selecting any two memory domains for merging. When selecting memory domains, priority should be given to those that can form contiguous physical pages after merging. For example, memory domain 0' includes physical page frames 1, 3, and 5; memory domain 1 includes physical page frames 2 and 4; and memory domain 2 includes physical page frames 8 and 9. It is evident that physical page frames 1, 3, and 5, as well as physical page frames 2 and 4, can form contiguous pages 1-5. Therefore, memory domain 0' and memory domain 1 can be merged first.

[0068] Furthermore, such as Figure 4b As shown, during the memory domain compression phase, after the memory domains are merged, the newly generated memory domain (i.e., memory domain 3) can be added to the memory domain set. In other words, the current memory domain set includes memory domain 0' and memory domain 3.

[0069] Understandably, for scenarios with low concurrency memory request requirements, this application can dynamically merge memory domains, thereby reducing fragmentation caused by memory domain boundaries and improving resource utilization.

[0070] It is understandable that when a process completes its execution, it releases memory blocks, which can then be added to a memory domain that is currently idle (i.e., an unserved memory domain, or allocable memory domain). To reduce resource conflict rates, this application can provide a memory buffer and set memory block release conditions for the buffer. Memory blocks released by a process are first stored in the memory buffer. Only when the memory block release conditions are met are the memory blocks in the memory buffer released to the memory domains in the memory domain set. For clarity, please refer to [further details omitted]. Figure 5 , Figure 5 This is a flowchart illustrating a data processing method provided in an embodiment of this application. The flowchart uses the example of a first process releasing a first target memory block to illustrate the specific method for releasing a memory block based on a memory buffer. Figure 5 As shown, the process may include at least the following steps S501-S503: Step S501: Receive a memory release request for the first target memory block sent by the first process, and check the storage status of the memory buffer according to the memory release request.

[0071] Specifically, when a memory release request for the first target memory block is received from the first process, the storage status of the memory buffer can be detected based on the memory release request. The specific implementation for detecting the storage status of the memory buffer can be as follows: Historical memory release behavior information and virtual address space of the first process can be obtained; subsequently, based on the historical memory release behavior information and virtual address space, the predicted amount of memory release requests from the first process within the target time period can be determined; subsequently, the target block count of the first target memory block and the predicted block count corresponding to the predicted memory release request can be obtained; the storage status of the memory buffer can be detected based on the target block count and the predicted block count.

[0072] One specific implementation for detecting the storage state of the memory buffer based on the number of target blocks and the number of predicted blocks is as follows: the number of target blocks and the number of predicted blocks can be calculated to obtain the total number; the remaining storage capacity of the memory buffer can be obtained; if the remaining storage capacity of the memory buffer is greater than the total number, the storage state of the memory buffer can be determined as the first storage state; and if the remaining storage capacity of the memory buffer is less than the total number, the storage state of the memory buffer can be determined as the second storage state.

[0073] Understandably, when a memory release request for a first target memory block is received from the first process, information on the first process's past memory request behavior (referred to as historical memory release behavior information) and the virtual address space segment corresponding to the first process can be collected. Based on this collected historical memory release behavior information, the probability of the first process generating subsequent memory release requests can be predicted. For example, if the current virtual address space segment contains a large number of memory blocks with the same lifecycle, and historical memory release behavior information indicates that the first process has already performed multiple memory release actions, then it can be predicted that the first process is highly likely to continue generating a batch of memory release requests in a short period of time. In other words, based on historical memory release behavior information and the virtual address space segment, the predicted amount of memory release requests from the first process within the target time period can be predicted, as well as the number of memory blocks to be released in each memory release request. This allows the determination of the predicted number of blocks corresponding to the predicted amount of memory release requests (i.e., the sum of the predicted number of blocks to be released in each predicted memory release request). Based on the number of target blocks of the first target memory block and the predicted number of blocks, the storage status of the memory buffer can be detected.

[0074] If the total number of target blocks and predicted blocks is less than the remaining storage capacity of the memory buffer, then the memory buffer can be considered sufficient to store the first target memory block and the predicted memory block corresponding to the predicted memory release request. The storage state of the memory buffer can be called the first storage state (sufficient storage state). If the total number of target blocks and predicted blocks is greater than the remaining storage capacity of the memory buffer, then the memory buffer can be considered insufficient to store the first target memory block and the predicted memory block corresponding to the predicted memory release request. The storage state of the memory buffer can be called the first storage state (insufficient storage capacity state).

[0075] Optionally, in addition to using historical memory release behavior information and virtual address space, there are other prediction methods for determining the predicted memory release request amount of the first process within the target time period. For example, prediction can be made using information actively provided by system calls or by using process behavior information obtained through offline sampling. This application does not limit the specific prediction method.

[0076] Step S502: If the storage state of the memory buffer is the first storage state, the first target memory block is added to the memory buffer. When the memory block release condition is met, the first target memory block in the memory buffer is released to the memory domain set.

[0077] Specifically, if the total number of target blocks and predicted blocks is less than the remaining storage capacity of the memory buffer, then the memory buffer can be considered sufficient to store the first target memory block and the predicted release memory block corresponding to the predicted memory release request (the memory buffer is in the first storage state). In this case, there is no need to adjust the memory buffer, and the first target memory block can be directly stored in the memory buffer. When the memory block release condition is met, the stored memory blocks in the memory buffer will be released in a unified manner.

[0078] One specific implementation of releasing the first target memory block in the memory buffer to the memory domain set is as follows: When the memory block release time is reached, the existing memory blocks included in the memory buffer can be obtained; wherein, the existing memory blocks include the first target memory block; at the memory block release time, the allocatable memory domains in the memory domain set can be obtained, and the allocatable memory domains can be used as memory domains to be added; each memory block in the allocatable memory domain is in an idle state; subsequently, the existing memory blocks can be released to the memory domains to be added.

[0079] It can be understood that the memory block release time can be the end time of the target time period. For example, if the target time period is 19:00-19:30 on October 26, 2021, where 19:00 on October 26, 2021 is the start time and 19:30 on October 26, 2021 is the end time, then the memory block release time can refer to the end time, 19:30 on October 26, 2021. The memory blocks actually released by the first process within this target time period (which can be called the real released memory blocks) are also stored in the memory buffer. At this time, the stored memory blocks in the memory buffer can be retrieved, and these stored memory blocks can be released to the memory domain set.

[0080] It is understandable that all existing memory blocks can be released to the same allocatable memory domain. However, if there are two or more allocatable memory domains, the existing memory blocks can also be stored in separate domains (i.e., each allocatable memory domain stores a portion of the existing memory blocks).

[0081] Optionally, and understandably, the memory block release condition can be set to other conditions besides the end timestamp of the target time period. For example, the memory block release condition can also be that the memory buffer's upper limit has been reached. For instance, if the memory buffer is adjusted based on historical memory release behavior information and the virtual address space, and the first process actually releases a large number of memory blocks within the target time period, reaching the upper limit of the memory buffer before the end of the target time period (i.e., the memory buffer's capacity is insufficient for storage), then the existing memory blocks in the memory buffer can be released first. Other conditions can, of course, be set for memory block release, but these will not be listed here.

[0082] Step S503: If the storage state of the memory buffer is the second storage state, the storage capacity of the memory buffer is adjusted according to the first target memory block to obtain an adjusted memory buffer. The first target memory block is added to the adjusted memory buffer. When the memory block release condition is met, the first target memory block in the adjusted memory buffer is released to the memory domain set.

[0083] Specifically, if the total number of target blocks and predicted blocks exceeds the remaining storage capacity of the memory buffer, then the memory buffer can be considered insufficient to store the first target memory block and the predicted release memory block corresponding to the predicted memory release request (the memory buffer is in a second storage state). In this case, the boundaries of the memory buffer can be adjusted (i.e., the storage capacity of the memory buffer can be increased) to obtain an adjusted memory buffer that can hold more physical page frames. After adjustment, the first target memory block can be added to the memory buffer. When the memory block release condition is met, the existing memory blocks stored in the adjusted memory buffer are released uniformly.

[0084] Specifically, the method for adjusting the storage capacity of the memory buffer based on the first target memory block to obtain the adjusted memory buffer can be as follows: The predicted memory release request amount of the first process within the target time period and the predicted number of blocks corresponding to the predicted memory release request amount can be obtained; subsequently, the target block number of the first target memory block can be obtained, and the total number corresponding to the target block number and the predicted block number can be determined; subsequently, the remaining storage capacity corresponding to the memory buffer can be obtained, and the storage capacity of the memory buffer can be adjusted based on the remaining storage capacity and the total number to obtain the adjusted memory buffer; wherein, the updated remaining storage capacity of the adjusted memory buffer is greater than the total number.

[0085] In this embodiment, a mechanism for dynamically adjusting the buffer can aggregate memory blocks released by processes in batches. Simultaneously, by utilizing historical memory release behavior information and the virtual address space of processes, potential subsequent memory release requests can be predicted. This allows for proactive adjustment of the buffer boundaries. By aggregating and uniformly releasing memory blocks through the buffer, the resource conflict rate of memory requests (such as concurrent memory allocation and release requests) targeting allocatable memory domains can be reduced, minimizing waste of memory resources limited by the memory buffer and improving resource utilization.

[0086] Furthermore, for ease of understanding, please refer to Figure 6 , Figure 6 This is a system structure diagram provided in an embodiment of this application. For example... Figure 6 As shown, the system architecture may include a lazy layer and a core layer. The lazy layer may include a dynamic memory buffer, and the core layer may include n memory domains (memory domain 0, memory domain 1, ..., memory domain n).

[0087] Understandably, when an application in the system generates a memory allocation or reclamation (also known as a release) request, the memory request (including memory allocation and memory release requests) can first be passed to the lazy layer. This lazy layer maintains a dynamic memory buffer for each CPU, predicting the number of subsequent memory requests and dynamically adjusting the memory buffer length based on the predicted number. Under certain conditions (such as issuing a memory allocation request or the completion of process memory reclamation), the lazy layer can interact with the kernel layer. For example, when a CPU issues a memory allocation request, it can obtain some free page frames from multiple memory domains included in the kernel layer. These free page frames can be sent to the lazy layer, which can then allocate them to the corresponding CPU. Similarly, when a process issues a memory release request, the released memory block can be stored in the lazy layer first, and then released to the kernel layer's memory domain when the memory block release conditions are met.

[0088] Understandably, the core layer can maintain a global pool of free page frames in the system, dividing page frames into multiple memory domains. The number of memory domains can be dynamically adjusted based on the actual concurrency requirements of the system. For example, under high concurrency, the number of memory domains can be expanded to provide multiple memory domains to simultaneously respond to multi-core demands; under low concurrency, the number of memory domains can be reduced, consolidating fragmented memory domains into a single large memory domain, expanding the resource pool, and reducing fragmentation.

[0089] In this embodiment, memory domains can be dynamically adjusted according to the concurrency requirements of processes. For example, under high concurrency memory requests, memory domains can be divided, thereby providing multiple memory domains to simultaneously respond to the memory request needs of multiple processes. For instance, when a first memory allocation request is received from a first process, the first process does not need to queue and wait for previous processes (such as processes that issued memory allocation requests before the first process) to complete their requests. Instead, it can directly and quickly determine the memory domain to be allocated for the first process based on multiple memory domains in the memory domain set, and allocate the first target memory block to the first process using that memory domain. This can reduce memory allocation latency and improve memory request response efficiency. Under low concurrency memory requests, memory domains can be merged and integrated, consolidating fragmented memory domains into a large resource pool to reduce fragmentation. In summary, this application can dynamically expand or merge memory domains according to the system's concurrency status. Under high concurrency, multiple memory domains can be provided to simultaneously respond to the memory allocation requests of multiple processes, reducing request response latency and improving memory allocation efficiency; under low concurrency, memory domains can be integrated to reduce fragmentation and improve resource utilization. Meanwhile, by dynamically adjusting the buffer mechanism, memory blocks released by processes in batches can be aggregated. By utilizing the historical memory release behavior information of processes and the virtual address space, subsequent potential memory release requests can be predicted. This allows for proactive adjustment of the buffer boundaries. Through the aggregation and unified release of memory blocks via the buffer, the resource conflict rate of memory requests (such as concurrent memory allocation requests and memory release requests) on allocable memory domains can be reduced, the waste of memory resources limited in the memory buffer can be reduced, and resource utilization can be further improved.

[0090] Further, please see Figure 7 , Figure 7 This is a schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application. The data processing apparatus can be a computer program (including program code) running on a computer device; for example, the data processing apparatus is an application software. The data processing apparatus can be used to execute... Figure 2 The method shown. (As illustrated) Figure 7 As shown, the data processing device 1 may include: a request processing module 11, a memory domain determination module 12, a memory block allocation module 13, and a memory domain update module 14.

[0091] Request processing module 11 is used to receive a first memory allocation request sent by the first process and obtain a set of memory domains according to the first memory allocation request; each memory domain in the set of memory domains consists of one or more memory blocks; The memory domain determination module 12 is used to determine the memory domain to be allocated for the first process based on the memory domain set. The memory block allocation module 13 is used to determine the first target memory block corresponding to the first process from one or more memory blocks included in the memory domain to be allocated according to the first memory allocation request, and allocate the first target memory block to the first process; The memory domain update module 14 is used to update the memory domain to be allocated in the memory domain set to the updated memory domain according to the first target memory block; the memory domain set containing the updated memory domain is used to allocate the second target memory block for the second process when the second memory allocation request of the second process is received.

[0092] The specific implementation methods of the request processing module 11, memory domain determination module 12, memory block allocation module 13, and memory domain update module 14 can be found in the above description. Figure 2 The descriptions of steps S101-S103 in the corresponding embodiments will not be repeated here.

[0093] In one embodiment, the memory domain determination module 12 may include a first domain detection unit 121 and a first domain acquisition unit 122.

[0094] The first domain detection unit 121 is used to detect memory domains in the memory domain set; The first domain acquisition unit 122 is used to acquire the memory domain to be allocated corresponding to the first process in the allocable memory domain if an allocable memory domain is detected in the memory domain set, and switch the memory domain to be allocated from the idle state to the locked state; each memory block in the allocable memory domain is in the idle state; there are no memory blocks in the locked memory domain that are in the idle state.

[0095] The specific implementation methods of the first domain detection unit 121 and the first domain acquisition unit 122 can be found in the above description. Figure 2 The description of step S102 in the corresponding embodiment will not be repeated here.

[0096] In one embodiment, the memory domain determination module 12 may include a second domain detection unit 123 and a second domain acquisition unit 124.

[0097] The second domain detection unit 123 is used to detect memory domains in the memory domain set; The second domain acquisition unit 124 is used to set the first process to a waiting state if no allocatable memory domain is detected in the memory domain set, and to switch the first process from the waiting state to the allocation state when an allocatable memory domain reappears in the memory domain set, to acquire the unallocated memory domain corresponding to the first process in the allocation state from the allocatable memory domain, and to switch the unallocated memory domain from the idle state to the locked state; each memory block in the allocatable memory domain is in an idle state; there are no memory blocks in the locked unallocated memory domain that are in an idle state.

[0098] The specific implementation methods of the second domain detection unit 123 and the second domain acquisition unit 124 can be found in the above description. Figure 2 The description of step S102 in the corresponding embodiment will not be repeated here.

[0099] In one embodiment, the memory domain update module 14 may include a block determination unit 141 and a domain composition unit 142.

[0100] The block determination unit 141 is used to identify memory blocks in the memory domain to be allocated, excluding the first target memory block, as the first remaining memory block. The domain composition unit 142 is used to compose an updated memory domain based on the first remaining memory block; the updated memory domain in the memory domain set belongs to the allocatable memory domain.

[0101] The specific implementation methods of the block determination unit 141 and the domain composition unit 142 can be found in the above description. Figure 2 The description of step S103 in the corresponding embodiment will not be repeated here.

[0102] In one embodiment, the memory domain update module 14 may include a domain partitioning unit 143 and an update domain determination unit 144.

[0103] The domain partitioning unit 143 is used to partition the memory domain to be allocated according to the first target memory block, so as to obtain the first partitioned memory domain and the second partitioned memory domain. The update domain determination unit 144 is used to determine the first partitioned memory domain and the second partitioned memory domain as the update memory domain; the update memory domain in the memory domain set belongs to the allocatable memory domain.

[0104] The specific implementation methods of the domain partitioning unit 143 and the update domain determination unit 144 can be found in the above description. Figure 2 The description of step S103 in the corresponding embodiment will not be repeated here.

[0105] In one embodiment, the domain partitioning unit 143 may include: a block determination subunit 1431, a difference block acquisition subunit 1432, and a domain composition subunit 1433.

[0106] The block to be partitioned determination subunit 1431 is used to determine the memory blocks to be partitioned in the memory domain to be allocated based on the first target memory block; the number of blocks to be partitioned is greater than the number of blocks in the first target memory block; The difference block acquisition subunit 1432 is used to acquire the difference memory block between the memory block to be divided and the first target memory block; The partitioning subunit 1433 is used to form a first partitioned memory domain based on the difference memory block and a second partitioned memory domain based on the second remaining memory block; the second remaining memory block refers to the memory block in the memory domain to be allocated other than the memory block to be partitioned.

[0107] The specific implementation methods of the sub-unit 1431 for determining the block to be divided, the sub-unit 1432 for obtaining the difference block, and the sub-unit 1433 for forming the partitioned domain can be found in the above description. Figure 2 The description of step S103 in the corresponding embodiment will not be repeated here.

[0108] In one embodiment, the memory domain determination module 12 may further include: a domain quantity determination unit 125 and a domain merging unit 126.

[0109] The domain number determination unit 125 is used to obtain the remaining memory domains in the allocable memory domains excluding the memory domains to be allocated, and the number of domains in the remaining memory domains; The domain merging unit 126 is used to merge the remaining memory domains when the number of domains exceeds the number threshold to obtain a merged memory domain; the merged memory domain in the memory domain set belongs to the allocatable memory domain.

[0110] The specific implementation methods of the domain number determination unit 125 and the domain merging unit 126 can be found in the above description. Figure 2 The description of step S102 in the corresponding embodiment will not be repeated here.

[0111] In one embodiment, the data processing device 1 may further include: a status detection module 15, a first memory block release module 16, and a second memory block release module 17.

[0112] The status detection module 15 is used to receive a memory release request for the first target memory block sent by the first process; The status detection module 15 is also used to detect the storage status of the memory buffer according to the memory release request; The first memory block release module 16 is used to add the first target memory block to the memory buffer if the storage state of the memory buffer is the first storage state. The first memory block release module 16 is also used to release the first target memory block in the memory buffer to the memory domain set when the memory block release condition is met; The second memory block release module 17 is used to adjust the storage capacity of the memory buffer according to the first target memory block if the storage state of the memory buffer is the second storage state, so as to obtain the adjusted memory buffer. The second memory block release module 17 is also used to add the first target memory block to the adjustment memory buffer, and release the first target memory block in the adjustment memory buffer to the memory domain set when the memory block release condition is met.

[0113] The specific implementation methods of the status detection module 15, the first memory block release module 16, and the second memory block release module 17 can be found in the above description. Figure 5 The descriptions of steps S501-S503 in the corresponding embodiments will not be repeated here.

[0114] In one embodiment, the state detection module 15 may include: a process information acquisition unit 151, a prediction quantity determination unit 152, and a state detection unit 153.

[0115] The process information acquisition unit 151 is used to acquire the historical memory release behavior information and virtual address space of the first process; The prediction quantity determination unit 152 is used to determine the predicted memory release request quantity of the first process within the target time period based on historical memory release behavior information and virtual address space. The status detection unit 153 is used to obtain the number of target blocks of the first target memory block and the number of predicted blocks corresponding to the predicted memory release request amount, and to detect the storage status of the memory buffer based on the number of target blocks and the number of predicted blocks.

[0116] The specific implementation methods of the process information acquisition unit 151, the prediction quantity determination unit 152, and the state detection unit 153 can be found in the above description. Figure 5 The description of step S501 in the corresponding embodiment will not be repeated here.

[0117] In one embodiment, the state detection unit 153 may include: an operation subunit 1531, a capacity acquisition subunit 1532, and a state determination subunit 1533.

[0118] The operation subunit 1531 is used to perform calculations on the number of target blocks and the number of predicted blocks to obtain the total number; Capacity acquisition subunit 1532 is used to acquire the remaining storage capacity of the memory buffer; The state determination subunit 1533 is used to determine the storage state of the memory buffer as the first storage state if the remaining storage capacity of the memory buffer is greater than the total number. The state determination subunit 1533 is also used to determine the storage state of the memory buffer as the second storage state if the remaining storage capacity of the memory buffer is less than the total number.

[0119] The specific implementation methods of the operation subunit 1531, the capacity acquisition subunit 1532, and the state determination subunit 1533 can be found in the above description. Figure 5 The description of step S501 in the corresponding embodiment will not be repeated here.

[0120] In one embodiment, the first memory block release module 16 may include: an existing block acquisition unit 161, a pre-determination unit 162, and a block addition unit 163.

[0121] The stored block acquisition unit 161 is used to acquire the stored memory blocks included in the memory buffer when the memory block release time is reached; the stored memory blocks include the first target memory block; The pre-determination unit 162 is used to obtain the allocatable memory domains in the memory domain set when the memory block is released, and to use the allocatable memory domains as memory domains to be added; each memory block in the allocatable memory domain is in an idle state. Block addition unit 163 is used to release an existing memory block to the memory domain to be added.

[0122] The specific implementation methods of the existing block acquisition unit 161, the pre-determination unit 162, and the block addition unit 163 can be found in the above description. Figure 5 The description of step S502 in the corresponding embodiment will not be repeated here.

[0123] In one embodiment, the second memory block release module 17 may include a quantity determination unit 171 and a capacity adjustment unit 172.

[0124] The quantity determination unit 171 is used to obtain the predicted memory release request amount of the first process within the target time period, and the predicted number of blocks corresponding to the predicted memory release request amount; The quantity determination unit 171 is also used to obtain the target block quantity of the first target memory block and determine the total quantity corresponding to the target block quantity and the predicted block quantity; The capacity adjustment unit 172 is used to obtain the remaining storage capacity corresponding to the memory buffer, and adjust the storage capacity of the memory buffer according to the remaining storage capacity and the total quantity to obtain the adjusted memory buffer; the updated remaining storage capacity of the adjusted memory buffer is greater than the total quantity.

[0125] The specific implementation methods of the quantity determination unit 171 and the capacity adjustment unit 172 can be found in the above description. Figure 5 The description of step S503 in the corresponding embodiment will not be repeated here.

[0126] In this embodiment, memory domains can be dynamically adjusted according to the concurrency requirements of processes. For example, under high concurrency memory requests, memory domains can be divided, thereby providing multiple memory domains to simultaneously respond to the memory request needs of multiple processes. For instance, when a first memory allocation request is received from a first process, the first process does not need to queue and wait for previous processes (such as processes that issued memory allocation requests before the first process) to complete their requests. Instead, it can directly and quickly determine the memory domain to be allocated for the first process based on multiple memory domains in the memory domain set, and allocate the first target memory block to the first process using that memory domain. This can reduce memory allocation latency and improve memory request response efficiency. Under low concurrency memory requests, memory domains can be merged and integrated, consolidating fragmented memory domains into a large resource pool to reduce fragmentation. In summary, this application can dynamically expand or merge memory domains according to the system's concurrency status. Under high concurrency, multiple memory domains can be provided to simultaneously respond to the memory allocation requests of multiple processes, reducing request response latency and improving memory allocation efficiency; under low concurrency, memory domains can be integrated to reduce fragmentation and improve resource utilization. Meanwhile, by dynamically adjusting the buffer mechanism, memory blocks released by processes in batches can be aggregated. By utilizing the historical memory release behavior information of processes and the virtual address space, subsequent potential memory release requests can be predicted. This allows for proactive adjustment of the buffer boundaries. Through the aggregation and unified release of memory blocks via the buffer, the resource conflict rate of memory requests (such as concurrent memory allocation requests and memory release requests) on allocable memory domains can be reduced, the waste of memory resources limited in the memory buffer can be reduced, and resource utilization can be further improved.

[0127] Further, please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Figure 8 As shown above, Figure 7The data processing device 1 in the corresponding embodiment can be applied to the aforementioned computer device 8000. The computer device 8000 may include a processor 8001, a network interface 8004, and a memory 8005. Furthermore, the computer device 8000 also includes a user interface 8003 and at least one communication bus 8002. The communication bus 8002 is used to enable communication between these components. The user interface 8003 may include a display screen and a keyboard; optionally, the user interface 8003 may also include a standard wired interface or a wireless interface. The network interface 8004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 8005 may be high-speed RAM or non-volatile memory, such as at least one disk storage device. Optionally, the memory 8005 may also be at least one storage device located remotely from the aforementioned processor 8001. Figure 8 As shown, the memory 8005, which is a computer-readable storage medium, may include an operating system, a network communication module, a user interface module, and a device control application program.

[0128] exist Figure 8 In the computer device 8000 shown, the network interface 8004 provides network communication functionality; the user interface 8003 is mainly used to provide an input interface for the user; and the processor 8001 can be used to call the device control application program stored in the memory 8005 to achieve: Receive the first memory allocation request sent by the first process, and obtain a set of memory domains according to the first memory allocation request; each memory domain in the set of memory domains consists of one or more memory blocks; The memory domain to be allocated for the first process is determined based on the set of memory domains. Based on the first memory allocation request, the first target memory block corresponding to the first process is determined from one or more memory blocks included in the memory domain to be allocated, and the first target memory block is allocated to the first process. Based on the first target memory block, the memory domain to be allocated in the memory domain set is updated to the updated memory domain; the memory domain set containing the updated memory domain is used to allocate the second target memory block for the second process when a second memory allocation request from the second process is received.

[0129] It should be understood that the computer device 8000 described in the embodiments of this application can execute the foregoing text. Figures 2 to 6 The description of the data processing method in the corresponding embodiment can also be performed as described above. Figure 7 The description of the data processing apparatus 1 in the corresponding embodiments will not be repeated here. Furthermore, the beneficial effects of using the same method will also not be repeated here.

[0130] Furthermore, it should be noted that this application embodiment also provides a computer-readable storage medium, which stores a computer program executed by the aforementioned data processing computer device 1000. The computer program includes program instructions, and when the processor executes the program instructions, it can execute the aforementioned... Figures 2 to 6 The description of the data processing method in the corresponding embodiments is already provided and will not be repeated here. Furthermore, the beneficial effects of using the same method will also not be repeated. For technical details not disclosed in the computer-readable storage medium embodiments related to this application, please refer to the description of the method embodiments of this application.

[0131] The aforementioned computer-readable storage medium can be an internal storage unit of the data processing apparatus or computer device provided in any of the foregoing embodiments, such as a hard disk or memory of the computer device. The computer-readable storage medium can also be an external storage device of the computer device, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., provided on the computer device. Furthermore, the computer-readable storage medium can include both internal storage units and external storage devices of the computer device. The computer-readable storage medium is used to store the computer program and other programs and data required by the computer device. The computer-readable storage medium can also be used to temporarily store data that has been output or will be output.

[0132] One aspect of this application provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method provided in one aspect of the embodiments of this application.

[0133] The terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the term "comprising," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, apparatus, product, or device that includes a series of steps or units is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other step units inherent to these processes, methods, apparatuses, products, or devices.

[0134] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0135] The methods and related apparatuses provided in this application are described with reference to the method flowcharts and / or structural diagrams provided in this application. Specifically, each block of the method flowchart and / or structural diagram, as well as combinations of blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to create a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing device, generate instructions for implementing the process. Figure 1 A schematic diagram of one or more processes and / or structures. Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 A schematic diagram of one or more processes and / or structures. Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 A process or multiple processes and / or structures illustrate the steps of the functions specified in one or more boxes.

[0136] The above-disclosed embodiments are merely preferred embodiments of this application and should not be construed as limiting the scope of this application. Therefore, any equivalent variations made in accordance with the claims of this application shall still fall within the scope of this application.

Claims

1. A data processing method, characterized in that, include: Receive a first memory allocation request sent by the first process, and obtain a set of memory domains based on the first memory allocation request; Each memory domain in the set of memory domains consists of one or more memory blocks; Based on the set of memory domains, determine the memory domain to be allocated corresponding to the first process; based on the first memory allocation request, determine the first target memory block corresponding to the first process from one or more memory blocks included in the memory domain to be allocated; and allocate the first target memory block to the first process. Based on the first target memory block, the memory domain to be allocated in the memory domain set is updated to an updated memory domain; the memory domain set containing the updated memory domain is used to allocate a second target memory block to the second process when a second memory allocation request from the second process is received; Receive a memory release request for the first target memory block sent by the first process, and detect the storage status of the memory buffer according to the memory release request; If the storage state of the memory buffer is the first storage state, then the first target memory block is added to the memory buffer. When the memory block release condition is met, the first target memory block in the memory buffer is released to the memory domain set. If the storage state of the memory buffer is the second storage state, then the storage capacity of the memory buffer is adjusted according to the first target memory block to obtain an adjusted memory buffer, the first target memory block is added to the adjusted memory buffer, and when the memory block release condition is met, the first target memory block in the adjusted memory buffer is released to the memory domain set. The method of detecting the storage status of the memory buffer based on the memory release request includes: obtaining historical memory release behavior information and virtual address space of the first process; determining the predicted memory release request amount of the first process within a target time period based on the historical memory release behavior information and the virtual address space; obtaining the target block number of the first target memory block and the predicted block number corresponding to the predicted memory release request amount; and detecting the storage status of the memory buffer based on the target block number and the predicted block number.

2. The method according to claim 1, characterized in that, The step of determining the memory domain to be allocated corresponding to the first process based on the set of memory domains includes: Detect the memory domains in the set of memory domains; If an allocatable memory domain is detected in the set of memory domains, the memory domain to be allocated corresponding to the first process is obtained from the allocatable memory domain, and the memory domain to be allocated is switched from an idle state to a locked state; each memory block in the allocatable memory domain is in an idle state; there are no memory blocks in an idle state in the memory domain to be allocated in the locked state.

3. The method according to claim 1, characterized in that, The step of determining the memory domain to be allocated corresponding to the first process based on the set of memory domains includes: Detect the memory domains in the set of memory domains; If no allocatable memory domain is detected in the set of memory domains, the first process is set to a waiting state. When the allocatable memory domain reappears in the set of memory domains, the first process is switched from the waiting state to the allocation state. The unallocated memory domain corresponding to the first process in the allocation state is obtained from the allocatable memory domains, and the unallocated memory domain is switched from an idle state to a locked state. Each memory block in the allocatable memory domain is in an idle state. There are no idle memory blocks in the unallocated memory domains in the locked state.

4. The method according to claim 2, characterized in that, The step of updating the unallocated memory domain in the memory domain set to the updated memory domain based on the first target memory block includes: The memory blocks in the memory domain to be allocated, excluding the first target memory block, are designated as the first remaining memory blocks; An updated memory domain is formed based on the first remaining memory block; the updated memory domain in the set of memory domains belongs to the allocatable memory domain.

5. The method according to claim 3, characterized in that, The step of updating the unallocated memory domain in the memory domain set to the updated memory domain based on the first target memory block includes: Based on the first target memory block, the memory domain to be allocated is divided into a first partitioned memory domain and a second partitioned memory domain. The first partitioned memory domain and the second partitioned memory domain are determined as the updated memory domain; the updated memory domain in the set of memory domains belongs to the allocatable memory domain.

6. The method according to claim 5, characterized in that, The step of dividing the memory domain to be allocated into a first partitioned memory domain and a second partitioned memory domain based on the first target memory block includes: Based on the first target memory block, a memory block to be partitioned is determined in the memory domain to be allocated; the number of blocks to be partitioned is greater than the number of blocks in the first target memory block; Obtain the difference memory block between the memory block to be divided and the first target memory block; The first partitioned memory domain is formed based on the difference memory blocks, and the second partitioned memory domain is formed based on the second remaining memory blocks; the second remaining memory blocks refer to the memory blocks in the memory domain to be allocated other than the memory blocks to be partitioned.

7. The method according to claim 2, characterized in that, The method further includes: Obtain the remaining memory domains in the allocable memory domains excluding the memory domain to be allocated, and the number of domains in the remaining memory domains; When the number of domains exceeds the quantity threshold, the remaining memory domains are merged to obtain a merged memory domain; the merged memory domain in the memory domain set belongs to the allocatable memory domain.

8. The method according to claim 1, characterized in that, The step of detecting the storage state of the memory buffer based on the target block count and the predicted block count includes: The total number is obtained by performing calculations on the target block count and the predicted block count. Obtain the remaining storage capacity of the memory buffer; If the remaining storage capacity of the memory buffer is greater than the total number, then the storage state of the memory buffer is determined as the first storage state; If the remaining storage capacity of the memory buffer is less than the total number, then the storage state of the memory buffer is determined to be the second storage state.

9. The method according to claim 1, characterized in that, The step of releasing the first target memory block in the memory buffer to the memory domain set when the memory block release condition is met includes: When the memory block release time is reached, the stored memory blocks included in the memory buffer are retrieved; the stored memory blocks include the first target memory block; At the time the memory block is released, the allocatable memory domains in the memory domain set are obtained, and the allocatable memory domains are used as memory domains to be added; each memory block in the allocatable memory domain is in an idle state; Release the existing memory block into the memory domain to be added.

10. The method according to claim 1, characterized in that, The step of adjusting the storage capacity of the memory buffer according to the first target memory block to obtain an adjusted memory buffer includes: Obtain the predicted memory release request volume of the first process within the target time period, and the predicted number of blocks corresponding to the predicted memory release request volume; Obtain the target block count of the first target memory block, and determine the total number corresponding to the target block count and the predicted block count; Obtain the remaining storage capacity corresponding to the memory buffer, and adjust the storage capacity of the memory buffer according to the remaining storage capacity and the total number to obtain the adjusted memory buffer; the updated remaining storage capacity of the adjusted memory buffer is greater than the total number.

11. A data processing apparatus, characterized in that, include: The request processing module is used to receive the first memory allocation request sent by the first process and obtain the memory domain set according to the first memory allocation request. Each memory domain in the set of memory domains consists of one or more memory blocks; A memory domain determination module is used to determine the memory domain to be allocated for the first process based on the memory domain set. The memory block allocation module is configured to determine, according to the first memory allocation request, a first target memory block corresponding to the first process from one or more memory blocks included in the memory domain to be allocated, and allocate the first target memory block to the first process; The memory domain update module is used to update the memory domain to be allocated in the memory domain set to an updated memory domain according to the first target memory block; the memory domain set containing the updated memory domain is used to allocate a second target memory block for the second process when a second memory allocation request from the second process is received; The status detection module is used to receive a memory release request for the first target memory block sent by the first process, and detect the storage status of the memory buffer according to the memory release request; The first memory block release module is used to add the first target memory block to the memory buffer if the storage state of the memory buffer is the first storage state, and release the first target memory block in the memory buffer to the memory domain set when the memory block release condition is met. The second memory block release module is used to adjust the storage capacity of the memory buffer according to the first target memory block if the storage state of the memory buffer is the second storage state, to obtain an adjusted memory buffer, add the first target memory block to the adjusted memory buffer, and release the first target memory block in the adjusted memory buffer to the memory domain set when the memory block release condition is met. The method of detecting the storage status of the memory buffer based on the memory release request includes: obtaining historical memory release behavior information and virtual address space of the first process; determining the predicted memory release request amount of the first process within a target time period based on the historical memory release behavior information and the virtual address space; obtaining the target block number of the first target memory block and the predicted block number corresponding to the predicted memory release request amount; and detecting the storage status of the memory buffer based on the target block number and the predicted block number.

12. A computer device, characterized in that, include: Processor, memory, and network interface; The processor is connected to the memory and the network interface, wherein the network interface is used to provide network communication functions, the memory is used to store program code, and the processor is used to call the program code to cause the computer device to execute the method according to any one of claims 1-10.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program adapted to be loaded by a processor and to execute the method according to any one of claims 1-10.

14. A computer program product, characterized in that, The computer program product includes computer instructions stored in a computer-readable storage medium, the computer instructions being adapted to be read and executed by a processor to cause a computer device having the processor to perform the method of any one of claims 1-10.

Images