Synchronization circuit, semiconductor device, and synchronization method

Abstract

This invention provides a synchronization circuit, a semiconductor device, and a synchronization method, comprising: a first delay circuit that delays an input synchronization signal by a first specific time to generate a first delayed synchronization signal; a second delay circuit that delays the first delayed synchronization signal by a second specific time to generate a second delayed synchronization signal; a first synchronization circuit that outputs first output data that synchronizes input data with the input synchronization signal; a second synchronization circuit that outputs second output data that synchronizes the input data with the first delayed synchronization signal; and a resynchronization circuit that, if the first output data and the second output data are inconsistent, resynchronizes the input data according to the second delayed synchronization signal and updates the first output data of the first synchronization circuit.

Description

Technical Field

[0001] This invention relates to synchronization circuits, semiconductor devices, and synchronization methods. Background Technology

[0002] In CMOS circuit logic design, there are power supply sustaining voltages VDD and VSS. However, if the input data to the flip-flop circuit does not maintain sufficient setup margin / hold margin relative to the clock, the output signal of the flip-flop circuit may enter a metastable state. In other words, if the timing of the input data is close to the timing of the input clock, and no setup margin or hold margin is maintained, the voltage of the output data will not be either VDD or VSS, but rather an intermediate voltage.

[0003] In this situation, the logic circuit that inputs this signal, which becomes part of the intermediate voltage, treats the intermediate voltage of the output signal as voltage VDD. This metastability may disrupt the system.

[0004] When transmitting and receiving data between different clock domains, although a synchronization circuit is used, metastability can occur within the synchronization circuit. A synchronization circuit using a data strobe signal synchronized with the data is known to suppress metastability when transmitting and receiving data between different clock domains (e.g., Patent Document: Japanese Patent Application Publication No. 10-135938).

[0005] Synchronization circuits like this require additional circuitry associated with the data selection signal. Due to the large circuit size, a synchronization circuit, semiconductor storage device, and synchronization method are needed that can synchronize with the clock of the input data receiving side with a smaller circuit size. Summary of the Invention

[0006] This invention provides a synchronization circuit, comprising: a first delay circuit for delaying an input synchronization signal by a first specific time to generate a first delayed synchronization signal; a second delay circuit for delaying the first delayed synchronization signal by a second specific time to generate a second delayed synchronization signal; a first synchronization circuit for outputting first output data that synchronizes input data with the input synchronization signal; a second synchronization circuit for outputting second output data that synchronizes the input data with the first delayed synchronization signal; and a resynchronization circuit for resynchronizing the input data according to the second delayed synchronization signal if the first output data and the second output data are inconsistent, thereby updating the first output data of the first synchronization circuit.

[0007] This invention provides a synchronization method, comprising: comparing first data that is synchronized with input data by a synchronization signal, and second data that is synchronized with the input data according to a signal that delays the synchronization signal; if the first data and the second data are different, outputting data that is synchronized with the input data according to a signal that delays the synchronization signal more, otherwise, outputting the first data.

[0008] The present invention provides a synchronization method, comprising: comparing each bit width of first data that is synchronized by a synchronization signal containing multiple bit widths, and each bit width of second data that is synchronized by a signal that delays the synchronization signal; if the first data and the second data have at least one bit width difference, outputting data that is synchronized by a signal that delays the synchronization signal more, otherwise, outputting the first data.

[0009] Based on the above, a synchronization circuit, a semiconductor memory device, and a synchronization method capable of synchronization on a small circuit scale can be realized. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 A circuit diagram illustrating the configuration of a synchronization circuit based on a first embodiment of the present invention.

[0011] Figure 2 To display Figure 1 The timing diagram shown illustrates the operation of the synchronization circuit when resynchronization is not performed.

[0012] Figure 3 To display Figure 1 The timing diagram shows the first action example of the synchronous circuit performing resynchronization.

[0013] Figure 4 To display Figure 1 The timing diagram shows the second action example of the synchronous circuit performing resynchronization.

[0014] Figure 5 A circuit diagram illustrating the configuration of a synchronization circuit based on a second embodiment of the present invention.

[0015] Figure 6 A circuit diagram illustrating the configuration of a synchronization circuit based on a third embodiment of the present invention.

[0016] Figure 7 To display Figure 6 The timing diagram shown illustrates the operation of the synchronization circuit when resynchronization is not performed.

[0017] Figure 8 To display Figure 6 The timing diagram shows an example of the operation of the synchronous circuit performing resynchronization.

[0018] Figure 9 To illustrate the clock in the synchronization circuit based on the first embodiment and based on Figure 5 The timing diagram shows the correspondence between the data strobe signals in the synchronization circuit of the second embodiment. Detailed Implementation

[0019] based on Figure 1 The synchronization circuit 201 shown in the embodiment synchronizes the input data DATA with the input clock Clk and outputs it as output data Q3. The synchronization circuit 201 can also be provided in a semiconductor device. The semiconductor device can be a semiconductor memory device such as a dynamic random access memory (DRAM). Furthermore, when the synchronization circuit 201 is provided in the DRAM, it can also process temperature data referenced when adjusting the update interval of the memory cells.

[0020] For example, the input data DATA is synchronized with the first series of clocks, and the clock Clk is synchronized with the second series of clocks. Therefore, the synchronization circuit 201 can transfer data from the first series of clocks to the second series of clocks.

[0021] The synchronization circuit 201 includes: a first D-type flip-flop circuit 211; a second D-type flip-flop circuit 213; and a third D-type flip-flop circuit 215. Here, the first D-type flip-flop circuit 211, the second D-type flip-flop circuit 213, and the third D-type flip-flop circuit 215 are examples of the first, second, and third synchronization circuits of the present invention, respectively. Additionally, the synchronization circuit 201 includes: two delay circuits 221 and 223; a two-input logic mutual exclusion OR gate 225; a two-input logic AND gate 227; and a two-input logic OR gate 229.

[0022] Input data DATA with a width of 1 bit is supplied to the input terminal D of the first D-type flip-flop circuit 211 and the input terminal D of the second D-type flip-flop circuit 213. Output data Q1 from the output terminal Q of the first D-type flip-flop circuit 211 is supplied to the input terminal D of the third type flip-flop circuit 215.

[0023] Delay circuit 221 delays the input clock Clk by a first specific delay time, outputting it as a first delayed clock Clk_d1. Delay circuit 223 delays the first delayed clock Clk_d1 by a second specific delay time, outputting it as a second delayed clock Clk_d2. Here, delay circuits 221 and 223 are examples of the first and second delay circuits of the present invention, respectively. Here, the input clock Clk, the first delayed clock Clk_d1, and the second delayed clock Clk_d2 are examples of the first, second, and third synchronization signals of the present invention, respectively.

[0024] The two-input logic mutex gate 225 takes the output data Q1 from the output terminal Q of the first D-type flip-flop circuit 211 and the output data Q2 from the output terminal Q of the second D-type flip-flop circuit 213, and performs a logical mutually exclusive OR operation on them, outputting a control signal qchk to display the result. Therefore, if the logic level of the output data Q1 from the output terminal Q of the first D-type flip-flop circuit 211 is the same as the logic level of the output data Q2 from the output terminal Q of the second D-type flip-flop circuit 213, the logic level of the control signal qchk is LOW; otherwise, it is HIGH.

[0025] The two-input AND gate 227 performs a logical AND operation between the control signal qchk and the second delayed clock Clk_d2, and outputs the result as the adaptive second delayed clock cclk. Therefore, if the logic level of the control signal qchk is HIGH, an adaptive second delayed clock cclk corresponding to the second delayed clock Clk_d2 is generated. However, if the logic level of the control signal qchk is LOW, no adaptive second delayed clock cclk corresponding to the second delayed clock Clk_d2 will be generated.

[0026] The two-input OR gate 229 takes the input clock Clk and the adaptive second delay clock cclk by performing a logical OR operation, and outputs the result as the master clock lclk.

[0027] The clock terminal CK of the first D-type flip-flop circuit 211 is supplied with the main clock lclk output from the two-input OR gate 229. The clock terminal CK of the second D-type flip-flop circuit 213 is supplied with the first delayed clock Clk_d1 from the first delay circuit 221. The clock terminal CK of the third D-type flip-flop circuit 215 is supplied with the second delayed clock Clk_d2 from the second delay circuit 223.

[0028] The first D-type flip-flop circuit 211 outputs output data Q1 from the output terminal Q. This output data Q1 is synchronized with the rising edge of the input data DATA supplied to the input terminal D and the rising edge of the master clock lclk supplied to the clock terminal CK from LOW to HIGH. The second D-type flip-flop circuit 213 outputs output data Q2 from the output terminal Q. This output data Q2 is synchronized with the rising edge of the input data DATA supplied to the input terminal D and the rising edge of the first delayed clock Clk_d1 supplied to the clock terminal CK from LOW to HIGH. The third D-type flip-flop circuit 215 outputs output data Q3 from the output terminal Q. This output data Q3 is synchronized with the rising edge of the data Q1 supplied to the input terminal D and the rising edge of the second delayed clock Clk_d2 supplied to the clock terminal CK from LOW to HIGH.

[0029] First, the input data DATA is synchronized with the master clock lclk in the first D-type flip-flop circuit 211. The master clock lclk is obtained by slightly delaying the input clock Clk using a two-input OR gate 229. The input data DATA synchronized with the master clock lclk is output as data Q1 from the output terminal Q of the first D-type flip-flop circuit 211. Next, the input data DATA is synchronized with the first delayed clock Clk_d1 in the second D-type flip-flop circuit 213. The first delayed clock Clk_d1 is obtained by delaying the input clock Clk using a delay circuit 221. The input data DATA synchronized with the first delayed clock Clk_d1 is output as data Q2 from the output terminal Q of the second D-type flip-flop circuit 213.

[0030] If the timing of the logic level change of the input data DATA is similar to the rising timing of the input clock Clk from LOW to HIGH (meaning that the set / hold boundaries required for the input data DATA of the input clock Clk are not guaranteed), there is a possibility that the output data Q1 of the first D-type flip-flop circuit 211 may become metastable. If the timing of the logic level change of the input data DATA is similar to the rising timing of the first delayed clock Clk_d1 (meaning that the set / hold boundaries required for the input data DATA of the first delayed clock Clk_d1 are not guaranteed), there is a possibility that the output data Q2 of the second D-type flip-flop circuit 213 may become metastable.

[0031] When the input data DATA maintains the same logic level, in the first D-type flip-flop circuit 211, the input data DATA is synchronized with the rise of the master clock lclk, which corresponds to the rise of the input clock Clk. Then, in the second D-type flip-flop circuit 213, if the input data DATA is synchronized with the first delayed clock Clk_d1, after the input data DATA is synchronized with the first delayed clock Clk_d1 in the second D-type flip-flop circuit 213, the logic level of the control signal qchk output from the two-input logic mutex gate 225 is LOW. Therefore, when the second delayed clock Clk_d2 rises, the logic level of the adaptive second delayed clock cclk supplied from the output terminal of the two-input logic AND gate 227 to the two-input logic OR gate 229 remains LOW, and the logic level of the master clock lclk also remains LOW. The input data DATA is no longer synchronized in the first D-type flip-flop circuit 211. Therefore, the logic level of the output data Q1 of the first D-type flip-flop circuit 211, which is synchronized with the rise of the master clock lclk, which corresponds to the rise of the input clock Clk, is maintained.

[0032] On the other hand, when the logic level of the input data DATA is a certain logic level (HIGH or LOW), in the first D-type flip-flop circuit 211, the input data DATA is synchronized by the rising of the master clock lclk corresponding to the rising of the input clock Clk. Then, since the logic level of the input data DATA changes to another logic level (LOW or HIGH), if the input data DATA is synchronized with the first delay clock Clk_d1 in the second D-type flip-flop circuit 213, the logic level of the control signal qchk output from the two-input logic mutex OR gate 225 is HIGH.

[0033] Therefore, even if the output data Q1 of the first D-type flip-flop circuit 211 or the output data Q2 of the second D-type flip-flop circuit 213 reaches a metastable state, and the second delayed clock Clk_d2 rises afterward, the logic level of the control signal qchk remains HIGH, and the adaptive second delayed clock cclk output from the two-input AND gate 227 also rises. Since the adaptive second delayed clock cclk is input to one of the input terminals of the two-input OR gate 229, and the logic level of the other input terminal remains LOW, the master clock lclk output from the two-input OR gate 229 delays the second delayed clock Clk_d2 by the two-input AND gate 227 and the two-input OR gate 229 before rising. Therefore, the master clock lclk corresponds to the rise of the second delayed clock Clk_d2, and the input data DATA is synchronized again in the first D-type flip-flop circuit 211 according to the rise of the master clock lclk.

[0034] The logic level of the output data Q1 of the first D-type flip-flop circuit 211, which is updated synchronously with the rising master clock lclk corresponding to the rising input clock Clk, becomes updated synchronously with the rising master clock lclk corresponding to the rising second delay clock Clk_d2. Furthermore, in this embodiment, the two-input logic mutex OR gate 225, the two-input logic AND gate 227, the two-input logic OR gate 229, and the first D-type flip-flop circuit 211 are examples of the resynchronization circuit of the present invention.

[0035] Reference Figure 2 This section describes an example of a situation where the input data DATA is not resynchronized in the first D-type flip-flop circuit 211.

[0036] At time t11, the logic level of the input data DATA changes from LOW to HIGH. At time tc1, the input data with a logic level of HIGH is synchronized in the first D-type flip-flop circuit 211 according to the rise of the master clock lclk, which corresponds to the rise of the input clock Clk. The logic level of the output data Q1 of the first D-type flip-flop circuit 211 becomes HIGH at time t12, slightly delayed from the rise of the input clock Clk at time tc1. At time tc2, the input data DATA with a logic level of HIGH is synchronized in the second D-type flip-flop circuit 213 according to the rise of the first delayed clock Clk_d1. The logic level of the output data Q2 of the second D-type flip-flop circuit 213 becomes HIGH at time t13, slightly delayed from the rise of the first delayed clock Clk_d1 at time tc2.

[0037] The logic level of the control signal qchk is HIGH from time t12 to time t13, but LOW after time t13. At time tc3, when the second delayed clock Clk_d2 rises, since the logic levels of output data Q1 and Q2 are the same, the logic level of the control signal qchk is LOW, and no adaptive second delayed clock cclk is generated. Therefore, the resynchronization in the first D-type flip-flop circuit 211 according to the rise of the master clock lclk corresponding to the rise of the second delayed clock Clk_d2 does not occur. By synchronizing with the rise of the master clock lclk corresponding to the rise of the input clock Clk, the logic level of the output data Q1 of the first D-type flip-flop circuit 211 updated at time t12 is maintained. The output data Q1, which is synchronized only once in the first D-type flip-flop circuit 211, is then synchronized in the third D-type flip-flop circuit 215 at the rise of the second delayed clock Clk_d2, and is output as output data Q3 from the output terminal Q of the third D-type flip-flop circuit 215.

[0038] Reference Figure 3This describes an example of a situation where the output data Q1 of the first D-type flip-flop circuit 211 becomes metastable, and therefore the input data DATA is resynchronized in the first D-type flip-flop circuit 211 according to the rise of the master clock lclk corresponding to the rise of the second delay clock Clk_d2.

[0039] At time tc1, the input data DATA, whose logic level changes from LOW to HIGH, is synchronized in the first D-type flip-flop circuit 211 according to the rise of the master clock lclk, which corresponds to the rise of the input clock Clk. However, because the necessary set / hold boundaries for the input data DATA of the input clock Clk are not ensured, the output data Q1 of the first D-type flip-flop circuit 211 becomes metastable after time tc1. Furthermore, through resynchronization described later, after time t22, the logic level of the output data Q1 of the first D-type flip-flop circuit 211 stabilizes at HIGH. At time tc2, the input data DATA, whose logic level is HIGH, is synchronized in the second D-type flip-flop circuit 213 according to the rise of the first delayed clock Clk_d1. The logic level of the output data Q2 of the second D-type flip-flop circuit 213 becomes HIGH after time t21, which is slightly delayed from the rise of the first delayed clock Clk_d1.

[0040] As described above, the output data Q1 of the first D-type flip-flop circuit 211 is in a metastable state from time tc1 to time t22. However, in the two-input logic mutex OR gate 225, the logic level is determined to be LOW. If the logic levels of output data Q1 and Q2 are different, the logic level of the control signal qchk output from the two-input logic mutex OR gate 225 will become HIGH. Therefore, the logic level of the control signal qchk is HIGH from time t21.

[0041] At time tc3, when the second delayed clock Clk_d2 rises, the logic level of the control signal qchk is HIGH, and the adaptive second delayed clock cclk also rises. Although not shown in the diagram, around time tc3, the logic level of the input clock Clk is LOW, and the corresponding main clock lclk, which also rises when the adaptive second delayed clock cclk rises, also rises.

[0042] Therefore, based on the rising of the master clock lclk corresponding to the rising of the second delayed clock Clk_d2, resynchronization is performed in the first D-type flip-flop circuit 211. At time t22, the logic level of the output data Q1 of the first D-type flip-flop circuit 211 is updated to the same HIGH as the logic level of the input data DATA, and the logic level of the control signal qchk becomes LOW. The output data Q1, which is resynchronized in the first D-type flip-flop circuit 211, is then synchronized in the third D-type flip-flop circuit 215 at the rising of the second delayed clock Clk_d2, and is output as output data Q3 from the output terminal Q of the third D-type flip-flop circuit 215.

[0043] Reference Figure 4 This illustrates an example where the output data Q2 of the second D-type flip-flop circuit 213 becomes metastable, and therefore the input data DATA is resynchronized in the first D-type flip-flop circuit 211 according to the rise of the master clock lclk corresponding to the rise of the second delay clock Clk_d2.

[0044] At time tc1, the input data DATA, with a logic level of LOW, is synchronized in the first D-type flip-flop circuit 211 according to the rise of the master clock lclk, which corresponds to the rise of the input clock Clk. The logic level of the output data Q1 of the first D-type flip-flop circuit 211 becomes LOW after a slight delay from the rise of the input clock Clk at time tc1. Furthermore, Figure 4 In the example, the logic level of the output data Q1 of the first D-type flip-flop circuit 211 is also LOW before time t31. At time tc2, the input data DATA, whose logic level changes from LOW to HIGH, is synchronized in the second D-type flip-flop circuit 213 according to the rising of the first delayed clock Clk_d1. However, because the necessary set / hold boundaries for the input data DATA of the first delayed clock Clk_d1 are not ensured, the output data Q2 of the second D-type flip-flop circuit 213 becomes metastable after time tc2. Furthermore, after time tc3, the logic level of the output data Q2 of the second D-type flip-flop circuit 213 stabilizes at HIGH.

[0045] Therefore, from time tc2 to time tc3, although the output data Q2 of the second D-type flip-flop circuit 213 is in a metastable state, the logic level in the two-input logic mutex OR gate 225 is determined to be HIGH. Since the logic levels of output data Q1 and Q2 are different, after time tc2, the logic level of the control signal qchk output from the two-input logic mutex OR gate 225 is HIGH. At time tc3, corresponding to the rise of the second delay clock Clk_d2, the logic level of the control signal qchk is HIGH, and the adaptive second delay clock cclk also rises. Although not shown in the diagram, around time tc3, the logic level of the input clock Clk is LOW, and the main clock lclk, corresponding to the rise of the adaptive second delay clock cclk, also rises.

[0046] Therefore, based on the rise of the master clock lclk corresponding to the rise of the second delayed clock Clk_d2, resynchronization is performed in the first D-type flip-flop circuit 211. At time t32, the logic level of the output data Q1 of the first D-type flip-flop circuit 211 is updated to the same HIGH as the logic level of the input data DATA. The output data Q1, which is resynchronized in the first D-type flip-flop circuit 211, is then synchronized in the third D-type flip-flop circuit 215 at the rise of the second delayed clock Clk_d2, and is output as output data Q3 from the output terminal Q of the third D-type flip-flop circuit 215.

[0047] Furthermore, if the sum of the first specific delay time via delay circuit 221 and the second specific delay time via delay circuit 223 is shorter than the period during which the input data DATA maintains the same logic level (e.g., the clock period of the input data DATA), the output data Q3 can be stably output from the synchronization circuit 201, and even if the output data Q1 becomes metastable after the initial synchronization, a stable output data Q1 can be obtained by resynchronization.

[0048] Figure 5 The synchronization circuit 203 based on the second embodiment is shown. When compared with the synchronization circuit 201 based on the first embodiment, the synchronization circuit 203 differs in the following aspects: the first D-type flip-flop circuit 211 and the second D-type flip-flop circuit 213 are replaced by the first latch circuit 241 and the second latch circuit 243, respectively; the third D-type flip-flop circuit 215 is omitted.

[0049] Additionally, refer to Figure 1 as well as Figure 5When comparing the synchronization circuit 203 with the synchronization circuit 201 based on the first embodiment, the following differences exist: the input clock Clk, the first delayed clock Clk_d1, and the second delayed clock Clk_d2 are respectively replaced by the input strobe signal Str, the first delayed strobe signal str_d1, and the second delayed strobe signal str_d2. The input strobe signal Str, the first delayed strobe signal str_d1, and the second delayed strobe signal str_d2 are other examples of the first synchronization signal, the second synchronization signal, and the third synchronization signal of the present invention. Furthermore, the adaptive second delayed clock cclk and the main clock lclk are respectively replaced by the adaptive second delayed strobe signal sstr and the main strobe signal lstr.

[0050] like Figure 9 As shown, at the rising moment tc1 of the input clock Clk, the input strobe signal Str decreases. At the rising moment tc2 of the first delayed clock Clk_d1, the first delayed strobe signal str_d1 decreases. At the rising moment tc3 of the second delayed clock Clk_d2, the second delayed strobe signal str_d2 decreases.

[0051] Additionally, the adaptive second delay strobe signal sstr, like the adaptive second delay clock cclk, is generated when the logic level of the control signal qchk is HIGH, and not generated otherwise. When the adaptive second delay strobe signal sstr is generated, it decreases at the same time as the rise of the adaptive second delay clock cclk. The main strobe signal lstr used for the first synchronization decreases at the same time as the rise of the main clock lclk used for the first synchronization. Furthermore, the main strobe signal lstr used for resynchronization decreases at the same time as the rise of the main clock lclk used for resynchronization.

[0052] Generally, a D-type flip-flop circuit is configured to output data in sync with the rising edge of the input clock. Conversely, a latch circuit maintains the input data as output data while the logic level of the strobe signal is HIGH, but maintains the output data at the logic level of the input data when the strobe signal falls. Therefore, the first latch circuit 241 and the second latch circuit 243 based on the second embodiment operate in the same way as the first D-type flip-flop circuit 211 and the second D-type flip-flop circuit 213 based on the first embodiment. Because replacing the D-type flip-flop circuit with a latch circuit reduces the circuit size.

[0053] In the second embodiment, there is no third latch circuit corresponding to the third D-type flip-flop circuit 215 in the first embodiment. However, a third latch circuit corresponding to the third D-type flip-flop circuit 215 may also be provided.

[0054] In a dynamic random access memory (DRAM), there is a renewal circuit for recharging storage cells to gradually reduce accumulated charge. In this renewal circuit, there are cases where the temperature data referenced for renewal rate control consists of multiple bit widths. When this multiple bit width temperature data is used as input data to a synchronization circuit, a clock transition is required. Synchronization circuits based on the first and second embodiments process input data consisting of only one bit width. However, for example, if multiple synchronization circuits processing only one bit width are arranged in parallel, the operation of the synchronization circuits may differ between bit widths, preventing correct clock transitions. That is, while resynchronization may occur in a synchronization circuit corresponding to a certain bit width, it may not occur in synchronization circuits corresponding to other bit widths, resulting in incorrect clock transitions. A synchronization circuit based on the third embodiment was developed to avoid such problems.

[0055] Figure 6 The synchronization circuit 205 based on the third embodiment is shown. In the synchronization circuit 203 based on the second embodiment, the number of bits of the input data DATA is 1, while in the synchronization circuit 205 based on the third embodiment, the number of bits of the input data DATA is a complex number n (n is an integer greater than or equal to 2).

[0056] When comparing the synchronization circuit 205 based on the third embodiment with the synchronization circuit 203 based on the second embodiment, the following differences exist: the first latch circuit 241, the second latch circuit 243, and the two-input logic mutex OR gate 225 are respectively replaced by a complex number (n in this case) of first latch circuits 241-1 to 241-n, a complex number (n in this case) of second latch circuits 243-1 to 243-n, and a complex number (n in this case) of two-input logic mutex OR gates 225-1 to 225-n; and an additional n-input logic OR gate 231 is added.

[0057] Multiple first latch circuits 241-1 to 241-n latch n-bit wide input data DATA using the main strobe signal lstr. <n:1>Q1 is the output data with an n-bit width. <n:1>Output. Multiple second latch circuits 243-1 to 243-n latch n-bit wide input data DATA using the first delayed strobe signal str_d1. <n:1>Q2 is the output data with an n-bit width. <n:1>Output. Calculate the output data Q1 from the i-th two-input logic mutex OR gate 225-1 to 225-n (i=1,2,…,n). <n:1>The i-th bit width and output data Q2 <n:1>The i-th bit-width logical mutual exclusion OR is used as the result to prepare the control signal Qchk. <n:1>The i-th bit width is output. The n-input logic OR gate 231 prepares the control signal Qchk. <n:1>The logic OR calculation will display the result, and the control signal QchkN will be supplied from the output terminal to one of the input terminals of the two-input AND gate 227. The two-input AND gate 227 and the two-input OR gate 229 are the same as those in the second embodiment.

[0058] Next, output data Q1 <n:1>And output data Q2 <n:1>Each bit width is compared using multiple two-input logic mutex gates 225-1 to 225-n. If the multiple two-input logic mutex gates 225-1 to 225-n are in the preparatory control signal Qchk at the output... <n:1>Display output data Q1 <n:1>And output data Q2 <n:1>Different in at least one bit width, when the main strobe signal lstr decreases corresponding to the decrease of the corresponding adaptive second delayed strobe signal sstr, the input data DATA <n:1>It is then latched again in multiple first latch circuits 241-1 to 241-n.

[0059] Reference Figure 7 Explain the n-bit wide input data DATA <n:1>There are no examples of cases where latching occurs again in multiple first latch circuits 241-1 to 241-n.

[0060] When the main strobe signal lstr decreases in response to the decrease of the corresponding input strobe signal Str, the n-bit wide input data DATA... <n:1>It is latched in multiple first latch circuits 241-1 to 241-n. Therefore, the output data Q1 of the multiple first latch circuits 241-1 to 241-n <n:1>It varies at time t41, which is slightly delayed from the moment tc1 when the input strobe signal Str drops.

[0061] When the first delayed strobe signal str_d1 falls, the n-bit wide input data DATA <n:1>It is latched in the second latch circuits 243-1 to 243-n. Therefore, the output data Q2 of the multiple second latch circuits 243-1 to 243-n is... <n:1>It changes at time t42, which is slightly delayed from the moment tc2 when the first delayed strobe signal str_d1 falls.

[0062] During the period from time t41 to time t42, the output data Q2 of multiple second latch circuits 243-1 to 243-n <n:1>At least a portion of the bit width of the logic level becomes the output data Q1 of the multiple first latch circuits 241-1 to 241-n. <n:1>The corresponding bit widths are inconsistent. Therefore, the preparatory control signal Qchk output from multiple two-input logic mutual exclusion OR gates 225-1 to 225-n is inconsistent. <n:1>At least one logic level of the input logic OR gate 231 becomes HIGH, and the logic level of the control signal QchkN output by the input logic OR gate 231 becomes HIGH.

[0063] After time t42, the output data Q2 of multiple second latch circuits 243-1 to 243-n <n:1>The logic level, and the output data Q1 of multiple first latch circuits 241-1 to 241-n <n:1>The logic level is consistent across all bit widths. Therefore, all preparatory control signals Qchk output from multiple two-input logic mutex OR gates 225-1 to 225-n are... <n:1>The logic level of the input is LOW, and the logic level of the control signal QchkN output by the n-input OR gate 231 is LOW.

[0064] At the moment tc3 when the second delayed strobe signal str_d2 falls, the logic level of the control signal QchkN becomes LOW. Therefore, the adaptive second delayed strobe signal sstr and the main strobe signal lstr do not fall, and re-latching does not occur in the multiple first latch circuits 241-1 to 241-n. The output data Q1 of the multiple first latch circuits 241-1 to 241-n that are latched... <n:1>The logic level is not updated by re-latching and remains unchanged.

[0065] Furthermore, during the period of length tTRAN from time tc3 to time t43, even if the n-bit wide input data DATA... <n:1>The output data Q1 of the multiple first latch circuits 241-1 to 241-n has changed. <n:1>The logic level remains unchanged. n-bit wide input data DATA <n:1>From time tc3 to time t43, it varies with the offset between bit widths.

[0066] Reference Figure 8 This indicates that when the main strobe signal lstr decreases in response to the decrease of the second delayed strobe signal str_d2, the n-bit wide input data DATA... <n:1>Examples of cases where latching occurs in multiple first latch circuits 241-1 to 241-n.

[0067] n-bit wide input data DATA <n:1>Based on the decrease of the main strobe signal lstr corresponding to the decrease of the input strobe signal Str, the signal is latched in multiple first latch circuits 241-1 to 241-n. Therefore, the output data Q1 of the multiple first latch circuits 241-1 to 241-n is... <n:1>It changes at a time t51, which is slightly delayed from the time tc1 when the input signal decreases.

[0068] and Figure 7 Similarly, starting from time t51, the output data Q1 of multiple first latch circuits 241-1 to 241-n <n:1>At least a portion of the bit width of the logic level becomes the output data Q2 of the multiple second latch circuits 243-1 to 243-n. <n:1>The corresponding bit widths are inconsistent. Therefore, starting from time t51, the preparatory control signal Qchk output by multiple two-input logic mutually exclusive OR gates 225-1 to 225-n is... <n:1>At least one logic level of the input logic OR gate 231 becomes HIGH, and the logic level of the control signal QchkN output by the input logic OR gate 231 becomes HIGH.

[0069] and Figure 7 The examples differ; around the time tc2 when the first delayed strobe signal str_d1 falls, the n-bit wide input data DATA... <n:1>The logic level changes. Set the n-bit wide input data DATA. <n:1>Based on the decrease of the first delayed strobe signal str_d1, it is latched in multiple second latch circuits 243-1 to 243-n.

[0070] Assume that at time tc2, the input data DATA is n bits wide. <n:1>The logic level of each bit width, and the n-bit wide input data DATA at time tc1. <n:1>The corresponding bit width logic levels are the same, in the corresponding Figure 7 After time t42 and time t52, the logic level of the control signal QchkN becomes LOW. Additionally, at... Figure 8 The example shown is for a case where the logic level of the control signal QchkN becomes LOW after time t52.

[0071] As mentioned above, around time tc2, due to the n-bit wide input data DATA <n:1>The logic level changes do not ensure that the input data DATA meets the set / hold boundaries required for the fall of the first delayed strobe signal str_d1. Therefore, the output data Q2 of the multiple second latch circuits 243-1 to 243-n is affected. <n:1>At least a portion of the bit width becomes metastable. Alternatively, the output data Q2 of multiple second latch circuits 243-1 to 243-n. <n:1>At least a portion of the bit width of the logic level, and the output data Q1 of the multiple first latch circuits 241-1 to 241-n. <n:1>The logic levels corresponding to the bit widths remain inconsistent. Therefore, after time t51, the logic levels of the outputs of at least a portion of the multiple two-input logic mutexes 225-1 to 225-n, whose logic levels are HIGH, remain inconsistent. Figure 7 The HIGH level remains after time t42 and time t52. Therefore, as Figure 8 As shown, the logic level of the control signal QchkN remains HIGH after time t52.

[0072] At the moment tc3 when the second delayed strobe signal str_d2 decreases, the logic level of the control signal QchkN is HIGH, and the adaptive second delayed strobe signal sstr also decreases. When the main strobe signal lstr, corresponding to the decrease of the adaptive second delayed strobe signal sstr, decreases, the input data DATA... <n:1>The data is then latched again in multiple first latch circuits 241-1 to 241-n. Therefore, at time t53, the output data Q1 of the multiple first latch circuits 241-1 to 241-n is... <n:1>The logic level is updated.

[0073] Furthermore, if the sum of the first specific delay time via delay circuit 221 and the second specific delay time via delay circuit 223 is set to be shorter than the time obtained by subtracting the maximum offset time from the period during which the input data DATA maintains the same logic level (e.g., the clock period of the input data DATA), the output data Q3 can be stably output from the synchronization circuit 205, and even if the output data Q1 becomes metastable after the initial synchronization, a stable output data Q1 can be obtained by resynchronization.

Claims

1. A synchronous circuit, characterized in that, include: The first delay circuit delays the input synchronization signal by a first specific time to generate a first delayed synchronization signal. The second delay circuit delays the first delay synchronization signal by a second specific time to generate a second delay synchronization signal. The first synchronization circuit outputs first output data that synchronizes the input data with the input synchronization signal. The second synchronization circuit outputs second output data that synchronizes the input data with the first delayed synchronization signal. If the first output data and the second output data are inconsistent, the resynchronization circuit generates an adaptive second delay synchronization signal corresponding to the second delay synchronization signal. The adaptive second delay synchronization signal is obtained by performing a first logic operation on the first output data and the second output data, and then performing a second logic operation on the second delay synchronization signal. The input data is resynchronized according to the adaptive second delay synchronization signal, and the first output data of the first synchronization circuit is updated. If the first output data and the second output data are consistent, the adaptive second delay synchronization signal will not be generated.

2. The synchronization circuit as described in claim 1, characterized in that, Also includes: The third synchronization circuit outputs third output data that synchronizes the first output data with the second delayed synchronization signal.

3. The synchronization circuit as described in claim 1 or 2, characterized in that, The sum of the first specific time and the second specific time is shorter than the shortest duration of the input data.

4. The synchronization circuit as described in claim 1, characterized in that, The input data, the first output data, and the second output data each contain multiple bit widths; If the first output data and the second output data have at least one bit width difference, the resynchronization circuit resynchronizes the input data according to the second delay synchronization signal and updates the first output data of the first synchronization circuit.

5. The synchronization circuit as described in claim 1, characterized in that, The first synchronization circuit is a first D-type flip-flop circuit, and the second synchronization circuit is a second D-type flip-flop circuit.

6. The synchronization circuit as described in claim 1, characterized in that, The first synchronization circuit is a first latch circuit, and the second synchronization circuit is a second latch circuit.

7. The synchronization circuit as described in claim 1, characterized in that, The resynchronization circuit includes a first two-input logic gate, which takes the output data from the output terminal of the first D-type flip-flop circuit and the output data from the output terminal of the second D-type flip-flop circuit, performs the first logic operation, and outputs a control signal for displaying the result. If the logic level of the output data from the output terminal of the first D-type flip-flop circuit is consistent with the logic level of the output data from the output terminal of the second D-type flip-flop circuit, the logic level of the control signal is low; otherwise, it is high. The first logic operation is a logical mutually exclusive OR.

8. The synchronization circuit as described in claim 7, characterized in that, The resynchronization circuit further includes a second two-input logic gate, which takes the control signal and the second delay clock and performs the second logic operation, and outputs the result as an adaptive second delay clock; therefore, if the logic level of the control signal is high, an adaptive second delay clock corresponding to the second delay clock is generated, wherein the second logic operation is a logical AND.

9. The synchronization circuit as described in claim 8, characterized in that, The resynchronization circuit further includes a two-input OR gate, which performs a logical OR operation on the input clock and an adaptive second delay clock, outputs the result as the master clock, and supplies the master clock output from the two-input OR gate to the clock terminal of the first D-type flip-flop circuit.

10. The synchronization circuit as described in claim 1, characterized in that, The resynchronization circuit includes: A two-input logic mutual exclusion OR gate is used to calculate the logical mutual exclusion OR of the i-th bit width of the first output data and the i-th bit width of the second output data, and the result is output as the i-th bit width of the pre-control signal; and An n-input AND gate performs a logical OR calculation on the preparatory control signal, and a control signal that displays the result is supplied from the output terminal to one of the input terminals of the two-input AND gate.

11. A semiconductor device, characterized in that, Includes the synchronization circuit of claim 1.

12. A synchronization method, characterized in that, include: The acquisition step involves delaying the input synchronization signal by a first specific time to generate a first delayed synchronization signal. The first delayed synchronization signal is delayed by a second specific time to generate a second delayed synchronization signal; first data synchronized with the input synchronization signal is acquired; and second data synchronized with the first delayed synchronization signal is acquired. The comparison step compares first data that is synchronized with the input data by a synchronization signal, and second data that is synchronized with the input data based on a signal that delays the synchronization signal. In the output step, if the first data and the second data are different, an adaptive second delay synchronization signal corresponding to the second delay synchronization signal is generated. The adaptive second delay synchronization signal is obtained by performing a first logic operation on the first data and the second data, and then performing a second logic operation on the second delay synchronization signal. The input data is synchronized by delaying the synchronization signal by more according to the adaptive second delay synchronization signal. If the first data and the second data are the same, the adaptive second delay synchronization signal is not generated, and the first data is output.

13. The synchronization method as described in claim 12, characterized in that, The input data contains multiple bit widths; The comparison step compares each bit width of the first data and the second data; If the first data and the second data have at least one different bit width, the output step outputs the data that synchronizes the input data based on a signal that delays the synchronization signal by more; otherwise, it outputs the first data.

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