Methods of forming package structures and dies

Abstract

This disclosure provides a method for forming a package structure, including forming a die and forming an encapsulation body on the side of the die to encapsulate and contact the sidewalls of the die's substrate and passivation layer. Forming the die includes forming a first pad and a second pad, a passivation layer, and a connector. Forming the connector includes forming a seed layer. The seed layer includes a first seed layer and a second seed layer located on the first seed layer. A first etching process is performed to remove the seed layer not covered by conductive pillars, leaving a first width of the first seed layer smaller than the first width of the conductive pillars. A second etching process is performed to remove test pads, wherein the conductive pillars are consumed during the second etching process, such that the base portion of the seed layer laterally protrudes from the sidewall of the conductive pillar.

Description

[0001] This disclosure is a divisional application of the invention patent application filed on May 8, 2019, with application number 201910381673.9 and the invention title "Encapsulation Structure, Chip and Manufacturing Method Thereof". Technical Field

[0002] This disclosure relates to a method for forming a packaging structure and a die. Background Technology

[0003] The semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). To a large extent, this increase in integration density stems from the continuous reduction in the minimum feature size, allowing more smaller components to be integrated into a given area. These smaller electronic components also require smaller packages with smaller areas compared to previous packages. Some smaller types of semiconductor component packages include quad flat packages (QFP), pin grid array (PGA) packages, ball grid array (BGA) packages, and so on.

[0004] Currently, integrated fan-out packages are becoming increasingly popular due to their compactness. Summary of the Invention

[0005] This disclosure provides a method for forming a package structure, characterized by comprising the following steps: forming a die, including forming the connector, comprising the following steps: forming a first pad and a second pad on a substrate; forming a passivation layer to cover a portion of the first pad and a portion of the second pad; forming the connector, the connector passing through the passivation layer and electrically connected to the first pad and the second pad, wherein the connector extends from the first pad to cover a portion of the passivation layer located between the first pad and the second pad, and continues to extend over the second pad; forming the connector comprises the following steps: forming a seed layer on the first pad, the portion of the passivation layer, and the second pad, wherein the seed layer includes a first seed layer and a second seed layer located on the first seed layer. A patterned mask layer with openings is formed on the seed layer, wherein the first and second seed layers of the seed layer are unpatterned layers, located between the patterned mask layer and the first pad, between the patterned mask layer and a portion of the passivation layer, and between the patterned mask layer and the second pad. Conductive pillars are formed in the openings of the patterned mask layer. Test pads are formed on the conductive pillars. The patterned mask layer is removed. A first etching process is performed to remove the seed layer not covered by the conductive pillars, leaving a first width of the first seed layer smaller than the first width of the conductive pillars. Electrical testing is performed through the test pads. A second etching process is performed to remove the test pads, wherein the conductive pillars are consumed during the second etching process, such that the base of the seed layer laterally protrudes from the sidewall of the conductive pillar. The seed layer comprises a first seed layer and a second seed layer located between the first seed layer and the conductive pillar, and the edges of the seed layer include a stepped structure. The material of the second seed layer is different from the material of the first seed layer but the same as the material of the conductive pillar. An encapsulation is formed on the die side to encapsulate and contact the sidewalls of the substrate and the passivation layer of the die. A redistribution layer structure is formed on the die and the encapsulation layer. Conductive terminals are formed, and the conductive terminals are electrically connected to the die via the redistribution layer structure.

[0006] This disclosure provides a method for forming a die, characterized by the following steps: Forming a pad on a substrate. Forming a passivation layer to cover a portion of the pad. Forming a connector that passes through the passivation layer and is electrically connected to the pad, and forming the connector. Forming a seed layer on the pad and the portion of the passivation layer, wherein the seed layer includes a first seed layer and a second seed layer located on the first seed layer. Forming a patterned mask layer with openings, wherein the first seed layer and the second seed layer of the seed layer are unpatterned layers covering the passivation layer, and the first seed layer and the second seed layer of the seed layer separate the passivation layer from the patterned mask layer. Forming conductive pillars in the openings of the patterned mask layer. Forming test pads on the conductive pillars. Removing the patterned mask layer. Performing a first etching process to remove the portion of the seed layer not covered by the conductive pillars, leaving a first width of the first seed layer smaller than the first width of the conductive pillars. Performing electrical testing through the test pads. A second etching process is performed to remove the test pad, wherein the conductive post is consumed during the etching process such that the base portion of the seed layer laterally protrudes from the sidewall of the conductive post, wherein the seed layer includes the first seed layer and the second seed layer located between the first seed layer and the conductive post, and the edge of the seed layer includes a stepped structure.

[0007] This disclosure provides a method for forming a die, characterized by the following steps: Forming a pad on a substrate. Forming a passivation layer to cover a portion of the pad. Forming a connector that passes through the passivation layer and is electrically connected to the pad, the connector forming the connector including the following steps: Forming a seed layer on the pad and the portion of the passivation layer, wherein the seed layer includes a first seed layer and a second seed layer located on the first seed layer. Forming a patterned mask layer with openings, wherein the first seed layer and the second seed layer of the seed layer are unpatterned layers covering the passivation layer, and the first seed layer and the second seed layer of the seed layer separate the passivation layer from the patterned mask layer. Forming conductive pillars in the openings of the patterned mask layer. Forming test pads on the conductive pillars. Removing the patterned mask layer. Performing a first etching process to remove the seed layer not covered by the conductive pillars, forming an undercut below the conductive pillars. Performing electrical testing through the test pads. A second etching process is performed to remove the test pads and a portion of the conductive pillars, reducing the width of the remaining conductive pillars, wherein the base portion of the seed layer laterally protrudes from the sidewall of the conductive pillar. The seed layer includes a first seed layer and a second seed layer located between the first seed layer and the conductive pillar, and the edge of the seed layer includes a stepped structure. Attached Figure Description

[0008] Figures 1A to 1J This is a schematic cross-sectional view illustrating a method of forming an encapsulation structure according to some embodiments of the present disclosure.

[0009] Figures 2 to 4 These are schematic cross-sectional views showing packaging structures according to some embodiments of the present disclosure.

[0010] Figure 5 This is a schematic cross-sectional view of a package-on-package (PoP) device according to some embodiments of the present disclosure. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a second feature on or over a first feature may include embodiments in which the second feature and the first feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the second feature and the first feature such that the second feature and the first feature are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the sake of brevity and clarity and does not in itself imply a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of explanation, this document may use spatial relative terms such as “beneath,” “below,” “lower,” “on,” “above,” and “upper” to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein may be interpreted accordingly.

[0013] This disclosure may also include other features and processes. For example, it may include test structures for verifying three-dimensional (3D) packaged or three-dimensional integrated circuit (3DIC) devices. The test structure may include, for example, test pads formed in a redistribution layer or on a substrate, to enable testing of the 3D package or 3D IC, use of probes and / or probe cards, etc. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0014] Figures 1A to 1J This is a schematic cross-sectional view illustrating a method of forming an encapsulation structure according to some embodiments of the present disclosure, wherein Figures 1A to 1F A method for forming a die according to some embodiments of the present disclosure is shown.

[0015] Reference Figure 1AA wafer is provided, the wafer comprising a plurality of dies 30. For simplicity, one die 30 is shown. In some embodiments, the dies 30 are arranged in an array in the wafer prior to performing a die-cutting process, but this disclosure is not limited thereto. In some other embodiments, the dies 30 are provided after performing a die-cutting process. That is, the dies 30 may have been cut from the wafer.

[0016] In some embodiments, the die 30 includes a substrate 13, a dielectric structure 14, an interconnect structure 15, a pad 16, and a passivation layer 17. In some embodiments, the substrate 13 is made of silicon or other semiconductor materials. Alternatively, or additionally, the substrate 13 may contain other elemental semiconductor materials, such as germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the substrate 13 may also include other features, such as various doped regions, buried layers, and / or epitaxial layers. Furthermore, in some embodiments, the substrate 13 is made of alloy semiconductors such as silicon germanium, silicon carbide germanium, gallium arsenide, or gallium indium phosphide. Additionally, the substrate 13 may be a semiconductor on insulator, such as silicon on insulator (SOI) or silicon on sapphire.

[0017] In some embodiments, a device (not shown) is formed in or on the substrate 13. In some embodiments, the device may be an active device, a passive device, or a combination thereof. In some embodiments, the device is an integrated circuit device. The device is, for example, a transistor, a capacitor, a resistor, a diode, a photodiode, a fuse, etc.

[0018] Interconnect structures 15 and dielectric structures 14 are formed on substrate 13 and over devices. Interconnect structures 15 are formed within dielectric structures 14 and connect to different devices to form functional circuitry. In some embodiments, dielectric structure 14 includes an inter-layer dielectric layer (ILD) and one or more inter-metal dielectric layers (IMDs). In some embodiments, interconnect structures 15 include multilayer metal wires and plugs (not shown). The metal wires and plugs comprise conductive materials, such as metals, metal alloys, or combinations thereof. For example, conductive materials may include tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or combinations thereof. Plugs include contact plugs and via plugs. Contact plugs are located in the ILD to connect to the metal wires and devices. Via plugs are located in the IMD to connect to metal wires in different layers.

[0019] A pad 16 is formed on the interconnect structure 15. The pad 16 is electrically connected to the interconnect structure 15 to provide external connectivity to the die 30. In some embodiments, the pad 16 is a top conductive feature of the interconnect structure 15. The material of the pad 16 may include a metal or metal alloy, such as aluminum, copper, nickel, or alloys thereof.

[0020] A passivation layer 17 is formed on the substrate 13 and covers a portion of the pad 16. A portion of the pad 16 is exposed by the passivation layer 17 and serves as an external connection for the die 30. The passivation layer 17 comprises an insulating material, such as silicon oxide, silicon nitride, a polymer, or a combination thereof. Polymers include, for example, polybenzoxazole (PBO), polyimide (PI), benzocyclobutene (BCB), and combinations thereof. The passivation layer 17 has an opening 18 exposing a portion of the pad 16. The passivation layer 17 can be a single-layer or multi-layer structure.

[0021] In some embodiments, the passivation layer 17 is a two-layer structure and includes a first passivation sublayer 17a and a second passivation sublayer 17b located on the first passivation sublayer 17a. The material of the first passivation sublayer 17a and the material of the second passivation sublayer 17b may be the same or different. In some embodiments, the second passivation sublayer 17b is also referred to as a post-passivation layer and is optionally formed. In some embodiments, the first passivation sublayer 17a may be a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a dielectric layer formed of other suitable dielectric materials. The second passivation sublayer 17b may be a polymer layer, such as comprising PBO, PI, BCB, combinations thereof, etc. However, this disclosure is not limited thereto.

[0022] The first passivation sublayer 17a and the second passivation sublayer 17b can be formed by the following process: a first passivation material layer is formed on the substrate 13 by spin coating, chemical vapor deposition (CVD), or other suitable techniques to cover the pad 16; then, the first passivation material layer is patterned by photolithography and etching processes to form openings in the first passivation material layer to expose portions of the pad 16. Next, a second passivation material layer (e.g., a polymer layer) is formed on the first passivation sublayer 17a and the pad 16, for example, by spin coating. Then, a curing process is performed to cure the polymer layer. Next, a laser drilling process is performed to pattern the second passivation material layer to form openings 18 to expose the pad 16. In some embodiments where the second passivation sublayer 17b is a PI layer, the curing process temperature ranges from 300°C to 400°C (e.g., 390°C), and the PI layer may also be referred to as a high-temperature PI layer.

[0023] Reference Figure 1B A seed layer 19 is formed on the substrate 13 using a physical vapor deposition (PVD) process (e.g., sputtering). In some embodiments, the seed layer 19 may be a copper seed layer or other suitable metal seed layer. The material of the seed layer 19 may include titanium (Ti), titanium-tungsten (TiW), tantalum (Ta), copper (Cu), or combinations thereof. The seed layer 19 may be a single-layer structure or a multi-layer structure. In some embodiments, the seed layer 19 includes a first seed layer (e.g., a titanium layer) and a second seed layer (e.g., a copper layer) located on the first seed layer.

[0024] In some embodiments, the seed layer 19 conformally covers the pad 16 and the passivation layer 17. That is, the seed layer 19 has a substantially equal thickness extending along the region on which the seed layer 19 is formed. The seed layer 19 is in electrical contact with the pad 16 and is further electrically connected to the interconnect structure 15 through the pad 16. The seed layer 19 covers the top surface of the passivation layer 17 and fills the opening 18 to cover the sidewalls of the passivation layer 17 and the top surface of the pad 16 exposed by the opening 18.

[0025] Reference Figure 1C A patterned mask layer 20 with openings 21 is formed on the substrate 13. For example, the patterned mask layer 20 may be a patterned photoresist. In some embodiments, in the opening 18 of the passivation layer 17 ( Figure 1B An opening 21 is formed directly above the patterned mask layer 20, exposing the seed layer 19 covering the surface of the opening 18 and a portion of the seed layer 19 on the top surface of the passivation layer 17. Then, conductive pillars 22 and test pads 23 are formed on the seed layer 19 exposed by the opening 21 of the patterned mask layer 20. The conductive pillars 22 may contain copper, nickel, combinations thereof, or other suitable metals, and can be formed by a plating process (e.g., electroplating, electroless plating, etc.). The conductive pillars 22 are electrically connected to the pads 16 via the seed layer 19.

[0026] In some embodiments, test pads 23 are formed on the conductive post 22 for verification testing, such as electrical testing in subsequent processes. The test pads 23 comprise a conductive material. In some embodiments, the test pads 23 are solder layers comprising tin or a tin alloy. The test pads 23 can be formed by a plating process (e.g., electroplating, electroless plating, etc.). The cross-sectional shape of the conductive post 22 can be square, rectangular, circular, or other suitable shapes. The top surface of the conductive post 22 can be flat, circular, arc-shaped, or similar in shape, and this disclosure is not limited thereto. The cross-sectional shape of the test pads 23 can be square, rectangular, arc-shaped, circular, or similar in shape, and the top surface of the test pads 23 can be flat, circular, arc-shaped, or similar in shape, and this disclosure is not limited thereto. In some embodiments, the sidewalls of the test pads 23 are aligned with the sidewalls of the conductive post 22.

[0027] Reference Figure 1C and Figure 1D For example, the patterned mask layer 20 is removed by an ashing process or an etching process (e.g., wet etching or dry etching). An etching process is performed using the conductive pillars 22 and test pads 23 as masks to remove the seed layer 19 not covered by the conductive pillars 22 and form a seed layer 19a located below the conductive pillars 22. The seed layer 19a forms a connector 25 with the conductive pillars 22. The etching process may include dry etching, wet etching, or a combination thereof. In some embodiments, the etching process is performed with a high etching selectivity of the seed layer 19 to the conductive pillars 22, and the conductive pillars 22 are not substantially etched during the etching process.

[0028] Referring to an enlarged view of connector 25. In some embodiments, during the etching process of seed layer 19, a portion of seed layer 19 located below conductive pillar 22 and adjacent to the edge of the sidewall of conductive pillar 22 may be over-etched, forming an undercut 24 below conductive pillar 22. In some embodiments, no undercut is formed. In some embodiments, the width W1 of undercut 24 is in the range of 0 μm to 0.5 μm, for example, 0.2 μm. However, this disclosure is not limited thereto.

[0029] Reference Figure 1D The undercut 24 is located between the conductive pillar 22 and the passivation layer 17. The sidewalls of the seed layer 19a are not aligned with the sidewalls of the conductive pillar 22 in the vertical direction (e.g., in a direction perpendicular to the top surface of the substrate 13), but are staggered. The conductive pillar 22 protrudes laterally from the seed layer 19a. In other words, in the horizontal direction, the sidewalls of the seed layer 19a are closer to the centerline of the connector 25 than the sidewalls of the conductive pillar 22.

[0030] In some embodiments, the conductive pillar 22 includes a first portion P1 and a second portion P2 located on the first portion P1. The first portion P1 is located in the opening 18 of the passivation layer 17 and is surrounded by a seed layer 19a. The sidewalls of the first portion P1 are covered by and in contact with the seed layer 19a. In some embodiments, the first portion P1 may be cylindrical or a truncated cone tapering toward the top surface of the substrate 13. The cross-sectional shape of the first portion P1 may be square, rectangular, inverted trapezoidal, etc. The second portion P2 is located on the first portion P1 and the seed layer 19a, and the sidewalls of the second portion P2 extend laterally beyond the sidewalls of the seed layer 19a. In some embodiments, the second portion P2 is cylindrical, and the cross-sectional shape of the second portion P2 may be square or rectangular, but this disclosure is not limited thereto.

[0031] In some embodiments, the width W2 of the seed layer 19a is less than the width W3 of the conductive pillar 22. The width W2 of the seed layer 19a refers to the distance between opposite ends of the seed layer 19a located on the top surface of the passivation layer 17, that is, the maximum width of the seed layer 19a in the horizontal direction parallel to the top surface of the substrate 13. The width W3 of the conductive pillar 22 refers to the width W3 of the second portion P2. The difference between the width W2 of the seed layer 19a and the width W3 of the second portion P2 is equal to the width W1 of the undercut 24.

[0032] Still refer to Figure 1D Test pad 23 is electrically connected to connector 25 and further electrically connected via connector 25 to pad 16 and interconnect structure 15. Probe 26 can be electrically coupled to test pad 23 for wafer or die testing to check if the die is a good die. In some embodiments, the test is also referred to as wafer acceptance testing (WAT). In some embodiments, test pad 23 is used to perform electrical testing to check if die 30 is a good die, but this disclosure is not limited thereto. Test pad 23 can be selected to test different properties of the wafer or die, such as leakage current, breakdown voltage, threshold voltage and effective channel length, saturation current, contact resistance, and connectivity.

[0033] Reference Figure 1D and Figure 1E After the test is completed, a removal process is performed to remove the test pad 23. In some embodiments, the removal process includes wet etching using an H2SO4-based etchant, an HNO3-based etchant, or a combination thereof. In some embodiments, the etchant may include, for example, nitric acid, ferric nitrate solution, and methanesulfonic acid. In embodiments of this disclosure, the test pad is removed after die testing and before the subsequent formation of a protective layer, thereby avoiding potential problems in subsequent processes caused by solder residue from the test pad.

[0034] In some embodiments, the conductive pillar 22 is locally consumed during the etching process of the test pad 23. In some embodiments, the etching process is performed with a low etch selectivity of the test pad 23 to the conductive pillar 22 and a high etch selectivity of the test pad 23 to the seed layer 19a. That is, during the etching process of the test pad 23, the etch selectivity of the test pad 23 to the conductive pillar 22 is less than the etch selectivity of the test pad 23 to the seed layer 19a. In some embodiments, for example, the etch selectivity of the test pad 23 to the conductive pillar 22 is in the range of 100 to 500, the etch selectivity of the test pad 23 to the seed layer 19 is in the range of 500 to 3000, and the etch selectivity of the seed layer 19 to the conductive pillar 22 is in the range of 0 to 0.2. However, this disclosure is not limited thereto.

[0035] Therefore, during the etching process of the test pad 23, the second portion P2 of the conductive post 22 is also etched and partially consumed, forming a conductive post 22a comprising the first portion P1 and the second portion P2'. The first portion P1 is not etched because it is surrounded by the seed layer 19a and covered by the second portion P2 during the etching process. In some embodiments, the seed layer 19a is substantially not etched. The seed layer 19a and the conductive post 22a form a connector 25a.

[0036] Reference Figure 1D and Figure 1E In some embodiments, the sidewalls of the conductive post 22 are consumed. The sidewalls of the conductive post 22a may be straight or inclined. The top surface of the conductive post 22 may or may not be consumed. The conductive post 22a is smaller in size than the conductive post 22. Specifically, the second portion P2' has a reduced width W3', which is smaller than the width W3 of the second portion P2 before the etching process. The height of the second portion P2' may not be reduced or may be slightly reduced, that is, the height of the second portion P2' may be the same as or less than the height of the second portion P2. In some embodiments, for example, the ratio of width W3' to width W3 is less than 1 and is in the range of 0.95 to 1. In some embodiments, the surface of the second portion P2' of the conductive post 22a may be flat or uneven. The cross-sectional shape of the second portion P2' of the conductive post 22a may be square, rectangular, trapezoidal or other suitable shape, and this disclosure is not limited thereto.

[0037] Still refer to Figure 1EIn some embodiments, after the etching process of the test pad 23 is performed, the width W3' of the second portion P2 of the conductive post 22a is smaller than the width W2 of the seed layer 19a, such that a portion of the seed layer 19a protrudes laterally from the sidewall of the second portion P2' of the conductive post 22a, and said portion of the seed layer 19a is also referred to as the base portion FP of the seed layer 19a.

[0038] In other words, the seed layer 19a includes a body portion BP and a base portion FP connected to each other. The body portion BP surrounds a first portion P1 of the conductive pillar 22a and is located below a second portion P2' of the conductive pillar 22a. The surface of the body portion BP is covered by and in contact with the conductive pillar 22a. The base portion FP is located on the top surface of the passivation layer 17 and surrounds the body portion BP. The base portion FP is exposed by the conductive pillar 22a, extends laterally beyond the sidewall of the second portion P2' of the conductive pillar 22a, and protrudes from the sidewall of the second portion P2' of the conductive pillar 22a.

[0039] In some embodiments, when the seed layer 19a and the conductive pillar 22a are projected onto the top surface of the substrate 13, the projection of the base portion FP of the seed layer 19a from a top view is annular and surrounds the conductive pillar 22a. That is, in the horizontal direction, the sidewall of the seed layer 19a is farther from the center line CL of the connector 25a than the sidewall of the conductive pillar 22a. The cross-sectional shape of the base portion FP can be square, rectangular, trapezoidal, or any other suitable shape, and this disclosure is not limited thereto. In some embodiments, the surface of the base portion FP can be flat or uneven. The top surface of the base portion FP can be concave, convex, wavy, or similar in shape, and this disclosure is not limited thereto.

[0040] In some embodiments, for example, the ratio of the width W3' of the conductive post 22a to the width W2 of the seed layer 19a is less than 1 and falls within the range of 0.95 to 1. In some embodiments, the width W4 of the base portion FP of the seed layer 19a is in the range of 0.1 μm to 0.5 μm or 0.1 μm to 1 μm, for example, 0.2 μm. In other words, the connector 25a includes the seed layer 19a and the conductive post 22a, and has a stepped structure. Specifically, the edge of the connector 25a located on the passivation layer 17 includes a stepped structure.

[0041] Reference Figure 1E In some embodiments, die 30a is thus completed. In some embodiments, after forming connector 25a, the wafer including die 30a is monomerized by a die sawing process, and a wafer with Figure 1EMultiple dies 30a are shown in the diagram. Each die 30a includes a substrate 13, a dielectric structure 14, an interconnect structure 15, a pad 16, a passivation layer 17, and a connector 25a. The connector 25a includes a seed layer 19a and a conductive pillar 22a, and the seed layer 19a includes a base portion FP that laterally protrudes from the sidewall of the conductive pillar 22a.

[0042] Reference Figures 1E to 1F In some other embodiments, prior to performing the die sawing process, a protective layer 27 laterally surrounding the connector 25a is formed on the passivation layer 17, thereby forming a die 30b including the protective layer 27. The protective layer 27 may be a polymer layer, such as a low-temperature polymer layer or a high-temperature polymer layer. In some embodiments, the protective layer 27 comprises PI (e.g., low-temperature PI (LTPI)), PBO (e.g., high-temperature PBO (HTPBO)), BCB, combinations thereof, etc. The material of the protective layer 27 may be the same as or different from the material of the second passivation sublayer 17b.

[0043] In some embodiments, the protective layer 27 may be formed by, for example, forming a protective material layer on the passivation layer 17 and the connector 25a by a spin coating process. The protective material layer covers the top surface of the passivation layer 17 and the top surface of the connector 25a. A curing process is then performed to cure the protective material layer. In some embodiments where both the second passivation sublayer 17b and the protective layer 27 are made of PI, the curing temperature of the protective layer 27 is lower than the curing temperature of the second passivation sublayer 17b. In some embodiments, the curing temperature of the protective material layer ranges from 170°C to 320°C, for example, 230°C. In some embodiments where the protective layer 27 comprises LTPI, bubble problems can be avoided. In some embodiments, after performing the curing process, a planarization process (e.g., chemical mechanical polishing (CMP)) is performed to remove a portion of the protective material layer located on the top surface of the connector 25a, thereby forming the protective layer 27. In some embodiments, the top surface of the protective layer 27 is substantially coplanar with the top surface of the connector 25a.

[0044] Still refer to Figure 1F The sidewalls of connector 25a are surrounded by and in contact with protective layer 27. The top surface and sidewalls of the base portion FP of seed layer 19a are covered by and in contact with protective layer 27.

[0045] Reference Figure 1GOne or more dies (e.g., dies 30b and 30c) formed by the aforementioned process are mounted onto the carrier plate 10. The carrier plate 10 may be a glass carrier plate, a ceramic carrier plate, etc. In some embodiments, a de-bonding layer 11 is formed on the carrier plate 10. The de-bonding layer 11 is formed by, for example, a spin coating method. In some embodiments, the de-bonding layer 11 may be formed of adhesives such as ultraviolet (UV) adhesive, light-to-heat conversion (LTHC) adhesive, or other types of adhesives. The de-bonding layer 11 can decompose under the heat of light, thereby allowing the carrier plate 10 to detach from the overlay structure to be formed in subsequent steps.

[0046] A dielectric layer 12 may optionally be formed on the release layer 11. In some embodiments, the dielectric layer 12 is a polymer layer. Polymers include, for example, PI, PBO, BCB, Ajinomoto Buildup Film (ABF), Solder Resist Film (SR), etc. The dielectric layer 12 is formed by suitable fabrication techniques such as spin coating, stacking, deposition, etc.

[0047] In some embodiments, dies 30b and 30c are bonded to dielectric layer 12 via adhesive layer 29 (e.g., die attach film (DAF), silver paste, etc.). Although two dies are shown in the figures, this disclosure is not limited thereto. In some other embodiments, one or more dies may be mounted on carrier board 10.

[0048] In some embodiments, dies 30b and 30c may be any of a system-on-chip (SoC) device, a memory device, an integrated passive device (IPD), or any other suitable type of device. In some embodiments, dies 30b and 30c may be application-specific integrated circuit (ASIC) chips, analog chips, sensor chips, wireless and RF chips, voltage regulator chips, memory chips, etc. Dies 30b and 30c may be the same type of die or different types of dies. In some embodiments, for example, die 30b is an SoC device and die 30c is an IPD device. In some embodiments, the two dies 30b and 30c are two smaller die partitions with different functions of a larger single die. The dimensions (height and / or width) of the two dies 30b and 30c may be the same or different.

[0049] In some embodiments, the die 30c has a similar Figure 1E The die 30a shown has a substantially the same structure, except that die 30c includes a different number of connectors 25a. It should be understood that the number of connectors 25a shown in dies 30a, 30b, and 30c is for illustrative purposes only, and this disclosure is not limited thereto.

[0050] Still refer to Figure 1G Similar to dies 30a or 30b, die 30c includes a substrate 13, a dielectric structure 14, an interconnect structure 15, a pad 16, a passivation layer 17, and a connector 25a. In some embodiments, die 30b includes a protective layer 27, while die 30c does not include a protective layer 27. That is, the top surface and sidewalls of the connector 25a of die 30c are exposed. However, this disclosure is not limited thereto. In some other embodiments, both die 30b and die 30c include a protective layer 27. In alternative embodiments, neither die 30b nor die 30c includes a protective layer 27.

[0051] Reference Figure 1H Next, an encapsulation 31 is formed on the carrier 10 to encapsulate the sidewalls of dies 30b and 30c. In some embodiments, the encapsulation 31 comprises a molding compound, a molding underfill, a resin (e.g., epoxy resin), or a combination thereof. In some other embodiments, the encapsulation 31 comprises a photosensitive material (e.g., PBO, PI, BCB, or a combination thereof), which can be easily patterned by an exposure and development process or a laser drilling process. In alternative embodiments, the encapsulation 31 comprises: a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or a combination thereof. The encapsulation 31 is formed by forming an encapsulation material layer on the carrier 10 using a suitable fabrication technique (e.g., spin coating, lamination, deposition, or a similar process). An encapsulation material layer encapsulates the top surfaces and sidewalls of dies 30b and 30c. Subsequently, a planarization process (e.g., grinding or polishing process (e.g., CMP)) is performed to remove a portion of the encapsulation material layer, exposing the top surface of connector 25a. In some embodiments, the top surface of connector 25a is substantially coplanar with the top surface of encapsulation 31.

[0052] Still refer to Figure 1HThe encapsulation 31 is located laterally on the sides of dies 30b and 30c, and surrounds and covers the sidewalls of dies 30b and 30c. In die 30b, connector 25a is surrounded by protective layer 27, and the sidewalls of protective layer 27 are covered by and in contact with encapsulation 31. A portion of encapsulation 31 is formed on passivation layer 17 and surrounds and contacts the sidewalls of connector 25a in die 30c. In die 30c, the sidewalls of seed layer 19a and conductive pillar 22a contact encapsulation 31. The top surface and sidewalls of the base portion FP of seed layer 19a are covered by and in contact with encapsulation 31.

[0053] Reference Figure 1I A redistribution layer (RDL) structure 32 electrically connected to dies 30b and 30c is formed on top of dies 30b and 30c. In some embodiments, dies 30b and 30c are electrically connected to each other via the RDL structure 32. In some embodiments, the RDL structure 32 is referred to as a "front-side redistribution layer structure," where "front-side" refers to the side near the connector 25a of dies 30b and 30c. In some embodiments, the RDL structure 32 includes alternating stacked polymer layers PM1, PM2, PM3, and PM4 and multiple redistribution layers RDL1, RDL2, RDL3, and RDL4. The number of polymer layers or redistribution layers is not limited in this disclosure.

[0054] Redistribution layer RDL1 passes through polymer layer PM1 and is physically and electrically connected to connector 25a of dies 30b and 30c. Redistribution layer RDL2 passes through polymer layer PM2 and is electrically connected to redistribution layer RDL1. Redistribution layer RDL3 passes through polymer layer PM3 and is electrically connected to redistribution layer RDL2. Redistribution layer RDL4 passes through polymer layer PM4 and is electrically connected to redistribution layer RDL3.

[0055] The materials of polymer layers PM1, PM2, PM3, and PM4 may be the same as or different from the material of the protective layer 27 or the encapsulation 31 of the die 30b. In some embodiments, each of polymer layers PM1, PM2, PM3, and PM4 comprises a photosensitive material, such as PBO, PI, BCB, or combinations thereof. In some embodiments, the protective layer 27 is also referred to as polymer layer PMO.

[0056] In some embodiments, each of the redistribution layers RDL1, RDL2, RDL3, and RDL4 comprises a conductive material. The conductive material includes a metal (e.g., copper, nickel, titanium, combinations thereof) and is formed by an electroplating process. In some embodiments, the redistribution layers RDL1, RDL2, RDL3, and RDL4 each comprise a seed layer (not shown) and a metal layer (not shown) formed on the seed layer. The seed layer may be a metal seed layer, such as a copper seed layer. In some embodiments, the seed layer comprises a first metal layer (e.g., a titanium layer) and a second metal layer (e.g., a copper layer) located above the first metal layer. The metal layer may be copper or other suitable metal.

[0057] In some embodiments, redistribution layers RDL1, RDL2, RDL3, and RDL4 each include a plurality of vias V and a plurality of traces T connected to each other. The vias V pass vertically through polymer layers PM1, PM2, PM3, and PM4 to connect with the traces T of redistribution layers RDL1, RDL2, RDL3, and RDL4, and the traces T are located on polymer layers PM1, PM2, PM3, and PM4, respectively, and extend horizontally on the top surface of polymer layers PM1, PM2, PM3, and PM4, respectively.

[0058] In some embodiments, the redistribution layer RDL4 is the topmost redistribution layer of the RDL structure 32 and is referred to as the under-ball metallurgy (UBM) layer for ball mounting.

[0059] Still refer to Figure 1I Subsequently, a plurality of connectors 33 electrically connected to the redistribution layer RDL4 of the RDL structure 32 are formed on top of the redistribution layer RDL4 of the RDL structure 32. In some embodiments, the connectors 33 are referred to as conductive terminals. In some embodiments, the connectors 33 may be ball grid array (BGA) connectors, solder balls, controlled collapse chip connection (C4) bumps, or combinations thereof. In some embodiments, the material of the connectors 33 includes copper, aluminum, lead-free alloys (e.g., gold, tin, silver, aluminum, or copper alloys) or lead alloys (e.g., lead-tin alloys). The connectors 33 may be formed by suitable processes such as vapor deposition, plating, ball dropping, screen printing and reflow processes, ball mounting processes, or C4 processes. In some embodiments, a metal post or metal pillar (not shown) may be further formed between the redistribution layer RDL4 and the connectors 33. The connectors 33 are electrically connected to the connectors 25a of the two dies 30b and 30c via the RDL structure 32.

[0060] Reference Figure 1I and Figure 1J The release layer 11 decomposes under the heat of light, which then causes the carrier plate 10 to detach. The dielectric layer 12 may optionally remain.

[0061] Reference Figure 1J The encapsulation structure 50a is thus completed. Encapsulation structure 50a is also referred to as a fan-out encapsulation structure. Encapsulation structure 50a includes the two dies 30b and 30c, an encapsulation body 31, an RDL structure 32, and a connector 33. Dies 30b and 30c are connected together via the RDL structure 32. Dies 30b and 30c each include a connector 25a. Connectors 25a are in electrical contact with pads 16 and are further electrically connected to the internal interconnect structure 15 of die 30b or 30c. Connectors 25a of die 30b or 30c include a seed layer 19a and conductive pillars 22a located on the seed layer 19a. The seed layer 19a includes a body portion covered by the conductive pillars 22a and a base portion FP protruding from the sidewall of the conductive pillars 22a. The conductive pillars 22a cover a portion of the top surface of the seed layer 19a and expose the base portion FP of the seed layer 19a. In some embodiments, the top surface and sidewalls of the base portion FP are covered by a protective layer 27 and are in physical contact with the protective layer 27 (e.g., die 30b). In some embodiments, the top surface and sidewalls of the base portion FP are covered by an encapsulation 31 and are in physical contact with the encapsulation 31 (e.g., die 30c).

[0062] In the foregoing embodiments, a connector 25a corresponds to a pad 16 in one of the cores 30a, 30b or 30c, but this disclosure is not limited thereto. Figure 2 The diagram shows a package structure 50b, which includes a die 30d having line connectors 25a' corresponding to two pads 16. In some embodiments, such as Figure 2 As shown, package structure 50b includes die 30d and die 30c. Package structure 50b is similar to package structure 50a, except that die 30d includes connector 25a', which is different from connector 25a.

[0063] Reference Figure 2 The die 30d includes connector 25a and connector 25a'. In some embodiments, connector 25' is formed on two pads 16, for example... Figure 2Two pads 16a are shown. A connector 25a' makes electrical and physical contact with the two pads 16, extending from a position above the first pad 16 to a position above the second pad 16 and covering the passivation layer 17 between the two pads 16. The top surface of the passivation layer 17 between the two pads 16 is covered by and contacts the connector 25a'. In some embodiments, the connector 25a' includes a seed layer 19a' and a conductive pillar 22a'. The seed layer 19a' and the conductive pillar 22a' extend from a position above the first pad 16 to a position above the second pad 16 and cover the passivation layer 17 between the two pads 16. The seed layer 19a' includes a body portion below the conductive pillar 22a' and a base portion FP protruding from the sidewall of the conductive pillar 22a'. Conductive post 22a' is located on seed layer 19a' and covers a portion of the top surface of seed layer 19a', exposing the base portion FP of seed layer 19a'. Although connector 25a' is shown connected to two pads 16, this disclosure is not limited thereto. Depending on the product design, connector 25a' may be connected to more than two pads 16. In some embodiments, connector 25a' is also referred to as a wire connector or wire via. Compared to connector 25a, connector 25a' connects to more pads 16 and has a larger area, thereby allowing connector 25a' to transmit larger or increased signals, providing better heat dissipation, and reducing resistance. Other features of die 30d are substantially the same as those of dies 30a, 30b, or 30c, and will not be described further herein. It should be noted that die 30c may also include wire connector 25a'.

[0064] Figure 3 A package structure 50c is shown, including dies 30e and 30f, wherein the seed layer 119a of the connector 125a of dies 30e or 30f includes a double-layer structure. Package structure 50c has a similar structure to package structure 50a. Figure 1J The structure is similar to that shown, except that the structure of the connector 125a of the cores 30e and 30f is different from that of the connector 25a of the cores 30b and 30c.

[0065] Reference Figure 3 In some embodiments, the seed layer 119a is a bilayer structure comprising a first seed layer 19b and a second seed layer 19c located on the first seed layer 19b. In some embodiments, the second seed layer 19c comprises a material different from that of the first seed layer 19b but the same as that of the conductive pillar 22a. For example, the first seed layer 19b is a titanium layer, the second seed layer 19c is a copper layer, and the conductive pillar 22a is a copper pillar. The first seed layer 19b and the second seed layer 19c can be formed by PVD (e.g., sputtering), electroplating, electroless plating, or a combination thereof.

[0066] Reference Figure 1D , Figure 1E and Figure 3 , Figure 3 The dashed lines in the enlarged view show the structure of the seed layer and conductive pillars before the etching process of test pad 23 is performed. For example... Figure 3 As shown in the enlarged view, prior to the etching process of the test pad 23, an undercut may be present between the second seed layer 19c and the passivation layer 17, and the sidewalls of the second seed layer 19c may be aligned with the sidewalls of the conductive pillar 22. During the etching process of the test pad 23, since the second seed layer 19c contains the same material as the conductive pillar 22a, the second seed layer 19c may also be etched and partially consumed, while the first seed layer 19b is substantially unetched, resulting in a seed layer 119a comprising the first seed layer 19b and the second seed layer 19c. The seed layer 119a and the conductive pillar 22a form a connector 125a.

[0067] Reference Figure 3 In some embodiments, the sidewalls of the second seed layer 19c are substantially aligned with the sidewalls of the conductive pillar 22a. The first seed layer 19b extends beyond and protrudes from the sidewalls of the second seed layer 19c and the conductive pillar 22a. The first seed layer 19b includes a foot portion FP that extends laterally beyond the sidewalls of the second seed layer 19c and the conductive pillar 22a. When the seed layers 19b and 19c and the conductive pillar 22a are projected onto the top surface of the substrate 13, the projection of the foot portion FP of the first seed layer 19b surrounds the projection of the second seed layer 19c and the conductive pillar 22a. That is, the second seed layer 19c and the conductive pillar 22a cover a portion of the top surface of the first seed layer 19b and expose the foot portion FP of the first seed layer 19b.

[0068] In other words, the edge of seed layer 119a includes a stepped structure on passivation layer 17, and in a horizontal direction parallel to the top surface of substrate 13, the sidewall of second seed layer 19c is closer to the center line CL of connector 125a than the sidewall of first seed layer 19b. In some embodiments where the die includes protective layer 27, such as die 30e shown, the top surface and sidewalls of the base portion FP of first seed layer 19b are covered by and in contact with protective layer 27. The top surface of second seed layer 19c is covered by conductive pillar 22a. In some embodiments, the top surface of second seed layer 19c is completely covered by conductive pillar 22a. The sidewalls of second seed layer 19c are covered by and in contact with protective layer 27. In some other embodiments where the die does not have protective layer, such as die 30f shown, the top surface and sidewalls of the base portion FP of first seed layer 19b are covered by and in contact with encapsulation 31. The top surface of the second seed layer 19c is covered by conductive pillars 22a. In some embodiments, the top surface of the second seed layer 19c is completely covered by conductive pillars 22a. The sidewalls of the second seed layer 19c are covered by and in contact with the encapsulation body 31.

[0069] Figure 4 The diagram shows a package structure 50d including die 30g and die 30h, wherein die 30g and die 30h do not include a second passivation sublayer. (Refer to...) Figure 4 Die 30g and die 30h are similar to die 30b and die 30c, respectively. Figure 1J The difference lies in the fact that the passivation layer 17 of the 30g and 30h dies has a single-layer structure. For example... Figure 4 As shown, in some embodiments, the passivation layer 17 includes a first passivation sublayer 17a but does not include a second passivation sublayer 17b. Figure 1J The dimensions (e.g., thickness) and shape of the first passivation sublayer 17a in this embodiment may be the same as or different from those in the foregoing embodiments (e.g., Figure 1J The dimensions and shape of the first passivation sublayer 17a are shown in the diagram. Other features of the package structure 50d are substantially the same as those of the package structure 50a, and will not be described again. It should be noted that although in Figure 4 Connector 25a is shown, however other types of connectors (e.g., connector 25a' or connector 125a) may also be used in the package structure 50d.

[0070] Figure 5 The diagram shows a package structure 50e including an integrated fan-out via (TIV) 60 and a stacked package (PoP) structure 100.

[0071] Reference Figures 1G to 1H and Figure 5 In some embodiments, a TIV 60 may be formed on the dielectric layer 12 and on or around the sides of the dies 30b and 30c before the encapsulation 31 is formed. In some embodiments, the TIV 60 comprises copper, nickel, solder, alloys thereof, etc. In some embodiments, the TIV 60 includes a seed layer and a conductive layer (not shown) formed on the seed layer. The seed layer is, for example, a titanium and / or copper composite layer. The conductive layer is, for example, a copper layer. An exemplary method of forming the TIV 60 includes forming a photoresist layer, for example, a dry film resist, on the substrate 10 before bonding the dies 30b and 30c. An opening is then formed in the photoresist layer, the opening exposing a portion of the top surface of the dielectric layer 12, and then the TIV 60 is formed by plating in the opening. In some other embodiments, the TIV 60 further includes a barrier layer (not shown) located below the seed layer to prevent metal diffusion. The barrier layer material includes, for example, metal nitrides, such as titanium nitride, tantalum nitride, or combinations thereof.

[0072] Reference Figure 5 The sidewalls of TIV 60 are encapsulated by encapsulation 31. A redistribution layer RDL1 is electrically connected to TIV 60, such that TIV 60 is electrically connected to dies 30b and 30c via RDL structure 32. Other features of package structure 50e are substantially the same as those of package structure 50a, and will not be described further.

[0073] Still refer to Figure 5 In some embodiments, the packaging structure 50e may be further electrically coupled to the packaging structure 63 to form a stacked package (POP) device 100, but this disclosure is not limited thereto.

[0074] In some embodiments, after the package structure 50e is formed, the dielectric layer 12 may be patterned, for example, by a laser drilling process, to form an opening 58. The opening 58 exposes portions of the bottom surface of the TIV 60. Then, a connector 61 fills the opening 58 in the dielectric layer 12 to electrically connect the TIV 60 of the package structure 50e to the package structure 63. The package structure 63 may be any type of package structure depending on the functional requirements of the PoP device 100. In some embodiments, the package structure 63 may be a dynamic random access memory (DRAM), static random access memory (SRAM), or other types of packages.

[0075] In some embodiments, a bottom filler layer 62 is also formed to fill the space between the package structure 50e and the package structure 63 and surround the connector 61. The PoP device 100, including the package structure 50e and the package structure 63, is thus completed, wherein the package structure 50e and the package structure 63 are connected together via the connector 61. Figure 5 The PoP device 100 shown is for illustrative purposes only, and this disclosure is not limited thereto. It should be noted that package structures 50b, 50c, and 50d may also include a TIV and may be further coupled to other packages to form a PoP device.

[0076] In the foregoing embodiments, the combination of dies encapsulated in the package structure is merely illustrative, and this disclosure is not limited thereto. Dies 30a, 30b, 30c, 30d, 30e, 30f, 30g, and 30h can be individually or in any kind of combination encapsulated in the package structure. Furthermore, although a fan-out package structure is shown in the figures, this disclosure is not limited thereto. Dies 30a, 30b, 30c, 30d, 30e, 30f, 30g, and 30h can also be used to form other types of package structures, such as fan-in packages.

[0077] In embodiments of this disclosure, the test pads are removed after die testing and before the protective layer is formed, thereby avoiding solder residue that may occur between the connector and the protective layer during the protective layer curing process. This improves wetting and adhesion between the connector and the protective layer or between the connector and the package, enhancing the performance and reliability of the die and package structure. Furthermore, it avoids potential problems caused by solder residue during defect scanning.

[0078] According to some embodiments of this disclosure, a method for forming a package structure is characterized by comprising the following steps: forming a die, including forming the connector, comprising the following steps: forming a first pad and a second pad on a substrate; forming a passivation layer to cover a portion of the first pad and a portion of the second pad; forming a connector that passes through the passivation layer and is electrically connected to the first pad and the second pad, wherein the connector extends from the first pad to cover a portion of the passivation layer located between the first pad and the second pad, and continues to extend over the second pad; forming the connector comprises the following steps: forming a seed layer on the first pad, the portion of the passivation layer, and the second pad, wherein the seed layer comprises a first seed layer and a second seed layer located on the first seed layer. A patterned mask layer with openings is formed on the seed layer, wherein the first and second seed layers of the seed layer are unpatterned layers, located between the patterned mask layer and the first pad, between the patterned mask layer and a portion of the passivation layer, and between the patterned mask layer and the second pad. Conductive pillars are formed in the openings of the patterned mask layer. Test pads are formed on the conductive pillars. The patterned mask layer is removed. A first etching process is performed to remove the seed layer not covered by the conductive pillars, leaving a first width of the first seed layer smaller than the first width of the conductive pillars. Electrical testing is performed through the test pads. A second etching process is performed to remove the test pads, wherein the conductive pillars are consumed during the second etching process, such that the base of the seed layer laterally protrudes from the sidewall of the conductive pillar. The seed layer comprises a first seed layer and a second seed layer located between the first seed layer and the conductive pillar, and the edges of the seed layer include a stepped structure. The material of the second seed layer is different from the material of the first seed layer but the same as the material of the conductive pillar. An encapsulation is formed on the die side to encapsulate and contact the sidewalls of the substrate and the passivation layer of the die. A redistribution layer structure is formed on the die and the encapsulation layer. Conductive terminals are formed, and the conductive terminals are electrically connected to the die via the redistribution layer structure.

[0079] In some embodiments of this disclosure, during the second etching process, the etching selectivity of the test pad to the conductive pillar is less than the etching selectivity of the test pad to the seed layer, and the conductive pillar is consumed from the sidewall of the conductive pillar during the second etching process.

[0080] In some embodiments of this disclosure, before performing the second etching process, the first width of the first seed layer is smaller than the first width of the conductive pillar. After performing the second etching process, the second width of the first seed layer is larger than the second width of the conductive pillar.

[0081] In some embodiments of this disclosure, prior to performing the first etching process, the passivation layer is covered by the first seed layer and the second seed layer and is not exposed. After performing the second etching process, the base portion of the seed layer extends beyond the sidewall of the conductive pillar.

[0082] In some embodiments of this disclosure, the method of forming an encapsulation structure by the encapsulating body contacting the sidewall of the conductive pillar and the top surface and sidewall of the stepped structure further includes forming a protective layer, the protective layer being located on the substrate and covering the sidewall of the conductive pillar of the connector and the sidewall and top surface of the base portion of the seed layer, wherein the encapsulating body contacts the sidewall of the protective layer.

[0083] According to some embodiments of this disclosure, a method for forming a die is characterized by comprising the following steps: forming a pad on a substrate; forming a passivation layer to cover a portion of the pad; forming a connector that passes through the passivation layer and is electrically connected to the pad; forming the connector by the following steps: forming a seed layer on the pad and the portion of the passivation layer, wherein the seed layer includes a first seed layer and a second seed layer located on the first seed layer; forming a patterned mask layer with openings, wherein the first seed layer and the second seed layer of the seed layer are unpatterned layers and cover the passivation layer, and the first seed layer and the second seed layer of the seed layer separate the passivation layer from the patterned mask layer; forming conductive pillars in the openings of the patterned mask layer; forming test pads on the conductive pillars; removing the patterned mask layer; performing a first etching process to remove the seed layer not covered by the conductive pillars, leaving a first width of the first seed layer smaller than the first width of the conductive pillars; performing electrical testing through the test pads. A second etching process is performed to remove the test pad, wherein the conductive post is consumed during the etching process such that the base portion of the seed layer laterally protrudes from the sidewall of the conductive post, wherein the seed layer includes the first seed layer and the second seed layer located between the first seed layer and the conductive post, and the edge of the seed layer includes a stepped structure.

[0084] In some embodiments of this disclosure, the method of forming a die further includes forming a protective layer located on the substrate and covering the sidewalls of the conductive pillars of the connector and the sidewalls and top surface of the base portion of the seed layer, the protective layer comprising low-temperature polyimide or high-temperature polybenzoxazole.

[0085] In some embodiments of this disclosure, the passivation layer is covered by the first seed layer and the second seed layer before the first etching process is performed, and is not exposed.

[0086] According to some embodiments of this disclosure, a method for forming a die is characterized by comprising the following steps: forming a pad on a substrate; forming a passivation layer to cover a portion of the pad; forming a connector that passes through the passivation layer and is electrically connected to the pad, the connection comprising the following steps: forming a seed layer on the pad and the portion of the passivation layer, wherein the seed layer includes a first seed layer and a second seed layer located on the first seed layer; forming a patterned mask layer with openings, wherein the first seed layer and the second seed layer of the seed layer are unpatterned layers and cover the passivation layer, and the first seed layer and the second seed layer of the seed layer separate the passivation layer from the patterned mask layer; forming conductive pillars in the openings of the patterned mask layer; forming test pads on the conductive pillars; removing the patterned mask layer; performing a first etching process to remove the seed layer not covered by the conductive pillars, forming an undercut below the conductive pillars; and performing electrical testing through the test pads. A second etching process is performed to remove the test pads and a portion of the conductive pillars, reducing the width of the remaining conductive pillars, wherein the base portion of the seed layer laterally protrudes from the sidewall of the conductive pillar. The seed layer includes a first seed layer and a second seed layer located between the first seed layer and the conductive pillar, and the edge of the seed layer includes a stepped structure.

[0087] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming an encapsulation structure, characterized in that, include: Forming a die includes: A first pad and a second pad are formed on the substrate; A passivation layer is formed to cover a portion of the first pad and a portion of the second pad; and A connector is formed that passes through the passivation layer and is electrically connected to the first pad and the second pad, wherein the connector extends from above the first pad to cover a portion of the passivation layer located between the first pad and the second pad, and continues to extend above the second pad, forming the connector comprising: A seed layer is conformally formed on the first pad, a portion of the passivation layer, and the second pad, wherein the seed layer includes a first seed layer and a second seed layer located on the first seed layer; A patterned mask layer with openings is formed on the seed layer, wherein the first seed layer and the second seed layer of the seed layer are located between the patterned mask layer and the first pad, between the patterned mask layer and the portion of the passivation layer, and between the patterned mask layer and the second pad; Conductive pillars are formed in the openings of the patterned mask layer; A test pad is formed on the conductive post; Remove the patterned mask layer; A first etching process is performed to remove the seed layer not covered by the conductive pillar, leaving a second seed layer with an undercut between it and the passivation layer, and the sidewall of the remaining second seed layer is aligned with the sidewall of the conductive pillar. Perform electrical testing via the test pad; and A second etching process is performed to remove the test pad, wherein the conductive post is consumed during the second etching process such that the base portion of the seed layer laterally protrudes from the sidewall of the conductive post, wherein the seed layer includes a first seed layer and a second seed layer located between the first seed layer and the conductive post, and the edge of the seed layer includes a stepped structure, and wherein the material of the second seed layer is different from the material of the first seed layer and the same as the material of the conductive post; An encapsulation body is formed on the side of the die to encapsulate and contact the substrate and the sidewall of the passivation layer of the die; A redistribution layer structure is formed on the die and the encapsulation; and A conductive terminal is formed, which is electrically connected to the die via the redistribution layer structure.

2. The method for forming an encapsulation structure according to claim 1, characterized in that, During the second etching process, the etching selectivity of the test pad to the conductive pillar is less than the etching selectivity of the test pad to the seed layer, and the conductive pillar is consumed from the sidewall of the conductive pillar during the second etching process.

3. The method for forming an encapsulation structure according to claim 1, characterized in that, The first seed layer of the seed layer includes the base portion.

4. The method for forming an encapsulation structure according to claim 1, characterized in that, Before the first etching process is performed, the passivation layer is covered by the first seed layer and the second seed layer and is not exposed; as well as After the second etching process is performed, the base portion of the seed layer extends beyond the sidewall of the conductive pillar.

5. The method for forming an encapsulation structure according to claim 1, characterized in that, The encapsulation body contacts the sidewall of the conductive pillar and the top surface and sidewall of the stepped structure.

6. The method for forming an encapsulation structure according to claim 1, characterized in that, It also includes forming a protective layer located on the substrate and covering the sidewalls of the conductive pillars of the connector and the sidewalls and top surface of the base portion of the seed layer, wherein the encapsulator contacts the sidewalls of the protective layer.

7. The method for forming an encapsulation structure according to claim 6, characterized in that, The protective layer comprises low-temperature polyimide or high-temperature polybenzoxazole.

8. The method for forming an encapsulation structure according to claim 6, characterized in that, The method for forming the protective layer includes: A protective material layer is formed on the passivation layer and on the connector; Perform a curing process to cure the protective material layer; and A planarization process is performed to remove the portion of the protective material layer located on the connector, thereby forming the protective layer.

9. The method for forming an encapsulation structure according to claim 8, characterized in that, Forming the passivation layer includes: Forming a first passivation sublayer to partially cover the first pad and the second pad; and A second passivation sublayer is formed on the first passivation sublayer and partially covers the first pad and the second pad.

10. The method for forming an encapsulation structure according to claim 9, characterized in that, The curing temperature of the protective material layer is lower than the curing temperature of the second passivation sublayer.

11. The method for forming an encapsulation structure according to claim 10, characterized in that, During the first etching process, the test pad covers the conductive post.

12. The method for forming an encapsulation structure according to claim 6, characterized in that, The etching agent used in the second etching process includes H2SO4-based etchants, HNO3-based etchants, or combinations thereof.

13. A method for forming a core, characterized in that, include: A pad is formed on the substrate; A passivation layer is formed to cover a portion of the pad; as well as Forming a connector that passes through the passivation layer and is electrically connected to the pad, the connector comprising: A seed layer is conformally formed on the pad and the portion of the passivation layer, wherein the seed layer includes a first seed layer and a second seed layer located on the first seed layer; A patterned mask layer with openings is formed, wherein the first seed layer and the second seed layer of the seed layer cover the passivation layer, and the first seed layer and the second seed layer of the seed layer separate the passivation layer from the patterned mask layer; Conductive pillars are formed in the openings of the patterned mask layer; A test pad is formed on the conductive post; Remove the patterned mask layer; A first etching process is performed to remove the seed layer not covered by the conductive pillar, leaving a second seed layer with an undercut between it and the passivation layer, and the sidewall of the remaining second seed layer is aligned with the sidewall of the conductive pillar. Perform electrical testing via the test pad; and A second etching process is performed to remove the test pad, wherein the conductive post is consumed during the etching process such that the base portion of the seed layer laterally protrudes from the sidewall of the conductive post, wherein the seed layer includes a first seed layer and a second seed layer located between the first seed layer and the conductive post, and the edge of the seed layer includes a stepped structure, and wherein the material of the second seed layer is different from the material of the first seed layer and the same as the material of the conductive post.

14. The method for forming a core according to claim 13, characterized in that, It also includes forming a protective layer located on the substrate and covering the sidewalls of the conductive pillars of the connector and the sidewalls and top surface of the base portion of the seed layer, the protective layer comprising low-temperature polyimide or high-temperature polybenzoxazole.

15. The method for forming a core according to claim 14, characterized in that, The method for forming the protective layer includes: Form a protective material layer; Perform a curing process to cure the protective material layer; and A planarization process is performed to remove the portion of the protective material layer located on the connector, thereby forming the protective layer.

16. The method for forming a core according to claim 15, characterized in that, Forming the passivation layer includes: Forming the first passivation sublayer; and A second passivation sublayer is formed on the first passivation sublayer and partially covers the pad.

17. The method for forming a core according to claim 16, characterized in that, The curing temperature of the protective material layer is lower than the curing temperature of the second passivation sublayer.

18. The method for forming a core according to claim 13, characterized in that, Before the first etching process is performed, the passivation layer is covered by the first seed layer and the second seed layer and is not exposed.

19. A method for forming a core, characterized in that, include: A pad is formed on the substrate; A passivation layer is formed to cover a portion of the pad; as well as Forming a connector that passes through the passivation layer and is electrically connected to the pad, the connector comprising: A seed layer is conformally formed on the pad and the portion of the passivation layer, wherein the seed layer includes a first seed layer and a second seed layer located on the first seed layer; A patterned mask layer with openings is formed, wherein the first seed layer and the second seed layer of the seed layer cover the passivation layer, and the first seed layer and the second seed layer of the seed layer separate the passivation layer from the patterned mask layer; Conductive pillars are formed in the openings of the patterned mask layer; A test pad is formed on the conductive post; Remove the patterned mask layer; A first etching process is performed to remove the seed layer not covered by the conductive pillar, forming an undercut below the conductive pillar; Perform electrical testing via the test pad; and A second etching process is performed to remove the test pads and a portion of the conductive pillars, thereby reducing the width of the remaining conductive pillars, wherein the base portion of the seed layer protrudes laterally from the sidewall of the conductive pillar. The seed layer includes a first seed layer and a second seed layer located between the first seed layer and the conductive pillar, and the edge of the seed layer includes a stepped structure, wherein the material of the second seed layer is different from the material of the first seed layer and the same as the material of the conductive pillar.

20. The method for forming a core according to claim 19, characterized in that, Before the first etching process is performed, the passivation layer is covered by the first seed layer and the second seed layer and is not exposed; as well as After the second etching process is performed, the base portion of the seed layer extends beyond the sidewall of the conductive pillar.

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