Chip packaging method, packaging structure and radio frequency front end module
By filling the area between the non-filtering functional chip and the substrate with a packaging layer in the packaging process of RF front-end devices, a cavity is formed between the filtering functional chip and the substrate. This solves the problem of unreasonable bottom cavity design for both filtering and non-filtering functional devices, improves the structural reliability of chip packaging, and reduces costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TIANTONG RUIHONG TECH CO LTD
- Filing Date
- 2023-01-19
- Publication Date
- 2026-08-04
AI Technical Summary
In the existing film-coating process for RF front-end devices, the bottom cavity design of filtering and non-filtering functional devices is unreasonable, affecting product performance and reliability.
An encapsulation layer is formed on the substrate surface of the filtering functional chip and the non-filtering functional chip. The encapsulation layer fills the area between the non-filtering functional chip and the substrate, and a cavity is formed between the filtering functional chip and the substrate. The cavity is formed between the isolation layer and the substrate to enhance the structural reliability.
Without compromising device performance, the structural reliability of the chip packaging was enhanced, the operation process was simplified, and material costs were reduced.
Smart Images
Figure CN116072555B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip packaging technology, and in particular to a chip packaging method, packaging structure and radio frequency front-end module. Background Technology
[0002] Currently, there are two packaging processes for radio frequency front-end devices in the industry: injection molding and film coating. Among them, film coating is simple and easy to implement, has low requirements for equipment and devices, and is widely used.
[0003] Currently, in the film-coated packaging of RF front-end devices, there are cavities at the bottom of all filtering and non-filtering devices that are not filled. However, from the perspective of the product performance and reliability of RF front-end devices, filtering devices require a cavity of a certain height at the bottom that cannot be filled, while non-filtering devices do not require a cavity of a certain height at the bottom and can be filled. Summary of the Invention
[0004] This invention provides a chip packaging method, packaging structure, and radio frequency front-end module to enhance the structural reliability of chip packaging without affecting the performance of the original filtering chip and the original non-filtering chip.
[0005] In a first aspect, embodiments of the present invention provide a chip packaging method, comprising:
[0006] A filter chip and a non-filter chip are provided, wherein an isolation layer is formed on the back side of the filter chip;
[0007] The original chip with filtering function and the original chip without filtering function are flip-mounted onto the substrate respectively;
[0008] An encapsulation layer is formed on the surface of the substrate on which the filtering functional chip and the non-filtering functional chip are flip-chipped. The encapsulation layer covers the filtering functional chip, the non-filtering functional chip and the substrate, wherein the encapsulation layer fills the area between the non-filtering functional chip and the substrate, and a first cavity is formed between the filtering functional chip and the substrate.
[0009] Optionally, before providing the original film with filtering function and the original film without filtering function, the following are also included:
[0010] The isolation layer is formed on the back side of the filter function wafer using a coating process, wherein the filter function wafer includes a plurality of filter function wafers;
[0011] The filtering function wafer is diced to obtain multiple filtering function original wafers, wherein the isolation layer is formed on the back side of the multiple filtering function original wafers.
[0012] Optionally, after flip-chipping the filtering original chip and the non-filtering original chip onto the substrate, the method further includes:
[0013] A pre-curing process is used to extend the isolation layer to the side of the filter functional chip, so that the isolation layer, the filter functional chip, and the substrate form a first cavity.
[0014] Optionally, an encapsulation layer is formed on the surface of the substrate on which the filtering functional chip and the non-filtering functional chip are flip-chipped, the encapsulation layer covering the filtering functional chip, the non-filtering functional chip, and the substrate, comprising:
[0015] The encapsulation layer is formed on the side of the filter functional chip and the non-filter functional chip away from the substrate using a coating process, wherein there is a first cavity between the filter functional chip and the substrate, and there is a second cavity between the non-filter functional chip and the substrate;
[0016] A curing process is used to extend the encapsulation layer to the area between the substrate, the filtering functional chip, and the non-filtering functional chip, so that the encapsulation layer fills the second cavity between the non-filtering functional chip and the substrate.
[0017] Optionally, the surface of the substrate is provided with a plurality of first pins, and the front sides of the filtering original chip and the non-filtering original chip are respectively provided with a plurality of second pins;
[0018] The filtering chip and the non-filtering chip are flip-chip mounted onto a substrate, respectively, including:
[0019] The side of the filter chip with the second pin is attached to the side of the substrate with the first pin, and the multiple second pins on the filter chip are electrically connected one-to-one with the multiple first pins on the substrate.
[0020] The side of the non-filtering functional chip with the second pin is attached to the side of the substrate with the first pin, and the multiple second pins on the non-filtering functional chip are electrically connected one-to-one with the multiple first pins on the substrate.
[0021] Optionally, the insulating layer comprises a polyester film, and the encapsulation layer comprises an epoxy resin film.
[0022] Optionally, the temperature range of the pre-curing process is 100-150℃, and the isothermal time range of the pre-curing process is 1-3h.
[0023] Optionally, the temperature range of the curing process is 150-200℃, and the isothermal time range of the curing process is 2-8h.
[0024] Secondly, embodiments of the present invention also provide a chip packaging structure, comprising:
[0025] The original chip with filtering function and the original chip without filtering function, wherein an isolation layer is formed on the back side of the original chip with filtering function;
[0026] The substrate, wherein the filtering original chip and the non-filtering original chip are respectively flip-mounted on the substrate;
[0027] An encapsulation layer covers the filtering functional chip, the non-filtering functional chip, and the substrate, wherein the encapsulation layer fills the area between the non-filtering functional chip and the substrate; a first cavity is formed between the filtering functional chip and the substrate.
[0028] Optionally, the surface of the substrate is provided with a plurality of first pins, and the front sides of the filtering original chip and the non-filtering original chip are respectively provided with a plurality of second pins;
[0029] The multiple second pins on the original filter chip are electrically connected one-to-one with the multiple first pins on the substrate.
[0030] The multiple second pins on the non-filtering functional chip are electrically connected one-to-one with the multiple first pins on the substrate.
[0031] Optionally, the isolation layer extends to the side of the filter functional chip, and the first cavity is formed by the isolation layer, the filter functional chip, and the substrate.
[0032] Thirdly, embodiments of the present invention also provide a radio frequency front-end module, including the chip packaging structure as described in any of the second aspects.
[0033] This invention provides a chip packaging method, packaging structure, and RF front-end module. The chip packaging method includes first providing a filtering functional wafer and a non-filtering functional wafer, wherein an isolation layer is formed on the back side of the filtering functional wafer; then flip-chip bonding the filtering functional wafer and the non-filtering functional wafer onto a substrate; finally, forming an encapsulation layer on the surface of the substrate with the flip-chip bonded filtering functional wafer and the non-filtering functional wafer, the encapsulation layer covering the filtering functional wafer, the non-filtering functional wafer, and the substrate, wherein the encapsulation layer fills the area between the non-filtering functional wafer and the substrate, forming a first cavity between the filtering functional wafer and the substrate. Using this method, the filtering functional wafer forms a cavity with the substrate through the isolation layer, and the encapsulation layer fills the space between the non-filtering functional wafer and the substrate, without affecting the performance of the filtering functional wafer and the non-filtering functional wafer, enhancing the structural reliability of the chip packaging, and simplifying the operation by eliminating the need for additional packaging processes, thus reducing the material costs required in the chip packaging process. Attached Figure Description
[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0035] Figure 1 This is a schematic flowchart of a chip packaging method provided in an embodiment of the present invention;
[0036] Figure 2 yes Figure 1 The diagram shows the structural flowchart of the chip packaging method.
[0037] Figure 3 This is a schematic flowchart of another chip packaging method provided in an embodiment of the present invention;
[0038] Figure 4 yes Figure 3 The diagram shows the structural flowchart of the chip packaging method.
[0039] Figure 5 This is a schematic flowchart of another chip packaging method provided in an embodiment of the present invention;
[0040] Figure 6 yes Figure 5 The diagram shows the structural flowchart of the chip packaging method.
[0041] Figure 7 This is a chip packaging structure provided in an embodiment of the present invention. Detailed Implementation
[0042] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.
[0043] The terminology used in the embodiments of this invention is for the purpose of describing specific embodiments only and is not intended to limit the invention. It should be noted that directional terms such as "upper," "lower," "left," and "right" described in the embodiments of this invention are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the embodiments of this invention. Furthermore, in the context, it should be understood that when referring to an element being formed "on" or "below" another element, it can be formed not only directly on or below the other element, but also indirectly on or below it through intermediate elements. The terms "first," "second," etc., are used for descriptive purposes only and do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0044] The term "comprising" and its variations as used in this invention are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment".
[0045] It should be noted that the concepts of "first" and "second" mentioned in this invention are only used to distinguish the corresponding contents and are not used to limit the order or interdependence.
[0046] It should be noted that the terms "a" and "a plurality of" used in this invention are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".
[0047] Figure 1 This is a schematic flowchart of a chip packaging method provided in an embodiment of the present invention. Figure 2 yes Figure 1 The structural flowchart of the chip packaging method shown is as follows: Figure 1 and Figure 2 As shown, the chip packaging method includes:
[0048] S110, providing a filter-function original film and a non-filter-function original film, wherein an isolation layer is formed on the back side of the filter-function original film.
[0049] Specifically, such as Figure 2As shown in Figure a), in terms of product performance, the bottom of the filter element 10 needs to have a cavity to ensure the normal operation of the filtering function. For example, the filter element 10 can be a surface acoustic wave filter. Conversely, the bottom of the non-filter element 20 does not need a cavity to ensure the normal operation of the non-filtering function. For example, the non-filter element 20 can be a low-noise amplifier, antenna switch, power amplifier, etc. An isolation layer 30 is formed on the back side of the filter element 10, which helps to form a cavity at the bottom of the filter element 10. Optionally, the isolation layer 30 includes a polyester film. Polyester film is typically a colorless, transparent, and glossy film with excellent mechanical properties, high rigidity, hardness, and toughness, puncture resistance, abrasion resistance, and resistance to high and low temperatures. It is one of the commonly used barrier composite film substrates.
[0050] S120. The original wafer with filtering function and the original wafer with non-filtering function are flip-mounted onto the substrate respectively.
[0051] Optionally, such as Figure 2 As shown in Figure b), the surface of the substrate 40 is provided with a plurality of first pins 41, and the front sides of the filtering original chip 10 and the non-filtering original chip 20 are respectively provided with a plurality of second pins 80. The filtering original chip 10 and the non-filtering original chip 20 are flip-mounted onto the substrate 40, including: attaching the side of the filtering original chip 10 with the second pins 80 to the side of the substrate 40 with the first pins 41, and electrically connecting the plurality of second pins 80 on the filtering original chip 10 to the plurality of first pins 41 on the substrate 40 one by one; attaching the side of the non-filtering original chip 20 with the second pins 80 to the side of the substrate 40 with the first pins 41, and electrically connecting the plurality of second pins 80 on the non-filtering original chip 20 to the plurality of first pins 41 on the substrate 40 one by one.
[0052] Specifically, such as Figure 2As shown in Figure b), the surface of the substrate 40 is provided with a plurality of first pins 41. The first pins 41 are used to make electrical connections with the filtering functional substrate 10 and the non-filtering functional substrate 20. The number of first pins 41 is determined by the actual electrical connection requirements. This is just an example and is not limited. For example, the number of first pins 41 can be 6 or 8. The front sides of the filtering functional substrate 10 and the non-filtering functional substrate 20 are respectively provided with a plurality of second pins 80. The second pins 80 are used to make electrical connections with the substrate 40. The number of second pins 80 is determined by the actual electrical connection requirements. This is just an example and is not limited. For example, the number of second pins 80 on the filtering functional substrate 10 can be 2 or 4, and the number of second pins 80 on the non-filtering functional substrate 20 can be 2 or 4. The side of the filter chip 10 with the second pin 80 is attached to the side of the substrate 40 with the first pin 41, and the side of the non-filter chip 20 with the second pin 80 is attached to the side of the substrate 40 with the first pin 41. This allows the filter chip 10 and the non-filter chip 20 to be flip-mounted onto the substrate 40, respectively. The first pin 41 on the substrate 40 is then attached to the second pin 80 on the filter chip 10 and the non-filter chip 20, respectively, to achieve electrical connection between the filter chip 10, the non-filter chip 20, and the substrate 40.
[0053] S130. An encapsulation layer is formed on the surface of a substrate on which a filter functional chip and a non-filter functional chip are flip-chipped. The encapsulation layer covers the filter functional chip, the non-filter functional chip and the substrate. The encapsulation layer fills the area between the non-filter functional chip and the substrate, and a first cavity is formed between the filter functional chip and the substrate.
[0054] Specifically, such as Figure 2As shown in Figure c), in the chip packaging process, an encapsulation layer 50 is formed on the surface of a substrate 40 on which a filter functional chip 10 and a non-filter functional chip 20 are flip-chip bonded. The encapsulation layer 50 should cover the filter functional chip 10, the non-filter functional chip 20, and the substrate 40. It should be noted that the encapsulation layer 50 needs to fill the area between the non-filter functional chip 20 and the substrate 40. The bottom of the non-filter functional chip 20 does not need to be provided with a cavity, and the encapsulation layer 50 does not need to fill the area between the filter functional chip 10 and the substrate 40. The bottom of the filter functional chip 10 needs to be provided with a first cavity 60. The first cavity 60 enables the filtering function of the filter functional chip 10 to function normally. If the bottom of the filter functional chip 10 does not provide a first cavity 60, the filtering function of the filter functional chip 10 will be abnormal or even unable to perform the filtering function. Optionally, the encapsulation layer 50 includes an epoxy resin film, which has excellent physical, mechanical and electrical insulation properties, adhesion to various materials, and flexibility in its application process, and is widely used in encapsulation processes.
[0055] The technical solution in this embodiment of the invention first provides a filtering functional chip and a non-filtering functional chip, wherein an isolation layer is formed on the back side of the filtering functional chip; then, the filtering functional chip and the non-filtering functional chip are flip-chip mounted onto a substrate respectively; finally, an encapsulation layer is formed on the surface of the substrate on which the filtering functional chip and the non-filtering functional chip are flip-chip mounted, the encapsulation layer covering the filtering functional chip, the non-filtering functional chip, and the substrate, wherein the encapsulation layer fills the area between the non-filtering functional chip and the substrate, and a first cavity is formed between the filtering functional chip and the substrate. Using the above method, the filtering functional chip forms a cavity with the substrate through the isolation layer, and the encapsulation layer fills the space between the non-filtering functional chip and the substrate, without affecting the performance of the filtering functional chip and the non-filtering functional chip, enhancing the structural reliability of the chip packaging, and simplifying the operation by eliminating the need for additional packaging processes, thus reducing the material costs required in the chip packaging process.
[0056] Figure 3 This is a schematic flowchart of another chip packaging method provided in an embodiment of the present invention. Figure 4 yes Figure 3 The flowchart of the chip packaging method shown is an optimization of the above embodiment. Optionally, before providing the original chip with filtering function and the original chip with non-filtering function, the method further includes:
[0057] An isolation layer is formed on the back side of the filter function wafer using a coating process, wherein the filter function wafer includes multiple filter function wafers;
[0058] Multiple filter function wafers are obtained by dicing filter function wafers, wherein an isolation layer is formed on the back side of the multiple filter function wafers.
[0059] Furthermore, after flip-chipping the filtering and non-filtering wafers onto the substrate respectively, the process also includes:
[0060] A pre-curing process is used to extend the isolation layer to the side of the filter functional chip, so that the isolation layer, the filter functional chip and the substrate form a first cavity.
[0061] For details not covered in this embodiment, please refer to the above embodiments. Figure 3 and Figure 4 As shown, the chip packaging method includes:
[0062] S210. An isolation layer is formed on the back side of the filter function wafer using a coating process, wherein the filter function wafer includes multiple filter function wafers.
[0063] Specifically, such as Figure 4 As shown in Figure a), the filtering function wafer 11 includes multiple filtering function wafers 10. Multiple second pins 80 are provided on the front side of the filtering function wafer 11. An isolation layer 30 can be formed on the back side of the filtering function wafer 11 by a coating process, and then the filtering function wafer 11 is diced. Compared with the previous process of dicing the filtering function wafer 11 and then forming the isolation layer 30 on the back side of the multiple filtering function wafers 10 by a coating process, the operation process is simplified and a large-scale coating operation of filtering function wafers 10 can be realized.
[0064] S220. Cut the filter function wafer to obtain multiple filter function wafers, wherein an isolation layer is formed on the back side of the multiple filter function wafers.
[0065] Specifically, such as Figure 4 As shown in Figure b), the filter function wafer 11 with the isolation layer 30 formed on the back side is cut to obtain multiple filter function wafers 10 with the isolation layer 30 formed on the back side. The isolation layer 30 can help form a cavity at the bottom of the filter function wafer 10.
[0066] S230, providing a filter-function original film and a non-filter-function original film, wherein an isolation layer is formed on the back side of the filter-function original film.
[0067] S240. The original wafers with filtering function and the original wafers without filtering function are flip-mounted onto the substrate respectively.
[0068] S250. A pre-curing process is used to extend the isolation layer to the side of the filter functional chip, so that the isolation layer, the filter functional chip and the substrate form a first cavity.
[0069] Specifically, such as Figure 4As shown in Figure e), after the filter original chip 10 and the non-filter original chip 20 are flip-chipped onto the substrate 40 respectively, the isolation layer 30 needs to be processed to form a first cavity 60 between the filter original chip 10 and the substrate 40, so as to ensure the normal operation of the filtering function of the filter original chip 10. A pre-curing process can be used to extend the isolation layer 30 on the back of the filter original chip 10 to the side of the filter original chip 10, or even to the surface of the substrate 40 adjacent to the bottom of the filter original chip 10. Such a structure of the isolation layer 30 can form a sealed space, i.e., the first cavity 60, between the filter original chip 10 and the substrate 40. Optionally, the temperature range of the pre-curing process is 100-150℃, and the temperature holding time range of the pre-curing process is 1-3h. When the temperature range and temperature holding time range of the pre-curing process are met, the isolation layer 30 extends from the back of the filter functional substrate 10 to the side of the filter functional substrate 10, and even extends to the surface of the substrate 40 adjacent to the bottom of the filter functional substrate 10.
[0070] S260. An encapsulation layer is formed on the surface of a substrate on which a filter functional chip and a non-filter functional chip are flip-chipped. The encapsulation layer covers the filter functional chip, the non-filter functional chip and the substrate, wherein the encapsulation layer fills the area between the non-filter functional chip and the substrate, and a first cavity is formed between the filter functional chip and the substrate.
[0071] The technical solution in this embodiment of the invention firstly uses a coating process to form an isolation layer on the back side of a filtering functional wafer, wherein the filtering functional wafer includes multiple filtering functional wafers. Then, the filtering functional wafer is diced to obtain multiple filtering functional wafers, wherein an isolation layer is formed on the back side of the multiple filtering functional wafers. Next, filtering functional wafers and non-filtering functional wafers are provided, wherein an isolation layer is formed on the back side of the filtering functional wafers. Then, the filtering functional wafers and non-filtering functional wafers are flip-chipped onto a substrate respectively. Then, a pre-curing process is used to extend the isolation layer to the side of the filtering functional wafers, so that the isolation layer, the filtering functional wafers, and the substrate form a first cavity. Finally, an encapsulation layer is formed on the surface of the substrate on which the filtering functional wafers and non-filtering functional wafers are flip-chipped. The encapsulation layer covers the filtering functional wafers, non-filtering functional wafers, and the substrate, wherein the encapsulation layer fills the area between the non-filtering functional wafers and the substrate, and the first cavity is formed between the filtering functional wafers and the substrate. Using the above method, an isolation layer is first formed on the back side of the filter function wafer, and then the filter function wafer is diced. After flip-chip operation, the isolation layer on the back side of the filter function wafer is extended to the side of the filter function wafer to form a sealed space between the filter function wafer and the substrate. The operation is simple and enhances the structural reliability of the filter function wafer without affecting the filtering performance of the filter function wafer or the normal function of the non-filter function wafer.
[0072] Figure 5This is a schematic flowchart of another chip packaging method provided in an embodiment of the present invention. Figure 6 yes Figure 5 The structural flowchart of the chip packaging method shown is an optimization based on the above embodiment. Optionally, an encapsulation layer is formed on the surface of a substrate on which a filtering functional wafer and a non-filtering functional wafer are flip-chipped. The encapsulation layer covers the filtering functional wafer, the non-filtering functional wafer, and the substrate, including:
[0073] An encapsulation layer is formed on the side of the filter functional chip and the non-filter functional chip away from the substrate using a coating process. There is a first cavity between the filter functional chip and the substrate, and a second cavity between the non-filter functional chip and the substrate.
[0074] A curing process is used to extend the encapsulation layer to the area between the substrate, the filtering functional chip, and the non-filtering functional chip, so that the encapsulation layer fills the second cavity between the non-filtering functional chip and the substrate.
[0075] For details not covered in this embodiment, please refer to the above embodiments. Figure 5 and Figure 6 As shown, the chip packaging method includes:
[0076] S310, providing a filter-function original film and a non-filter-function original film, wherein an isolation layer is formed on the back side of the filter-function original film.
[0077] S320. The original wafers with filtering function and the original wafers without filtering function are flip-mounted onto the substrate respectively.
[0078] S330. An encapsulation layer is formed on the side of the filter functional wafer and the non-filter functional wafer away from the substrate using a coating process, wherein there is a first cavity between the filter functional wafer and the substrate, and a second cavity between the non-filter functional wafer and the substrate.
[0079] Specifically, such as Figure 6 As shown in Figure c), a coating process is used to form an encapsulation layer 50 on the side of the filter functional chip 10 and the non-filter functional chip 20 away from the substrate 40 to achieve chip encapsulation. However, due to the physical properties of the encapsulation layer 50, it cannot directly fill the area between the filter functional chip 10 and the substrate 40, nor can it directly fill the area between the non-filter functional chip 20 and the substrate 40. Therefore, at this time, there is a first cavity 60 between the filter functional chip 10 and the substrate 40, and a second cavity 70 between the non-filter functional chip 20 and the substrate 40.
[0080] S340. A curing process is used to extend the encapsulation layer to the area between the substrate, the filtering functional chip, and the non-filtering functional chip, so that the encapsulation layer fills the second cavity between the non-filtering functional chip and the substrate.
[0081] Specifically, such as Figure 6 As shown in Figure d), to improve the structural reliability of the chip package, without affecting the working performance of the filtering functional chip 10 and the non-filtering functional chip 20, a first cavity 60 should exist between the filtering functional chip 10 and the substrate 40, while a second cavity 70 is not required between the non-filtering functional chip 20 and the substrate 40. Therefore, a curing process can be used to extend the encapsulation layer 50 formed on the side of the filtering functional chip 10 and the non-filtering functional chip 20 away from the substrate 40 toward the surface of the substrate 40, until the encapsulation layer 50 extends to the surface of the substrate 40, and the encapsulation layer 50 can fill the area of the second cavity 70 between the non-filtering functional chip 20 and the substrate 40. It should be noted that since the isolation layer 30 forms the first cavity 60 between the filtering functional chip 10 and the substrate 40, the encapsulation layer 50 cannot fill the area between the filtering functional chip 10 and the substrate 40. Optionally, the curing process has a temperature range of 150-200℃ and a constant temperature time range of 2-8h. When the temperature range and constant temperature time range of the curing process are met, the area of the second cavity 70 between the non-filtering original sheet 20 and the substrate 40 is filled with the encapsulation layer 50, while the area between the filtering original sheet 10 and the substrate 40 forms the encapsulation structure of the first cavity 60.
[0082] The technical solution in this embodiment of the invention first provides a filtering functional chip and a non-filtering functional chip. An isolation layer is formed on the back side of the filtering functional chip. Then, the filtering functional chip and the non-filtering functional chip are flip-chip mounted onto a substrate. Next, a coating process is used to form an encapsulation layer on the side of the filtering functional chip and the non-filtering functional chip away from the substrate. A first cavity exists between the filtering functional chip and the substrate, and a second cavity exists between the non-filtering functional chip and the substrate. Finally, a curing process is used to extend the encapsulation layer to the area between the substrate, the filtering functional chip, and the non-filtering functional chip, so that the encapsulation layer fills the second cavity between the non-filtering functional chip and the substrate. Using this method, the area of the first cavity between the non-filtering functional chip and the substrate is filled with the encapsulation layer, while the area between the filtering functional chip and the substrate forms the first cavity encapsulation structure. This enhances the structural reliability of the chip packaging without affecting the working performance of the filtering functional chip and the non-filtering functional chip, and simplifies the operation process. The coating process encapsulates the surfaces of the filtering functional chip and the non-filtering functional chip with an isolation layer and an encapsulation layer, eliminating the need for additional packaging steps and effectively reducing the material costs in the chip packaging process.
[0083] Figure 7 This is a chip packaging structure provided in an embodiment of the present invention, such as... Figure 7As shown, a chip packaging structure prepared by any one of the chip packaging methods of the present invention includes: a filtering functional wafer 10 and a non-filtering functional wafer 20, wherein an isolation layer 30 is formed on the back side of the filtering functional wafer 10; a substrate 40 on which the filtering functional wafer 10 and the non-filtering functional wafer 20 are flip-chip mounted; and an encapsulation layer 50 covering the filtering functional wafer 10, the non-filtering functional wafer 20 and the substrate 40, wherein the encapsulation layer 50 fills the area between the non-filtering functional wafer 20 and the substrate 40; and a first cavity 60 is formed between the filtering functional wafer 10 and the substrate 40.
[0084] Specifically, a lamination process is used to form an isolation layer 30 on the back side of the filter function chip 10, and the filter function chip 10 with the isolation layer 30 formed on the back side is flip-chip mounted on the substrate 40. The non-filter function chip 20 is flip-chip mounted on the substrate 40. It should be noted that there needs to be a cavity at the bottom of the filter function chip 10 to ensure the normal operation of the filtering function of the filter function chip 10. There is no cavity at the bottom of the non-filter function chip 20, which also allows the normal operation of the non-filter function of the non-filter function chip 20. An encapsulation layer 50 is formed on the surface of a substrate 40 on which a filter functional chip 10 and a non-filter functional chip 20 are flip-chip bonded. The encapsulation layer 50 can cover the filter functional chip 10, the non-filter functional chip 20 and the substrate 40. The encapsulation layer 50 can fill the area between the non-filter functional chip 20 and the substrate 40, so that there is no cavity between the non-filter functional chip 20 and the substrate 40. However, since the isolation layer 30 isolates the filter functional chip 10 from the encapsulation layer 50, the encapsulation layer 50 cannot fill the area between the filter functional chip 10 and the substrate 40, and a first cavity 60 is formed between the filter functional chip 10 and the substrate 40.
[0085] This invention provides a chip packaging structure in which a cavity is formed between the filtering functional chip and the substrate through an isolation layer, and an encapsulation layer is filled between the non-filtering functional chip and the substrate. This structure enhances the structural reliability of the chip packaging without affecting the performance of the filtering and non-filtering functional chips. The isolation layer and encapsulation layer are formed by a film coating process, eliminating the need for additional encapsulation materials and reducing the material costs required in the chip packaging process.
[0086] Optionally, continue to refer to Figure 7 The surface of the substrate 40 is provided with a plurality of first pins 41, and the front sides of the filtering original chip 10 and the non-filtering original chip 20 are respectively provided with a plurality of second pins 80; the plurality of second pins 80 on the filtering original chip 10 are electrically connected to the plurality of first pins 41 on the substrate 40 in a one-to-one correspondence; the plurality of second pins 80 on the non-filtering original chip 20 are electrically connected to the plurality of first pins 41 on the substrate 40 in a one-to-one correspondence.
[0087] Specifically, the side of the filter chip 10 with the second pin 80 is attached to the side of the substrate 40 with the first pin 41, and the side of the non-filter chip 20 with the second pin 80 is attached to the side of the substrate 40 with the first pin 41, so that the filter chip 10 and the non-filter chip 20 are flip-mounted on the substrate 40 respectively. Specifically, the second pin 80 and the first pin 41 are electrically connected in a one-to-one correspondence, so that the filter chip 10 and the non-filter chip 20 can be connected to the external circuit through the substrate 40.
[0088] Optionally, continue to refer to Figure 7 The isolation layer 30 extends to the side of the filter functional chip 10, and the first cavity 60 is formed by the isolation layer 30, the filter functional chip 10 and the substrate 40.
[0089] Specifically, the isolation layer 30 formed on the back side of the filter original chip 10 can be extended to the side of the filter original chip 10, or even to the surface of the substrate 40 adjacent to the bottom surface of the filter original chip 10, by a pre-curing process. Such an isolation layer 30 structure can form a first cavity 60 between the filter original chip 10 and the substrate 40, so as to satisfy the normal operation of the filtering function of the filter original chip 10.
[0090] Based on the same inventive concept, embodiments of the present invention also provide a radio frequency (RF) front-end module, which includes the chip packaging structure provided in any of the above embodiments. Because this RF front-end module uses the chip packaging structure provided in the above embodiments, it possesses the same or similar beneficial effects as the chip packaging structure, which will not be elaborated further here.
[0091] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.
Claims
1. A chip packaging method, characterized by, include: A filter chip and a non-filter chip are provided, wherein an isolation layer is formed on the back side of the filter chip; The original chip with filtering function and the original chip without filtering function are flip-mounted onto the substrate respectively; An encapsulation layer is formed on the surface of the substrate on which the filter functional chip and the non-filter functional chip are flip-chipped. The encapsulation layer covers the filter functional chip, the non-filter functional chip and the substrate. The encapsulation layer fills the area between the non-filter functional chip and the substrate, and a first cavity is formed between the filter functional chip and the substrate. Before providing the original film with filtering function and the original film without filtering function, it also includes: The isolation layer is formed on the back side of the filter function wafer using a coating process, wherein the filter function wafer includes a plurality of filter function wafers; The filtering function wafer is diced to obtain a plurality of filtering function original wafers, wherein the isolation layer is formed on the back side of the plurality of filtering function original wafers; After flip-chipping the filtering chip and the non-filtering chip onto the substrate, the process further includes: A pre-curing process is used to extend the isolation layer to the side of the filter functional chip, so that the isolation layer, the filter functional chip, and the substrate form a first cavity.
2. The chip packaging method of claim 1, wherein, An encapsulation layer is formed on the surface of the substrate on which the filtering functional chip and the non-filtering functional chip are flip-chipped, the encapsulation layer covering the filtering functional chip, the non-filtering functional chip and the substrate, comprising: The encapsulation layer is formed on the side of the filter functional chip and the non-filter functional chip away from the substrate using a coating process, wherein there is a first cavity between the filter functional chip and the substrate, and there is a second cavity between the non-filter functional chip and the substrate; A curing process is used to extend the encapsulation layer to the area between the substrate, the filtering functional chip, and the non-filtering functional chip, so that the encapsulation layer fills the second cavity between the non-filtering functional chip and the substrate.
3. The chip packaging method of claim 1, wherein, The surface of the substrate is provided with a plurality of first pins, and the front sides of the filtering original chip and the non-filtering original chip are respectively provided with a plurality of second pins. The filtering chip and the non-filtering chip are flip-chip mounted onto a substrate, respectively, including: The side of the filter chip with the second pin is attached to the side of the substrate with the first pin, and the multiple second pins on the filter chip are electrically connected one-to-one with the multiple first pins on the substrate. The side of the non-filtering functional chip with the second pin is attached to the side of the substrate with the first pin, and the multiple second pins on the non-filtering functional chip are electrically connected one-to-one with the multiple first pins on the substrate.
4. The chip packaging method of claim 1, wherein, The insulating layer comprises a polyester film, and the encapsulation layer comprises an epoxy resin film.
5. The chip packaging method of claim 1, wherein, The temperature range of the pre-curing process is 100-150℃, and the constant temperature time range of the pre-curing process is 1-3h.
6. The chip packaging method of claim 2, wherein, The curing process has a temperature range of 150-200℃ and a constant temperature time range of 2-8h.
7. A chip package structure, characterized by comprising: The chip is prepared by the chip packaging method according to any one of claims 1-6, comprising: The original chip with filtering function and the original chip without filtering function, wherein an isolation layer is formed on the back side of the original chip with filtering function; The substrate, wherein the filtering original chip and the non-filtering original chip are respectively flip-mounted on the substrate; An encapsulation layer covers the filtering functional chip, the non-filtering functional chip, and the substrate, wherein the encapsulation layer fills the area between the non-filtering functional chip and the substrate; a first cavity is formed between the filtering functional chip and the substrate.
8. The chip package structure of claim 7, wherein, The surface of the substrate is provided with a plurality of first pins, and the front sides of the filtering original chip and the non-filtering original chip are respectively provided with a plurality of second pins. The multiple second pins on the original filter chip are electrically connected one-to-one with the multiple first pins on the substrate. The multiple second pins on the non-filtering functional chip are electrically connected one-to-one with the multiple first pins on the substrate.
9. The chip package structure of claim 7, wherein, The isolation layer extends to the side of the filter functional chip, and the first cavity is formed by the isolation layer, the filter functional chip, and the substrate.
10. A radio frequency front end module, characterized by Includes the chip packaging structure as described in any one of claims 7-9.