A trench electrode-containing single event effect resistant finfet device and method of making the same

Abstract

The application discloses a kind of trench electrode-containing anti-single particle effect FinFET device and preparation method thereof, the device includes substrate layer, fin, shallow trench isolation region, gate oxide layer, trench metal electrode and gate, wherein shallow trench isolation region is arranged on the upper surface of substrate layer, fin is arranged in the central region above shallow trench isolation region and extends to the upper surface of substrate layer downwards, and fin includes source and drain located at two ends and conductive channel located between source and drain along longitudinal direction;One trench metal electrode is arranged on the two sides of longitudinal direction of fin respectively, the side of trench metal electrode is spaced apart from fin and the lower surface of trench metal electrode extends to the inside of substrate layer;Gate oxide layer covers the upper surface and side of conductive channel;Gate covers the upper surface and side of gate oxide layer.The application controls the electric field below Fin by manufacturing two trench electrodes on the substrate of FinFET device, and solves the weak anti-single particle effect of FinFET device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a FinFET device with trench electrodes that resists single-event effects and its fabrication method. Background Technology

[0002] With the rapid development of aerospace technology, the number of electronic devices requiring operation in various space radiation environments is increasing. Currently, radiation effects caused by the space radiation environment acting on electronic systems have become a significant cause of spacecraft failure. According to statistics released by the European Space Agency (ESA) in 2011, approximately 75% of the failures of its four geostationary satellites over 50 years were caused by radiation effects, while for satellites operating in low Earth orbit, this proportion reached as high as 90%. Clearly, radiation effects are a major contributing factor to spacecraft failures, and in-depth research into radiation hardening technology for integrated circuits used in aerospace applications has become a crucial factor determining the success or failure of aerospace engineering projects.

[0003] Single event effects (SEE), a type of radiation effect of considerable interest in digital signal circuits, have also become a research hotspot in the aerospace and defense fields. When a single high-energy particle enters a sensitive region of a semiconductor device, it interacts with the device along its incident trajectory, ionizing and generating a large amount of charge. This charge is collected at the device's drain, inducing current pulses that can alter the device's logic state or cause permanent damage, directly threatening the safe operation of spacecraft and military detection equipment. Therefore, SEE-resistant devices have received widespread attention.

[0004] FinFET (Fin Field-Effect Transistor) is a novel multi-gate three-dimensional transistor. Its channel is surrounded by a gate, and the narrow, tall channel connecting the source and drain regions resembles a fish fin, hence the name "fin." FinFET transistors have a smaller area compared to planar transistors and enhance the gate's control over the channel potential, effectively suppressing short-channel effects. Therefore, FinFET technology has gradually become the mainstream process for chip manufacturers.

[0005] FinFET devices are highly sensitive to single-event effects. The main reason for their relatively weak resistance to single-event effects is that the FinFET process allows for smaller feature sizes and lower operating voltages. Even a small amount of collected charge can trigger a single-event upset (SWE), increasing the error rate of large-scale integrated circuits and affecting the reliability of electronic devices. When heavy ions are incident on conventional FinFET devices, they interact with the silicon material, generating a large number of electron-hole pairs below the Fin. These induced electron-hole pairs separate under the influence of source-drain voltage and migrate directionally, eventually being collected by the device electrodes to form transient currents. This interferes with the voltage of sensitive nodes in the device or circuit, and in severe cases, can lead to single-event upsets or multiple-event upsets (MEIs). Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a trench electrode-based FinFET device resistant to single-event effects and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] One aspect of the present invention provides a single-event-resistant FinFET device with a trench electrode, comprising a substrate, a fin, a shallow trench isolation region, a gate oxide layer, a trench metal electrode, and a gate, wherein,

[0008] The shallow trench isolation region is disposed on the upper surface of the substrate layer, and the fin is disposed in the central region above the shallow trench isolation region and extends downward to contact the upper surface of the substrate layer. The fin includes a source and a drain at both ends and a conductive channel between the source and the drain in the longitudinal direction.

[0009] A trench metal electrode is provided on each of the two sides of the longitudinal direction of the fin. The side of the trench metal electrode is spaced from the fin and the lower surface of the trench metal electrode extends into the interior of the substrate layer. The gate oxide layer covers the upper surface and side of the conductive channel. The gate electrode covers the upper surface and side of the gate oxide layer.

[0010] In one embodiment of the present invention, the anti-single-event FinFET device includes a plurality of fins, which are arranged in parallel in the central region of the upper surface of the shallow trench isolation region and extend downward to contact the upper surface of the substrate layer.

[0011] In one embodiment of the present invention, the substrate layer is made of Si material, and the substrate layer is doped with phosphorus ions or arsenic ions at a doping concentration of 1×10⁻⁶. 16 cm -3 ~5×10 16 cm -3 .

[0012] In one embodiment of the present invention, the shallow trench isolation region is made of Si3N4 material, and the gate oxide layer is made of HfO2 material.

[0013] In one embodiment of the present invention, the fin is made of Si material, wherein both the source and the drain are N-type doped with a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 The conductive channel is P-type doped with a doping concentration of 1×10⁻⁶. 17 cm -3 ~5×10 17 cm -3 .

[0014] In one embodiment of the present invention, the distance between the trench metal electrode and the fin is 10 nm to 50 nm.

[0015] In one embodiment of the present invention, the trench metal electrode is made of one of Al, Ni, Ti, and chromium-nickel alloy; the gate electrode is made of one of Al, Ni, Ti, and chromium-nickel alloy.

[0016] Another aspect of the present invention provides a method for fabricating a trench electrode-based FinFET device resistant to single-event effects, used to fabricate the trench electrode-based FinFET device resistant to single-event effects as described in any of the above embodiments, the fabrication method comprising:

[0017] S1: Phosphorus or arsenic ions are doped into Si material to form a P-type substrate layer;

[0018] S2: At least one fin is formed on the upper surface of the P-type substrate layer, the fin including a source and a drain at both ends and a conductive channel between the source and the drain;

[0019] S3: Prepare shallow trench isolation regions on the upper surface of the P-type substrate layer on both sides of the fin;

[0020] S4: A trench is formed on the shallow trench isolation area on both sides of the fin, and the trench extends downward into the interior of the P-type substrate layer;

[0021] S5: A source electrode and a drain electrode located at both ends and a conductive channel located in the middle are formed on the fin, and a gate oxide layer is prepared on the conductive channel;

[0022] S6: A trench metal electrode is formed inside the trench, and a gate electrode is formed on the gate oxide layer.

[0023] In one embodiment of the present invention, S2 includes:

[0024] S2.1: A Si3N4 layer and a polycrystalline silicon auxiliary layer are sequentially prepared on the substrate layer 1;

[0025] S2.2: Etch away both sides of the polysilicon auxiliary layer to form a hard mask auxiliary layer located in the middle of the upper surface of the Si3N4 layer, and grow SiO2 on the Si3N4 layer and the hard mask auxiliary layer to form a SiO2 layer covering the Si3N4 layer and the hard mask auxiliary layer;

[0026] S2.3: Etch the SiO2 layer to form sidewalls on both sides of the hard mask auxiliary layer; then remove the hard mask auxiliary layer between the sidewalls;

[0027] S2.4: Using the sidewall as a mask, perform photolithography on the Si3N4 layer and the substrate layer to etch away the Si3N4 layer and part of the substrate layer in the area not covered by the sidewall to form the fin; then remove the sidewall and retain the Si3N4 layer above the fin.

[0028] In one embodiment of the present invention, S5 includes:

[0029] N-type doping is performed at both ends of the fin in the longitudinal direction using phosphorus ion implantation to form the source and drain. P-type doping is performed on the conductive channel between the source and drain of the fin using boron ion implantation. After annealing, HfO2 material is deposited on the upper surface and side surface of the conductive channel of the fin to form a gate oxide layer.

[0030] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0031] 1. This invention creates two trench electrodes on the substrate of a FinFET device by etching a Si substrate to form trenches and depositing metal in the trenches. By controlling the electric field below the Fin, it overcomes the weakness of FinFET devices in resisting single-event effects. During device operation, the voltage between these two trench electrodes is controlled to introduce an external electric field, causing electron-hole pairs generated by particle incident to drift rapidly out of the sensitive region. This reduces the charge collection and transient current at the drain, thus achieving the goal of resisting single-event effects.

[0032] 2. This invention is compatible with existing FinFET processes, improves the performance of FinFET devices against single-event irradiation in space environments, and has strong application potential. It is an ideal structure for high-stability, high-performance, single-event-resistant bulk silicon FinFETs.

[0033] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a FinFET transistor with trench electrodes that resists single-event effects, provided in an embodiment of the present invention.

[0035] Figure 2 This is a specific schematic diagram of a fin provided in an embodiment of the present invention;

[0036] Figure 3 This is a process flow diagram of a FinFET transistor with trench electrodes that resists single-event effects, provided by an embodiment of the present invention.

[0037] Figure 4 This is an electron distribution diagram (vertical cross-sectional view) of a conventional FinFET device under single-event simulation;

[0038] Figure 5 This is an electron distribution diagram (longitudinal cross-sectional view) of a trench electrode-based FinFET transistor device resisting single-event effects provided by an embodiment of the present invention under single-event simulation.

[0039] Figure 6 The graphs show the current transient curves of a conventional FinFET device and the FinFET transistor of Embodiment 5 of this invention under single-particle incident conditions.

[0040] Explanation of reference numerals in the attached figures:

[0041] 1-Substrate; 2-Fin; 21-Source; 22-Conductive channel; 23-Drain; 3-Shallow trench isolation region; 4-Gate oxide layer; 5-Trench metal electrode; 6-Gate. Detailed Implementation

[0042] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following, in conjunction with the accompanying drawings and specific embodiments, provides a detailed description of a trench electrode-based FinFET device and its fabrication method based on the present invention.

[0043] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0044] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element.

[0045] Example 1

[0046] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a single-event resisting FinFET device with trench electrodes provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a fin provided in an embodiment of the present invention. The single-event resisting FinFET device includes a substrate layer 1, a fin 2, a shallow trench isolation region 3, a gate oxide layer 4, a trench metal electrode 5, and a gate 6. The shallow trench isolation region 3 is disposed on the upper surface of the substrate layer 1. The fin 2 is disposed in the central region above the shallow trench isolation region 3 and extends downward to contact the upper surface of the substrate layer 1. The fin 2 includes a source electrode 21 and a drain electrode 23 located at both ends along the longitudinal direction, and a conductive channel 22 located between the source electrode 21 and the drain electrode 23. In other words, each fin 2 includes a source electrode 21, a conductive channel 22, and a drain electrode 23 connected sequentially along its longitudinal direction, such as... Figure 2 As shown.

[0047] A trench metal electrode 5 is disposed on each of the two sides of the fin 2 in the longitudinal direction. The side surface of the trench metal electrode 5 is spaced apart from the fin 2, and the lower surface of the trench metal electrode 5 extends into the substrate layer 1. In this embodiment, the lower end of the trench metal electrode 5 is embedded in the shallow trench isolation region 3 and the substrate layer 1, with an embedding depth of 100nm to 500nm. The two trench metal electrodes on both sides of the fin 2 can form a controllable electric field below the fin 2 to reduce the collected charge of the drain electrode and reduce the impact of single-event effects on the device.

[0048] The distance between the grooved metal electrode 5 and the fin 2 is 10 nm to 50 nm.

[0049] Gate oxide layer 4 covers the upper surface and side surface of conductive channel 22; gate 6 covers the upper surface and side surface of gate oxide layer 4.

[0050] In this embodiment, the anti-single-event FinFET device may include multiple fins 2, which are arranged in parallel in the central region of the upper surface of the shallow trench isolation region 3 and extend downward to contact the upper surface of the substrate layer 1.

[0051] Furthermore, substrate 1 is made of Si material and is doped with phosphorus or arsenic ions at a concentration of 1 × 10⁻⁶. 16 cm -3 ~5×10 16 cm -3 The shallow trench isolation region 3 is made of Si3N4 material, and the gate oxide layer 4 is made of HfO2 material. The fin 2 is made of Si material, wherein the source 21 and drain 23 are both N-type doped with a doping concentration of 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 The conductive channel 22 is P-type doped with a doping concentration of 1×10⁻⁶. 17 cm -3 ~5×10 17 cm -3 .

[0052] Furthermore, the distance between the trench metal electrode 5 and the fin 2 is 10 nm to 50 nm. The trench metal electrode 5 is made of one of Al, Ni, Ti, or a chromium-nickel alloy; the gate electrode 6 is made of one of Al, Ni, Ti, or a chromium-nickel alloy.

[0053] This embodiment of the anti-single-event FinFET device creates trenches by etching a Si substrate and depositing metal in the trenches. Two trench electrodes are fabricated on the FinFET device substrate, and the electric field below the Fin electrode is controlled, overcoming the weakness of FinFET devices in resisting single-event effects. During device operation, the voltage between these two trench electrodes is controlled to introduce an external electric field, causing electron-hole pairs generated by particle incident to rapidly drift out of the sensitive region. This reduces the charge collection at the drain and transient current, achieving the goal of resisting single-event effects.

[0054] Example 2

[0055] Based on Example 1, this example provides a method for fabricating a FinFET device with trench electrodes that resists single-event effects. Please refer to [link to example]. Figure 3 , Figure 3 This is a process flow diagram of a trench electrode-based FinFET transistor designed to resist single-event effects, provided by an embodiment of the present invention. The fabrication method includes:

[0056] S1: Doping Si material with phosphorus or arsenic ions to form a P-type substrate layer, such as... Figure 3 As shown in (a).

[0057] Specifically, a thermal diffusion method is used to dope Si material with ions to form a P-type substrate layer. The doping ions are phosphorus or arsenic, and the doping concentration is 1×10⁻⁶. 16 cm -3 ~5×10 16 cm -3 .

[0058] S2: At least one fin is formed on the upper surface of the P-type substrate layer, the fin including a source and a drain at both ends and a conductive channel between the source and the drain;

[0059] In this embodiment, step S2 includes:

[0060] S2.1: A Si3N4 layer and a polycrystalline silicon auxiliary layer are sequentially prepared on the substrate layer 1.

[0061] Specifically, Si3N4 is deposited on substrate 1 using PECVD (plasma-enhanced chemical vapor deposition) to form Si3N4 layer a, and polycrystalline silicon is deposited on Si3N4 layer a using LPCVD (low-pressure chemical vapor deposition) to form polycrystalline silicon auxiliary layer b. Figure 3 As shown in (b).

[0062] S2.2: Etch away the left and right sides of the polysilicon auxiliary layer b to form a hard mask auxiliary layer c located in the middle of the upper surface of the Si3N4 layer a. Then, grow SiO2 on the Si3N4 layer a and the hard mask auxiliary layer c to form a SiO2 layer d covering the Si3N4 layer a and the hard mask auxiliary layer c. Figure 3 As shown in (c).

[0063] S2.3: Etch the SiO2 layer d to form sidewalls e located on both sides of the hard mask auxiliary layer c; then remove the hard mask auxiliary layer c between the sidewalls e.

[0064] S2.4: Using sidewall e as a hard mask, photolithography is performed on Si3N4 layer a and substrate layer 1 to etch away the Si3N4 layer a and part of the substrate layer 1 in the area not covered by sidewall e, in order to form fin 2, as shown. Figure 3 As shown in (f). The sidewall e is then removed, leaving the Si3N4 layer a above the fin, as shown. Figure 3 As shown in (g).

[0065] S3: Prepare shallow trench isolation areas on the upper surface of the P-type substrate layer on both sides of the fin.

[0066] SiO2 was deposited on the substrate layer 1 on both sides of the fin 2 using HDPCVD (high-density plasma chemical vapor deposition) to form an oxide layer f covering the substrate layer 1; the oxide layer f was planarized by CMP (chemical mechanical polishing) to expose the upper surface of the Si3N4 layer a, such as... Figure 3 As shown in (h); using Si3N4 layer a as a hard mask, wet etching is employed to etch the oxide layer f at a height of 40 nm, thus preserving the oxide layer f located on substrate layer 1. This preserved oxide layer f is then used as a shallow trench isolation region 3. Figure 3 As shown in (i).

[0067] S4: A trench is prepared on the shallow trench isolation area on both sides of the fin, and the trench extends downward into the interior of the P-type substrate layer.

[0068] Specifically, the substrate with the SiO2 layer deposited is placed in a reactive ion etching (RIE) machine. The RIE process conditions are set as follows: etching gas is CHF3, gas pressure is 2–20 Pa, RF power is 400–500 W, gas flow rate is 30–40 sccm, and reaction chamber temperature is 30–50°C. The shallow trench isolation regions 3 and the substrate layer 1 on both sides of the fin 2 are etched using RIE to form two trenches g. The two trenches g are located on the front and rear sides of the fin, respectively. Figure 3 As shown in (j), the depth of the trench is 100nm to 500nm, and the distance from the fin is 10nm to 50nm.

[0069] S5: A source and a drain are formed at both ends and a conductive channel is formed in the middle on the fin, and a gate oxide layer is prepared on the conductive channel.

[0070] Specifically, N-type doping is performed at both ends of the fin in the longitudinal direction using phosphorus ion implantation to form the source and drain electrodes; P-type doping is performed on the conductive channel between the source and drain electrodes of the fin using boron ion implantation; annealing is performed to repair the Si surface crystal damage caused by ion implantation; subsequently, HfO2 material is deposited on the upper surface and side surfaces of the conductive channel of the fin to form the gate oxide layer 4, as shown. Figure 3 As shown in (k).

[0071] The N-type doping concentration is 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 The P-type doping concentration is 1×10⁻⁶. 17 cm -3 ~5×10 17 cm -3 .

[0072] S6: A trench metal electrode is formed inside the trench, and a gate electrode is formed on the gate oxide layer.

[0073] Metal Al is deposited in trench g using a sputtering process in a vacuum environment to form trench metal electrode 5; gate metal Al is deposited on the upper and side surfaces of multiple gate oxide layers 4 using a sputtering process in a vacuum environment to form an integral gate 6, thus completing the fabrication of the entire field-effect transistor. Figure 3 As shown in (l).

[0074] The fabrication method of the trench electrode-based single-event resistant FinFET device in this embodiment is compatible with existing FinFET processes, improves the single-event irradiation resistance of FinFET devices in space environments, and has strong application potential. The fabricated FinFET device is an ideal structure for high-stability, high-performance, single-event resistant bulk silicon FinFETs.

[0075] Example 3

[0076] Based on the above embodiments, this embodiment provides a method for fabricating a FinFET transistor with trench electrodes that resists single-event effects, comprising:

[0077] Step 1: Prepare doped substrate layer 1.

[0078] Specifically, Si was selected as the substrate material; phosphorus ions were doped into the Si material using a thermal diffusion method to form a doping concentration of 1×10⁻⁶. 16 cm -3 The P-type substrate layer.

[0079] Step 2: Prepare Si3N4 layer a and polycrystalline silicon auxiliary layer b on substrate layer 1.

[0080] Specifically, Si3N4 is deposited on substrate 1 using PECVD (plasma-enhanced chemical vapor deposition) to form Si3N4 layer a; subsequently, polycrystalline silicon is deposited on Si3N4 layer a using LPCVD (low-pressure chemical vapor deposition) to form polycrystalline silicon auxiliary layer b.

[0081] Step 3: Prepare a hard mask auxiliary layer c and a SiO2 layer d on the Si3N4 layer a.

[0082] Specifically, the left and right sides of the polysilicon auxiliary layer b are etched to form a hard mask auxiliary layer c located in the middle of the upper surface of the Si3N4 layer a; subsequently, SiO2 is grown on the Si3N4 layer a and the hard mask auxiliary layer c using PECVD to form a SiO2 layer d covering the Si3N4 layer a and the hard mask auxiliary layer c.

[0083] Step 4: Prepare sidewall e on Si3N4 layer a.

[0084] Specifically, the SiO2 layer d is etched using plasma etching to form sidewalls e located on both sides of the hard mask auxiliary layer c; then the hard mask auxiliary layer c is removed using RIE (reactive ion etching).

[0085] Step 5: Prepare fins 2 on substrate 1.

[0086] Specifically, using the sidewall e as a hard mask, photolithography is performed on the Si3N4 layer a and the substrate layer 1 to etch away the Si3N4 layer a in the area not covered by the sidewall e and a portion of the substrate layer 1 to form the fin 2. Subsequently, reactive ion etching is used to remove the sidewall e, leaving the Si3N4 layer a above the fin 2. In this embodiment, the etching depth of the substrate layer 1 is 50 nm to 100 nm.

[0087] Step 6: Prepare shallow groove isolation areas 3 on both sides of fin 2.

[0088] Specifically, SiO2 is deposited on the substrate layer 1 on both sides of the fin 2 using HDPCVD (high-density plasma chemical vapor deposition) to form an oxide layer f covering the substrate layer 1; the oxide layer f is planarized by CMP (chemical mechanical polishing) to expose the upper surface of the Si3N4 layer a; using the Si3N4 layer a as a hard mask, a portion of the oxide layer f is etched using wet etching to retain the oxide layer f located on the substrate layer. The height of the retained oxide layer f is 40 nm, and the retained oxide layer f is used as the shallow trench isolation region 3.

[0089] Step 7: Prepare the groove g.

[0090] Specifically, the substrate with the SiO2 layer deposited is placed in a reactive ion etching machine. The etching gas is set to CHF3, the gas pressure is 10 Pa, the radio frequency power is 450 W, the gas flow rate is 37 sccm, and the reaction chamber temperature is 40 °C. The shallow trench isolation region 3 and the substrate layer 1 are etched by reactive ion etching to form two trenches g. The two trenches g are located on the front and rear sides of the fin, respectively. The depth of the trenches is 100 nm and the distance from the fin is 10 nm.

[0091] Step 8: Prepare a gate oxide layer 4 on the fin 2.

[0092] Specifically, N-type doping was performed at both ends of the longitudinal direction of fin 2 using phosphorus ion implantation, with a doping concentration of 1×10⁻⁶. 19 cm -3 The source and drain electrodes are formed; the conductive channel between the source and drain electrodes of each fin 2 is p-type doped using boron ion implantation, with a doping concentration of 1×10⁻⁶. 17 cm -3Annealing was performed to repair the crystal damage on the Si surface caused by ion implantation. HfO2 was deposited on the upper and side surfaces of the conductive channel of each fin 2 using PECVD to form a gate oxide layer 4.

[0093] Step 9: Fabricate trench metal electrodes and gate.

[0094] Specifically, metal Al is deposited in trench g using a sputtering process in a vacuum environment to form trench metal electrode 5; gate metal Al is deposited on the upper surface and sides of multiple gate oxide layers 4 using a sputtering process in a vacuum environment to form an integral gate 6, thus completing the fabrication of the entire field-effect transistor.

[0095] Example 4

[0096] Based on the above embodiments, this embodiment provides another method for fabricating a trench electrode-based FinFET transistor resistant to single-event effects, including:

[0097] Step 1: Prepare the doped substrate layer 1.

[0098] 1a) Si is selected as the substrate material;

[0099] 1b) Arsenic ions were doped into Si material using the thermal diffusion method to form a doping concentration of 3 × 10⁻⁶. 16 cm -3 The P-type substrate layer.

[0100] Step 2: Prepare a Si3N4 layer a and a polycrystalline silicon auxiliary layer b on substrate layer 1.

[0101] 2a) Si3N4 was deposited on substrate 1 using PECVD to form Si3N4 layer a;

[0102] 2b) Polycrystalline silicon was deposited on Si3N4 layer a using LPCVD to form polycrystalline silicon auxiliary layer b.

[0103] Step 3: Prepare a hard mask auxiliary layer c and a SiO2 layer d on the Si3N4 layer a.

[0104] 3a) Etch the left and right sides of the polysilicon auxiliary layer b to form the hard mask auxiliary layer c located in the middle of the Si3N4 layer a;

[0105] 3b) SiO2 is grown on Si3N4 layer a and hard mask auxiliary layer c using PECVD to form SiO2 layer d.

[0106] Step 4: Prepare sidewall e on Si3N4 layer a.

[0107] 4a) Part of the SiO2 is etched away using plasma etching to form sidewalls e on both sides of the auxiliary layer c of the hard mask;

[0108] 4b) Use RIE to remove the hard mask auxiliary layer c.

[0109] Step 5: Prepare fins 2 on substrate 1.

[0110] 5a) Using the sidewall e as a hard mask, photolithography is performed on the Si3N4 layer a and the substrate layer 1 to etch away the Si3N4 layer a not covered by the sidewall e and the substrate layer 1 of a certain thickness to form the fin 2.

[0111] 5c) The sidewall e is removed by reactive ion etching, while the Si3N4 layer a above the fin 2 is retained.

[0112] Step 6: Prepare shallow trench isolation zone 3.

[0113] 6a) SiO2 is deposited on substrate 1 using HDPCVD to prepare an oxide layer f covering the substrate;

[0114] 6b) The oxide layer f is planarized by CMP to expose the upper surface of the Si3N4 layer a;

[0115] 6c) Using Si3N4 layer a as a hard mask, a portion of the oxide layer f is etched using wet etching to preserve the oxide layer f located on substrate layer 1. The preserved oxide layer has a height of 50nm and is used as a shallow trench isolation region 3.

[0116] Step 7: Prepare the groove g.

[0117] 7a) Place the substrate with the SiO2 layer deposited in a reactive ion etching machine, set the etching gas to CHF3, the gas pressure to 2 Pa, the RF power to 400 W, the gas flow rate to 30 sccm, and the reaction chamber temperature to 30 °C, and use reactive ion etching to etch the shallow trench isolation region 3.

[0118] 7b) The substrate layer 1 is further etched using reactive ion etching to form two trenches g, with a depth of 300 nm and a distance of 30 nm from the fin.

[0119] Step 8: Prepare a gate oxide layer 4 on the fin 2.

[0120] 8a) N-type doping was performed at both ends of the longitudinal direction of the fin using phosphorus ion implantation, with a doping concentration of 1×10⁻⁶. 21 cm -3 This forms the source and drain.

[0121] 8b) The conductive channel between the source and drain is p-type doped using boron ion implantation, with a doping concentration of 3 × 10⁻⁶. 17 cm -3 ;

[0122] 8c) Annealing to repair the crystal damage on the Si surface caused by ion implantation;

[0123] 8d) HfO2 was deposited on the conductive channel of each fin using PECVD to form a gate oxide layer 4.

[0124] Step 9: Prepare the trench metal electrode and gate.

[0125] 9a) Deposit metallic Ni in the trench using a sputtering process in a vacuum environment to form a trench metal electrode 5;

[0126] 9b) In a vacuum environment, a sputtering process is used to deposit gate metal Ni on multiple gate oxide layers 4 to form an integral gate 6, thus completing the fabrication of the entire field-effect transistor.

[0127] Example 5

[0128] Based on the above embodiments, this embodiment provides another method for fabricating a trench electrode-based FinFET transistor resistant to single-event effects, including:

[0129] Step a, prepare doped substrate layer 1.

[0130] a1) Si was selected as the substrate material;

[0131] a2) Phosphorus ions were doped into Si material using the thermal diffusion method to form a doping concentration of 5 × 10⁻⁶. 16 cm -3 The P-type substrate layer.

[0132] Step b: Prepare a Si3N4 layer a and a polycrystalline silicon auxiliary layer b on substrate layer 1.

[0133] b1) Si3N4 is deposited on the substrate using PECVD to form a Si3N4 layer a;

[0134] b2) Polycrystalline silicon is deposited on Si3N4 layer a using LPCVD to form polycrystalline silicon auxiliary layer b.

[0135] Step c: Prepare a hard mask auxiliary layer c and a SiO2 layer d on the Si3N4 layer a.

[0136] c1) Etch the left and right sides of the polysilicon auxiliary layer b to form a hard mask auxiliary layer c located in the middle of the Si3N4 layer a;

[0137] c2) SiO2 is grown on Si3N4 layer a and hard mask auxiliary layer c using PECVD to form SiO2 layer d.

[0138] Step d: Prepare sidewall e on Si3N4 layer a.

[0139] d1) Part of the SiO2 is etched away using plasma etching to form sidewalls e on both sides of the auxiliary layer c of the hard mask;

[0140] d2) Use RIE to remove the hard mask auxiliary layer c;

[0141] Step e: Prepare fins 2 on substrate layer 1.

[0142] e1) Using the sidewall e as a hard mask, photolithography is performed on the Si3N4 layer a and the substrate layer 1 to etch away the Si3N4 layer a not covered by the sidewall e and the substrate layer 1 of a certain thickness to form the fin 2.

[0143] e2) The sidewall e is removed by reactive ion etching, while the Si3N4 layer a above the fin 2 is retained.

[0144] Step f: Prepare shallow trench isolation zone 3.

[0145] f1) SiO2 is deposited on substrate 1 using HDPCVD to prepare an oxide layer f covering the substrate;

[0146] f2) The oxide layer f is planarized by CMP to expose the upper surface of the Si3N4 layer a;

[0147] f3) Using Si3N4 layer a as a hard mask, a portion of the oxide layer is etched using wet etching to preserve the oxide layer f on the substrate. The preserved oxide layer has a height of 60nm and is used as a shallow trench isolation region 3.

[0148] Step g, prepare the trench g.

[0149] g1) The substrate with SiO2 deposited layer is placed in a reactive ion etching machine. The etching gas is set to CHF3, the gas pressure is 2Pa, the radio frequency power is 400W, the gas flow rate is 30sccm, and the reaction chamber temperature is 30℃. The shallow trench isolation region 3 is etched by reactive ion etching.

[0150] g2) The substrate layer 1 is further etched using reactive ion etching to form two trenches g, with a depth of 500 nm and a distance of 50 nm from the fin.

[0151] Step h: Prepare a gate oxide layer 4 on the fin 2.

[0152] h1) N-type doping was performed at both ends of the longitudinal direction of the fin using phosphorus ion implantation, with a doping concentration of 1×10⁻⁶. 20 cm -3 This forms the source and drain.

[0153] h2) The conductive channel between the source and drain electrodes was p-type doped using boron ion implantation, with a doping concentration of 5 × 10⁻⁶. 17 cm -3 ;

[0154] h3) Annealing to repair the crystal damage on the Si surface caused by ion implantation;

[0155] h4) HfO2 was deposited on the conductive channel of each fin by PECVD to form a gate oxide layer 4;

[0156] Step i: Prepare trench metal electrode 5 and gate electrode 6.

[0157] i1) Deposit metallic Ti in the trench using a sputtering process in a vacuum environment to form a trench metal electrode 5;

[0158] i2) In a vacuum environment, a sputtering process is used to deposit gate metal Ti on multiple gate oxide layers 4 to form an integral gate 6, thus completing the fabrication of the entire field-effect transistor.

[0159] Furthermore, to demonstrate the single-event immunity of the trench electrode-containing FinFET transistor of the present invention compared to conventional FinFET devices, the following simulation results will be used for illustration:

[0160] (I) Simulation Parameters

[0161] Assume a drain voltage of 0.8V, a gate voltage of 0V, a source and substrate grounded, and a trench metal electrode bias voltage of 0.2V; the incident particle energy LET is 20MeV·cm. 2 / mg, with a characteristic radius of 0.05um, incident perpendicularly from the drain electrode.

[0162] (II) Simulation Content

[0163] Under the above parameter conditions, the single-event effect simulation was performed on a conventional FinFET transistor and the transistor of Embodiment 5 of this invention using the device simulation function of Silvaco TCAD software. Please refer to [link to relevant documentation]. Figures 4 to 6 ,in, Figure 4 This is an electron distribution diagram (vertical cross-sectional view) of a conventional FinFET device under single-event simulation; Figure 5 This is an electron distribution diagram (longitudinal cross-sectional view) of a trench electrode-based FinFET transistor device resisting single-event effects provided by an embodiment of the present invention under single-event simulation. Figure 6 The graphs show the current transient curves of a conventional FinFET device and the FinFET transistor of Embodiment 5 of this invention under single-particle incident conditions.

[0164] from Figure 4 and Figure 5It can be seen that conventional FinFET devices have a radially symmetrical potential distribution around the ion orbitals. Under the same particle incident conditions, the device prepared in Example 5 of this invention exhibits a significantly reduced electron density distribution in the region below the Fin due to the presence of the trench electrode. This traps a large number of electrons generated by single-particle incident, preventing diffusion to the drain region. The hole density results are similar to the electron density results.

[0165] from Figure 6 As can be seen, the peak drain current of the FinFET resisting single-event effects of this invention is 0.5 mA, and the collected charge is 3.22 fF obtained by integrating the current with time. The peak drain current of a conventional FinFET is 1.75 mA, and the collected charge is 13.34 fF obtained by integrating the current with time. The single-event-resistant structure of this invention has a smaller peak drain current and less collected charge, and has better performance under single-event irradiation conditions.

[0166] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A FinFET device with trench electrodes that resists single-event effects, characterized in that, It includes a substrate layer (1), a fin (2), a shallow trench isolation region (3), a gate oxide layer (4), a trench metal electrode (5), and a gate (6), wherein, The shallow trench isolation region (3) is disposed on the upper surface of the substrate layer (1), and the fin (2) is disposed in the central region above the shallow trench isolation region (3) and extends downward to contact the upper surface of the substrate layer (1). The fin (2) includes a source electrode (21) and a drain electrode (23) located at both ends along the longitudinal direction, and a conductive channel (22) located between the source electrode (21) and the drain electrode (23). A trench metal electrode (5) is provided on each side of the longitudinal direction of the fin (2). The side of the trench metal electrode (5) is spaced from the fin (2) and the lower surface of the trench metal electrode (5) extends into the substrate layer (1). The gate oxide layer (4) covers the upper surface and side of the conductive channel (22). The gate (6) covers the upper surface and side of the gate oxide layer (4). The lower end of the trench metal electrode (5) is embedded in the shallow trench isolation region (3) and the substrate layer (1) with an embedding depth of 100nm~500nm. The distance between the trench metal electrode (5) and the fin (2) is 10nm~50nm; The trench metal electrode (5) is made of one of Al, Ni, Ti, or chromium-nickel alloy; When the device is in operation, a controllable electric field is formed in the substrate layer (1) below the fin (2) by applying a voltage to the two trench metal electrodes (5), causing electrons generated by single-particle incident to... Hole pairs are displaced before reaching the drain, thus reducing the amount of charge collected at the drain. The anti-single-event FinFET device includes multiple fins (2), which are arranged in parallel in the central region of the upper surface of the shallow trench isolation region (3) and extend downward to contact the upper surface of the substrate layer (1).

2. The trench electrode-based FinFET device resistant to single-event effects according to claim 1, characterized in that, The substrate (1) is made of Si material and is doped with phosphorus or arsenic ions at a concentration of 1. 10 16 cm -3 ~5 10 16 cm -3 .

3. The single-event resisting FinFET device with trench electrodes according to claim 1, characterized in that, The shallow trench isolation region (3) is made of Si3N4 material, and the gate oxide layer (4) is made of HfO2 material.

4. The trench electrode-based FinFET device resistant to single-event effects according to claim 1, characterized in that, The fin (2) is made of Si material, wherein the source (21) and the drain (23) are both N-type doped with a doping concentration of 1. 10 19 cm -3 ~1 10 21 cm -3 The conductive channel (22) is P-type doped with a doping concentration of 1. 10 17 cm -3 ~5 10 17 cm -3 .

5. The trench electrode-based FinFET device resistant to single-event effects according to claim 1, characterized in that, The gate (6) is made of one of Al, Ni, Ti, or chromium-nickel alloy.

6. A method for fabricating a FinFET device with trench electrodes that resists single-event effects, characterized in that, The method for fabricating a trench electrode-resistant FinFET device according to any one of claims 1 to 5, the fabrication method comprising: S1: Phosphorus or arsenic ions are doped into Si material to form a P-type substrate layer; S2: At least one fin is formed on the upper surface of the P-type substrate layer, the fin including a source and a drain at both ends and a conductive channel between the source and the drain; S3: Prepare shallow trench isolation regions on the upper surface of the P-type substrate layer on both sides of the fin; S4: A trench is formed on the shallow trench isolation area on both sides of the fin, and the trench extends downward into the interior of the P-type substrate layer; S5: A source electrode and a drain electrode located at both ends and a conductive channel located in the middle are formed on the fin, and a gate oxide layer is prepared on the conductive channel; S6: A trench metal electrode is formed inside the trench, and a gate electrode is formed on the gate oxide layer.

7. The method for fabricating a trench electrode-based FinFET device resistant to single-event effects according to claim 6, characterized in that, S2 includes: S2.1: A Si3N4 layer and a polycrystalline silicon auxiliary layer are sequentially prepared on the P-type substrate layer; S2.2: Etch away both sides of the polysilicon auxiliary layer to form a hard mask auxiliary layer located in the middle of the upper surface of the Si3N4 layer, and grow SiO2 on the Si3N4 layer and the hard mask auxiliary layer to form a SiO2 layer covering the Si3N4 layer and the hard mask auxiliary layer; S2.3: Etch the SiO2 layer to form sidewalls on both sides of the hard mask auxiliary layer; then remove the hard mask auxiliary layer between the sidewalls; S2.4: Using the sidewall as a mask, perform photolithography on the Si3N4 layer and the P-type substrate layer to etch away the Si3N4 layer and part of the thickness of the P-type substrate layer in the area not covered by the sidewall to form the fin; then remove the sidewall and retain the Si3N4 layer above the fin.

8. The method for fabricating a trench electrode-based FinFET device resistant to single-event effects according to claim 6 or 7, characterized in that, S5 includes: N-type doping is performed at both ends of the fin in the longitudinal direction using phosphorus ion implantation to form the source and drain. P-type doping is performed on the conductive channel between the source and drain of the fin using boron ion implantation. After annealing, HfO2 material is deposited on the upper surface and side surface of the conductive channel of the fin to form a gate oxide layer.

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