Package structure and method of forming the same

Abstract

The embodiments of the present disclosure provide a packaging structure and a forming method thereof. The packaging structure comprises a first die and a second die, and a packaging connecting member comprising a bridge die and an encapsulation layer. The packaging connecting member is arranged on one side of the first die and the second die in a first direction perpendicular to main surfaces of the first die and the second die, and is electrically connected to the first die and the second die. The bridge die comprises at least a first interconnection structure. The first interconnection structure comprises a first organic dielectric structure and a first rewiring structure. The first rewiring structure is embedded in the first organic dielectric structure and is used to electrically connect the first die to the second die. The encapsulation layer is arranged on the side of the bridge die in a second direction parallel to the main surfaces of the first die and the second die, and encapsulates at least the sidewall of the bridge die.

Description

Technical Field

[0001] Embodiments of this disclosure relate to an encapsulation structure and a method of forming the same. Background Technology

[0002] Semiconductor packaging technology can integrate multiple chips together, such as a system-on-a-chip (SoC) and a memory chip, to provide high bandwidth and enable high-performance computing (HPC) to the SoC. However, reducing manufacturing costs, minimizing signal loss, and improving power integrity remain challenges for current packaging technologies. Summary of the Invention

[0003] According to at least one embodiment of the present disclosure, a packaging structure is provided, comprising: a first die and a second die; and a packaging connection member including a bridging die and an encapsulation layer, wherein the packaging connection member is disposed on one side of the first die and the second die in a first direction perpendicular to the main surfaces of the first die and the second die, and is electrically connected to the first die and the second die, wherein the bridging die includes at least a first interconnect structure, the first interconnect structure including a first organic dielectric structure and a first rewiring structure, the first rewiring structure being embedded in the first organic dielectric structure and used to electrically connect the first die to the second die; and the encapsulation layer is disposed on the side of the bridging die in a second direction parallel to the main surfaces of the first die and the second die, and at least encapsulates the sidewall of the bridging die.

[0004] In the packaging structure provided according to at least one embodiment of the present disclosure, the packaging connection member further includes: a conductive post located on the side of the bridge die in the first direction and laterally encapsulated by the encapsulation layer, wherein the conductive post provides an electrical connection between the first die and the second die and an external conductive connector.

[0005] The packaging structure provided according to at least one embodiment of the present disclosure further includes: a second interconnect structure disposed in the first direction between the bridging die, the encapsulation layer, the conductive post, and the first die and the second die, and the second interconnect structure includes a second organic dielectric structure and a second rewiring structure embedded in the second organic dielectric structure, wherein the first die and the second die are electrically connected to each other through a first portion of the second rewiring structure and the bridging die, and are electrically connected to the conductive post through a second portion of the second rewiring structure.

[0006] In the packaging structure provided according to at least one embodiment of the present disclosure, the line spacing of the rewiring layer in the first rewiring structure is smaller than the line spacing of the rewiring layer in the second rewiring structure.

[0007] In a packaging structure provided according to at least one embodiment of the present disclosure, the first organic dielectric structure and the first redistribution structure include at least one organic dielectric layer and at least one redistribution layer stacked on top of each other. The first redistribution layer in the at least one redistribution layer includes a seed layer and a conductive layer, and the orthographic projection of the seed layer on the main surface of the first organic dielectric structure in the first direction is located within the orthographic projection range of the conductive layer on the main surface of the first organic dielectric structure in the first direction.

[0008] In a packaging structure provided according to at least one embodiment of the present disclosure, in the second direction, the sidewall of the seed layer is laterally recessed relative to the sidewall of the conductive layer.

[0009] In a packaging structure provided according to at least one embodiment of the present disclosure, the conductive layer has a sidewall in contact with the at least one organic dielectric layer.

[0010] In a packaging structure provided according to at least one embodiment of the present disclosure, the first organic dielectric structure includes a first organic dielectric layer and a second organic dielectric layer; the first redistribution structure includes an initial redistribution layer and a first redistribution layer, the initial redistribution layer being embedded in the first organic dielectric layer, and the first redistribution layer extending through the first organic dielectric layer to connect to the initial redistribution layer; the first redistribution layer includes a via portion located in the first organic dielectric layer and a trace portion located in the second organic dielectric layer, wherein the main surface of the second organic dielectric layer is closer to the first die and the second die than the main surface of the trace portion of the first redistribution layer.

[0011] In the packaging structure provided according to at least one embodiment of the present disclosure, the organic dielectric structure comprises a polymer material.

[0012] In the encapsulation structure provided according to at least one embodiment of the present disclosure, the encapsulation layer comprises an organic dielectric material.

[0013] In a packaging structure provided according to at least one embodiment of the present disclosure, the surface of the first interconnect structure of the bridge die away from the first die and the second die is flush with the surface of the encapsulation layer away from the first die and the second die in the second direction.

[0014] In a packaging structure provided according to at least one embodiment of the present disclosure, the bridge die further includes a substrate located on the side of the first interconnect structure away from the first die and the second die, and a portion of the encapsulation layer is located on the side of the substrate in the second direction.

[0015] In the packaging structure provided according to at least one embodiment of the present disclosure, the substrate includes a semiconductor substrate or an insulating substrate.

[0016] The packaging structure provided according to at least one embodiment of the present disclosure further includes: a passive device die, embedded in the packaging connection member, wherein the passive device die is arranged side by side with the bridge die in the second direction and is laterally encapsulated by the encapsulation layer, and the passive device die is electrically connected to at least one of the first die and the second die.

[0017] In a packaging structure provided according to at least one embodiment of the present disclosure, the passive device die includes a deep trench capacitor.

[0018] The packaging structure provided according to at least one embodiment of this disclosure further includes: a conductive connector disposed on the side of the packaging connector away from the first die and the second die, and electrically connected to the first die and the second die through the packaging connector; and a packaging substrate disposed on the side of the conductive connector away from the packaging connector, and electrically connected to the first die and the second die through the conductive connector and the packaging connector.

[0019] At least one embodiment of this disclosure provides a method for forming a package structure, comprising: providing a first die and a second die; and forming a package connection member for electrically connecting to the first die and the second die, the package connection member being disposed on one side of the first die and the second die in a first direction perpendicular to the main surfaces of the first die and the second die, wherein forming the package connection member comprises: forming a bridging die, the bridging die including at least a first interconnect structure, the first interconnect structure including a first organic dielectric structure and a first rewiring structure, the first rewiring structure being embedded in the first organic dielectric structure and used to electrically connect the first die to the second die; and forming an encapsulation layer, the encapsulation layer being formed on the side of the bridging die in a second direction parallel to the main surfaces of the first die and the second die to encapsulate the sidewall of the bridging die.

[0020] According to at least one embodiment of the present disclosure, the method of forming a packaging structure includes: providing a substrate; and forming a first interconnect structure on the substrate, wherein forming the first interconnect structure includes: forming an initial organic dielectric layer on the substrate, and forming an initial redistribution layer on a side of the initial organic dielectric layer away from the substrate; forming a first organic dielectric layer with an opening on the side of the initial organic dielectric layer and the initial redistribution layer away from the substrate, the opening exposing a portion of the surface of the initial redistribution layer away from the substrate; forming a seed layer on the first organic dielectric layer, and the seed layer filling the opening to contact the initial redistribution layer; forming a conductive layer on a first portion of the seed layer; and removing a second portion of the seed layer not covered by the conductive layer, wherein the remaining first portion of the seed layer and the conductive layer constitute a first redistribution layer, the first redistribution layer being electrically connected to the initial redistribution layer.

[0021] In a method for forming a packaging structure according to at least one embodiment of the present disclosure, forming the conductive layer on the first portion of the seed layer includes: forming a patterned mask layer having a mask opening on the seed layer to cover the second portion of the seed layer, wherein the mask opening exposes the first portion of the seed layer; and forming the conductive layer in the mask opening on the first portion of the seed layer.

[0022] In a method for forming a packaging structure according to at least one embodiment of the present disclosure, removing the second portion of the seed layer not covered by the conductive layer includes: removing the patterned mask layer; and using the conductive layer as an etching mask to perform an etching process on the seed layer.

[0023] The method for forming a packaging structure according to at least one embodiment of the present disclosure further includes: removing the substrate of the bridging die, and such that the first interconnect structure of the bridging die and the encapsulation layer have surfaces flush with each other in the second direction on the side away from the first die and the second die.

[0024] In a method for forming an encapsulation structure according to at least one embodiment of the present disclosure, forming the encapsulation connection member further includes: forming a conductive post before forming the encapsulation layer, wherein the conductive post is disposed on the side of the bridge tube core in the second direction, and the encapsulation layer is formed to also encapsulate the sidewall of the conductive post.

[0025] In a method for forming a packaging structure according to at least one embodiment of the present disclosure, forming the packaging connection member further includes: forming a second interconnect structure on the side of the bridging die, the conductive post, and the encapsulation layer near the first die and the second die, the second interconnect structure including a second organic dielectric structure and a second rewiring structure embedded in the second organic dielectric structure, wherein the first die and the second die are electrically connected to the bridging die and the conductive post through the second rewiring structure.

[0026] In a method for forming a packaging structure according to at least one embodiment of the present disclosure, before forming the encapsulation layer, the method further includes: providing a passive device die, wherein the passive device die and the bridge die are arranged side by side in the second direction, and the encapsulation layer is formed to also encapsulate the sidewall of the passive device die.

[0027] The method for forming a packaging structure according to at least one embodiment of the present disclosure further includes: forming a conductive connector on the side of the packaging connecting member away from the first die and the second die; and electrically connecting the conductive connector to the packaging substrate. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0029] Figure 1A and Figure 1B A schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown.

[0030] Figure 2A and Figure 2B A schematic cross-sectional view of a packaging structure according to other embodiments of the present disclosure is shown; Figure 2C A schematic plan view of a packaging structure according to some embodiments of the present disclosure is shown.

[0031] Figures 3A to 3P A schematic cross-sectional view showing a method for forming a bridge pipe core according to some embodiments of the present disclosure.

[0032] Figures 4A to 4G A schematic cross-sectional view is shown illustrating a method of forming a packaging structure according to some embodiments of the present disclosure.

[0033] Figures 5A to 5B A schematic cross-sectional view showing a method of forming a packaging structure according to other embodiments of the present disclosure. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0035] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0036] Figure 1A and Figure 1B A schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown.

[0037] Reference Figure 1A In some embodiments, the encapsulation structure 50a includes a die 10, a die 20a, a die 20b, an encapsulation connection member 9a, an encapsulation layer 12, and an external connector 15. Dies 10, 20a, and 20b are disposed on one side of the encapsulation connection member 9a and are surrounded and covered by the encapsulation layer 12. The connector 15 is disposed on the side of the encapsulation connection member 9a opposite to the dies 10a, 20a, and 20b. The plurality of dies 10, 20a, and 20b are electrically connected to each other through the encapsulation connection member 9a and can be further connected to the external connector 15 through the encapsulation connection member 9a. The encapsulation structure 50a can be further connected to other encapsulation components through the external connector 15.

[0038] In some embodiments, the encapsulation connection member 9a may be an interposer and includes, for example, a substrate 1, a through-substrate via (TSV) 2, and an interconnect structure 6. The substrate 1 may be a semiconductor substrate, such as a silicon substrate. The interconnect structure 6 is disposed on the side of the substrate 1 near the die and may include a dielectric structure 3 and conductive traces 5 embedded in the dielectric structure 3. The conductive traces 5 provide electrical connections between the individual dies and between the individual dies and the through-substrate via 2; that is, dies 10, 20a, and 20b are electrically connected to each other through some portions of the conductive traces 5 in the interposer and electrically connected to the external connector 15 through other portions of the conductive traces 5 in the interposer and the through-substrate via 2. In some embodiments, the dielectric structure 3 includes an inorganic dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, the like, or combinations thereof; the conductive traces 5 may include a metallic material such as copper and may be formed in the dielectric structure 3 by an inlay process (e.g., a damascene process). In some embodiments, the interposer may also include a passive device integrated therein, such as a capacitor (not shown).

[0039] Reference Figure 1B Package structure 50b is similar to package structure 50a, except that in package structure 50b, the package connection member 9b includes a bridge die 8, an encapsulation structure MS, and multiple conductive members 7a and 7b. Multiple dies 10, 20a, and 20b are electrically connected to each other via the bridge die 8 and conductive members 7a, and are connected to conductive connector 15 via conductive members 7b. In some embodiments, the bridge die 8 is, for example, a die formed based on a semiconductor substrate (e.g., a silicon substrate), and may include conductive traces 8b embedded in the dielectric structure 8a to provide electrical connections between different dies. The dielectric structure 8a may include inorganic dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride. The conductive traces 8b may include metallic materials such as copper, and the conductive traces 8b may be formed in the dielectric structure 8a via a damascene process (e.g., a dual damascene process). The encapsulation structure MS surrounds and encapsulates the bridge die 8 and the multiple conductive members 7a and 7b. The encapsulation structure MS may include organic dielectric materials such as polymers; for example, the encapsulation structure MS may be a molding compound. In some embodiments, the bridge core 8 includes only a substrate and interconnect structures for electrical connection, without additional active or passive devices.

[0040] In package structures 50a and 50b, dies 10, 20a, and 20b are integrated together via an interposer or a package connection component including bridge dies; for example, die 10 is a system-on-chip (SoC), and dies 20a and 20b are memory dies, such as high-bandwidth memory (HBM) chips. However, in Figure 1A In embodiments using an interposer as a package interconnect component, the interposer is formed from a large-size silicon substrate, and the interconnect structure 6 is formed using semiconductor processes including damascene technology. This results in higher manufacturing costs and smaller linewidths of the formed conductive traces 5, potentially leading to greater signal loss. Furthermore, when the interposer includes passive components such as capacitors, the larger silicon interposer may generate significant capacitor leakage current, thus affecting the yield of the package structure. Figure 1B In embodiments using a bridging die as a package connection component, the conductive traces in the bridging die are formed within an inorganic dielectric structure using an inlay process. This manufacturing process may limit the production of the bridging die 8 to silicon wafer fabrication plants, thereby restricting the supply chain of the bridging die 8 to some extent. Furthermore, the conductive traces formed by the inlay process have a smaller linewidth and higher signal loss, thus affecting device performance. On the other hand, the dielectric structure 8a and the encapsulation structure MS in the bridging die 8 are made of inorganic and organic dielectric materials, respectively, with a significant difference in their coefficients of thermal expansion. This mismatch in coefficients of thermal expansion may lead to warping of the package structure and generate additional stress on the components within the package structure. Additionally, in the package structure 50b, no capacitor is provided in the package connection component including the bridging die, which may affect the power integrity (PI) of the package structure to some extent.

[0041] To address the aforementioned problems, other embodiments of this disclosure provide a packaging structure and a method for manufacturing the same. The packaging structure includes a plurality of dies and packaging connection members. The packaging connection members provide interconnections between the plurality of dies and electrical connections between the plurality of dies and external components. For example, the packaging connection members include bridging dies and an encapsulation layer. The bridging dies include at least an interconnection structure for realizing electrical connections between the plurality of dies. For example, the interconnection structure includes a redistribution structure embedded in a dielectric structure. In some embodiments, the interconnection structure of the bridging dies is formed using an organic dielectric material, and the redistribution structure formation process includes forming a seed layer using a sputtering process and forming a conductive layer on the seed layer using a plating (e.g., electroplating) process. The redistribution layer in the redistribution structure formed using this process is compared to... Figure 1A and Figure 1B Conductive traces formed using damascene technology (e.g., Figure 1AConductive traces 5 and 6 in the interconnect structure 6 Figure 1B The conductive traces 8b) of the bridge core 8 can have a larger line width / pitch and / or thickness, which can reduce signal loss and, for example, facilitate high-speed signal transmission, thereby improving device performance. In this document, "line width" refers to the width of a trace or wiring in a direction perpendicular to its extension direction, and "pitch" refers to the distance between the centers of adjacent traces or wirings, and may also be referred to as the center-to-center spacing.

[0042] On the other hand, the interconnect structure in the bridge die uses an organic dielectric structure, and the encapsulation layer also includes an organic dielectric material. Since their coefficients of thermal expansion are similar, this avoids or reduces the mismatch in the coefficients of thermal expansion between the dielectric structure in the interconnect structure and the encapsulation layer, thereby avoiding or reducing problems such as package warpage caused by this mismatch. Furthermore, in this embodiment, the dielectric structure in the interconnect structure of the bridge die uses an organic dielectric material, and the redistribution layer is formed within the dielectric structure using the aforementioned processes including sputtering and plating. This manufacturing process for the interconnect structure can also be completed at the outsourced semiconductor assembly and testing (OSAT) end. Therefore, the supply chain for the bridge die in this embodiment is more flexible, and the manufacturing cost is lower.

[0043] Furthermore, a passive device die (e.g., including a capacitor) can be incorporated into the encapsulation connection component to improve the power integrity of the device; and, compared to Figure 1A The passive device integrated into the silicon interposer in this embodiment can be embedded in the encapsulation layer and can be arranged separately side-by-side with the bridge die. During the packaging process, selecting a suitable passive device die for packaging can avoid issues such as… Figure 1A The illustrated embodiment may show a situation where leakage current generated by passive devices such as capacitors can cause the entire package connection component to fail. This can be better controlled and improve product yield.

[0044] Figure 2A and 2B A schematic cross-sectional view of a packaging structure according to some embodiments of the present disclosure is shown. Figure 2C A schematic top view of a packaging structure according to some embodiments of the present disclosure is shown. It should be understood that, for the sake of brevity, Figure 2C The image shows some of the components in the packaging structure.

[0045] Reference Figure 2A and Figure 2CIn some embodiments, the package structure 200 includes a plurality of dies (e.g., dies 120 and 122), a package connection member 110, an encapsulation layer 126, and a conductive connector 130. The package connection member 110 is located on one side of dies 120 and 122 in a direction perpendicular to the main surfaces of dies 120 and 122 (e.g., direction D1) and is used to integrate the plurality of dies 120 and 122 together. The encapsulation layer 126 is located on the side of the package connection member 110 near the dies 120 and 122 in direction D1 and surrounds and encapsulates the plurality of dies 120 and 122. The conductive connector 130 is located on the side of the package connection member 110 away from the plurality of dies 120 and 122 and is electrically connected to the package connection member 110. For example, the package connection member 110 may provide electrical connections between the plurality of dies 120 and 122 and electrical connections between the plurality of dies 120 and 122 and the conductive connector 130. That is, multiple dies 120 and 122 are electrically connected to each other through encapsulation connection member 110, and can be connected to conductive connector 130 through encapsulation connection member 110, and can be further connected to other encapsulation members, such as encapsulation substrate, through conductive connector 130.

[0046] In some embodiments, die 120 and die 122 may also be referred to as the first die and the second die, respectively; it should be understood that the number of dies shown in the figures is merely illustrative and is not intended to limit the scope of this disclosure. Each die may be of any suitable type, such as a system-on-a-chip (SoC), a memory chip, or other type of chip, and the dies may be or include dies of the same or different types. For example, die 120 may be a SoC and include logic circuits and input / output circuits; die 122 may be a memory die, and in some examples a high bandwidth memory (HBM) chip, but this disclosure is not limited thereto. Dies 120 and 122 are arranged side-by-side in a direction D2 that intersects (e.g., is substantially perpendicular to) direction D1. The dimensions of dies 120 and 122 may be the same or different from each other, and this disclosure is not intended to limit the scope of this disclosure.

[0047] In some embodiments, the encapsulation connection member 110 includes a bridging die BD, a conductive post 105, an encapsulation layer 106, and an interconnection structure 108. A plurality of dies 120 and 122 are electrically connected to each other via the interconnection structure 108 and the bridging die BD, and are electrically connected to a conductive connector 130 via the interconnection structure 108 and the conductive post 105. The bridging die BD is disposed on one side of the plurality of dies 120 and 122 in direction D1 and may overlap (e.g., partially overlap) with the plurality of dies 120 and 122. For example, the orthographic projection of the bridging die BD in direction D1 onto the main surface of the encapsulation connection member 110 partially coincides with the orthographic projection of the plurality of dies 120 and 122 in direction D1 onto the main surface of the encapsulation connection member 110. The bridging die BD is used to provide electrical interconnection between the plurality of dies 120 and 122.

[0048] In some embodiments, the bridging die BD includes a substrate 80 and an interconnect structure 88. The substrate 80 may be a semiconductor substrate or an insulating substrate. For example, the substrate 80 may be a silicon substrate, a glass substrate comprising silicon oxide, or an insulating substrate comprising an organic dielectric material. The interconnect structure 88 is located on one side of the substrate 80 near the plurality of dies 120 and 122, and may include an organic dielectric structure OS1 and a redistribution structure RS1. The redistribution structure RS1 is embedded in the organic dielectric structure OS1 and is used to provide electrical connections between the plurality of dies 120 and 122.

[0049] Figure 3P A schematic cross-sectional view of a bridge pipe core BD according to some embodiments of the present disclosure is shown.

[0050] Reference Figure 2A and Figure 3PIn some embodiments, in the bridge core BD, the organic dielectric structure OS1 and the redistribution structure RS1 of the interconnect structure 88 include at least one organic dielectric layer and at least one redistribution layer stacked on top of each other. For example, the organic dielectric structure OS1 includes multiple (e.g., sequentially stacked in direction D1) organic dielectric layers 81, 82, 83, 84, and the redistribution structure RS1 includes multiple (e.g., sequentially stacked in direction D1) redistribution layers RL1, RL2, RL3, RL4. Multiple organic dielectric layers 81-84 and multiple redistribution layers RL1-RL4 are stacked alternately on top of each other. For example, redistribution layer RL1 is located on organic dielectric layer 81, and organic dielectric layer 82 covers redistribution layer RL1; redistribution layer RL2 is located on organic dielectric layer 82 and extends through organic dielectric layer 82 to be electrically connected to redistribution layer RL1; organic dielectric layer 83 covers redistribution layer RL2, and redistribution layer RL3 is located on organic dielectric layer 83 and extends through organic dielectric layer 83 to be electrically connected to redistribution layer RL2; organic dielectric layer 84 covers redistribution layer RL3, and redistribution layer RL4 is located on organic dielectric layer 84 and extends through organic dielectric layer 84 to be electrically connected to redistribution layer RL3. In some embodiments, the organic dielectric layer 81 and the redistribution layer RL1, which are closest to the substrate 80 and furthest from the dies 120 and 122, may be referred to as the initial organic dielectric layer and the initial redistribution layer, respectively; the organic dielectric layers 82 and 83 may be referred to as the first organic dielectric layer and the second organic dielectric layer, respectively; the redistribution layers RL2 and RL3 may be referred to as the first redistribution layer and the second redistribution layer, respectively; and the organic dielectric layer 84, which is furthest from the substrate 80 and closest to the dies 120 and 122, and the redistribution layer RL4 may be referred to as the end organic dielectric layer and the conductive pad, respectively.

[0051] In some embodiments, the plurality of organic dielectric layers in the organic dielectric structure OS1 may each comprise a suitable organic dielectric material, such as a polymer material including polyimide. The plurality of redistribution layers RL1-RL4 in the redistribution structure RS1 may comprise metallic materials such as titanium, copper, or tungsten. Each redistribution layer may comprise a seed layer and a conductive layer. For example, such as... Figure 3P As shown in the enlarged view, the redistribution layer RL2 includes a seed layer SL and a conductive layer ML. The seed layer SL is a metal seed layer, such as a copper metal layer, and may include metal materials such as titanium, copper, and tungsten. The conductive layer ML includes metal materials such as copper.

[0052] Continue to refer to Figure 2A and Figure 3PIn some embodiments, the conductive layer ML is located on the side of the seed layer SL away from the substrate 80 and close to the dies 120 and 122. The seed layer SL and the conductive layer ML overlap each other in direction D1, and the orthographic projection of the seed layer SL in direction D1 onto the main surface of the organic dielectric structure OS1 is within the orthographic projection range of the conductive layer ML in direction D1 onto the main surface of the organic dielectric structure OS1. In some embodiments, the sidewall S1 of the seed layer SL is laterally recessed in direction D2 relative to the sidewall S2 of the conductive layer ML.

[0053] In some embodiments, one or more redistribution layers each include via portions and trace portions connected to each other, the via portions being embedded in a respective organic dielectric layer, and the trace portions extending on the main surface of the organic dielectric layer. The trace portions of redistribution layers located in different layers are electrically connected to each other through the via portions. For example, redistribution layer RL2 includes a via portion V embedded in organic dielectric layer 82 and a trace portion T extending on the main surface of organic dielectric layer 82, with organic dielectric layer 83 covering the sidewalls of trace portion T and its surface away from organic dielectric layer 82. In some embodiments, the surface of organic dielectric layer 83 away from organic dielectric layer 82 and the surface of trace portion T of redistribution layer RL2 away from organic dielectric layer 82 are at different horizontal heights. For example, the surface of organic dielectric layer 83 away from organic dielectric layer 82 is further away from substrate 80 and closer to dies 120 and 122 than the surface of trace portion T of redistribution layer RL2 away from organic dielectric layer 82.

[0054] In some embodiments, each redistribution layer has a generally flat main surface, but this disclosure is not limited thereto.

[0055] Continue to refer to Figure 2A In some embodiments, the encapsulation layer 106 is located on the sides of the bridging die BD and the conductive pillar 105 in a direction parallel to the main surfaces of dies 120 and 122 (e.g., direction D2), and laterally encapsulates the sidewalls of the bridging die BD and the conductive pillar 105. For example, the encapsulation layer 106 surrounds the sidewalls of the organic dielectric structure OS1 that covers and contacts the substrate 80 of the bridging die BD and the interconnect structure 88. In some embodiments, the encapsulation layer 106 may also extend to cover the surface of the organic dielectric structure OS1 near the side of dies 120 and 122 (e.g., the main surface of the end organic dielectric layer 84 near the side of dies 120 and 122) and surround the sidewalls covering the portion of the redistribution layer RL4 that protrudes from the main surface of the organic dielectric layer 84.

[0056] In some embodiments, the encapsulation layer 80 also includes an organic dielectric material. For example, the encapsulation layer 80 may include a molding compound, such as an epoxy molding compound (EMC), but this disclosure is not limited thereto. Since the organic dielectric structure OS1 of the interconnect structure 88 of the bridging die BD uses an organic dielectric material, the coefficients of thermal expansion of the organic dielectric structure OS1 and the encapsulation layer 80 are similar. This avoids or reduces problems such as package structure warpage caused by the mismatch of the coefficients of thermal expansion between the dielectric structure OS1 of the bridging die and the encapsulation layer 80. On the other hand, in embodiments where the substrate 80 is an insulating substrate (e.g., a glass substrate), the coefficient of thermal expansion of the insulating substrate can be adjusted to be similar to that of the encapsulation layer 106 and / or the organic dielectric structure OS1, thereby avoiding or reducing problems such as package structure warpage caused by the mismatch of the coefficients of thermal expansion between different materials.

[0057] Continue to refer to Figure 2A In some embodiments, a plurality of conductive posts 105 are arranged in direction D2 around the bridging die BD and are laterally encapsulated by an encapsulation layer 106. An interconnection structure 108 is located between the bridging die BD and the encapsulation layer 106 and the plurality of dies 120 and 122, and provides electrical connections between the plurality of dies 120 and 122 and the bridging die BD, as well as electrical connections between the plurality of dies 120 and 122 and the conductive posts 105.

[0058] In some embodiments, interconnect structure 108 has a similar structure to interconnect structure 88 in bridge core BD, and interconnect structure 88 and interconnect structure 108 may be referred to as the first interconnect structure and the second interconnect structure, or vice versa. For example, interconnect structure 108 includes an organic dielectric structure OS2 and a redistribution structure RS2. The organic dielectric structure OS2 and redistribution structure RS2 may include at least one organic dielectric layer and at least one redistribution layer stacked on top of each other. For example, redistribution structure RS2 includes a plurality of redistribution layers RL11, RL12, RL13, and RL14 connected to each other. For simplicity, Figure 2A The number of organic dielectric layers included in the organic dielectric structure OS2 is not specifically shown in the figure. It should be understood that the number of organic dielectric layers and / or redistribution layers in the interconnect structures 88 and 108 shown in the figure are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0059] In some embodiments, a plurality of dies 120 and 122 are electrically connected to a redistribution structure RS2 of an interconnection structure 108 via a plurality of conductive connectors 123. In some embodiments, the interconnection structure 108 provides electrical connections between dies 120 and 122, and electrical connections between dies 120 and 122 and conductive posts 105; for example, in the interconnection structure 108, the redistribution structure RS2 includes a first portion P1 electrically connecting dies 120 and 122 to a bridging die BD and a second portion P2 electrically connecting dies 120 and 122 to the plurality of conductive posts 105. That is, dies 120 and 122 are electrically connected to each other via the first portion of the redistribution structure RS2 in the interconnection structure 108 and the redistribution structure RS1 in the bridging die BD, and dies 120 and 122 are connected to conductive connectors 130 via the second portion of the redistribution structure RS2 in the interconnection structure 108 and the plurality of conductive posts 105.

[0060] In some embodiments, interconnect structures 88 and 108 have different dimensions. For example, in direction D1, the dimensions (e.g., width, area, etc.) of interconnect structure 88 are smaller than those of interconnect structure 108, and the orthographic projection of interconnect structure 88 onto the main surface of encapsulation connection member 110 in direction D1 lies within the orthographic projection of interconnect structure 108 onto the main surface of encapsulation connection member 110 in direction D1. Interconnect structure 108 extends laterally beyond the sidewalls of interconnect structure 88 in direction D2, and the sidewalls of interconnect structure 108 may be substantially aligned with the sidewalls of encapsulation layer 106 in direction D1. In some embodiments, the linewidth of the redistribution layer of redistribution structure RS1 in interconnect structure 88 may be different from the linewidth of the redistribution layer of redistribution structure RS2 in interconnect structure 108. For example, the linewidth of the redistribution layer of redistribution structure RS1 may be smaller than the linewidth of the redistribution layer of redistribution structure RS2. In some embodiments, the thickness of the rerouting layer of rerouting structure RS1 in direction D1 is less than or equal to the thickness of the rerouting layer of rerouting structure RS2 in direction D1. In some embodiments, the rerouting structures of bridging core BD and interconnect structure 108 employ different line widths / spacings / thicknesses. On the other hand, the line width / spacing / thickness of the rerouting structure of bridging core BD is compared to... Figure 1B The conductive traces 8b of the bridge core B shown (formed in the inorganic dielectric structure 8a using an inlay process) have a larger line width, spacing, and thickness, which reduces signal loss.

[0061] Continue to refer to Figure 2A and Figure 2CIn some embodiments, the package structure 200 further includes a passive device die PD, which may be embedded in the package connection member 110 and connected to at least one of the plurality of dies 120 and 122. The passive device die PD may include passive devices such as capacitors (e.g., deep trench capacitors).

[0062] For example, a passive device die PD is arranged side-by-side with a bridging die BD and a conductive post 105 in direction D2, and is spaced apart from the bridging die BD. An encapsulation layer 106 encapsulates at least the sidewalls of the passive device die PD in direction D2. The passive device die PD has a conductive terminal CT, which is electrically connected to the redistribution structure RS2 of the interconnection structure 108. At least one of a plurality of dies 120 and 122 (e.g., die 120) is electrically connected to the conductive terminal CT of the passive device die PD via a conductive connector 123 and the interconnection structure 108 (e.g., the third portion P3 of the redistribution structure RS2). By incorporating, for example, a passive device die including a capacitor, the power integrity of the package structure 200 can be improved. On the other hand, since the passive device die PD is embedded in the packaging connection member 110 and is discretely separated from the bridge die BD, yield can be better controlled. For example, in the packaging process, selecting a good passive device die for packaging can avoid issues such as… Figure 1A The illustrated embodiment may show a situation where leakage current generated by passive devices such as capacitors can cause the entire package connection component to fail, thereby improving product yield.

[0063] In some embodiments, the surfaces of the substrate 80 of the bridging die BD, the passive device die PD, the plurality of conductive pillars 105, and the encapsulation layer 106 on the side away from the interconnect structure 108 and the plurality of dies 120 and 122 are substantially flush with each other in a direction parallel to the main surfaces of the plurality of dies 120 and 122 (e.g., direction D2). However, this disclosure is not limited thereto.

[0064] Figure 2B A schematic cross-sectional view of a package structure 200' according to an alternative embodiment of the present disclosure is shown. Package structure 200' is similar to package structure 200, except that in package structure 200', the bridge die BD includes interconnect structure 88 but does not include a substrate.

[0065] Reference Figure 2BThe interconnect structure 88 of the bridging die BD includes an organic dielectric structure OS1 and a redistribution structure RS1 embedded in the organic dielectric structure OS1. In some embodiments, the bridging die BD does not have a substrate on the side of the interconnect structure 88 away from the interconnect structure 108 and the plurality of dies 120 and 122, and the surface of the organic dielectric structure OS1 on the side away from the interconnect structure 108 and the plurality of dies 120 and 122 is substantially flush with the surfaces of the passive device die PD, the plurality of conductive pillars 105, and the encapsulation layer 106 on the side away from the interconnect structure 108 and the plurality of dies 120 and 122 in direction D2. In this embodiment, the bridging die BD does not include a substrate, thus avoiding problems such as package structure warping caused by thermal expansion coefficient mismatch due to the large difference in thermal expansion coefficients between the substrate material and the organic dielectric structure OS1 and the encapsulation layer 106. This also allows for greater freedom in the selection of the substrate material for the bridging die BD in the packaging structure manufacturing process.

[0066] In some embodiments, the packaging structures 200 and 200' may be further connected to other packaging components, such as the packaging substrate 220, via conductive connector 130. Figure 4G and Figure 5B ).

[0067] Figures 3A to 3P A schematic cross-sectional view is shown of each process step in a method for forming a bridge pipe core BD according to some embodiments of the present disclosure.

[0068] Reference Figure 3A A substrate 80 is provided, which may include semiconductor materials, insulating materials, or combinations thereof. For example, substrate 80 may be a semiconductor substrate (e.g., a silicon substrate), a glass substrate (e.g., including silicon oxide), but may alternatively or additionally include other suitable semiconductor materials and / or insulating materials (e.g., organic insulating materials). In some embodiments, the coefficient of thermal expansion of substrate 80 may be adjusted according to product requirements. For example, when using a glass substrate (or silicon oxide substrate), the coefficient of thermal expansion of the substrate may be adjusted by doping the silicon oxide glass and / or adjusting the type and amount of dopant, so that the coefficient of thermal expansion of substrate 80 is within a suitable range to be similar to the coefficient of thermal expansion of the subsequently formed encapsulation layer. In some embodiments, substrate 80 is a wafer including a plurality of die regions and diced regions (not shown), the diced regions being located between the plurality of die regions, and... Figures 3A to 3P The diagram illustrates the manufacturing process in a die region of a wafer. It should be understood that, prior to the dicing process, the structures and manufacturing processes of multiple die regions are substantially the same.

[0069] In some embodiments, an organic dielectric layer 81 is formed on the substrate 80. The material of the organic dielectric layer 81 may include polymer materials such as polyimide (PI), and it may be formed on the substrate 80 by a deposition process such as chemical vapor deposition or a spin coating process.

[0070] Reference Figures 3B to 3F A redistribution layer RL1 is formed on the organic dielectric layer 81. The redistribution layer RL1 includes a conductive material, such as a metallic material like titanium, copper, or tungsten. In some embodiments, forming the redistribution layer RL1 includes the following processes.

[0071] Reference Figure 3B A seed layer SL0' is formed on the organic dielectric layer 81. The seed layer SL0' can be a metallic seed layer, such as a seed layer used for copper plating. For example, the seed layer SL0' can include metallic materials such as titanium, tungsten, and copper, such as metal alloys including TiCu and TiWCu. In some embodiments, the seed layer SL0' can be formed by a sputtering process.

[0072] Reference Figure 3C In some embodiments, a patterned mask layer 79 is formed on the seed layer SL0' to cover a portion of the surface of the seed layer SL0' away from the organic dielectric layer 81. The patterned mask layer 79 may include a patterned photoresist layer and may be formed by forming a photoresist layer on the seed layer SL0' and then performing a photolithography process including exposure and development on the photoresist layer to remove a portion of the photoresist layer and form a mask opening 79a to expose a portion of the surface of the seed layer SL0'.

[0073] Reference Figure 3D A conductive layer ML0 is formed in the mask opening 79a of the patterned mask layer 79 on the portion of the seed layer SL0' exposed by the mask opening 79a. The conductive layer ML0 may include a metallic material such as copper and may be formed by a plating (e.g., electroplating) process.

[0074] Reference Figures 3D to 3FThe patterned mask layer 79 is removed to expose the seed layer SL0'. Then, the portion of the seed layer SL0' not covered by the conductive layer ML0 (i.e., the portion previously covered by the patterned mask layer 79) is removed to form the seed layer SL0. For example, after removing the patterned mask layer 79, the seed layer SL0' is etched using the conductive layer ML0 as an etching mask to remove the portion of the seed layer SL0' not covered by the conductive layer ML0. The remaining seed layer SL0 is located below the conductive layer ML0 (e.g., directly below in the figure), and the surface of the seed layer SL0 away from the organic dielectric layer 81 is covered by the conductive layer ML0 (e.g., completely covered). The seed layer SL0 and the conductive layer ML0 together constitute the redistribution layer RL1. In some embodiments, the orthographic projection of the seed layer SL0 onto the main surface of the substrate 80 in a direction perpendicular to the main surface of the substrate 80 is within the range of the orthographic projection of the conductive layer ML0 onto the main surface of the substrate 80 in a direction perpendicular to the main surface of the substrate 80.

[0075] Reference Figure 3F In some embodiments, the etching process described above includes a wet etching process and is, for example, isotropic. Therefore, the sidewalls of the formed seed layer SL0 may be laterally recessed relative to the sidewalls of the conductive layer ML0. That is, a lateral recess RC is formed on the side of the seed layer SL0 in a direction parallel to the main surface of the substrate 80, and the lateral recess RC is located between the conductive layer ML0 and the organic dielectric layer 81 in a direction perpendicular to the main surface of the substrate 80. However, the embodiments disclosed herein are not limited thereto.

[0076] Reference Figure 3G An organic dielectric layer 82 is formed on the redistribution layer RL1 to cover the sidewalls of the redistribution layer RL1 and its surface away from the organic dielectric layer 81. The material and formation method of the organic dielectric layer 82 are similar to those of the organic dielectric layer 81, and will not be described again here. It should be understood that, for the sake of brevity and clarity of the diagram, Figure 3G The seed layer and conductive layer of the redistribution layer RL1 are not specifically shown in the subsequent figures.

[0077] Reference Figure 3H The organic dielectric layer 82 is patterned to remove portions of the organic dielectric layer 82 that cover the redistribution layer RL1, and to form one or more openings OP1 in the organic dielectric layer 82. The openings expose portions of the surface of the redistribution layer RL1 away from the substrate 80. In some embodiments, the patterning process may include photolithography (including exposure and development), laser drilling, similar processes, or combinations thereof.

[0078] Reference Figure 3IA seed layer SL' is formed on the organic dielectric layer 82. The seed layer SL' can be a metallic seed layer, such as a seed layer for copper plating. The seed layer SL' covers the surface of the organic dielectric layer 82 away from the substrate 80 and the organic dielectric layer 81, and fills the opening OP1 to liner the surface of the opening OP1 and contact the portion of the redistribution layer RL1 previously exposed by the opening OP1. In some embodiments, the seed layer SL' can be a conformal layer, but this disclosure is not limited thereto. The seed layer SL' can include metallic materials such as titanium, tungsten, and copper, such as metal alloys including TiCu and TiWCu. In some embodiments, the seed layer SL' can be formed by a sputtering process.

[0079] Reference Figure 3J In some embodiments, a patterned mask layer 89 is formed on the seed layer SL' to cover a portion of the surface of the seed layer SL' remote from the organic dielectric layer 82. The patterned mask layer 89 may include a patterned photoresist layer and can be formed by forming a photoresist layer on the seed layer SL' and then performing a photolithography process including exposure and development on the photoresist layer to remove a portion of the photoresist layer and form a mask opening MOP. In some embodiments, the mask opening MOP exposes a portion of the seed layer SL' located in the opening OP1 and a portion located on the main surface of the organic dielectric layer 82.

[0080] Reference Figure 3K A conductive layer ML is formed in the mask opening MOP of the patterned mask layer 89 on the portion of the seed layer SL' exposed by the mask opening MOP. The conductive layer ML may include a metallic material such as copper and may be formed by a plating (e.g., electroplating) process.

[0081] Reference Figures 3L to 3M The patterned mask layer 89 is removed, followed by the removal of the portion of the seed layer SL' not covered by the conductive layer ML (i.e., the portion previously covered by the patterned mask layer 89) to form the seed layer SL. For example, after removing the patterned mask layer 89, the seed layer SL' is etched using the conductive layer ML as an etching mask to remove the portion of the seed layer SL' not covered by the conductive layer ML. The remaining seed layer SL is located below the conductive layer ML (e.g., directly below in the figure), and the surface of the seed layer SL away from the redistribution layer RL1 is covered by the conductive layer ML (e.g., completely covered). The seed layer SL and the conductive layer ML together constitute the redistribution layer RL2.

[0082] Reference Figure 3MThe figure shows an enlarged schematic diagram of a portion of the redistribution layer RL2. A seed layer SL is located between the conductive layer ML and the organic dielectric layer 82, and between the conductive layer ML and the redistribution layer RL1. The seed layer SL and the conductive layer ML overlap each other (e.g., completely overlap) in a direction perpendicular to the main surface of the substrate 80. In other words, the orthographic projections of the seed layer SL and the conductive layer ML onto the main surface of the substrate 80 in a direction perpendicular to the main surface of the substrate 80 coincide (e.g., completely coincide). In some embodiments, the orthographic projection of the seed layer SL onto the main surface of the substrate 80 is within the range of the orthographic projection of the conductive layer ML onto the main surface of the substrate 80.

[0083] In some embodiments, the redistribution layer RL2 includes a via portion V located in the opening OP1 of the organic dielectric layer 82 and a trace portion T extending on the main surface of the organic dielectric layer 82 away from the organic dielectric layer 81 (e.g., the top surface shown in the figure). The via portion V of the redistribution layer RL2 includes portions of the seed layer SL and the conductive layer ML located in the opening OP1 of the organic dielectric layer 82. In the via portion V, the seed layer SL surrounds the sidewall of the conductive layer ML and its surface near the side of the redistribution layer RL. The trace portion T of the redistribution layer RL2 includes portions of the seed layer SL and the conductive layer ML located on the main surface of the organic dielectric layer 82. In some embodiments, similar to the redistribution layer RL1, the seed layer of the redistribution layer RL2 also has similar characteristics. Figure 3F The lateral groove RC is shown; for example, in the trace portion T, the sidewall S1 of the seed layer SL is laterally recessed relative to the sidewall S2 of the conductive layer ML in a direction parallel to the main surface of the substrate 80, that is, a lateral groove is provided on the side of the seed layer SL, and the lateral groove is located between the conductive layer ML and the organic dielectric layer 82 in a direction perpendicular to the main surface of the substrate 80. The sidewall S2 of the conductive layer ML in the trace portion T is not covered by the seed layer SL.

[0084] As shown in the enlarged view of the redistribution layer RL2, in some embodiments, the main surface of the redistribution layer RL2 away from the redistribution layer RL1 is generally flat, but this disclosure is not limited thereto.

[0085] In some embodiments, the redistribution layer formed using the above-described process can have a larger linewidth / spacing and / or thickness compared to conductive traces formed using a mosaic process, thereby reducing signal loss and improving device performance. For example, the thickness T1 of the trace portion of the redistribution layer RL2 can be greater than 2 micrometers, for example, in the range of 2 to 5 micrometers.

[0086] Reference Figures 3N to 3P Then proceed with... Figure 3G to 3MA similar process is used to form more layers of organic dielectric layers and redistribution layers on organic dielectric layer 82 and redistribution layer RL2. For example, an organic dielectric layer 83 is formed on the side of the organic dielectric layer 82 and the redistribution layer RL2 away from the organic dielectric layer 81. The organic dielectric layer 83 covers the sidewalls of the redistribution layer RL2 and its surface away from the redistribution layer RL1. In this embodiment, the organic dielectric layer 83 covers and directly contacts the sidewalls S1 of the seed layer SL and the sidewalls S2 of the conductive layer ML of the redistribution layer RL2. Next, some portions of the organic dielectric layer 83 are removed to expose the portion of the redistribution layer RL2 surface away from the redistribution layer RL1. A redistribution layer RL3 is formed on the organic dielectric layer 83. The redistribution layer 83 extends on the main surface of the organic dielectric layer 83 away from the organic dielectric layer 82 and fills the opening of the organic dielectric layer 83 to be electrically connected to the redistribution layer RL2. Next, an organic dielectric layer 84 and a redistribution layer RL4 are formed on the organic dielectric layer 83 and the redistribution layer RL3. The redistribution layer RL4 extends through the organic dielectric layer 84 to be electrically connected to the redistribution layer RL3. It should be noted that the fabrication process of each redistribution layer RL1-RL4 is similar to that of redistribution layer RL2, and both include a seed layer and a conductive layer. However, for the sake of simplicity in the diagram, Figures 3J to 3K The seed layer and conductive layer of each redistribution layer are not specifically shown in the figure. It should be understood that the number of organic dielectric layers and redistribution layers shown in the figure is only for illustrative purposes, and this disclosure is not limited thereto. The number of organic dielectric layers and redistribution layers can be adjusted based on product needs.

[0087] In some embodiments, the redistribution layer RL3 also includes via portions embedded in the organic dielectric layer 83 and trace portions extending on the main surface of the organic dielectric layer 83; the redistribution layer furthest from the substrate 80 (e.g., the uppermost redistribution layer RL4 in the figure) includes via portions located in the organic dielectric layer 84 and pad portions protruding from the main surface of the organic dielectric layer 84, the pad portions being used for electrical connection with external components. In some embodiments, the redistribution layer RL4 may also be referred to as the conductive pad of the bridging core BD.

[0088] Reference Figure 3POrganic dielectric layers 81-84 constitute an organic dielectric structure OS1, redistribution layers RL1-RL4 constitute a redistribution structure RS1, and the organic dielectric structure OS1 and the redistribution structure RS1 constitute an interconnect structure 88. In some embodiments, the substrate 80 is a wafer, and the interconnect structure 88 is formed in each die region of the wafer. After the interconnect structure 88 is formed, a dicing process (e.g., laser dicing, mechanical sawing, or a combination thereof) is performed along the dicing region of the wafer to cut the multiple die regions of the wafer apart and form multiple independent bridge dies BD.

[0089] The bridging die BD includes a substrate 80 and an interconnect structure 88 located on one side of the substrate 80. In some embodiments, the bridging die BD does not include active devices such as transistors or passive devices such as capacitors. The bridging die BD can further be used in the packaging process to provide electrical connections between different dies (e.g., between a system-on-a-chip and a memory chip).

[0090] Figures 4A to 4G Schematic cross-sectional views are shown of various steps in a method of forming a package structure according to some embodiments of the present disclosure, wherein the package structure uses... Figures 3A to 3P The bridge tube core BD formed by the process is used as part of the encapsulation connection component.

[0091] Reference Figure 4A The present disclosure provides a carrier substrate 100, which may be, for example, a temporary carrier to be removed in subsequent process steps, and may be a glass carrier, a ceramic carrier, or a similar carrier, but is not limited thereto. The carrier substrate 100 may be made of any material that can provide structural support for the overlay structure in subsequent processes. In some embodiments, the carrier substrate 100 has a release layer 101 formed thereon, which may be formed of adhesives such as ultraviolet (UV) adhesive, light-to-heat conversion (LTHC) adhesive, or other types of adhesives. In subsequent processes, the release layer 101 may decompose under photothermal conditions, losing or reducing its adhesiveness, thereby detaching the carrier substrate 100 from the overlay structure to be formed in subsequent steps.

[0092] In some embodiments, a dielectric layer PL is formed over a carrier substrate 100. The dielectric layer PL may include, for example, a polymer material such as polyimide. A seed layer 102 is formed on the dielectric layer PL. The seed layer 102 may be a metal seed layer, such as a seed layer for copper plating. The seed layer 102 may include, for example, a metal material such as titanium, tungsten, or copper, and may be formed by a sputtering process. In some embodiments, the seed layer 102 may include TiCu, TiWCu, or the like. However, this disclosure is not limited thereto.

[0093] Reference Figure 4B A plurality of conductive pillars 105 are formed on the side of the seed layer 102 away from the carrier substrate 100. The conductive pillars 105 may include a metal material such as copper and can be formed by the following method: First, a patterned mask layer (e.g., a patterned photoresist layer) is formed on the side of the seed layer 102 away from the carrier substrate 100. The patterned mask layer has a plurality of mask openings to expose a portion of the surface of the seed layer 120 away from the carrier substrate 100. The positions of the plurality of mask openings correspond to the positions where the conductive pillars 105 are to be formed. Then, the plurality of conductive pillars 105 are formed on the seed layer 102 in the openings of the patterned mask layer by a plating (e.g., electroplating) process. After that, the patterned mask layer is removed.

[0094] Continue to refer to Figure 4B In some embodiments, the self Figures 3A to 3P The bridging die BD formed by the manufacturing process shown is mounted onto the carrier substrate 100. For example, the bridging die BD can be attached to the seed layer 102 on the carrier substrate 100 via a die attach film (DAF). In some embodiments, the substrate 80 of the bridging die BD faces the carrier substrate 100, and its redistribution structure RS1 is located on the side of the substrate 80 away from the carrier substrate 100, that is, the conductive pad RL4 of the redistribution structure RS1 faces upward for electrical connection in subsequent processes.

[0095] In some embodiments, a passive device die (PD) is also mounted above the carrier substrate 100, and its mounting method can be similar to that of the bridging die BD described above. The bridging die BD, the passive device die PD, and the conductive posts 105 are arranged side by side and spaced apart from each other on the carrier substrate 100. For example, the conductive posts 105 are disposed around the bridging die BD and the passive device die PD. It should be understood that, for the sake of simplicity, the die attachment film used to attach the bridging die BD and the passive device die PD is not shown in the figure. Furthermore, before mounting the bridging die BD and the passive device die PD onto the carrier substrate 100, both are tested, and known good dies are selected for mounting onto the carrier substrate 100 to control and improve product yield.

[0096] Passive device dies (PDs) may include passive devices such as capacitors and resistors, and this disclosure does not limit the type of passive device; appropriate types of passive device dies can be selected based on product requirements. Furthermore, the number of bridging dies (BDs) and passive device dies (PDs) shown in the figures is merely illustrative, and this disclosure is not limited thereto; appropriate numbers of bridging dies and passive device dies (PDs) can be selected based on product requirements.

[0097] like Figure 4B As shown in the enlarged view of the passive device die PD, in some embodiments, the passive device die PD may be or include a deep trench capacitor (DTC), and may include a substrate 90, electrodes E1 and E2, a dielectric material layer 91, conductive terminals CT1 and CT2, and a dielectric layer 92. The material of the substrate 90 may be selected from the same candidate material as the substrate 80 of the bridging die BD, and may be similar, the same, or different from the material of the substrate 80. For example, the substrate 90 may be a semiconductor substrate, such as a silicon substrate, but this disclosure is not limited thereto; the substrate 90 may also be an insulating substrate, such as a glass substrate, and may include insulating materials such as silicon oxide.

[0098] A deep trench capacitor includes electrodes E1 and E2 facing each other and a portion of a dielectric material layer 91 (or inter-electrode dielectric layer) interposed between electrodes E1 and E2. In some embodiments, a substrate 90 has a deep trench, and the capacitor electrodes E1 and E2, as well as a portion of the inter-electrode dielectric layer, extend into the deep trench of the substrate 90. In some embodiments where the substrate 90 is a semiconductor substrate, an insulating liner is also provided between the substrate 90 and the electrode E1 to electrically isolate the substrate 90 and the electrode E1.

[0099] In some embodiments, a dielectric material layer 91 covers the surfaces of electrodes E1 and E2 away from the substrate 90 and is located between electrodes E1 and E2 to isolate electrodes E1 and E2 from each other. The dielectric material layer 91 may comprise multiple dielectric materials, for example, a first dielectric layer located on the main surface of the substrate 90 and on the side of electrode E1, a second dielectric layer located on the side of the first dielectric layer away from the substrate and between electrodes E1 and E2 (at least a portion of the second dielectric layer serves as an inter-electrode dielectric layer), and a third dielectric layer located on the side of the second dielectric layer and electrode E2 away from the substrate. In some embodiments, the materials of the first to third dielectric layers may be the same or different, and may be selected from inorganic dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride, organic dielectric materials such as polypropylene, polystyrene, and polyethylene terephthalate, the like, or combinations thereof. In some embodiments, the second dielectric layer, including the inter-electrode dielectric layer, may be or include a high-k dielectric material, such as silicon nitride.

[0100] The dielectric layer 92 is disposed on the side of the dielectric material layer 91 away from the substrate 90, and may also be referred to as a passivation layer. In some embodiments, the dielectric layer 92 may be selected from inorganic dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride, organic dielectric materials including polymer materials such as polyimide, the like, or combinations thereof.

[0101] The deep trench capacitor includes multiple conductive terminals CT, including conductive terminals CT1 and CT2 respectively connected to electrodes E1 and E2. For example, conductive terminal CT1 extends through dielectric layer 92 and dielectric material layer 91 to be electrically connected to electrode E1, and conductive terminal CT2 extends through dielectric layer 92 and dielectric material layer 91 to be electrically connected to electrode E2. It should be understood that the number of conductive terminals CT shown in the figure is merely illustrative and is not intended to be limiting; for simplicity, the number of terminals CT is... Figure 4B The subsequent diagrams do not show the specific structure of the passive device die PD, and use two conductive terminals CT to indicate that it may include more conductive terminals.

[0102] In some embodiments, the materials of electrodes E1, E2 and conductive terminal CT may each be selected from suitable conductive materials, such as metallic materials such as copper, and the materials of electrodes E1, E2 and conductive terminal CT may be the same or different from each other.

[0103] Continue to refer to Figure 4BIn some embodiments, the bridging die BD and the passive device die PD may have approximately the same height. For example, the surface of the redistribution layer RL4 of the bridging die BD on the side away from the carrier substrate 100 and the surface of the conductive terminal CT of the passive device die PD on the side away from the carrier substrate 100 may be at approximately the same horizontal height relative to the main surface of the carrier substrate 100. However, this disclosure is not limited thereto.

[0104] Reference Figure 4C In some embodiments, an encapsulation layer 106 is formed on the carrier substrate 100. The encapsulation layer 106 is formed on the sides of the bridging die BD, the passive device die PD, and the conductive pillar 105, surrounding and encapsulating the sidewalls of the bridging die BD, the passive device die PD, and the conductive pillar 105. In some embodiments, it may also cover a portion of the surface of the bridging die BD and the passive device die PD away from the carrier substrate 100. In some embodiments, the encapsulation layer 80 comprises an organic dielectric material. For example, the encapsulation layer 80 may comprise a molding compound, such as an epoxy molding compound (EMC), but this disclosure is not limited thereto. Encapsulation layer 80 may be formed, for example, by forming an encapsulation material layer over a carrier substrate 100 to encapsulate the sidewalls of the bridging die BD, the passive device die PD, and the conductive pillar 105, as well as the surface of the conductive pillar 105 away from the carrier substrate 100; then, performing a planarization process (e.g., a grinding process, chemical mechanical polishing) on ​​the encapsulation material layer to remove a portion of the encapsulation material layer and expose the redistribution layer RL4 of the bridging die BD, the conductive terminal CT of the passive device die PD, and the surface of the conductive pillar 105 away from the carrier substrate 100. In some embodiments, after the planarization process, the encapsulation layer 106, the redistribution layer RL4 of the bridging die BD, the conductive terminal CT of the passive device die PD, and the surface of the conductive pillar 105 away from the carrier substrate 100 (e.g., the top surface shown in the figure) are substantially flush with each other in a direction parallel to the main surface of the carrier substrate 100 (e.g., direction D2), that is, at approximately the same horizontal height relative to the main surface of the carrier substrate 100.

[0105] In some embodiments, the encapsulation layer 106 surrounds the encapsulating bridge die BD and contacts the organic dielectric structure OS1 of the redistribution structure RS1 of the bridge die BD. For example, the encapsulation layer 106 covers the sidewalls of the organic dielectric structure OS1, and in some embodiments may also cover the main surface of the organic dielectric structure OS1 away from the substrate 80. In this embodiment, both the encapsulation layer 106 and the organic dielectric structure OS1 comprise organic dielectric materials, and their coefficients of thermal expansion are similar, thus avoiding problems such as package warpage caused by mismatch in coefficients of thermal expansion. In some embodiments, the substrate 90 of the passive device die PD ( Figure 4B The device uses a glass substrate, and the coefficient of thermal expansion of the glass substrate can be adjusted to be similar to that of the encapsulation layer 106. One or more of the dielectric material layers 91 and 92 can be organic material layers. This makes the relevant materials of the passive device die PD have a similar coefficient of thermal expansion to the encapsulation layer 106, thereby avoiding or reducing problems such as packaging structure warping caused by the mismatch of the coefficients of thermal expansion between the corresponding material layers of the passive device die PD and the encapsulation layer.

[0106] Reference Figure 4D An interconnect structure 108 is formed on the side of the encapsulation layer 106 away from the carrier substrate 100. Similar to the interconnect structure 88, the interconnect structure 108 includes an organic dielectric structure OS2 and a redistribution structure RS2 embedded in the organic dielectric structure OS2. In some embodiments, the interconnect structure 108 includes a plurality of organic dielectric layers 111, 112, 113 and a plurality of redistribution layers RL11, RL12, RL13 stacked alternately on top of each other; the redistribution layer RL11 extends through the organic dielectric layer 111 to be electrically connected to the redistribution layer RL4 of the bridging die BD, the conductive terminal CT of the passive device die PD, and the conductive post 105; the redistribution layer RL12 extends through the organic dielectric layer 112 to be electrically connected to the redistribution layer RL11; and the redistribution layer RL13 extends through the organic dielectric layer 113 to be electrically connected to the redistribution layer 112.

[0107] The materials and formation methods of interconnect structure 108 are similar to those of interconnect structure 88. For example, organic dielectric structure 108 includes organic dielectric materials such as polymers (e.g., polyimide), and redistribution structure RS2 includes metallic materials such as titanium, copper, and tungsten. The formation method of interconnect structure 108 includes, for example, forming an organic dielectric layer 111 on the side of encapsulation layer 106 away from the carrier substrate 100, forming openings in the organic dielectric layer 111 using laser drilling, exposure and development, or similar processes to expose a portion of the surface of conductive pillar 105, conductive terminal CT, and conductive pad RL4; and forming an opening in the organic dielectric layer... A seed layer is formed on the side of 111 away from the encapsulation layer 106 and in its opening; a patterned mask layer is formed on the seed layer, the patterned mask layer having mask openings corresponding to the positions where the redistribution layer is to be formed; a conductive layer is formed on the seed layer exposed by the mask openings; the patterned mask layer is removed, and the seed layer is etched using the conductive layer as an etching mask to remove the portion of the seed layer not covered by the conductive layer, the remaining seed layer and the conductive layer together constitute the redistribution layer RL11; then the above-mentioned similar process is repeated to form organic dielectric layer 112, redistribution layer RL12, organic dielectric layer 113 and redistribution layer RL13.

[0108] In some embodiments, redistribution layers RL11 and RL12 have via portions V11 and V12 embedded in organic dielectric layers 111 and 112, respectively, and trace portions T11 and T12 extending on the main surfaces of organic dielectric layers 111 and 112 away from the encapsulation layer. Trace portion T11 is connected to underlying conductive components such as conductive post 105, conductive terminal CT, and conductive pad RL4 via via portion V11; trace portion T12 is connected to trace portion T11 of redistribution layer R11 via via portion V12. In some embodiments, the redistribution layer furthest from the encapsulation layer 106 in the redistribution structure RS2, for example, the topmost redistribution layer RL13 shown in the figure, may also be referred to as a conductive pad for electrical connection with subsequently disposed components. Redistribution layer RL13 may include via portions located in organic dielectric layer 113, and in some embodiments may also include pad portions (not shown) located on the surface of organic dielectric layer 113 away from organic dielectric layer 112.

[0109] In some embodiments, each rewiring layer in rewiring structure RS1 may have approximately the same linewidth / thickness, and each rewiring layer in rewiring structure RS2 may have approximately the same linewidth / thickness; however, multiple rewiring layers in the same rewiring structure may also have different linewidths / thicknesses. Furthermore, the linewidth / thickness of each rewiring layer RL1-RL3 in rewiring structure RS1 of the bridging core BD is different from the linewidth / thickness of each rewiring layer RL11-RL13 in interconnect structure 108. For example, the linewidth / spacing (i.e., the linewidth / spacing of the trace portion) and / or thickness of each rewiring layer RL1-RL3 in rewiring structure RS1 is less than or equal to the linewidth (i.e., the linewidth / spacing of the trace portion) and / or thickness of each rewiring layer RL11-RL13 in rewiring structure RS2. For example, such as... Figure 4D As shown in the enlarged view, the trace width and thickness T1 of the redistribution layer in interconnect structure 88 are smaller than the trace width and thickness T2 of the redistribution layer T11 in interconnect structure 108. In some embodiments, the thickness of the via portion and the thickness of the organic dielectric layer in the redistribution layer of interconnect structure 88 are also smaller than the thickness of the via portion and the thickness of the organic dielectric layer in the redistribution layer of interconnect structure 108.

[0110] In this way, a packaged connection component 110 is formed, which includes a bridge die BD, multiple conductive pillars 105, an encapsulation layer 106 and an interconnection structure 108, and a passive device die PD is embedded in the packaged connection component 110.

[0111] Reference Figure 4E The system provides multiple dies (e.g., dies 120 and 122) and electrically connects the dies to the package connection member 110 via a conductive connector 123. In some embodiments, the conductive connector 123 is disposed between the multiple dies 120 and 122 and the redistribution layer RL13 of the interconnect structure 108 to provide an electrical connection between the multiple dies 120 and 122 and the interconnect structure 108. The conductive connector 123 may include multiple conductive bumps, such as multiple micro-bumps.

[0112] Continue to refer to Figure 4E In some embodiments, an encapsulation layer 126 is formed on the side of the interconnect structure 108 away from the bridge die BD and encapsulation layer 106 to surround and encapsulate the plurality of dies 120 and 122. The method of forming the encapsulation layer 126 may include forming an encapsulation material layer on the interconnect structure 108, the encapsulation material layer encapsulating the sidewalls of the plurality of dies and their surfaces away from the interconnect structure 108. In some embodiments, the encapsulation material layer may optionally be further planarized (e.g., polishing or CMP) to remove a portion of the encapsulation material layer and expose the surfaces of the plurality of dies away from the interconnect structure 108 (not shown).

[0113] In some embodiments, the encapsulation layer 126 is also formed between the plurality of dies 120 and 122 and the interconnect structure 108 to surround and cover the plurality of conductive connectors 123, but this disclosure is not limited thereto. In other embodiments, before forming the encapsulation layer 126, an underfill layer is formed between the plurality of dies 120 and 122 and the interconnect structure 108 to surround and cover the plurality of conductive connectors 123; then, the encapsulation layer 126 is formed to encapsulate the plurality of dies 120 and 122 and the underfill layer.

[0114] Reference Figure 4E and Figure 4F The carrier substrate 100, dielectric layer PI, and seed layer 102 are removed to expose the surface of the conductive pillar 105 away from the interconnect structure 108. For example, the release layer 101 is illuminated (e.g., by UV light or laser), causing it to decompose and lose its adhesiveness under photothermal action, thereby allowing the carrier substrate 100 to detach from its overlying structure. The dielectric layer PI and seed layer 102 can then be removed by a polishing and / or etching process. In this embodiment, because the seed layer 102 is removed, the conductive pillar 105 may substantially not include a seed layer. However, this disclosure is not limited thereto.

[0115] In some embodiments, a plurality of conductive connectors 130 are formed on the side of the encapsulation connection member 110 away from the interconnect structure 108. The conductive connectors 130 are connected to a redistribution structure in the interconnect structure 108 via conductive posts 105, and are further electrically connected to a plurality of dies 120 and 122 via the interconnect structure 108. The conductive connectors 130 may include conductive bumps, such as controlled collapsed chip connection (C4) bumps, but this disclosure is not limited thereto. In some embodiments, prior to forming the conductive connectors 130, an additional interconnect structure, including an organic dielectric structure and an additional redistribution structure, may be formed on the side of the encapsulation layer 106 away from the interconnect structure 108; subsequently, a plurality of conductive connectors 130 are formed on the side of the additional interconnect structure away from the encapsulation layer 106, and the plurality of conductive connectors 130 are connected to the conductive posts 105 via the additional redistribution structure.

[0116] Reference Figure 4F Thus, the encapsulation structure 200 is formed. In some embodiments, the encapsulation structure 200 can be connected to other encapsulation components via conductive connectors 130. For example, refer to... Figures 4F to 4GIn some embodiments, the package structure 200 can be further connected to the package substrate 220 via the conductive connector 130 to form the package structure 500. The package substrate 220 is disposed on the side of the package connection member 110 away from the dies 120 and 122. The plurality of dies 120 and 122 are electrically connected to the package substrate 220 via the conductive connector 123, the interconnection structure 108 and the conductive post 105 in the package connection member 110, and the conductive connector 130.

[0117] In some embodiments, the package structure 500 further includes a conductive connector 230 formed on the side of the package substrate 220 away from the package connection member 110. The conductive connector 230 may be or include a solder ball, such as a ball grid array (BGA), but this disclosure is not limited thereto. In some embodiments, the package structure 500 may be further connected to other external components, such as a printed circuit board, via the conductive connector 230. For example, the package structure 500 may be mounted on a printed circuit board, which may be disposed on the side of the package substrate 220 away from the package connection member 110, and the conductive connector 230 may be disposed between the package substrate 220 and the printed circuit board to provide an electrical connection between the package structure 500 and the printed circuit board.

[0118] Figures 5A to 5B A method for forming a package structure 200' according to other embodiments of the present disclosure is shown. (Refer to...) Figure 4E and Figure 5A In some embodiments, when from Figure 4E After removing the carrier substrate 100, release layer 101, and seed layer 102 to expose the conductive pillars 105, bridging die BD, passive device die PD, and encapsulation layer 106, a planarization process (e.g., including polishing and / or CMP processes) can be performed from the side of the bridging die BD away from the interconnect structure 108 and dies 120 and 122 to remove the substrate 80 of the bridging die BD and expose the interconnect structure 88 of the bridging die BD. In some embodiments, the planarization process also removes portions of the encapsulation layer 106, passive device die PD, and conductive pillars 105 located on the side of the substrate 80 of the bridging die BD in a direction parallel to the main surfaces of dies 120 and 220.

[0119] In some embodiments, such as Figure 5A As shown, after the planarization process, the surfaces of the interconnect structure 88 (e.g., organic dielectric structure OS1) of the bridging die BD, the passive device die PD, the conductive pillar 105, and the encapsulation layer 106 on the side away from the interconnect structure 108 and dies 120 and 122 are substantially flush with each other in a direction parallel to the main surfaces of dies 120 and 122.

[0120] Reference Figure 5A and Figure 5B A conductive connector 130 is formed on the side of the conductive post 105 away from the interconnect structure 108, thereby forming an encapsulation structure 200'. In some embodiments, the encapsulation structure 200' can be further connected to other encapsulation components, such as an encapsulation substrate 220, via the conductive connector 130. A conductive connector 230 may be formed on the side of the encapsulation substrate 220 away from the conductive connector 130, thereby forming an encapsulation structure 500'.

[0121] It should be understood that the above-described process for removing the substrate from the bridging die is merely illustrative and is not intended to limit the scope of this disclosure. For example, in alternative embodiments, it is possible to... Figure 4B Before mounting the bridging core BD onto the carrier substrate 100 in the packaging process, the substrate 80 is removed, so that... Figure 4B In the following steps, a bridge die BD, including the interconnect structure 88 but excluding the substrate 80, is mounted onto the carrier substrate 100, thereby ensuring that the bridge die BD does not include the substrate 80 in the final package structure 200'. For example, in Figures 3A to 3F In the process of forming the bridged-tube die BD, after forming the interconnect structure 88 on the substrate 80 and before the dicing process, the substrate 80 is removed, followed by the dicing process, so that the formed bridged-tube die BD does not include the substrate 80. In this embodiment, removing the substrate 80 may include forming a release layer on the substrate 80 before forming the organic dielectric layer 81, and after forming the interconnect structure 88, irradiating the release layer with light, causing the release layer to decompose under photothermal action and lose its adhesiveness, thereby allowing the substrate 80 to detach from the interconnect structure 88; alternatively, a process such as CMP may be used to remove the substrate 80.

[0122] In these embodiments, since the substrate 80 of the bridging die BD is ultimately removed, the difference in the coefficient of thermal expansion between the bridging die BD and the encapsulation layer 106 can be further reduced, thereby further avoiding problems such as package structure warping caused by the mismatch in the coefficient of thermal expansion between the bridging die BD and the encapsulation layer 106. Moreover, in this embodiment, in Figures 3A to 3P In the manufacturing process of the bridge-pipe BD, the choice of substrate 80 material does not need to consider the impact on subsequent packaging processes, thus allowing for greater freedom in material selection.

[0123] The following points need to be explained:

[0124] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0125] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure can be combined with each other.

[0126] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A packaging structure, comprising: First die and second die; as well as An encapsulation connection component includes a bridging core and an encapsulation layer. The encapsulation connection component is disposed on one side of the first and second cores in a first direction perpendicular to the main surfaces of the first and second cores, and is electrically connected to the first and second cores. The bridge die includes at least a first interconnect structure, the first interconnect structure includes a first organic dielectric structure and a first rewiring structure, the first rewiring structure is embedded in the first organic dielectric structure and is used to electrically connect the first die to the second die; as well as The encapsulation layer is disposed on the side of the bridging tube core in a second direction parallel to the main surfaces of the first and second cores, and at least encapsulates the sidewall of the bridging tube core. The first organic dielectric structure and the first redistribution structure each include at least one organic dielectric layer and at least one redistribution layer stacked on top of each other. The first redistribution layer in the at least one redistribution layer includes a seed layer and a conductive layer. The orthographic projection of the seed layer on the main surface of the first organic dielectric structure in the first direction is located within the orthographic projection range of the conductive layer on the main surface of the first organic dielectric structure in the first direction. The bridging die partially overlaps with the first die and the second die in the first direction, and the first die and the second die extend beyond the edge of the bridging die in the second direction. The first interconnect structure is located within the bridging die, and at least a portion of the edge of the bridging die is defined by the sidewall of the first organic dielectric structure of the first interconnect structure.

2. The packaging structure according to claim 1, wherein the packaging connection member further comprises: A conductive post is located on the side of the bridge die in the first direction and is laterally encapsulated by the encapsulation layer, wherein the conductive post provides an electrical connection between the first die and the second die and an external conductive connector.

3. The packaging structure according to claim 2, wherein the packaging connection member further comprises: The second interconnect structure is disposed in the first direction between the bridge die, the encapsulation layer, the conductive post, and the first die and the second die. The second interconnect structure includes a second organic dielectric structure and a second rewiring structure embedded in the second organic dielectric structure. The first die and the second die are electrically connected to each other through a first part of the second rewiring structure and the bridge die, and are electrically connected to the conductive post through a second part of the second rewiring structure.

4. The packaging structure according to claim 3, wherein the line spacing of the rewiring layer in the first rewiring structure is smaller than the line spacing of the rewiring layer in the second rewiring structure.

5. The packaging structure according to claim 1, wherein in the second direction, the sidewall of the seed layer is laterally recessed relative to the sidewall of the conductive layer.

6. The packaging structure according to claim 1, wherein the conductive layer has a sidewall in contact with the at least one organic dielectric layer.

7. The packaging structure according to claim 1, wherein... The first organic dielectric structure includes a first organic dielectric layer and a second organic dielectric layer; The first rewiring structure includes an initial rewiring layer and a first rewiring layer, wherein the initial rewiring layer is embedded in the first organic dielectric layer, and the first rewiring layer extends through the first organic dielectric layer to connect to the initial rewiring layer. The first redistribution layer includes via portions located in the first organic dielectric layer and trace portions located in the second organic dielectric layer, wherein the main surface of the second organic dielectric layer is closer to the first die and the second die than the main surface of the trace portions of the first redistribution layer.

8. The encapsulation structure according to claim 1, wherein the organic dielectric structure comprises a polymer material.

9. The encapsulation structure according to claim 1, wherein the encapsulation layer comprises an organic dielectric material.

10. The packaging structure of claim 1, wherein the surface of the first interconnect structure of the bridge die away from the first die and the second die is flush with the surface of the encapsulation layer away from the first die and the second die in the second direction.

11. The packaging structure of claim 1, wherein the bridge die further comprises a substrate, the substrate being located on a side of the first interconnect structure away from the first die and the second die, and a portion of the encapsulation layer being located on the side of the substrate in the second direction.

12. The packaging structure according to claim 11, wherein the substrate comprises a semiconductor substrate or an insulating substrate.

13. The packaging structure of claim 1, wherein the bridge die further comprises a substrate, the substrate being located on the side of the first interconnect structure away from the first die and the second die in the first direction, and the orthographic projection of the first organic dielectric structure and the first redistribution structure of the first interconnect structure onto a reference plane perpendicular to the first direction is located within the orthographic projection of the substrate onto the reference plane.

14. The packaging structure according to claim 1, further comprising: A passive device die is embedded in the encapsulation connection member, wherein the passive device die is arranged side by side with the bridge die in the second direction and is laterally encapsulated by the encapsulation layer, and the passive device die is electrically connected to at least one of the first die and the second die.

15. The packaging structure of claim 14, wherein the passive device die comprises a deep trench capacitor.

16. The packaging structure according to any one of claims 1-15, further comprising: A conductive connector is disposed on the side of the encapsulation connection member away from the first die and the second die, and is electrically connected to the first die and the second die through the encapsulation connection member; as well as The packaging substrate is disposed on the side of the conductive connector away from the packaging connection member, and is electrically connected to the first die and the second die through the conductive connector and the packaging connection member.

17. A method for forming an encapsulation structure, comprising: Provide a first die and a second die; as well as An encapsulation connection member is formed to electrically connect to the first die and the second die. The encapsulation connection member is disposed on one side of the first die and the second die in a first direction perpendicular to the main surfaces of the first die and the second die. The formation of the encapsulation connection member includes: A bridging die is formed, the bridging die including at least a first interconnect structure, the first interconnect structure including a first organic dielectric structure and a first rewiring structure, the first rewiring structure being embedded in the first organic dielectric structure and used to electrically connect the first die to the second die; as well as An encapsulation layer is formed on the side of the bridge tube core in a second direction parallel to the main surfaces of the first and second cores, to encapsulate the sidewalls of the bridge tube core. The first organic dielectric structure and the first redistribution structure each include at least one organic dielectric layer and at least one redistribution layer stacked on top of each other. The first redistribution layer in the at least one redistribution layer includes a seed layer and a conductive layer. The orthographic projection of the seed layer on the main surface of the first organic dielectric structure in the first direction is located within the orthographic projection range of the conductive layer on the main surface of the first organic dielectric structure in the first direction. The bridging die partially overlaps with the first die and the second die in the first direction, and the first die and the second die extend beyond the edge of the bridging die in the second direction. The first interconnect structure is located within the bridging die, and at least a portion of the edge of the bridging die is defined by the sidewall of the first organic dielectric structure of the first interconnect structure.

18. The method of forming a packaging structure according to claim 17, wherein forming the bridge tube core comprises: Provide substrate; and forming the first interconnect structure on the substrate, wherein forming the first interconnect structure includes: An initial organic dielectric layer is formed on the substrate, and an initial redistribution layer is formed on the side of the initial organic dielectric layer away from the substrate; A first organic dielectric layer with an opening is formed on the side of the initial organic dielectric layer and the initial redistribution layer away from the substrate, the opening exposing a portion of the surface of the initial redistribution layer away from the substrate; A seed layer is formed on the first organic dielectric layer, and the seed layer fills the opening to contact the initial redistribution layer; The conductive layer is formed on a first portion of the seed layer; and The second portion of the seed layer not covered by the conductive layer is removed, and the remaining first portion of the seed layer and the conductive layer constitute the first redistribution layer, which is electrically connected to the initial redistribution layer.

19. The method of forming a packaging structure according to claim 18, wherein forming the conductive layer on the first portion of the seed layer comprises: A patterned mask layer with mask openings is formed on the seed layer to cover the second portion of the seed layer, and the mask openings expose the first portion of the seed layer; as well as The conductive layer is formed in the mask opening on the first portion of the seed layer.

20. The method of forming a package structure according to claim 19, wherein removing the second portion of the seed layer not covered by the conductive layer comprises: Remove the patterned mask layer; as well as The conductive layer is used as an etching mask to perform an etching process on the seed layer.

21. The method for forming the packaging structure according to claim 18, further comprising: Remove the substrate of the bridging die, such that the first interconnect structure and the encapsulation layer of the bridging die have surfaces flush with each other in the second direction on the side away from the first die and the second die.

22. The method for forming a packaging structure according to claim 17, wherein forming the packaging connection member further comprises: Before forming the encapsulation layer, conductive pillars are formed, wherein the conductive pillars are disposed on the side of the bridge tube core in the second direction, and the encapsulation layer is formed to also encapsulate the sidewalls of the conductive pillars.

23. The method for forming a packaging structure according to claim 22, wherein forming the packaging connection member further comprises: A second interconnect structure is formed on the side of the bridging die, the conductive post, and the encapsulation layer near the first die and the second die. The second interconnect structure includes a second organic dielectric structure and a second rewiring structure embedded in the second organic dielectric structure, wherein the first die and the second die are electrically connected to the bridging die and the conductive post through the second rewiring structure.

24. The method of forming an encapsulation structure according to claim 17, wherein before forming the encapsulation layer, it further comprises: A passive device die is provided, wherein the passive device die and the bridge die are arranged side by side in the second direction, and the encapsulation layer is formed to further encapsulate the sidewall of the passive device die.

25. The method for forming the packaging structure according to claim 17, further comprising: A conductive connector is formed on the side of the encapsulation connection member away from the first die and the second die; as well as The conductive connector is electrically connected to the packaging substrate.

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