IGBT device and method of manufacturing the same

Abstract

This invention provides an IGBT device and its manufacturing method. Multiple parallel second trench gates extending along a second direction are added between two parallel first trench gates. The ends of each second trench gate extend to the sidewalls of the two first trench gates and are integrated with them, forming a surrounding trench gate around each emitter region. This allows for the formation of corresponding emitter regions between adjacent second trench gates through a self-aligning method. Furthermore, the electrical contact between the emitter metal layer formed on the substrate surface and the emitter region does not require contact holes, simplifying the fabrication process and saving the cost of an emitter region photomask, a contact hole photomask, and the corresponding photolithography process. It also avoids the limitations imposed by the photolithography process on the emitter region and contact holes on device size miniaturization, facilitating further reduction in IGBT device size while ensuring device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to an IGBT device and its manufacturing method. Background Technology

[0002] IGBT (Insulated Gate Bipolar Transistor) devices combine the voltage control of MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) with the conductivity modulation current characteristics of BJT (Bipolar Junction Transistor). They feature high input impedance, low switching losses, high speed, and low voltage drive power, and are widely used in many fields such as power transmission and transformation, high-speed train traction, industrial drives, and clean energy.

[0003] However, the existing structural design and manufacturing process of IGBT devices cannot further reduce their size, thus restricting the further development of IGBT devices towards miniaturization. Summary of the Invention

[0004] The purpose of this invention is to provide an IGBT device and its manufacturing method, which can help to further reduce the size of the IGBT device.

[0005] To achieve the above objectives, the present invention provides an IGBT device, characterized in that it comprises:

[0006] Substrate of the first conductivity type;

[0007] Two parallel first trench gates are disposed in the substrate and extend along a first direction;

[0008] Multiple parallel second trench gates are disposed in the substrate between two first trench gates and extend along a second direction, which intersects with the first direction. Both ends of each second trench gate extend to the sidewalls of the two first trench gates and are integrated with the sidewalls of the two first trench gates to form a surrounding trench gate around each emission region.

[0009] Multiple emitter regions of a first conductivity type are disposed in the surface layer of the substrate and are self-aligned with the spacing between corresponding adjacent second trench gates.

[0010] Optionally, the top surfaces of both the first trench gate and the second trench gate are lower than the top surface of the substrate; the IGBT device further includes:

[0011] A gate isolation layer covers the top surfaces of the first trench gate and the second trench gate, and the top surface of the gate isolation layer is not higher than the top surface of the emission region;

[0012] An emitter metal layer covers the top surface of the substrate and the gate isolation layer, and the bottom surface of the emitter metal layer is in electrical contact with the top surface of the emitter region;

[0013] Alternatively, the IGBT device may further include:

[0014] A gate isolation layer covers the top surfaces of the first trench gate and the second trench gate;

[0015] A contact plug penetrates the gate isolation layer and its bottom surface is in electrical contact with the top surface of the transmitting region;

[0016] An emitter metal layer covers the top surface of the gate isolation layer, and the bottom surface of the emitter metal layer is in electrical contact with the top surface of the contact plug.

[0017] Optionally, the IGBT device further includes a gate dielectric layer formed in the substrate, the gate dielectric layer covering the sidewalls and bottom surface of the first trench gate and the sidewalls and bottom surface of the second trench gate, respectively.

[0018] Optionally, the first trench gate and the second trench gate have the same depth in the substrate.

[0019] Optionally, the substrate includes a substrate of a first conductivity type and a drift region of a first conductivity type stacked sequentially, wherein the bottom surfaces of the first trench gate and the second trench gate are higher than the bottom surface of the drift region.

[0020] Optionally, the IGBT device further includes a base region of a second conductivity type, the base region being formed in the drift region, and the emitter region being formed in the surface layer of the base region.

[0021] Optionally, the IGBT device further includes a charge storage layer of a first conductivity type, the charge storage layer being formed in a drift region below the base region, wherein the bottom surfaces of the first trench gate and the second trench gate are both higher than the bottom surface of the charge storage layer.

[0022] Optionally, the IGBT device further includes a collector region of a second conductivity type disposed on the bottom surface of the substrate.

[0023] Based on the same inventive concept, the present invention also provides a method for manufacturing an IGBT device as described herein, which includes the following steps:

[0024] A substrate of a first conductivity type is provided, and two parallel first trench gates and a plurality of parallel second trench gates are formed in the substrate. The first trench gates extend along a first direction, and each second trench gate is disposed in the substrate between the two first trench gates and extends along a second direction, which intersects with the first direction. Both ends of each second trench gate extend to the sidewalls of the two first trench gates and are integrated with the sidewalls of the two first trench gates to form a surrounding trench gate around each of the emission regions.

[0025] Using the first trench gate and the second trench gate as masks, ion implantation of a first conductivity type is performed on the surface layer of the substrate to form a plurality of emission regions that are self-aligned with the spacing between the corresponding adjacent second trench gates.

[0026] Optionally, the manufacturing method further includes:

[0027] Before or after forming the self-aligned emitter region, the first trench gate and the second trench gate are etched back such that the top surfaces of both the first trench gate and the second trench gate are lower than the top surface of the substrate.

[0028] After the first trench gate and the second trench gate are etched back and before or after the formation of the self-aligned emitter region, a gate isolation layer is formed covering the top surface of the first trench gate and the second trench gate, the top surface of the gate isolation layer not higher than the top surface of the substrate and exposing the top surface of the substrate in the gap between adjacent second trench gates.

[0029] After forming the emitter region and the gate isolation layer, an emitter metal layer is deposited on the top surface of the substrate, the bottom surface of the emitter metal layer being in contact with the top surface of the emitter region.

[0030] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0031] 1. Multiple parallel second trench gates extending along a second direction are added between two parallel first trench gates extending in a first direction. The two ends of each second trench gate extend to the sidewalls of the two first trench gates and are integrated with the sidewalls of the two first trench gates to form a surrounding trench gate around each emitter region. This allows for the formation of corresponding emitter regions between adjacent second trench gates through self-alignment. On the one hand, this eliminates the need for photolithography to define the emitter region in the prior art, simplifying the fabrication process and saving the cost of an emitter region photomask and the corresponding photolithography process. It also avoids the limitation of emitter region photolithography on device size miniaturization. On the other hand, each emitter region and its surrounding surrounding trench gate can be used to form a surrounding channel, which helps to increase the current density of the device. This facilitates further reduction in the size of the IGBT device while ensuring device performance, thus enabling the miniaturization of IGBT devices.

[0032] 2. A gate isolation layer with a top surface no higher than the top surface of the emitter region is formed on the top surface of the first trench gate and the second trench gate. This allows the emitter metal layer to be electrically isolated from the first trench gate and the second trench gate, while simultaneously achieving electrical contact between the emitter metal layer and the emitter region. This eliminates the need for photolithography and etching processes to form contact holes on the emitter region, simplifying the fabrication process and saving the cost of a contact hole photomask and the corresponding process. It also avoids the limitations imposed by the contact hole process on device size miniaturization, thus facilitating further reduction in the size of IGBT devices.

[0033] 3. The manufacturing process of the IGBT device of the present invention is fully compatible with existing processes and will not bring about equipment costs due to process upgrades. Attached Figure Description

[0034] Figure 1 This is a three-dimensional structural diagram of an existing IGBT device (the emitter metal layer is omitted).

[0035] Figure 2 yes Figure 1 The diagram shows a cross-sectional structure of the IGBT device (showing the emitter metal layer).

[0036] Figure 3 This is a three-dimensional structural diagram of an IGBT device according to an embodiment of the present invention (the emitter metal layer is omitted).

[0037] Figure 4 yes Figure 3 The diagram shows a three-dimensional structure of the IGBT device after being cut across the bottom surface of the gate isolation layer.

[0038] Figure 5 yes Figure 3 The diagram shows a cross-sectional view of the IGBT device along line AA (showing the emitter metal layer).

[0039] Figure 6 yes Figure 3 The diagram shows a cross-sectional view of the IGBT device along the BB line (showing the emitter metal layer).

[0040] Figure 7 This is a flowchart of a manufacturing method for an IGBT device according to an embodiment of the present invention.

[0041] The specific reference numerals in the attached figures are as follows:

[0042] 100, 200 - Substrate; 101, 201 - Epitaxial layer (i.e., drift region); 102, 202 - Base region; 103, 203 - Charge storage layer; 104 - Gate trench; 105, 205 - Gate dielectric layer; 106 - Gate; 107, 207 - Emitter region; 108 - Body contact region; 109 - Emitter contact plug; 110, 210 - Collector region; 111, 209 - Emitter metal layer; 204a - First gate trench; 204b - Second gate trench; 206a - First trench gate; 206b - Second trench gate; 208 - Gate isolation layer. Detailed Implementation

[0043] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout. It should be understood that when an element or layer is referred to as "on" or "connected to" other elements or layers, it may be directly on or connected to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on" or "directly connected to" other elements or layers, there are no intervening elements or layers. Although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion. Spatial relation terms such as “below,” “under,” “below,” “above,” “on top,” “above,” etc., may be used herein for convenience of description to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then the element or feature described as “below,” “under,” or “below” will be oriented “on top” of other elements or features. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptions used herein will be interpreted accordingly. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of possible features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0044] like Figure 1 and Figure 2As shown, an existing N-type IGBT device includes a substrate (N+ type) 100, an epitaxial layer (N-type epitaxial layer, also known as an N-drift region) 101 on the substrate 100, a base region (P type, also known as a body region) 102 in the upper part of the epitaxial layer 101, a charge storage layer (N+ type) 103 at the bottom of the base region 102, a body contact region (P+ type) 108 aligned with the emitter contact plug 109 at the top of the base region 102, an emitter region (N+ type, also known as a source region) 107 in the base region 102 on both sides of the body contact region 108, and gate trenches on both sides of the base region 102. A gate dielectric layer 105 is formed on the inner surface of the gate trench 104 and a gate 106 is filled therein. An N+ emitter region 107 extends along the length of the gate trench 104. An oxide layer 112 and a top metal layer 111 are stacked sequentially on the front side of the substrate 100. The top metal layer 111 is electrically connected to the emitter region 107 and the body contact region 108 through an emitter contact plug 109 (i.e., a conductive contact hole) that penetrates the oxide layer 112. A collector region (P+ type) 110 is provided on the back side of the substrate 100. A metal collector electrode (not shown) that is in ohmic contact with the collector region 110 can be formed on the bottom surface of the collector region 110.

[0045] In the aforementioned IGBT devices, on the one hand, not only is it necessary to define the N+ emitter region 107 outside the sidewall of the gate trench 104 through a photolithography process, but also another photolithography process is needed to define the contact hole required for the emitter contact plug 109. The process is complex and costly, and the photolithography accuracy is limited by the process conditions, which restricts the further reduction of the IGBT device size. On the other hand, since the N+ emitter region 107 extends along the length direction of the gate trench 104, it is difficult to further increase the current density of the IGBT device, which further restricts the miniaturization of the IGBT device.

[0046] Based on this, the present invention mainly provides an IGBT device and its manufacturing method, which can form the emitter region through a self-aligned injection process, thereby eliminating the use of the emitter region photomask. It can also avoid photolithography and etching of the contact holes on the emitter region, thereby simplifying the process, saving photomasks, and enabling the cell spacing to be made very small as needed, so as to maximize the current density of the cells, which is conducive to the further miniaturization of IGBT devices.

[0047] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0048] Figures 3 to 6This actually shows a schematic diagram of the device structure of one cell region of the IGBT device in this embodiment.

[0049] Please refer to Figures 3 to 6 This embodiment provides an IGBT device, which includes a substrate of a first conductivity type, a first trench gate 206a, a second trench gate 206b, a gate dielectric layer 205, an emitter region of the first conductivity type (i.e., the N+ emitter region in the figure) 207, a gate isolation layer 208, an emitter metal layer 209, and a collector region of the second conductivity type (i.e., the P+ collector region in the figure) 210.

[0050] Taking N-type as the first conductivity type and P-type as the second conductivity type as an example, in this embodiment, the substrate includes an N+ substrate 200 and an N-drift region 201 formed on the N+ substrate 200. The N-drift region 201 can be an N-epitaxial layer formed on the N+ substrate 200 by an epitaxial growth process, or an ion-implanted layer formed by an ion implantation process, etc. The material of the N+ substrate 200 can be any suitable substrate material, such as silicon, germanium, silicon-on-insulator, silicon-germanium, or gallium arsenide, etc.

[0051] The substrate also contains two parallel first gate trenches 204a extending along a first direction and multiple parallel second gate trenches 204b extending along a second direction. The first and second directions may intersect perpendicularly or not perpendicularly. The two ends of each second gate trench 204b extend to the corresponding first gate trenches 204a on both sides to connect the two first gate trenches 204a. Each first trench gate 206a is filled in a corresponding first gate trench 204a, and each second trench gate 206b is filled in a corresponding second gate trench 204b. Thus, the two ends of each second trench gate 206b extend to the sidewalls of the two first trench gates 206a on both sides and are integrated with the sidewalls of the two first trench gates 206a, defining a plurality of N+ emitter regions 207. Each N+ emitter region 207 extends along the second direction and is parallel to each other. The second trench gates 206b and the first trench gates 206a around the N+ emitter region 207 defined by the two adjacent second trench gates 206b and the two first trench gates 206a form a surrounding trench gate around the N+ emitter region 207. Each N+ emitter region 207 and the surrounding trench gate can form a surrounding channel, thereby increasing the effective length of the channel and improving the current density and performance of the device.

[0052] A gate dielectric layer 205 is formed on the sidewalls and bottom surface of the first gate trench 204a and the second gate trench 204b, respectively, to surround the sidewalls and bottom surface of the first trench gate 206a and the sidewalls and bottom surface of the second trench gate 206b, so that the first trench gate 206a and the second trench gate 206b are electrically isolated from the substrate.

[0053] Furthermore, the top surfaces of the first trench gate 206a and the second trench gate 206b are lower than the top surface of the N+ emitter region 207. The gate isolation layer 208 fills the first gate trench 204a above the first trench gate 206a and the second gate trench 204b above the second trench gate 206b, respectively. The top surface of the gate isolation layer 208 is not higher than the top surface of the N+ emitter region 207, so that the top surface of the N+ emitter region 207 can be exposed after the gate isolation layer 208 is formed. The gate isolation layer 208 is used to achieve electrical isolation between the emitter metal layer 209 and the first trench gate 206a and the second trench gate 206b, respectively. The bottom surface of the emitter metal layer 209 is in electrical contact with the top surface of the exposed N+ emitter region 207.

[0054] The depths of the first gate trench 204a and the second gate trench 204b can be the same or different. Preferably, the depths of the first gate trench 204a and the second gate trench 204b are the same, so that the first gate trench 204a and the second gate trench 204b can be formed simultaneously through the same photolithography and etching process.

[0055] In addition, the depths of the first gate trench 204a and the second gate trench 204b are insufficient to penetrate the N-drift region 201, that is, the bottom surfaces of the first gate trench 204a and the second gate trench 204b are both higher than the bottom surface of the N-drift region 201.

[0056] Furthermore, it should be understood that the widths of the first gate trench 204a and the second gate trench 204b can be the same or different, and the second gate trench 204b can be distributed at equal intervals or at unequal intervals, all depending on the design requirements of the device.

[0057] A P-type base region 202 is formed in the N-drift region 201 enclosed between each two adjacent second gate trenches 204b and two first gate trenches 204a. An N+ charge storage layer 203 connected to the P-type base region 202 is also formed in the N-drift region 201 below the P-type base region 202. An N+ emitter region 207 is formed in the surface layer of the P-type base region 202 between each two adjacent second gate trenches 204b and two first gate trenches 204a. The bottom surfaces of the first trench gate 206a and the second trench gate 206b are both higher than the bottom surface of the charge storage layer 203.

[0058] The P+ collector region 210 is formed on the back side of the N+ substrate 200 and can be formed by ion implantation or epitaxial growth processes.

[0059] It should be understood that when the IGBT device of this embodiment has multiple cell regions, these cell regions can be arranged in parallel and formed on the same N-drift region 201. That is, at this time, a number of pairs of first gate trenches 204a are formed in the N-drift region 201, and a corresponding P-type base region 202 and a number of parallel second gate trenches 204b are formed between each pair of adjacent first gate trenches 204a.

[0060] As an example, the material of the gate dielectric layer 205 can be silicon dioxide or a high-k dielectric, and the first trench gate 206a and the second trench gate 206b are made of the same material, such as doped polysilicon. The material of the gate isolation layer 208 includes at least one of silicon dioxide, silicon nitride, silicon oxynitride, and low-k dielectric (dielectric constant k is less than 2.5).

[0061] The manufacturing process of the IGBT device in this embodiment is fully compatible with the existing manufacturing process of IGBT devices. The corresponding steps and procedures can be exactly the same. The main difference is that the original gate layout is modified to add multiple second trench gates between the two first trench gates on the basis of the conventional first trench gate, and the emitter region is formed by self-alignment process, and the process of making contact holes on the emitter region is eliminated.

[0062] For details, please refer to Figure 7 An embodiment of the present invention provides a method for manufacturing an IGBT device, which includes the following steps:

[0063] S1, a substrate of a first conductivity type is provided, and two parallel first trench gates and multiple parallel second trench gates are formed in the substrate. The first trench gates extend along a first direction, and each second trench gate is disposed in the substrate between the two first trench gates and extends along a second direction, which intersects with the first direction. Both ends of each second trench gate extend to the sidewalls of the two first trench gates and are integrated with the sidewalls of the two first trench gates to form a surrounding trench gate around each emission region.

[0064] S2, etch back the first trench gate and the second trench gate so that the top surfaces of both the first trench gate and the second trench gate are lower than the top surface of the substrate;

[0065] S3, using the first trench gate and the second trench gate as masks, perform ion implantation of the first conductivity type on the surface layer of the substrate to form a plurality of emission regions that are self-aligned with the spacing between the corresponding adjacent second trench gates;

[0066] S4, forming a gate isolation layer covering the top surface of the first trench gate and the second trench gate, wherein the top surface of the gate isolation layer is not higher than the top surface of the substrate and exposes the top surface of the substrate in the gap between adjacent second trench gates;

[0067] S5, deposit an emitter metal layer on the top surface of the substrate, wherein the bottom surface of the emitter metal layer is in contact with the top surface of the emitter region.

[0068] Please combine Figures 3 to 6 As shown, in step S1, firstly, a substrate is provided, which is a substrate material after at least one process such as epitaxial growth, ion implantation or device isolation structure fabrication, and may include an N+ substrate 200 and an N- drift region 201 formed on the N+ substrate 200.

[0069] As an example, in step S1, the step of providing a substrate includes: first, providing an N+ substrate 200, which can be any suitable semiconductor material, such as silicon, germanium, silicon-on-insulator, gallium arsenide, etc.; then, forming an N- drift region 201 on the surface of the substrate 200 by an ion implantation process or an epitaxial growth process; next, first performing N-type ion implantation into the N- drift region 201 to form an N+ charge storage layer 205, and then performing P-type ion implantation into the N+ charge storage layer 205 to form a P-type base region 202; then, fabricating a shallow trench isolation structure in the N- drift region 201 containing the P-type base region 202 and the N+ charge storage layer 205 by a shallow trench isolation process to define the individual cell regions (i.e., the active regions) of the IGBT device.

[0070] Please continue to combine Figures 3 to 6 As shown, in step S1, a protective dielectric layer (such as silicon nitride or silicon oxide) is deposited on the substrate, and the active region of the substrate is photolithographically etched and etched using a gate photomask to form two parallel first gate trenches 204a extending in a first direction in the N- drift region 201 containing the P-type base region 202 and the N+ charge storage layer 205. Additionally, multiple parallel second gate trenches 204b extending in a second direction are located between the two first gate trenches 204a. The second gate trenches 204b and the first gate trenches 204a are interconnected. From a top view of the substrate, they form a flat, ladder-shaped trench, and the second gate trenches 204b and the first gate trenches 204a have the same depth.

[0071] It should be understood that in other embodiments of the present invention, the depths of the second gate trench 204b and the first gate trench 204a may also be different. In this case, in step S1, the active region of the substrate needs to be photolithographically etched and etched with a gate photomask to form one of the first gate trench 204a and the second gate trench 204b in the N- drift region 201 containing the P-type base region 202 and the N+ charge storage layer 205. Then, a sacrificial material layer is filled to protect the formed gate trench. Next, the active region of the substrate is photolithographically etched and etched again with another gate photomask to form another of the first gate trench 204a and the second gate trench 204b in the N- drift region 201 containing the P-type base region 202 and the N+ charge storage layer 205. The sacrificial material layer filled in the former gate trench is removed, thereby obtaining the connected first gate trench 204a and the second gate trench 204b.

[0072] Please continue to combine Figures 3 to 6 As shown, in step S1, a gate dielectric layer 205 is then formed on the inner surfaces of the first gate trench 204a and the second gate trench 204b using a suitable process such as thermal oxidation or deposition. Then, polysilicon is deposited into the first gate trench 204a and the second gate trench 204b to form a first trench gate 206a filled in the first gate trench 204a and a second trench gate 206b filled in the second gate trench 204b. Optionally, after depositing the polysilicon, a chemical mechanical polishing process can be used to planarize the top of the polysilicon to remove excess polysilicon around the first gate trench 204a and the second gate trench 204b.

[0073] Please continue to combine Figures 3 to 6 As shown, in step S2, a suitable polysilicon etching process is used to perform back etching on the first trench gate 206a and the second trench gate 206b, so that the top surfaces of the first trench gate 206a and the second trench gate 206b are lower than the top surface of the P-type base region 202.

[0074] Please continue to combine Figures 3 to 6 As shown, in step S3, using the first trench gate 206a and the second trench gate 206b as masks, the P-type base region 202 is subjected to self-aligned N-type ion implantation and annealing to form an N+ emission region 207. Thus, the N+ emission region 207 is so-called region self-aligned with the two first trench gates 206a and the two adjacent second trench gates 206b. In other words, each N+ emission region 207 is one-to-one corresponding to and self-aligned with the corresponding two adjacent second trench gates 206b.

[0075] Please continue to combine Figures 3 to 6As shown, in step S4, firstly, a gate isolation layer 208 is deposited on the substrate using a suitable process such as chemical vapor deposition. The material of the gate isolation layer 208 may include one or a combination of silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate, and low-k dielectric. The deposition thickness of the gate isolation layer 208 is sufficient to bury the top surfaces of both the first trench gate 206a and the second trench gate 206b. The deposition thickness may or may not completely fill the first gate trench 204a and the second gate trench 204. Then, a chemical mechanical polishing process can be used to planarize the top of the gate isolation layer 208 until the top surface of the N+ emitter region 207 is exposed.

[0076] Please continue to combine Figures 3 to 6 As shown, in step S5, an emitter metal layer 209 can be deposited on the device surface by a suitable process such as electroplating, chemical plating, sputtering, etc., thereby making electrical contact between the emitter metal layer 209 and the top surface of the N+ emitter region 207. This electrical contact can be an ohmic contact.

[0077] Optionally, photolithography and etching processes can be used to etch the emitter metal layer 209 to pattern the emitter metal layer 209.

[0078] Furthermore, in the manufacturing method of the IGBT device of this embodiment, after completing the process on the front side of the substrate, the substrate can be flipped to thin the back side of the N+ substrate 200. Then, N-type ions are implanted on the back side of the N+ substrate 200 to form an N-type field-blocking layer (not shown). Next, P-type ions are implanted on the back side of the N-type field-blocking layer to form a P+ collector region 210. Then, a collector metal layer (not shown) is deposited on the back side of the P+ collector region 210 using suitable processes such as electroplating, electroless plating, or sputtering. The collector metal layer is further photolithographically and etched to form the final collector terminal, thereby making electrical contact between the collector terminal and the collector region 210. The materials of the collector metal layer and the emitter metal layer 209 can be the same or different. The materials of the collector metal layer and the emitter metal layer 209 can be any common and suitable single metal or alloy used for fabricating metal electrodes, such as tungsten, aluminum, titanium, copper, or copper-aluminum alloys.

[0079] It should be noted that in the above embodiments, the IGBT device and its manufacturing method of the present invention are introduced using N-type as the first conductivity type and P-type as the second conductivity type. In other embodiments of the present invention, the first conductivity type can be replaced with P-type and the second conductivity type can be replaced with N-type according to the device design requirements.

[0080] It should also be noted that, in the above embodiments, the back etching of the first trench gate 206a and the second trench gate 206b is performed before the formation of the N+ emitter region 207, and the formation of the gate isolation layer 208 is performed after the formation of the N+ emitter region 207, as an example. However, the technical solution of the present invention is not limited to this. In another embodiment of the present invention, steps S2 and S3 can be interchanged as needed. That is, after the formation of the self-aligned N+ emitter region 207, the first trench gate 206a and the second trench gate 206b are etched back so that the top surfaces of the first trench gate 206a and the second trench gate 206b are both lower than the top surface of the N+ emitter region 207. The order of each step in the manufacturing method of the IGBT device in this embodiment is S1, S3, S2, S4, S5. In another embodiment of the present invention, step S4 can be swapped and placed between steps S2 and S3 as needed. That is, after etching back the first trench gate 206a and the second trench gate 206b so that the top surfaces of the first trench gate 206a and the second trench gate 206b are both lower than the top surface of the N+ emitter region 207, and before forming the self-aligned N+ emitter region 207, a gate isolation layer 208 is deposited first, and the top of the gate isolation layer 208 is planarized to expose the top surface of the N+ emitter region 207. The order of steps in the manufacturing method of the IGBT device in this embodiment is S1, S2, S4, S3, S5.

[0081] Furthermore, it should be understood that the above embodiments have eliminated the fabrication of contact holes above the emitter region. However, the technical solution of the present invention is not limited to this. It can also be like the prior art, fabricating contact holes above the emitter region so that the emitter metal layer is electrically connected to the emitter region through contact plugs in the contact holes. In this case, in the IGBT device and manufacturing method of the present invention, the top surfaces of the first trench gate and the second trench gate are allowed to be lower than, flush with, or higher than the top surface of the emitter region. The gate isolation layer can only cover the top surfaces of the first trench gate and the second trench gate, or it can cover the substrate surface including the first trench gate, the second trench gate, and the emitter region. In the IGBT device and manufacturing method of the present invention, it is necessary to form contact holes that penetrate the gate isolation layer and expose the top surface of the emitter region, and fill the contact holes with conductive contact plugs. The bottom surface of the contact plugs is electrically in contact with the top surface of the emitter region, and the bottom surface of the emitter metal layer covering the top surface of the gate isolation layer is electrically in contact with the top surface of the contact plugs. Thus, the emitter metal layer is electrically connected to the emitter region through the contact plugs.

[0082] In summary, the IGBT device and its manufacturing method of the present invention add multiple parallel second trench gates extending along a second direction between two parallel first trench gates extending in a first direction. The two ends of each second trench gate extend to the sidewalls of the two first trench gates and are integrated with the sidewalls of the two first trench gates to form a surrounding trench gate around each emitter region. This allows for the formation of corresponding emitter regions between adjacent second trench gates through a self-aligning method. On one hand, this eliminates the need for photolithography to define the emitter region in the prior art, simplifying the fabrication process and saving the cost of an emitter region photomask and the corresponding photolithography process. It also avoids the limitation of emitter region photolithography on device size miniaturization. On the other hand, each emitter region and its surrounding surrounding trench gate can be used to form a surrounding channel, thereby increasing the current density of the device. This facilitates further reduction in the size of the IGBT device while maintaining its performance, thus enabling the miniaturization of IGBT devices. Furthermore, a gate isolation layer with a top surface no higher than the top surface of the emitter region is formed on the top surface of the first trench gate and the second trench gate. This allows the emitter metal layer to be electrically isolated from the first trench gate and the second trench gate, while simultaneously achieving electrical contact between the emitter metal layer and the emitter region. As a result, the process of forming contact holes on the emitter region using photolithography and etching, which is required in the prior art, is eliminated, simplifying the fabrication process and saving the cost of a contact hole photomask and the corresponding process. At the same time, it avoids the limitation of contact hole process on device size miniaturization, thus facilitating further reduction in the size of IGBT devices.

[0083] Moreover, the manufacturing process of the IGBT device of the present invention is fully compatible with existing processes, and will not bring about equipment costs due to process upgrades.

[0084] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the present invention.

Claims

1. An IGBT device, characterized in that, include: A substrate of a first conductivity type, the substrate comprising a base of the first conductivity type and a drift region of the first conductivity type stacked sequentially; Two parallel first trench gates are disposed in the substrate and extend along a first direction; Multiple parallel second trench gates are disposed in the substrate between two first trench gates and extend along a second direction, which intersects with the first direction. Both ends of each second trench gate extend to the sidewalls of the two first trench gates and are integrated with the sidewalls of the two first trench gates to form a surrounding trench gate around each emission region. The bottom surfaces of the first trench gates and the second trench gates are both higher than the bottom surface of the drift region. Multiple emitter regions of the first conductivity type are disposed in the surface layer of the substrate and are respectively aligned with the spacing between adjacent second trench gates.

2. The IGBT device as described in claim 1, characterized in that, The top surfaces of both the first trench gate and the second trench gate are lower than the top surface of the substrate; the IGBT device further includes: A gate isolation layer covers the top surfaces of the first trench gate and the second trench gate, and the top surface of the gate isolation layer is not higher than the top surface of the emitter region of the first conductivity type; An emitter metal layer covers the top surface of the substrate and the gate isolation layer, and the bottom surface of the emitter metal layer is in electrical contact with the top surface of the emitter region of the first conductivity type; Alternatively, the IGBT device may further include: A gate isolation layer covers the top surfaces of the first trench gate and the second trench gate; A contact plug penetrates the gate isolation layer and its bottom surface is in electrical contact with the top surface of the emitter region of the first conductivity type; An emitter metal layer covers the top surface of the gate isolation layer, and the bottom surface of the emitter metal layer is in electrical contact with the top surface of the contact plug.

3. The IGBT device as described in claim 1, characterized in that, It also includes a gate dielectric layer formed in the substrate, the gate dielectric layer covering the sidewalls and bottom surface of the first trench gate and the sidewalls and bottom surface of the second trench gate, respectively.

4. The IGBT device as described in claim 1, characterized in that, The first trench gate and the second trench gate have the same depth in the substrate.

5. The IGBT device as described in claim 1, characterized in that, It also includes a base region of a second conductivity type, the base region being formed in the drift region, and an emitter region of the first conductivity type being formed in the surface layer of the base region.

6. The IGBT device as described in claim 5, characterized in that, It also includes a charge storage layer of a first conductivity type, the charge storage layer being formed in a drift region below the base region, wherein the bottom surfaces of the first trench gate and the second trench gate are both higher than the bottom surface of the charge storage layer.

7. The IGBT device as described in claim 1, characterized in that, It also includes a current collector region of a second conductivity type, disposed on the bottom surface of the substrate.

8. A method for manufacturing an IGBT device as described in any one of claims 1-7, characterized in that, Includes the following steps: A substrate of a first conductivity type is provided, and two parallel first trench gates and multiple parallel second trench gates are formed in the substrate. The first trench gates extend along a first direction, and each second trench gate is disposed in the substrate between the two first trench gates and extends along a second direction, which intersects with the first direction. Both ends of each second trench gate extend to the sidewalls of the two first trench gates and are integrated with the sidewalls of the two first trench gates to form a surrounding trench gate around each emission region. Using the first trench gate and the second trench gate as masks, ion implantation of a first conductivity type is performed on the surface layer of the substrate to form a plurality of emission regions that are self-aligned with the spacing between the corresponding adjacent second trench gates.

9. The manufacturing method as described in claim 8, characterized in that, Also includes: Before or after forming the self-aligned emitter region, the first trench gate and the second trench gate are etched back such that the top surfaces of both the first trench gate and the second trench gate are lower than the top surface of the substrate. After the first trench gate and the second trench gate are etched back and before or after the formation of the self-aligned emitter region, a gate isolation layer is formed covering the top surface of the first trench gate and the second trench gate, the top surface of the gate isolation layer not higher than the top surface of the substrate and exposing the top surface of the substrate in the gap between adjacent second trench gates. After forming the emitter region and the gate isolation layer, an emitter metal layer is deposited on the top surface of the substrate, with the bottom surface of the emitter metal layer in contact with the top surface of the emitter region.

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