Thin film transistor and display device including the same

Abstract

A thin-film transistor (TFT) and a display device including the TFT are provided. The TFT includes: an active layer; and a gate that at least partially overlaps with a portion of the active layer, wherein the active layer includes: a channel portion; a first connection portion contacting one side of the channel portion; and a second connection portion contacting the other side of the channel portion, wherein the channel portion includes a first region and a second region, each of the first region and the second region extending from the first connection portion to the second connection portion, wherein the TFT further includes: a first conductive material layer overlapping the channel portion; and a first spacer overlapping the channel portion, wherein the channel portion is disposed between the first conductive material layer and the gate, and the first conductive material layer is connected to the first connection portion.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0148501, filed on November 2, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This invention relates to a thin-film transistor and a display device including a thin-film transistor. Background Technology

[0004] In the field of electronic devices, transistors are widely used as switching or driving devices. In particular, because thin-film transistors can be fabricated on glass or plastic substrates, they are widely used as switching devices in display devices such as liquid crystal displays or organic light-emitting diodes.

[0005] Display devices may include, for example, switching thin-film transistors (TFTs) and driving thin-film transistors (TFTs). Generally, it is advantageous for switching TFTs to have a smaller S-factor to improve on-off characteristics and for driving TFTs to have a larger S-factor to represent grayscale levels.

[0006] Thin-film transistors (TFTs) typically have a small S-factor to ensure on-off characteristics. When these TFTs are used as driver TFTs in display devices, it is difficult to reproduce the grayscale levels of the display.

[0007] Therefore, thin-film transistors (TFTs) with large S-factors are needed for driving TFTs in display devices to easily represent grayscale levels. Furthermore, even if a TFT has a large S-factor, it must also possess excellent current characteristics in the on-state. Summary of the Invention

[0008] The present invention was made in view of the above problems. One object of the present invention is to provide a thin-film transistor having a large S-factor and excellent current characteristics in the on state.

[0009] Another object of the present invention is to provide a thin-film transistor that has a large S-factor during the period when the threshold voltage occurs and a large current value in the on state.

[0010] Another object of the present invention is to provide a thin-film transistor designed to have a large S-factor during the threshold voltage period, such that the effective gate voltage of the first region of the channel is lower than the effective gate voltage of the second region of the channel. The effective gate voltage is a portion of the voltage applied to the gate that actually enables current flow, compared to the voltage applied from an external power source.

[0011] Another object of the present invention is to provide a thin-film transistor designed such that, since it is not necessary to increase the S-factor of the thin-film transistor by increasing the spacing between the gate and the active layer, the spacing between the gate and the active layer is not greater than a necessary value, so as to have excellent / improved on-current characteristics.

[0012] Another object of the present invention is to provide a thin-film transistor in which spacers are disposed along one direction of the channel portion in order to have a large S-factor and a large on-current characteristic.

[0013] Another object of the present invention is to provide a thin-film transistor in which a conductive material layer is disposed along one direction of the channel portion in order to have a large S-factor and a large conduction current.

[0014] Another object of the present invention is to provide a display device that has excellent grayscale rendering capability and excellent current characteristics by including a driving thin-film transistor having a large S-factor and a large on-current characteristic.

[0015] In addition to the objectives of the invention as described above, those skilled in the art will clearly understand additional objectives and features of the invention from the following description.

[0016] According to one aspect of the invention, the above and other objects can be achieved by providing a thin-film transistor comprising: an active layer; and a gate at least partially overlapping a portion of the active layer, wherein the active layer comprises: a channel portion; a first connection portion contacting one side of the channel portion; and a second connection portion contacting the other side of the channel portion, wherein the channel portion comprises a first region and a second region, each of the first region and the second region extending from the first connection portion to the second connection portion, wherein the thin-film transistor further comprises: a first conductive material layer overlapping the channel portion; and a first spacer overlapping the channel portion, wherein the channel portion is disposed between the first conductive material layer and the gate, the first conductive material layer being connected to the first connection portion.

[0017] According to another aspect of the present invention, a thin-film transistor includes: an active layer; and a gate that at least partially overlaps with a portion of the active layer, wherein the active layer includes: a channel portion; a first connection portion contacting one side of the channel portion; and a second connection portion contacting the other side of the channel portion, wherein the channel portion includes a first region and a second region, each of the first region and the second region extending from the first connection portion to the second connection portion, wherein the thin-film transistor further includes: a first conductive material layer overlapping the channel portion, wherein the channel portion is disposed between the first conductive material layer and the gate, the first conductive material layer being connected to the first connection portion; and a second conductive material layer, the second conductive material layer being separated from the first conductive material layer and overlapping the channel portion, wherein the channel portion is disposed between the second conductive material layer and the gate, the second conductive layer being connected to the first connection portion.

[0018] According to another aspect of the present invention, a thin-film transistor includes: an active layer; and a gate that at least partially overlaps with the active layer, wherein the active layer includes: a channel portion; a first connection portion contacting one side of the channel portion; and a second connection portion contacting the other side (opposite side) of the channel portion, wherein the channel portion includes a first region and a second region disposed parallel to the first region, each of the first region and the second region extending from the first connection portion to the second connection portion, and an effective gate voltage applied to the first region is less than an effective gate voltage applied to the second region.

[0019] The channel portion may further include a third region separated from the first region, wherein the second region is inserted between the first region and the third region, the third region may extend from at least the first connection portion to the second connection portion, and the effective gate voltage applied to the third region may be less than the effective gate voltage applied to the second region.

[0020] The channel portion may further include a fourth region separated from the second region, wherein the first region is inserted between the second region and the fourth region, the fourth region may extend from at least the first connection portion to the second connection portion, and the effective gate voltage applied to the fourth region may be greater than the effective gate voltage applied to the first region.

[0021] The thin-film transistor may further include a first conductive material layer overlapping the channel portion, wherein the channel portion may be disposed between the first conductive material layer and the gate, and the first conductive material layer may be connected to the first connection portion.

[0022] The first conductive material layer may overlap with the first region.

[0023] The thin-film transistor may further include a first spacer that overlaps with the channel portion.

[0024] The first spacer may not overlap with the first area, and the first spacer may overlap with the second area.

[0025] The channel portion may further include a third region, which is separated from the first region and does not overlap with the first spacer.

[0026] The first spacer may be disposed between the channel portion and the first conductive material layer.

[0027] The first spacer and the first conductive material layer may be disposed on the same layer.

[0028] The thin-film transistor may further include a second spacer, which is separated from the first spacer and overlaps with the channel portion.

[0029] The channel portion may further include a fourth region that overlaps with the second spacer.

[0030] The first region may overlap with the gap space (referring to the gap or space) between the first spacer and the second spacer.

[0031] The first spacer and the second spacer may be disposed between the channel portion and the first conductive material layer.

[0032] The first conductive material layer, the first spacer, and the second spacer may be disposed on the same layer, and the first conductive material layer may be disposed between the first spacer and the second spacer.

[0033] The thin-film transistor may further include a second conductive material layer, which is separated from the first conductive material layer and overlaps with the channel portion, wherein the channel portion may be disposed between the second conductive material layer and the gate, and the second conductive material layer may be connected to the first connection portion.

[0034] The channel portion may further include a third region overlapping with the second conductive material layer.

[0035] The thin-film transistor may further include a first spacer located between the first conductive material layer and the second conductive material layer.

[0036] The first conductive material layer, the second conductive material layer, and the first spacer can be disposed on the same layer.

[0037] The second region may overlap with the gap space between the first conductive material layer and the second conductive material layer.

[0038] The thin-film transistor may further include a conductive pattern separated from the active layer, with the first conductive material layer interposed between the conductive pattern and the active layer.

[0039] The thin-film transistor may further include a conductive pattern separated from the active layer, wherein the first conductive material layer and the second conductive material layer are interposed between the conductive pattern and the active layer.

[0040] The active layer may include an oxide semiconductor material.

[0041] The oxide semiconductor material may include at least one of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials.

[0042] The active layer may include: a first oxide semiconductor layer; and a second oxide semiconductor layer on the first oxide semiconductor layer.

[0043] The active layer may also include a third oxide semiconductor layer on the second oxide semiconductor layer.

[0044] According to another aspect of the invention, the above and other objectives can be achieved by providing a display device including the aforementioned thin-film transistors. Attached Figure Description

[0045] The above and other objects, features, and advantages of the invention will become more clearly understood from the following detailed description given with reference to the accompanying drawings. In the drawings:

[0046] Figure 1A This is a plan view illustrating a thin-film transistor according to one embodiment of the present invention;

[0047] Figure 1B , 1C 1D is a cross-sectional view illustrating a thin-film transistor according to an embodiment of the present invention;

[0048] Figure 1E and 1F This is a cross-sectional view illustrating a thin-film transistor according to another embodiment of the present invention;

[0049] Figure 2A This is a plan view illustrating a thin-film transistor according to another embodiment of the present invention;

[0050] Figure 2B , 2C2D is a cross-sectional view illustrating a thin-film transistor according to another embodiment of the present invention;

[0051] Figure 3A This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0052] Figure 3B , Figure 3C and 3D This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0053] Figure 4A This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0054] Figure 4B , Figure 4C and 4D This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0055] Figure 5A This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0056] Figure 5B , Figure 5C and 5D This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0057] Figure 6A This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0058] Figure 6B , Figure 6C and 6D This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0059] Figure 7A This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0060] Figure 7B , Figure 7C and 7D This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0061] Figure 8A This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0062] Figure 8B , Figure 8C and 8D This is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention;

[0063] Figure 9Aand 9B This is a schematic diagram illustrating the effective gate voltage of a thin-film transistor;

[0064] Figure 10A and 10B This is a schematic diagram illustrating the effective gate voltage of a thin-film transistor according to an embodiment of the present invention;

[0065] Figure 11 It is a graph illustrating the threshold voltage of a thin-film transistor;

[0066] Figure 12 It is a graphical representation of the S-factor and on-current distribution curves of a thin-film transistor.

[0067] Figure 13 This is a schematic diagram illustrating a display device according to another embodiment of the present invention;

[0068] Figure 14 It is a diagram Figure 13 The circuit diagram of any pixel;

[0069] Figure 15 It is a diagram Figure 14 A planar image of pixels;

[0070] Figure 16 It is along Figure 15 A sectional view taken by line I-I';

[0071] Figure 17 This is a circuit diagram illustrating any pixel of a display device according to yet another embodiment of the present invention;

[0072] Figure 18 This is a circuit diagram illustrating any pixel of a display device according to another embodiment of the present invention. Detailed Implementation

[0073] The advantages and features of the invention, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the disclosure of the invention comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art. Furthermore, the invention is defined only by the scope of the claims.

[0074] The shapes, sizes, proportions, angles, and quantities disclosed in the drawings to describe various embodiments of the invention are merely examples, and therefore the invention is not limited to the details illustrated. Similar reference numerals refer to similar elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention.

[0075] Where the terms “including,” “having,” and “contains” are used in the description in this application, other parts may be added unless “only” is used.

[0076] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0077] When describing positional relationships, such as when the positional relationship is described as "on," "above," "below," and "after," one or more additional parts may be placed between the two parts, unless "exactly" or "directly" is used.

[0078] This document may use spatially relative terms such as “below,” “lower,” “below,” “above,” and “upper” to readily describe the relationship of one or more elements shown in the figures to other elements. It will be understood that these terms are intended to cover different orientations of the device beyond those depicted in the figures. For example, if the device shown in the figures is reversed, a device described as being “below” or “lower” to other devices may be arranged to be “above” to other devices. Thus, the exemplary term “below or lower” may include both “below or lower” and “upper” orientations. Similarly, the exemplary term “upper” or “above” may include both “above” and “below or lower” orientations.

[0079] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless “exactly” or “directly” is used.

[0080] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0081] The term "at least one" should be understood to include any one and all combinations of one or more of the relevant listed items. For example, "at least one of the first, second and third items" means a combination of all items selected from the first, second and third items, as well as the first, second or third item.

[0082] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The various embodiments of the present invention can be implemented independently of each other, or implemented jointly in a mutually dependent relationship.

[0083] In the accompanying drawings, even when depicted in different figures, the same or similar elements are referred to by the same reference numerals.

[0084] In embodiments of the present invention, for ease of description, the source and drain are distinguished from each other. However, the source and drain can be used interchangeably. The source can be the drain, and the drain can be the source. Furthermore, the source in any embodiment of the present invention can be the drain in another embodiment of the present invention, and the drain in any embodiment of the present invention can be the source in another embodiment of the present invention.

[0085] For ease of description, in some embodiments of the present invention, the source region is separated from the source, and the drain region is separated from the drain. However, the embodiments of the present invention are not limited to this structure. For example, the source region can be the source, and the drain region can be the drain. Furthermore, the source region can be the drain, and the drain region can be the source.

[0086] Figure 1A This is a plan view illustrating a thin-film transistor 100 according to an embodiment of the present invention; Figure 1B , 1C Figure 1D is a cross-sectional view illustrating a thin-film transistor 100 according to an embodiment of the present invention.

[0087] A thin-film transistor 100 according to one embodiment of the present invention includes an active layer 130 and a gate 150 at least partially overlapping the active layer 130. The active layer 130 includes: a channel portion (CH) 130n; a first connection portion 131 contacting one side of the channel portion 130n; and a second connection portion 132 contacting the other side of the channel portion 130n. According to one embodiment of the present invention, the channel portion 130n includes a first region Ar1 and a second region Ar2 disposed parallel to the first region Ar1, wherein the first region Ar1 and the second region Ar2 are connected from the first connection portion 131 to the second connection portion 132, and the effective gate voltage applied to the first region Ar1 is less than the effective gate voltage applied to the second region Ar2.

[0088] According to one embodiment of the present invention, the channel portion 130n further includes a third region Ar3 spaced apart from the first region Ar1, and a second region Ar2 is inserted between the first region Ar1 and the third region Ar3, and the effective gate voltage applied to the third region Ar3 is less than the effective gate voltage applied to the second region Ar2.

[0089] According to one embodiment of the present invention, the thin-film transistor 100 may further include a first conductive material layer 71 overlapping with a channel portion 130n, and a first spacer 11 located between the channel portion 130n and the first conductive material layer 71. The channel portion 130n is disposed between the first conductive material layer 71 and the gate 150, and the first conductive material layer 71 may be connected to the first connection portion 131.

[0090] The following will refer to Figures 1A to 1D A thin-film transistor 100 according to one embodiment of the present invention will be described in more detail.

[0091] Figure 1A This is a plan view of a thin-film transistor 100 according to one embodiment of the present invention. Figure 1B It is along Figure 1A The sectional view taken from line 1I-1I'. Figure 1C It is along Figure 1A The sectional view taken from line 1II-1II'. Figure 1D It is along Figure 1A The sectional view taken from line 1III-1III'.

[0092] Reference Figures 1A to 1D The first conductive material layer 71 is disposed on the substrate 110.

[0093] Glass or plastic can be used as substrate 110. Transparent plastics with flexible properties, such as polyimide, can be used as plastic. When polyimide is used as substrate 110, heat-resistant polyimide that can withstand high temperatures can be used, taking into account the high-temperature deposition process performed on substrate 110.

[0094] A first conductive material layer 71 is disposed on the substrate 110. Although Figures 1A to 1D Not shown, however, the lower buffer layer 220 may be disposed between the substrate 110 and the first conductive material layer 71 (see [reference]). Figure 14 and 16 The lower buffer layer 220 can planarize the upper portion of the substrate 110, has air and moisture barrier properties, and can have insulating properties to protect the thin-film transistor 100.

[0095] The first conductive material layer 71 is conductive. The first conductive material layer 71 may comprise at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). The first conductive material layer 71 may have a multilayer structure, comprising at least two conductive layers having different physical properties from each other.

[0096] Furthermore, the first conductive material layer 71 may have light-shielding properties. Therefore, the first conductive material layer 71 can be used as a light-shielding layer. The first conductive material layer 71 can block light incident from the outside to protect the channel portion 130n. The first conductive material layer 71 may be referred to as a light-shielding layer.

[0097] The first conductive material layer 71 is disposed between the substrate 110 and the active layer 130, and the first conductive material layer 71 overlaps with the channel portion 130n of the active layer 130.

[0098] Reference Figures 1A to 1D A first spacer 11 is disposed on the first conductive material layer 71. The first spacer 11 is disposed between the first conductive material layer 71 and the channel portion 130n to space the first conductive material layer 71 and the channel portion 130n apart from each other.

[0099] According to one embodiment of the present invention, the first spacer 11 may have a thickness of 1 μm to 10 μm. The thickness of the first spacer 11 may vary depending on the size of the thin-film transistor 100. The first spacer 11 may have a thickness of, for example, 10 μm to 20 μm. When the thin-film transistor 100 according to one embodiment of the present invention is used in a display device, the first spacer 11 may have a thickness of, for example, 2 μm to 5 μm. According to one embodiment of the present invention, the thickness of the first spacer 11 may be referred to as the distance between the two surfaces of the first spacer 11, measured along a direction perpendicular to the surface of the substrate 110.

[0100] According to one embodiment of the invention, the first spacer 11 may have a thickness at least twice that of the buffer layer (BUF) 120.

[0101] The first spacer 11 may be made of an insulating material comprising at least one selected from silicon oxide, silicon nitride, and metal-based oxides. The first spacer 11 may have a linear shape. For example, the cross-section of the first spacer 11 may have a trapezoidal linear shape.

[0102] A buffer layer 120 is disposed on the first conductive material layer 71 and the first spacer 11. The buffer layer 120 may include at least one of silicon oxide, silicon nitride, and metal-based oxide. According to one embodiment of the present invention, the buffer layer 120 may include at least one of silicon oxide and silicon nitride. The buffer layer 120 may have a single-layer structure or a multi-layer structure.

[0103] The buffer layer 120 protects the active layer 130. Furthermore, the buffer layer 120 is formed such that the first conductive material layer 71 and the channel portion 130n are separated from and insulated from each other.

[0104] The active layer 130 is disposed on the buffer layer 120.

[0105] The active layer 130 may be formed of a semiconductor material. The active layer 130 may include any one of amorphous silicon semiconductor material, polycrystalline silicon semiconductor material, and oxide semiconductor material.

[0106] According to one embodiment of the present invention, the active layer 130 may include an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials. However, one embodiment of the present invention is not limited thereto, and the active layer 130 may be made of other oxide semiconductor materials known in the art.

[0107] The active layer 130 includes a channel portion 130n, a first connection portion 131, and a second connection portion 132. One side of the channel portion 130n contacts the first connection portion 131, and the other side of the channel portion 130n contacts the second connection portion 132. The channel portion 130n overlaps with the gate 150 and serves as the channel of the thin-film transistor 100.

[0108] The first connection portion 131 and the second connection portion 132 of the active layer 130 do not overlap with the gate 150. The first connection portion 131 and the second connection portion 132 can be formed by selectively conductiveizing the semiconductor material. Conductivity is a process in which layers A and B absorb oxygen from a portion of the first active layer in contact with the conductive material layer, thereby creating oxygen vacancies in the portions of the active layer in contact with layers A and B, thus making the portions of the active layer in contact with the conductive material layer "conductive".

[0109] According to one embodiment of the present invention, the first connection portion 131 of the active layer 130 may be a source region, and the second connection portion 132 may be a drain region. According to one embodiment of the present invention, the first connection portion 131 may be referred to as the source, and the second connection portion 132 may be referred to as the drain.

[0110] However, one embodiment of the present invention is not limited to the above example; the first connection portion 131 may be a drain region, and the second connection portion 132 may be a source region. Furthermore, the first connection portion 131 may be referred to as the drain, and the second connection portion 132 may be referred to as the source.

[0111] According to one embodiment of the present invention, the channel portion 130n includes a first region Ar1 and a second region Ar2 disposed parallel to the first region Ar1. (See also...) Figure 1A and 1BThe first spacer 11 does not overlap with the first region Ar1, but overlaps with the second region Ar2. According to one embodiment of the invention, the region of the channel portion 130n that overlaps with the first spacer 11 may be referred to as the second region Ar2, and a region of the channel portion 130n that is separated by the first spacer 11 and does not overlap with the first spacer 11 may be referred to as the first region Ar1.

[0112] Reference Figure 1A and 1B The channel portion 130n also includes a third region Ar3. The third region Ar3 does not overlap with the first spacer 11. The third region Ar3 is spaced apart from the first region Ar1, and the second region Ar2 is inserted between the first region Ar1 and the third region Ar3.

[0113] Reference Figure 1A and 1B The first region Ar1 and the second region Ar2 are arranged parallel to each other and extend from the first connecting portion 131 to the second connecting portion 132. The third region Ar3 is also arranged parallel to the second region Ar2 and extends from at least the first connecting portion 131 to the second connecting portion 132.

[0114] According to one embodiment of the invention, the effective gate voltage applied to the first region Ar1 is less than the effective gate voltage applied to the second region Ar2. Furthermore, the effective gate voltage applied to the third region Ar3 is less than the effective gate voltage applied to the second region Ar2. The effective gate voltages will be described later.

[0115] A gate insulating layer (GI) 140 is disposed on the active layer 130. The gate insulating layer 140 may comprise at least one of silicon oxide, silicon nitride, and metal-based oxide. The gate insulating layer 140 may have a single-layer structure or a multilayer structure.

[0116] Reference Figures 1B to 2D The gate insulating layer 140 may be integrally formed on the entire surface of the substrate 110 without being patterned, but one embodiment of the invention is not limited thereto. The gate insulating layer 140 may be patterned. For example, the gate insulating layer 140 may be patterned to a shape corresponding to the gate 150.

[0117] The gate insulating layer 140 protects the channel portion 130n.

[0118] The gate 150 is disposed on the gate insulating layer 140. The gate 150 overlaps with the channel portion 130n of the active layer 130.

[0119] The gate 150 may comprise at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate 150 may have a multilayer structure comprising at least two conductive layers with different physical properties from each other.

[0120] An interlayer insulating layer 180 is disposed on the gate 150. The interlayer insulating layer 180 is an insulating layer made of insulating material. The interlayer insulating layer 180 may be made of organic material, may be made of inorganic material, or may be made of a stack of organic and inorganic layers.

[0121] The source 161 and the drain 162 are disposed on the interlayer insulating layer 180.

[0122] The source electrode 161 can be connected to the first conductive material layer 71 via contact hole CH1. The source electrode 161 is also connected to the active layer 130 via contact hole CH2. Specifically, the source electrode 161 can be electrically connected to the first connection portion 131 of the active layer 130 via contact hole CH2. As a result, the first conductive material layer 71 can be connected to the first connection portion 131 of the active layer 130.

[0123] The drain 162 is separated from the source 161 and is therefore connected to the active layer 130 via the contact hole CH3. Specifically, the drain 162 can be electrically connected to the second connection portion 132 of the active layer 130 via the contact hole CH3.

[0124] Each of the source electrode 161 and the drain electrode 162 may contain at least one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof. Each of the source electrode 161 and the drain electrode 162 may be composed of a single layer made of metal or metal alloy, or may be formed as two or more layers.

[0125] Reference Figure 1C and 1D The first connection portion 131 and the source electrode 161 are shown as distinct from each other, but one embodiment of the invention is not limited thereto. The first connection portion 131 may be the source electrode, and the electrode indicated by the reference numeral "161" may be a connecting electrode or a bridge.

[0126] Reference Figure 1C and 1D The second connection portion 132 and the drain 162 are shown as distinct from each other, but one embodiment of the invention is not limited thereto. The second connection portion 132 may be a drain, and the electrode indicated by the reference numeral "162" may be a connecting electrode or a bridge.

[0127] According to one embodiment of the present invention, since the first conductive material layer 71 is connected to the source electrode 161, a voltage identical to the voltage applied to the source electrode 161 can be applied to the first conductive material layer 71. Since the first conductive material layer 71 is disposed between the substrate 110 and the active layer 130, the voltage applied to the first conductive material layer 71 can affect the channel portion 130n.

[0128] For example, due to the electrical influence of the first conductive material layer 71, the electric field effect applied to the channel portion 130n through the gate 150 can be selectively reduced. Specifically, an electric field is applied to the channel portion 130n through the gate 150, and the electric field effect applied to the second region of the channel portion 130n can be selectively reduced due to the electrical influence of the first conductive material layer 71.

[0129] According to one embodiment of the present invention, the effective gate voltage V eff The effective gate voltage V applied to the first region Ar1 of the channel portion 130n, which is disposed adjacent to the first conductive material layer 71, can be reduced. eff It can be less than the effective gate voltage V applied to the second region Ar2, which is located away from the channel portion 130n of the first conductive material layer 71. eff .

[0130] Similarly, the effective gate voltage V eff The effective gate voltage V applied to the third region Ar3 of the channel portion 130n, which is disposed adjacent to the first conductive material layer 71, can be reduced. eff It can be less than the effective gate voltage V applied to the second region Ar2, which is located away from the first conductive material layer 71. eff .

[0131] As described above, when the effective gate voltage decreases in the channel portion 130n, the S-factor of the thin-film transistor 100 can increase.

[0132] The S factor will be described in detail below.

[0133] In the drain-source current curve corresponding to the gate voltage of the thin-film transistor 100, the S-factor (sub-threshold oscillation) is obtained by the inverse value of the slope of the curve during the threshold voltage Vth period (i.e., at the threshold voltage Vth). For example, during the threshold voltage Vth period of the thin-film transistor 100, the S-factor can be used as an index to represent the level (i.e., rate of change) of the drain-source current corresponding to the gate voltage.

[0134] When the S-factor increases, the drain-source current I corresponding to the gate voltage increases. DSThe rate of change (or rate of change) decreases.

[0135] The S-factor can be obtained, for example, through... Figure 11 The current change curve shown is used to describe this. Figure 11 This is a threshold voltage curve of a thin-film transistor. Specifically, Figure 11 The gate voltage V is illustrated. GS The corresponding drain-source current I DS .exist Figure 11 The curve shown represents the time period of the threshold voltage Vth (i.e., for the threshold voltage Vth), and the gate voltage V. GS The corresponding drain-source current I DS The slope or inverse of the gradient of the curve is the S-factor. A steep slope results in a smaller S-factor; a gentle slope results in a larger S-factor. A larger S-factor corresponds to a larger drain-source current I corresponding to the gate voltage during the threshold voltage Vth period. DS The rate of change is low.

[0136] When the S-factor increases, the drain-source current I corresponding to the gate voltage during the threshold voltage Vth period increases. DS The rate of change is low, so it is easy to adjust the gate voltage V. GS To adjust the drain-source current I DS The range.

[0137] In current-driven display devices, such as organic light-emitting display devices, the drain-source current I of the driving thin-film transistor can be adjusted. DS The grayscale level of a pixel is controlled by the amplitude of the gate voltage. The drain-source current I of the driving thin-film transistor is determined by the gate voltage. DS The amplitude of the light-emitting diode (LED) is thus increased. Therefore, in an organic light-emitting display device driven by current, the gray level of the pixel becomes easier to adjust as the S-factor of the driving thin-film transistor increases.

[0138] Reference Figure 1B Since the first region Ar1 and the third region Ar3 of the channel portion 130n are positioned adjacent to the first conductive material layer 71, the first conductive material layer 71 can electrically influence the second region of the channel portion 130n when a voltage identical to the voltage applied to the source 161 is applied to the first conductive material layer 71. Due to the electrical influence of the first conductive material layer 71, the electric field effect applied to the second region of the channel portion 130n through the gate 150 can be reduced. As a result, the S-factor of the thin-film transistor 100 including the first conductive material layer 71 can be increased.

[0139] The influence of the first conductive material layer 71 on the S-factor of the thin-film transistor 100 can be achieved through... Figure 9A , 9BIt can be described using 10A and 10B.

[0140] Figure 9A and 9B This is a diagram illustrating the effective gate voltage V of a thin-film transistor. eff A schematic diagram. Specifically, Figure 9A and 9B The diagram has a similar Figures 1A to 1D The effective gate voltage V of a thin-film transistor (Comparative Example 1) without a first conductive material layer 71 has a structure. eff A schematic diagram.

[0141] Figure 9A A schematic diagram illustrates the effect of gate voltage V GS The capacitance Cap that can be generated when applied to a thin-film transistor. Gate voltage V. GS It is the voltage between the source 162 and the gate 150. According to one embodiment of the present invention, the gate voltage V GS This can be referred to as the voltage between the first connection portion 131 and the gate 150.

[0142] Figure 9A The diagram illustrates the relationship between the threshold voltage Vth and the capacitance Cap near the threshold voltage Vth before the thin-film transistor is fully turned on.

[0143] like Figure 9A As shown, when the gate voltage V GS When applied to a thin-film transistor that does not have a first conductive material layer 71 (Comparative Example 1), a capacitance C can be formed between the channel portion 130n of the active layer 130 and the gate 150 (gate). GI Furthermore, a capacitor C can be formed between the channel portion 130n and the first connection portion 131 (source). CH .

[0144] The capacitor C formed between the channel portion 130n and the first connection portion 131 (source) CH It can be described as a capacitor formed in the channel portion 130n made of an oxide semiconductor layer having N-type semiconductor characteristics, by the voltage difference between the drain 162, which is a high-voltage terminal, and the source 161, which is a low-voltage terminal.

[0145] Figure 9A The relationship between the voltage and capacitance Cap shown can be displayed as follows: Figure 9B As shown. (Refer to...) Figure 9B Due to the capacitance C between the channel portion 130n and the second connection portion 132 (source), CH Not all gate voltages V GS Both are effectively applied to the channel section 130n. As a result, voltage loss can occur.

[0146] Reference Figure 9B When a gate voltage V130n is effectively applied to the channel portion during the driving of the thin-film transistor... GS A portion of this is referred to as the effective gate voltage V. eff At that time, the effective gate voltage V eff It can be obtained through Equation 1 below.

[0147] [Equation 1]

[0148] V eff =[C GI / (C GI +C CH )]x V GS

[0149] Figure 10A and 10B This diagram illustrates the effective gate voltage V of a thin-film transistor 100 according to an embodiment of the present invention. eff A schematic diagram.

[0150] Figure 10A A schematic diagram illustrates the effect of gate voltage V GS Capacitance Cap that can be generated when applied to a thin-film transistor 100 according to an embodiment of the present invention. Figure 10A The diagram illustrates the relationship between the threshold voltage Vth and the capacitance Cap near the threshold voltage Vth before the thin-film transistor is fully turned on.

[0151] like Figure 10A As shown, when the gate voltage V GS When applied to a thin-film transistor, a capacitance C can be formed between the channel portion 130n of the active layer 130 and the gate 150. GI A capacitor C can be formed between the channel portion 130n and the first connection portion 131 (source). CH Furthermore, a capacitor C can be additionally formed between the channel portion 130n and the first conductive material layer 71. BUF .

[0152] Reference Figure 1A and 1B The capacitance C between the channel portion 130n and the first conductive material layer 71 BUF It can be the sum of the first capacitor Cap11 between the first region Ar1 and the first conductive material layer 71 of the channel portion 130n, the second capacitor Cap12 between the second region Ar2 and the first conductive material layer 71 of the channel portion 130n, and the third capacitor Cap13 between the third region Ar3 and the first conductive material layer 71 of the channel portion 130n. Specifically, the capacitance C between the channel portion 130n and the first conductive material layer 71... BUFIt can be calculated using Equation 2 below.

[0153] [Equation 2]

[0154] C BUF =Cap11 + Cap12 + Cap13

[0155] According to one embodiment of the present invention, since the distance between the first region Ar1 and the first conductive material layer 71 in the channel portion 130n and the distance between the third region Ar3 and the first conductive material layer 71 are both shorter than the distance between the second region Ar2 and the first conductive material layer 71 in the channel portion 130n, the following relationships 3 and 4 can be established between the first capacitor Cap11, the second capacitor Cap12 and the third capacitor C13:

[0156] [Relationship 3]

[0157] Cap11>Cap12

[0158] [Relationship 4]

[0159] Cap13 > Cap12

[0160] according to Figure 10A The relationship between voltage and capacitance Cap can be as follows: Figure 10B As shown in the diagram. (Refer to...) Figure 10B Due to the capacitance C between the channel portion 130n and the first connection portion 131 (source), CH And the capacitance C between the channel portion 130n and the first conductive material layer 71 BUF Not all gate voltages V GS Both are effectively applied to the channel section 130n, which can generate voltage loss.

[0161] Since the first conductive material layer 71, the source electrode 161, and the first connection portion 131 are electrically connected to each other, an additional capacitance C is generated between the channel portion 130n and the first conductive material layer 71. BUF This results in voltage loss due to the capacitance C. CH +C BUF Increase.

[0162] Specifically, when the gate voltage V GS The voltage that is effectively applied to the channel section at 130n is called Figure 10B The effective gate voltage V eff At that time, the effective gate voltage V eff It can be obtained through Equation 5 below.

[0163] [Equation 5]

[0164] V eff =[CGI / (C GI +C CH +C BUF )]x V GS

[0165] Referring to Equation 5, due to the capacitance C between the channel portion 130n and the first conductive material layer 71 BUF Therefore, the denominator of equation 5 increases, and the effective gate voltage V increases accordingly. eff The reduction can be relatively greater than Equation 1. Therefore, when a gate voltage V is applied... GS In a thin-film transistor 100 according to an embodiment of the present invention, the drain-source current I... DS The rate of increase (i.e., the rate or slope of increase relative to the gate voltage change) decreases, resulting in an increase in the S-factor.

[0166] According to one embodiment of the present invention, the capacitance Cap11 between the first region Ar1 and the first conductive material layer 71 of the channel portion 130n is greater than the capacitance Cap12 between the second region Ar2 and the first conductive material layer 71 of the channel portion 130n. Furthermore, the capacitance Cap13 between the third region Ar3 and the first conductive material layer 71 of the channel portion 130n is greater than the capacitance Cap12 between the second region Ar2 and the first conductive material layer 71 of the channel portion 130n. As a result, the effective gate voltage V... eff It can be significantly reduced in the first region Ar1 and the third region Ar3 located near the first conductive material layer 71 in the channel portion 130n.

[0167] Therefore, according to one embodiment of the present invention, the effective gate voltage V applied to the first region Ar1 is... eff The amplitude is less than the effective gate voltage V applied to the second region Ar. eff The amplitude. Furthermore, the effective gate voltage V applied to Ar3 in the third region. eff The amplitude is less than the effective gate voltage V applied to the second region Ar2. eff The range.

[0168] Due to the effective gate voltage V in region Ar1 and region Ar3 eff The current I is relatively small, so during the period before the thin-film transistor 100 is fully turned on, the threshold voltage Vth is low. DS The rate of increase becomes slower / smaller, thereby increasing the S-factor. As described above, according to one embodiment of the present invention, the S-factor of the thin-film transistor 100 can be increased without increasing the spacing between the channel portion 130n and the gate 150.

[0169] When the thin-film transistor 100 is turned on, the capacitance C between the channel portion 130n and the first connection portion 131 (source) is... CH And the capacitance C between the channel portion 130n and the first conductive material layer 71 BUF It can be ignored, and the current I DS Through the capacitance C between the channel portion 130n and the gate 150 GI The current flows between the drain 162 and the source 161. According to one embodiment of the invention, since the spacing between the channel portion 130n and the gate 150 is not increased, the on-current of the thin-film transistor 100 is not reduced when the thin-film transistor 100 is turned on. In particular, when the thin-film transistor 100 is turned on, the second region Ar2 of the channel portion 130n becomes the dominant current region, thereby improving the on-current of the thin-film transistor 100.

[0170] In methods that increase the S-factor by increasing the distance between the gate and the channel, a problem arises where the on-current of the thin-film transistor decreases despite the increase in the S-factor.

[0171] On the other hand, according to one embodiment of the present invention, the S-factor of the thin-film transistor 100 can be increased, and the thin-film transistor 100 can have excellent / high on-current characteristics. Since the thin-film transistor 100 according to one embodiment of the present invention has a large S-factor, the thin-film transistor 100 can be used as a driving transistor for a display device.

[0172] Figure 1E and 1F This is a cross-sectional view illustrating a thin-film transistor according to another embodiment of the present invention.

[0173] exist Figure 1E In thin-film transistors, compared to Figures 1A to 1D The thin-film transistor 100 has an active layer 130 with a multilayer structure.

[0174] Reference Figure 1E The active layer 130 includes a first oxide semiconductor layer 130a on the substrate 110 and a second oxide semiconductor layer 130b on the first oxide semiconductor layer 130a. The first oxide semiconductor layer 130a and the second oxide semiconductor layer 130b may contain the same semiconductor material or may contain different semiconductor materials.

[0175] The first oxide semiconductor layer 130a supports the second oxide semiconductor layer 130b. Therefore, the first oxide semiconductor layer 130a is referred to as a "support layer". A channel portion 130n may be formed in the second oxide semiconductor layer 130b. Therefore, the second oxide semiconductor layer 130b is referred to as a "channel layer", but one embodiment of the present invention is not limited thereto, and the channel portion 130n may be formed in the first oxide semiconductor layer 130a.

[0176] The structure of the active layer 130, which includes a first oxide semiconductor layer 130a and a second oxide semiconductor layer 130b, is called a bi-layer structure.

[0177] exist Figure 1F In thin-film transistors, compared to Figure 1E The thin-film transistor has an active layer that further includes a third oxide semiconductor layer 130c located on the second oxide semiconductor layer 130b.

[0178] Reference Figure 1F The active layer 130 includes a first oxide semiconductor layer 130a, a second oxide semiconductor layer 130b, and a third oxide semiconductor layer 130c. However, another embodiment of the present invention is not limited thereto, and the active layer 130 may further include other semiconductor layers.

[0179] Figure 2A This is a plan view illustrating a thin-film transistor 200 according to another embodiment of the present invention. Figure 2B , 2C 2D is a cross-sectional view illustrating a thin-film transistor 200 according to another embodiment of the present invention. Specifically, Figure 2B It is along Figure 2A The sectional view taken by line 2I-2I'. Figure 2C It is along Figure 2A The sectional view taken from line 2II-2II'. Figure 2D It is along Figure 2A The sectional view taken from line 2III-2III'.

[0180] compared to Figure 1A Thin-film transistor 100, Figure 2A The thin-film transistor 200 includes a first spacer 21 and a second spacer 22. In the following text, to avoid repetition, descriptions of the already described elements will be omitted.

[0181] Reference Figure 2A and 2B A first spacer 21 and a second spacer 22 are disposed on the first conductive material layer 71. The first spacer 21 and the second spacer 22 are disposed between the first conductive material layer 71 and the channel portion 130n to space the first conductive material layer 71 and the channel portion 130n apart from each other.

[0182] Reference Figure 2A The channel portion 130n includes a first region Ar1, a second region Ar2, and a fourth region Ar4. In a thin-film transistor 200 according to another embodiment of the present invention, the channel portion 130n includes a fourth region Ar4 spaced apart from the second region Ar2, and the first region Ar1 is interposed between the second region Ar2 and the fourth region Ar4. The effective gate voltage applied to the fourth region Ar4 is configured to be greater than the effective gate voltage applied to the first region Ar1.

[0183] The first spacer 21 overlaps with the second region Ar2 but not with the first region Ar1. The fourth region Ar4 of the channel portion 130n overlaps with the second spacer 22. In this case, the first region Ar1 is located between the second region Ar2 and the fourth region Ar4.

[0184] According to another embodiment of the present invention, the first spacer 21 and the second spacer 22 are separated from each other, and the first region Ar1 overlaps with the gap space between the first spacer 21 and the second spacer 22.

[0185] Reference Figure 2B The first capacitor Cap21 is formed between the first region Ar1 of the channel portion 130n and the first conductive material layer 71, the second capacitor Cap22 is formed between the second region Ar2 of the channel portion 130n and the first conductive material layer 71, and the fourth capacitor C24 is formed between the fourth region Ar4 of the channel portion 130n and the first conductive material layer 71.

[0186] According to another embodiment of the present invention, since the distance between the fourth region Ar4 and the first conductive material layer 71 in the channel portion 130n is greater than the distance between the first region Ar1 and the first conductive material layer 71 in the channel portion 130n, the fourth capacitor Cap24 is smaller than the first capacitor Cap21. Therefore, the effective gate voltage V in the fourth region Ar4 of the channel portion 130n is... eff The reduction is less compared to the first region Ar1. As a result, the effective gate voltage V applied to the fourth region Ar4 is... eff Greater than the effective gate voltage V applied to the first region Ar1 eff .

[0187] According to another embodiment of the present invention, when a gate voltage V is applied to the channel portion 130n GS At that time, the drain-source current I DS The rate of increase in S-factor is reduced in the thin-film transistor 200 through the first capacitor Cap21, the second capacitor Cap22, and the fourth capacitor Cap24, thus increasing the S-factor. In particular, the S-factor of the thin-film transistor 200 can be significantly increased through the first capacitor Cap21.

[0188] Furthermore, according to another embodiment of the present invention, since it is not necessary to increase the spacing between the channel portion 130n and the gate 150 to increase the S-factor, the on-current of the thin-film transistor 200 does not decrease when the thin-film transistor 200 is turned on. As a result, the thin-film transistor 200 can have excellent on-current characteristics. In particular, when the thin-film transistor 200 is turned on, the second region Ar2 and the fourth region Ar4 of the channel portion 130n become the dominant current regions, thereby improving the on-current of the thin-film transistor 200.

[0189] Figure 3A This is a plan view illustrating a thin-film transistor 300 according to another embodiment of the present invention. Figure 3B , 3C 3D is a cross-sectional view illustrating a thin-film transistor 300 according to another embodiment of the present invention. Specifically, Figure 3B It is along Figure 3A The sectional view taken from line 3I-3I'. Figure 3C It is along Figure 3A The sectional view taken from line 3II-3II'. Figure 3D It is along Figure 3A The sectional view taken from line 3III-3III'.

[0190] compared to Figure 1A Thin-film transistor 100, Figure 3A The thin-film transistor 300 includes a first conductive material layer 81 and a second conductive material layer 82.

[0191] Reference Figure 3A and 3B A first conductive material layer 81 and a second conductive material layer 82 are disposed on the substrate 110 and overlap with the channel portion 130n. For example... Figure 3B As shown, the channel portion 130n is disposed between the first conductive material layer 81, the second conductive material layer and the gate 150.

[0192] Each of the first conductive material layer 81 and the second conductive material layer 82 is connected to the first connection portion 131.

[0193] Reference Figure 3A and 3C Each of the first conductive material layer 81 and the second conductive material layer 82 is connected to the pad portion 85. The pad portion 85 may be integrally formed with the first conductive material layer 81 and the second conductive material layer 82. (Refer to...) Figure 3C and 3D The pad portion 85 is connected to the source electrode 161 via contact hole CH1, and the source electrode 161 is connected to the first connection portion 131 via contact hole CH2. As a result, each of the first conductive material layer 81 and the second conductive material layer 82 can be connected to the first connection portion 131 via the pad portion 85 and the source electrode 161.

[0194] Reference Figure 3A and 3B The first spacer 11 is disposed between the first conductive material layer 81 and the second conductive material layer 82. The first spacer 11 overlaps with the channel portion 130n, which is disposed between the first spacer 11 and the gate 150.

[0195] According to another embodiment of the present invention, the first conductive material layer 81, the second conductive material layer 82, and the first spacer 11 may be disposed on the same layer (see [reference]). Figure 3B ).

[0196] Reference Figure 3A The channel portion 130n includes a first region Ar1, a second region Ar2, and a third region Ar3. The first region Ar1 overlaps with the first conductive material layer 81, the second region Ar2 overlaps with the first spacer 11, and the third region Ar3 overlaps with the second conductive material layer 82.

[0197] The first conductive material layer 81 overlaps with the first region Ar1 but not with the second region Ar2. The first spacer 11 does not overlap with the first region Ar1 but overlaps with the second region Ar2.

[0198] The second conductive material layer 82 overlaps with the third region Ar3, but does not overlap with the first spacer 11.

[0199] Reference Figure 3B The first capacitor Cap31 is formed between the first region Ar1 of the channel portion 130n and the first conductive material layer 81, and the third capacitor Cap33 is formed between the third region Ar3 of the channel portion 130n and the second conductive material layer 82.

[0200] According to another embodiment of the present invention, capacitor Cap is substantially not formed between the second region Ar2 of the channel portion 130n and the substrate 110 located below the second region Ar2. Therefore, the effective gate voltage V in the second region Ar2 of the channel portion 130n is... eff Compared to the effective gate voltage V in the first region Ar1 and the third region Ar3 eff The reduction is even less. As a result, the effective gate voltage V applied to Ar3 in the third region is reduced. eff Less than the effective gate voltage V applied to Ar2 in the second region eff .

[0201] According to another embodiment of the present invention, when a gate voltage V is applied to the channel portion 130n... GS At that time, the drain-source current I DS The rate of increase is reduced in the thin-film transistor 300 by the first capacitor Cap31 and the third capacitor Cap33, and the S factor increases.

[0202] Furthermore, according to another embodiment of the present invention, since it is not necessary to increase the spacing between the channel portion 130n and the gate 150 to increase the S-factor, the on-current of the thin-film transistor 300 does not need to decrease when the thin-film transistor 300 is turned on. As a result, the thin-film transistor 300 can have excellent on-current characteristics. In particular, when the thin-film transistor 300 is turned on, the second region Ar2 of the channel portion 130n becomes the dominant current region, thereby improving the on-current of the thin-film transistor 300.

[0203] Figure 4A This is a plan view illustrating a thin-film transistor 400 according to yet another embodiment of the present invention. Figure 4B , 4C 4D is a cross-sectional view illustrating a thin-film transistor 400 according to another embodiment of the present invention. Specifically, Figure 4B It is along Figure 4A A sectional view taken from line 4I-4I'. Figure 4C It is along Figure 4A The sectional view taken from line 4II-4II'. Figure 4D It is along Figure 4A The sectional view taken from line 4III-4III'.

[0204] compared to Figure 2A Thin-film transistor 200, Figure 4A The thin-film transistor 400 includes a first conductive material layer 91 located between a first spacer 21 and a second spacer 22.

[0205] Specifically, Figure 4A The thin-film transistor 400 includes a first conductive material layer 91, a first spacer 21, and a second spacer 22 overlapping with a channel portion 130n. The channel portion 130n is disposed between the first conductive material layer 91, the first spacer 21, the second spacer 22, and the gate 150.

[0206] The first conductive material layer 91 is connected to the first connection portion 131.

[0207] Reference Figure 4A and 4C The first conductive material layer 91 is connected to the pad portion 95. The pad portion 95 may be integrally formed with the first conductive material layer 91. (Refer to...) Figure 4C and 4D The pad portion 95 is connected to the source electrode 161 via contact hole CH1, and the source electrode 161 is connected to the first connection portion 131 via contact hole CH2. As a result, the first conductive material layer 91 can be connected to the first connection portion 131 via the pad portion 95 and the source electrode 161.

[0208] Reference Figure 4BA first conductive material layer 91 is disposed between the first spacer 21 and the second spacer 22. According to another embodiment of the present invention, the first conductive material layer 91, the first spacer 21, and the second spacer 22 may be disposed on the same layer (see [reference]). Figure 4B ).

[0209] Reference Figure 4A The channel portion 130n includes a first region Ar1, a second region Ar2, and a fourth region Ar4. The first region Ar1 overlaps with the first conductive material layer 91, the second region Ar2 overlaps with the first spacer 21, and the fourth region Ar4 overlaps with the second spacer 22.

[0210] The first conductive material layer 91 overlaps with the first region Ar1. The first region Ar1 is disposed between the second region Ar2 and the fourth region Ar4. The fourth region Ar4 may extend from at least the first connecting portion 131 to the second connecting portion 132.

[0211] The first spacer 21 overlaps with the second zone Ar2 but not with the first zone Ar1. The second spacer 22 overlaps with the fourth zone Ar4 but not with the first zone Ar1.

[0212] Reference Figure 4A and 4B A first capacitor, Cap41, is formed between the first region Ar1 of the channel portion 130n and the first conductive material layer 91. However, capacitor Cap is not substantially formed between the second region Ar2 of the channel portion 130n and the substrate 110 located below the second region Ar2. Furthermore, capacitor Cap is not formed between the fourth region Ar4 of the channel portion 130n and the substrate 110 located below the fourth region Ar4. Therefore, the effective gate voltage V in the second region Ar2 and the fourth region Ar4 of the channel portion 130n... eff The reduction is less compared to the first region Ar1. As a result, the effective gate voltage V applied to each of the second region Ar2 and the fourth region Ar4 of the channel portion 130n is... eff Greater than the effective gate voltage V applied to the first region Ar1 eff .

[0213] According to another embodiment of the present invention, when a gate voltage V is applied to the channel portion 130n... GS At that time, the drain-source current I DS The rate of increase is reduced in the thin-film transistor 400 through the first capacitor Cap41, and the S factor increases.

[0214] Furthermore, according to another embodiment of the present invention, since it is not necessary to increase the spacing between the channel portion 130n and the gate 150 to increase the S-factor, the on-current of the thin-film transistor 400 does not decrease when the thin-film transistor 400 is turned on. As a result, the thin-film transistor 400 can have improved / superior on-current characteristics. In particular, when the thin-film transistor 400 is turned on, the second region Ar2 and the fourth region Ar4 of the channel portion 130n become the dominant current regions, thereby improving the on-current of the thin-film transistor 400.

[0215] Figure 5A This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention. Figure 5B , 5C 5D is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention. Specifically, Figure 5B It is along Figure 5A The sectional view taken from line 5I-5I'. Figure 5C It is along Figure 5A A sectional view taken from line 5II-5II'. Figure 5D It is along Figure 5A The sectional view taken from line 5III-5III'.

[0216] compared to Figure 3A Thin-film transistor 300, Figure 5A The thin-film transistor 500 does not include the first spacer 11.

[0217] Reference Figure 5A and 5B A first conductive material layer 81 and a second conductive material layer 82 are disposed on the substrate 110 and overlap with the channel portion 130n. For example... Figure 5B As shown, the channel portion 130n is disposed between the first conductive material layer 81, the second conductive material layer 82 and the gate 150.

[0218] Each of the first conductive material layer 81 and the second conductive material layer 82 is connected to the first connection portion 131.

[0219] Reference Figure 5A and 5C Each of the first conductive material layer 81 and the second conductive material layer 82 can be connected to the pad portion 85, and can be connected to the first connection portion 131 via the pad portion 85 and the source electrode 161.

[0220] According to another embodiment of the present invention, the first conductive material layer 81 and the second conductive material layer 82 may be disposed on the same layer (see [reference]). Figure 5B However, another embodiment of the present invention is not limited thereto. The first conductive material layer 81 and the second conductive material layer 82 may be disposed in different layers from each other.

[0221] Reference Figure 5A The channel portion 130n includes a first region Ar1, a second region Ar2, and a third region Ar3. The first region Ar1 overlaps with the first conductive material layer 81, and the third region Ar3 overlaps with the second conductive material layer 82. According to another embodiment of the present invention, the first conductive material layer 81 and the second conductive material layer 82 are separated from each other in a plane, and the second region Ar2 of the channel portion 130n overlaps with the gap space between the first conductive material layer 81 and the second conductive material layer 82.

[0222] The first conductive material layer 81 overlaps with the first region Ar1 but not with the second region Ar2. The second conductive material layer 82 overlaps with the third region Ar3 but not with the second region Ar2.

[0223] Reference Figure 5B The first capacitor Cap51 is formed between the first region Ar1 of the channel portion 130n and the first conductive material layer 81, and the third capacitor Cap53 is formed between the third region Ar3 of the channel portion 130n and the second conductive material layer 82.

[0224] According to another embodiment of the present invention, capacitor Cap is substantially not formed between the second region Ar2 of the channel portion 130n and the substrate 110 located below the second region Ar2. Therefore, the effective gate voltage V in the second region Ar2 of the channel portion 130n is... eff Compared to the effective gate voltage V in the first region Ar1 and the third region Ar3 eff The reduction is even less. As a result, the effective gate voltage V applied to Ar3 in the third region is reduced. eff Less than the effective gate voltage V applied to Ar2 in the second region eff .

[0225] According to another embodiment of the present invention, when a gate voltage V is applied to the channel portion 130n... GS At that time, the drain-source current I DS The rate of increase is reduced in the thin-film transistor 500 by the first capacitor Cap51 and the third capacitor Cap53, and the S factor increases.

[0226] Furthermore, according to another embodiment of the present invention, since it is not necessary to increase the spacing between the channel portion 130n and the gate 150 to increase the S-factor, the on-current of the thin-film transistor 500 does not decrease when the thin-film transistor 500 is turned on. As a result, the thin-film transistor 50 can have improved / superior on-current characteristics.

[0227] Figure 6A This is a plan view illustrating a thin-film transistor 600 according to yet another embodiment of the present invention. Figure 6B , 6C6D is a cross-sectional view illustrating a thin-film transistor 600 according to another embodiment of the present invention. Specifically, Figure 6B It is along Figure 6A The sectional view taken from line 6I-6I'. Figure 6C It is along Figure 6A The sectional view taken from line 6II-6II'. Figure 6D It is along Figure 6A The sectional view taken from line 6III-6III'.

[0228] compared to Figure 5A Thin-film transistor 500, Figure 6A The thin-film transistor 600 further includes a conductive pattern 111.

[0229] Reference Figures 6B to 6D Conductive pattern 111 is disposed on substrate 110.

[0230] The conductive pattern 111 is conductive. The conductive pattern 111 may comprise at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). The conductive pattern 111 may have a multilayer structure comprising at least two conductive layers having different physical properties from each other.

[0231] The conductive pattern 111 may have light-shielding properties. Therefore, the conductive pattern 111 can be used as a light-shielding layer. The conductive pattern 111 can block light incident from the outside to protect the channel portion 130n. The conductive pattern 111 may be referred to as a light-shielding layer.

[0232] A first buffer layer 121 is disposed on the conductive pattern 111, a first conductive material layer 81 and a second conductive material layer 82 are disposed on the first buffer layer 121, and a second buffer layer 122 is disposed on the first conductive material layer 81 and the second conductive material layer 82. Both the first buffer layer 121 and the second buffer layer 122 can be referred to as buffer layer 120. Both the first buffer layer 121 and the second buffer layer 122 are made of insulating material. The first buffer layer 121 and the second buffer layer 122 may have the same composition or may have different compositions from each other.

[0233] The active layer 130 is disposed on the second buffer layer 122.

[0234] Reference Figures 6A to 6D The conductive pattern 111 is spaced apart from the active layer 130, and a first conductive material layer 81 and a second conductive material layer 82 are interposed therebetween. The conductive pattern 111 overlaps with the channel portion 130n.

[0235] According to another embodiment of the present invention, the conductive pattern 111 is connected to the first connecting portion 131.

[0236] Reference Figure 6A and 6D The conductive pattern 111 is connected to the source 161 via the contact hole CH4. Since the source 161 is connected to the first connection portion 131 via the contact hole CH2, the conductive pattern 111 can be connected to the first connection portion 131 via the source 161.

[0237] Each of the first conductive material layer 81 and the second conductive material layer 82 is connected to the first connection portion 131 via a pad portion 85 and a source electrode 161. Therefore, the same voltage can be applied to the conductive pattern 111, the first conductive material layer 81, and the second conductive material layer 82.

[0238] Reference Figure 6A The channel portion 130n includes a first region Ar1, a second region Ar2, and a third region Ar3. The first region Ar1 overlaps with the first conductive material layer 81, and the third region Ar3 overlaps with the second conductive material layer 82. The second region Ar2 of the channel portion 130n overlaps with the gap space between the first conductive material layer 81 and the second conductive material layer 82.

[0239] Reference Figure 6B The first capacitor Cap61 is formed between the first region Ar1 of the channel portion 130n and the first conductive material layer 81, the second capacitor Cap62 is formed between the second region Ar2 of the channel portion 130n and the conductive pattern 111, and the third capacitor Cap63 is formed between the third region Ar3 of the channel portion 130n and the second conductive material layer 82.

[0240] The distance between the second region Ar2 and the conductive pattern 111 in the channel portion 130n is greater than the distance between the first region Ar1 and the first conductive material layer 81 in the channel portion 130n, and the distance between the third region Ar3 and the second conductive material layer 82 in the channel portion 130n. Therefore, the second capacitor Cap62 is smaller than the first capacitor Cap61 and the third capacitor Cap63. As a result, the effective gate voltage V in the second region Ar2 of the channel portion 130n is... eff Compared to the effective gate voltage V in the first region Ar1 and the third region Ar3 eff The effective gate voltage V applied to the first region Ar1 and the third region Ar3 is reduced even further. eff Less than the effective gate voltage V applied to Ar2 in the second region eff .

[0241] According to another embodiment of the present invention, when a gate voltage V is applied to the channel portion 130n... GS At that time, the drain-source current I DSThe rate of increase is reduced in the thin-film transistor 600 through the first capacitor Cap61, the second capacitor Cap62, and the third capacitor Cap63, and the S factor increases.

[0242] Furthermore, according to another embodiment of the present invention, since it is not necessary to increase the spacing between the channel portion 130n and the gate 150 to increase the S-factor, the on-current of the thin-film transistor 600 does not decrease when the thin-film transistor 600 is turned on. As a result, the thin-film transistor 600 can have excellent on-current characteristics.

[0243] Figure 7A This is a plan view illustrating a thin-film transistor 700 according to yet another embodiment of the present invention. Figure 7B , 7C 7D is a cross-sectional view illustrating a thin-film transistor 700 according to another embodiment of the present invention. Specifically, Figure 7B It is along Figure 7A The sectional view taken from line 7I-7I'. Figure 7C It is along Figure 7A The sectional view taken from line 7II-7II'. Figure 7D It is along Figure 7A The sectional view taken from line 7III-7III'.

[0244] compared to Figure 4A Thin-film transistor 400, Figure 7A The thin-film transistor 700 does not include the first spacer 21 and the second spacer 22.

[0245] Reference Figure 7A and 7B The first conductive material layer 91 disposed on the substrate 110 overlaps with the channel portion 130n. For example... Figure 7B As shown, the channel portion 130n is disposed between the first conductive material layer 91 and the gate 150.

[0246] The first conductive material layer 91 is connected to the first connection portion 131. (Refer to...) Figure 7C and 7D The first conductive material layer 91 can be connected to the first connection portion 131 via the pad portion 95 and the source electrode 161.

[0247] Reference Figure 7A The channel portion 130n includes a first region Ar1, a second region Ar2, and a fourth region Ar4. The first region Ar1 overlaps with the first conductive material layer 91. The second region Ar2 and the fourth region Ar4 do not overlap with the first conductive material layer 91. According to another embodiment of the present invention, the first region Ar1 may be disposed between the second region Ar2 and the fourth region Ar4.

[0248] Reference Figure 7BA first capacitor, Cap71, is formed between the first region Ar1 of the channel portion 130n and the first conductive material layer 91. However, capacitor Cap is essentially not formed between the second region Ar2 of the channel portion 130n and the substrate 110 located below the second region Ar2. Furthermore, capacitor Cap is not formed between the fourth region Ar4 of the channel portion 130n and the substrate 110 located below the fourth region Ar4. Therefore, the effective gate voltage V in the second region Ar2 and the fourth region Ar4 of the channel portion 130n... eff Compared to the effective gate voltage V in the first region Ar1 eff The reduction is even greater. As a result, the effective gate voltage V applied to each of the second region Ar2 and the fourth region Ar4 is... eff Greater than the effective gate voltage V applied to the first region Ar1 eff .

[0249] According to another embodiment of the present invention, when a gate voltage V is applied to the channel portion 130n... GS At that time, the drain-source current I DS The rate of increase is reduced in the thin-film transistor 700 through the first capacitor Cap71, and the S factor increases.

[0250] Furthermore, according to another embodiment of the present invention, since it is not necessary to increase the spacing between the channel portion 130n and the gate 150 to increase the S-factor, the on-current of the thin-film transistor 700 does not decrease when the thin-film transistor 700 is turned on. As a result, the thin-film transistor 700 can have excellent on-current characteristics. In particular, when the thin-film transistor 700 is turned on, the second region Ar2 and the fourth region Ar4 of the channel portion 130n become the dominant current regions, thereby improving the on-current of the thin-film transistor 700.

[0251] Figure 8A This is a plan view illustrating a thin-film transistor according to yet another embodiment of the present invention. Figure 8B , 8C 8D is a cross-sectional view illustrating a thin-film transistor according to yet another embodiment of the present invention. Specifically, Figure 8B It is along Figure 8A The sectional view taken from line 8I-8I'. Figure 8C It is along Figure 8A The sectional view taken from line 8II-8II'. Figure 8D It is along Figure 8A The sectional view taken from line 8III-8III'.

[0252] compared to Figure 7A Thin-film transistor 700, Figure 8A The thin-film transistor 800 further includes a conductive pattern 111.

[0253] Reference Figures 8B to 8D Conductive pattern 111 is disposed on substrate 110.

[0254] The conductive pattern 111 is conductive. Furthermore, the conductive pattern 111 may have a light-shielding pattern. Therefore, the conductive pattern 111 may be referred to as a light-shielding layer.

[0255] The first buffer layer 121 is disposed on the conductive pattern 111, the first conductive material layer 91 is disposed on the first buffer layer 121, the second buffer layer 122 is disposed on the first conductive material layer 91, and the active layer 130 is disposed on the second buffer layer 122.

[0256] Reference Figures 8A to 8D The conductive pattern 111 is spaced apart from the active layer 130, and a first conductive material layer 91 is inserted therebetween.

[0257] The conductive pattern 111 overlaps with the channel portion 130n and is connected to the first connection portion 131.

[0258] Reference Figure 8A and 8D The conductive pattern 111 is connected to the source 161 via the contact hole CH4. Since the source 161 is connected to the first connection portion 131 via the contact hole CH2, the conductive pattern 111 can be connected to the first connection portion 131 via the source 161.

[0259] The first conductive material layer 91 is connected to the first connection portion 131 via the pad portion 95 and the source 161. Therefore, the same voltage can be applied to the conductive pattern 111 and the first conductive material layer 91.

[0260] Reference Figure 8A The channel portion 130n includes a first region Ar1, a second region Ar2, and a fourth region Ar4. The first region Ar1 overlaps with the first conductive material layer 91. The first region Ar1 may be located between the second region Ar2 and the fourth region Ar4.

[0261] Reference Figure 8B The first capacitor Cap81 is formed between the first region Ar1 of the channel portion 130n and the first conductive material layer 91, the second capacitor Cap82 is formed between the second region Ar2 of the channel portion 130n and the conductive pattern 111, and the fourth capacitor Cap84 is formed between the fourth region Ar4 of the channel portion 130n and the conductive pattern 111.

[0262] The distances between the second region Ar2 and the conductive pattern 111 in the channel portion 130n, and between the fourth region Ar4 and the conductive pattern 111, are both greater than the distance between the first region Ar1 and the first conductive material layer 91 in the channel portion 130n. Therefore, the second capacitor Cap82 and the fourth capacitor Cap84 are both smaller than the first capacitor Cap81. Consequently, the effective gate voltage V in the second region Ar2 and the fourth region Ar4 of the channel portion 130n is... eff Compared to the effective gate voltage V in the first region Ar1 eff The effective gate voltage V applied to the first region Ar is reduced even further. eff Less than the effective gate voltage V applied to the second region Ar2 and the fourth region Ar4 eff .

[0263] According to another embodiment of the present invention, when a gate voltage V is applied to the channel portion 130n... GS At that time, the drain-source current I DS The rate of increase is reduced in the thin-film transistor 800 through the first capacitor Cap81, the second capacitor Cap82 and the fourth capacitor Cap84, and the S factor increases.

[0264] Furthermore, according to another embodiment of the present invention, since it is not necessary to increase the spacing between the channel portion 130n and the gate 150 to increase the S-factor, the on-current of the thin-film transistor 800 does not need to decrease when the thin-film transistor 800 is turned on. As a result, the thin-film transistor 800 can have excellent on-current characteristics.

[0265] Figure 11 This is a threshold voltage curve of a thin-film transistor (TFT). The threshold voltage curve of a TFT is determined by the gate voltage V. GS The corresponding drain-source current I DS It is represented by a curve graph.

[0266] exist Figure 11 In the above, Embodiment 1 is the threshold voltage curve of the thin-film transistor 100 in Figure 1.

[0267] exist Figure 11 In the example, Comparative Example 1 shows the threshold voltage curve of the thin-film transistor of Comparative Example 1. (Compared to...) Figure 1B Compared to the thin-film transistor 100, the thin-film transistor according to Comparative Example 1 does not include the first conductive material layer 71 and the first spacer 11.

[0268] exist Figure 11 In the example, Comparative Example 2 shows the threshold voltage curve of the thin-film transistor of Comparative Example 2. Figure 1BCompared to the thin-film transistor 100, the thin-film transistor according to Comparative Example 2 has a thick gate insulating layer 140 instead of a first conductive material layer 71 and a first spacer 11, in order to increase the S-factor of the thin-film transistor, thereby increasing the separation distance between the channel portion 130n and the gate 150.

[0269] Reference Figure 11 Please note that during the threshold voltage Vth period, the thin-film transistor of Embodiment 1 has a larger S-factor than the thin-film transistor of Comparative Example 1. Also note that the thin-film transistor of Embodiment 1 has a larger on-current than the thin-film transistor of Comparative Example 2. As described above, according to one embodiment of the present invention, a thin-film transistor with a large S-factor and excellent on-current characteristics can be manufactured.

[0270] Figure 12 This is a graphical representation of the S-factor and on-current distribution curves of a thin-film transistor. In this case, the on-current Ion5 represents the current when the gate voltage V... GS This refers to the current amplitude at 5V. (Refer to...) Figure 12 Please note that the thin-film transistor according to the embodiment of the present invention has a larger S-factor and a larger on-current (the "dec" in the unit in the figure represents decimal) compared to the thin-film transistor according to the comparative example.

[0271] The following will describe in detail the display devices including the thin-film transistors 100, 200, 300, 400, 500, 600, 700 and 800 described above.

[0272] Figure 13 This is a schematic diagram illustrating a display device 900 according to another embodiment of the present invention.

[0273] like Figure 13 As shown, a display device 900 according to another embodiment of the present invention includes a display panel 310, a gate driver 320, a data driver 330, and a controller 340.

[0274] Gate lines GL and data lines DL are disposed in the display panel 310, and multiple pixels P are disposed in the intersection area of ​​gate lines GL and data lines DL. Images are displayed by driving the pixels P.

[0275] The controller 340 controls the gate driver 320 and the data driver 330.

[0276] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 using signals provided from an external system (not shown). Furthermore, the controller 340 samples input image data from the external system, rearranges the sampled data, and provides the rearranged digital image data (RGB) to the data driver 330.

[0277] The gate control signal GCS includes the gate start pulse GSP, the gate shift clock GSC, the gate output enable signal GOE, the start signal Vst, and the gate clock GCLK. Additionally, control signals for controlling the shift register may be included in the gate control signal GCS.

[0278] The data control signal DCS includes the source start pulse SSP, the source shift clock signal SSC, the source output enable signal SOE, and the polarity control signal POL.

[0279] The data driver 330 provides data voltage to the data line DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltage and provides the data voltage to the data line DL.

[0280] Gate driver 320 may include shift register 350.

[0281] The shift register 350 sequentially provides gate pulses to the gate line GL within a frame using a start signal and a gate clock transmitted from the controller 340. In this case, a frame refers to the time period during which an image is output through the display panel 310. The gate pulses have an on-state voltage capable of turning on the switching elements (thin-film transistors) disposed in the pixel P.

[0282] In addition, shift register 350 provides a gate cutoff signal to gate line GL during other periods of a frame when no gate pulse is provided, which enables the switching element to turn off. Hereinafter, the gate pulse and gate cutoff signal will be collectively referred to as the scan signal SS or Scan.

[0283] According to one embodiment of the present invention, the gate driver 320 may be packaged on the substrate 110. In this way, the structure in which the gate driver 320 is directly packaged on the substrate 110 is referred to as a gate-in-panel (GIP) structure.

[0284] Figure 14 It is a diagram Figure 13 The circuit diagram of any pixel P. Figure 15 It is a diagram Figure 14 A planar image of pixel P. Figure 16 It is along Figure 15 A sectional view taken from line I-I'.

[0285] Figure 14 The circuit diagram is an equivalent circuit diagram of the pixel P of the display device 900, which includes an organic light-emitting diode (OLED) as a display element 710.

[0286] Pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710.

[0287] Figure 14 The pixel driving circuit PDC includes a first thin-film transistor TR1 as a switching transistor and a second thin-film transistor TR2 as a driving transistor. For example, thin-film transistors 100, 200, 300, 400, 500, 600, 700 and 800 described in the embodiments can be used as the second thin-film transistor TR2.

[0288] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by the scan signal SS provided via the gate line GL.

[0289] The data line DL provides the data voltage Vdata to the pixel driving circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0290] The driving power line PL provides a driving voltage Vdd to the display element 710, and the second thin-film transistor TR2 controls the driving voltage Vdd. The driving voltage Vdd is the pixel driving voltage used to drive the organic light-emitting diode (OLED) that serves as the display element 710.

[0291] When the first thin-film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 via the gate line GL, the data voltage Vdata provided via the data line DL is supplied to the gate G2 of the second thin-film transistor TR2, which is connected to the display element 710. The data voltage Vdata is charged into the first capacitor C1 formed between the gate G2 and the source S2 of the second thin-film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

[0292] The amount of current supplied to the organic light-emitting diode (OLED) of the display element 710 via the second thin-film transistor TR2 is controlled according to the data voltage Vdata, thereby controlling the gray level of the light emitted from the display element 710.

[0293] Reference Figure 15 and 16 The first thin-film transistor TR1 and the second thin-film transistor TR2 are disposed on the substrate 110.

[0294] The substrate 110 may be made of glass or plastic. Plastics with flexible properties, such as polyimide (PI), may be used as the substrate 110.

[0295] A lower buffer layer 220 is disposed on the substrate 110, and a first conductive material layer 71 is disposed on the lower buffer layer 220. (Refer to...) Figure 15 and 16 The first conductive material layer 71 is only disposed in the second thin film transistor TR2, which serves as the driving transistor. However, one embodiment of the present invention is not limited to this, and the first conductive material layer 71 may be disposed in the first thin film transistor TR1.

[0296] Furthermore, the light-shielding layer 111 may be disposed on the substrate 110. The light-shielding layer 111 may be disposed below the first conductive material layer 71. For example, the light-shielding layer 111 may be disposed on the substrate 110, the lower buffer layer 220 may be disposed on the light-shielding layer 111, and the first conductive material layer 71 may be disposed on the lower buffer layer 220.

[0297] like Figure 15 and 16 As illustrated, the light-shielding layer 111 is disposed below the first thin-film transistor TR1.

[0298] Reference Figure 15 and 16 The first spacer 11 is disposed on the first conductive material layer 71.

[0299] A buffer layer 120 is disposed on the first conductive material layer 71, the first spacer 11, and the light-shielding layer 111. The buffer layer 120 is made of an insulating material and protects the active layers A1 and A2 from external moisture or oxygen.

[0300] The first active layer A1 of the first thin-film transistor TR1 and the second active layer A2 of the second thin-film transistor TR2 are disposed on the buffer layer 120.

[0301] Each of the first active layer A1 and the second active layer A2 may include, for example, at least one of amorphous silicon semiconductor material, polycrystalline silicon semiconductor material, and oxide semiconductor material. Each of the first active layer A1 and the second active layer A2 may be composed of an oxide semiconductor layer made of an oxide semiconductor material.

[0302] In the first thin-film transistor TR1, the first active layer A1 may include a channel portion, a first connection portion, and a second connection portion. The channel portion of the first active layer A1 overlaps with the gate G1. According to another embodiment of the present invention, the first connection portion may be referred to as the first source S1, and the second connection portion may be referred to as the first drain D1.

[0303] In the second thin-film transistor TR2, the second active layer A2 may include a channel portion, a first connection portion, and a second connection portion. The channel portion of the second active layer A2 overlaps with the gate G2. According to another embodiment of the present invention, the first connection portion may be referred to as the second drain D2, and the second connection portion may be referred to as the second source S2.

[0304] Reference Figure 15 and 16 A portion of the first active layer A1 can be made conductive to become the first capacitor electrode C11 of the first capacitor C1.

[0305] A gate insulating layer 140 is disposed on the first active layer A1 and the second active layer A2. The gate insulating layer 140 may cover the entire upper surface of the first active layer A1 and the second active layer A2, or it may cover only a portion of the first active layer A1 and the second active layer A2.

[0306] The gate G1 of the first thin-film transistor TR1 and the gate G2 of the second thin-film transistor TR2 are disposed on the gate insulating layer 140.

[0307] An interlayer insulating layer 180 is disposed on gates G1 and G2.

[0308] The data cable DL and the drive power cable PL are mounted on the interlayer insulation layer 180.

[0309] The data line DL contacts the first source S1 formed in the first active layer A1 via the first contact hole H1. According to another embodiment of the present invention, the portion of the data line DL that overlaps with the first active layer A1 may be referred to as the first source S1.

[0310] The drive power line PL contacts the second drain electrode D2 formed in the second active layer A2 via the fifth contact hole H5. According to another embodiment of the present invention, the portion of the drive power line PL that overlaps with the second active layer A2 may be referred to as the second drain electrode D2.

[0311] Reference Figure 15 and 16 The second capacitor electrode C12 of the first capacitor C1, the first bridge BR1 and the second bridge BR2 are disposed on the interlayer insulating layer 180.

[0312] The second capacitor electrode C12 overlaps with the first capacitor electrode C11 to form the first capacitor C1.

[0313] The first bridge BR1 can be integrally formed with the second capacitor electrode C2. The first bridge BR1 is connected to the first conductive material layer 71 via the second contact hole H2 and to the second source S2 via the third contact hole H3. As a result, the first conductive material layer 71 can be connected to the second source S2 of the second thin film transistor TR2.

[0314] The second bridge BR2 is connected to the gate G2 of the second thin-film transistor TR2 via the fourth contact hole H4, and is connected to the first capacitor electrode C11 of the first capacitor C1 via the seventh contact hole H7.

[0315] In addition, refer to Figure 15 The third bridge BR3 is disposed on the interlayer insulating layer 180. The third bridge BR3 is connected to the gate line GL via the eighth contact hole H8, thereby connecting to the first gate G1, and to the light-shielding layer 111 of the first thin-film transistor TR1 via the ninth contact hole H9. Although Figure 15 The diagram illustrates the connection of the light-shielding layer 111 to the first gate G1. However, one embodiment of the present invention is not limited to this, and the light-shielding layer 111 may also be connected to the first source S1 or the first drain D1.

[0316] A planarization layer 175 is disposed on the data line DL, the drive power line PL, the second capacitor electrode C12, the first bridge BR1, the second bridge BR2, and the third bridge BR3. The planarization layer 175 planarizes the upper portions of the first thin-film transistor TR1 and the second thin-film transistor TR2, and protects the first thin-film transistor TR1 and the second thin-film transistor TR2.

[0317] The first electrode 711 of the display element 710 is disposed on the planarization layer 175. The first electrode 711 of the display element 710 contacts the second capacitor electrode C12 integrally formed with the first bridge BR1 via a sixth contact hole H6 formed in the planarization layer 175. As a result, the first electrode 711 can be connected to the second source S2 of the second thin film transistor TR2.

[0318] The embankment 750 is disposed at the edge of the first electrode 711. The embankment 750 defines the light-emitting area of ​​the display element 710.

[0319] An organic light-emitting layer 712 is disposed on the first electrode 711, and a second electrode 713 is disposed on the organic light-emitting layer 712. Thus, the display element 710 is completed. Figure 16 The display element 710 shown is an organic light-emitting diode (OLED). Therefore, the display device 900 according to one embodiment of the present invention is an organic light-emitting display device.

[0320] According to another embodiment of the present invention, the second thin-film transistor TR2 may have a large S-factor. The second thin-film transistor TR2 can be used as a driving transistor to improve the grayscale rendering capability of the display device 900.

[0321] Figure 17 This is a circuit diagram illustrating any pixel P of a display device 1000 according to another embodiment of the present invention.

[0322] Figure 17 This is an equivalent circuit diagram illustrating the pixel P of an organic light-emitting display device.

[0323] Figure 17 The pixel P of the display device 1000 shown includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0324] In pixel P, signal lines DL, GL, PL, RL, and SCL are set to provide signals to the pixel driving circuit PDC.

[0325] The data voltage Vdata is provided to the data line DL, the scan signal SS is provided to the gate line GL, the driving voltage Vdd for driving the pixel is provided to the driving power line PL, the reference voltage Vref is provided to the reference line RL, and the sensing control signal SCS is provided to the sensing control line SCL.

[0326] Reference Figure 17 Assume that the gate line of the nth pixel P is GLn, and the gate line of the (n-1)th pixel P adjacent to the nth pixel P is GLn-1. The gate line GLn-1 of the (n-1)th pixel P is used as the sensing control line SCL of the nth pixel P.

[0327] The pixel driving circuit PDC includes, for example, a first thin-film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL; a second thin-film transistor TR2 (driving transistor) for controlling the amplitude of the current output to the display element 710 according to the data voltage Vdata transmitted via the first thin-film transistor TR1; and a third thin-film transistor TR3 (reference transistor) for sensing the characteristics of the second thin-film transistor TR2.

[0328] A first capacitor C1 is disposed between the gate G2 of the second thin-film transistor TR2 and the display element 710. The first capacitor C1 is referred to as the storage capacitor Cst.

[0329] The first thin-film transistor TR1 is turned on by a scan signal SS provided to the gate line GL to transmit the data voltage Vdata provided to the data line DL to the gate G2 of the second thin-film transistor TR2.

[0330] The third thin-film transistor TR3 is connected to the first node n1 and the reference line RL located between the second thin-film transistor TR2 and the display element 710, thereby being turned on or off by the sensing control signal SCS, and sensing the characteristics of the second thin-film transistor TR2 as a driving transistor during the sensing period.

[0331] A second node n2, connected to the gate G2 of the second thin-film transistor TR2, is connected to the first thin-film transistor TR1. A first capacitor C1 is formed between the second node n2 and the first node n1.

[0332] When the first thin-film transistor TR1 is turned on, the data voltage Vdata supplied via the data line DL is provided to the gate G2 of the second thin-film transistor TR2. The data voltage Vdata is charged into the first capacitor C1 formed between the gate G2 and the source S2 of the second thin-film transistor TR2.

[0333] When the second thin-film transistor TR2 is turned on, current is supplied to the display element 710 via the second thin-film transistor TR2 according to the driving voltage Vdd used to drive the pixel, thereby outputting light from the display element 710.

[0334] Figure 18 This is a circuit diagram illustrating the pixels of a display device 1100 according to another embodiment of the present invention.

[0335] Figure 18 The pixel P of the display device 1100 shown includes an organic light-emitting diode (OLED) as a display element 710 and a pixel driving circuit PDC for driving the display element 710. The display element 710 is connected to the pixel driving circuit PDC.

[0336] The pixel drive circuit PDC includes thin-film transistors TR1, TR2, TR3, and TR4.

[0337] In pixel P, signal lines DL, EL, GL, PL, SCL, and RL are set to provide drive signals to the pixel drive circuit PDC.

[0338] and Figure 17 Compared to the pixel P, Figure 18 The pixel P further includes an emission control line EL. An emission control signal EM is provided to the emission control line EL.

[0339] In addition, with Figure 17 Compared to the pixel drive circuit PDC, Figure 18 The pixel driving circuit PDC further includes a fourth thin-film transistor TR4 as a light-emitting control transistor for controlling the light-emitting timing of the second thin-film transistor TR2.

[0340] Reference Figure 18 Assume that the gate line of the nth pixel P is GLn, and the gate line of the (n-1)th pixel P adjacent to the nth pixel P is GLn-1. The gate line GLn-1 of the (n-1)th pixel P is used as the sensing control line SCL of the nth pixel P.

[0341] The first capacitor C1 is disposed between the gate G2 of the second thin-film transistor TR2 and the display element 710. The second capacitor C2 is disposed between a terminal of the fourth thin-film transistor TR4, which is supplied with a drive voltage Vdd, and an electrode of the display element 710.

[0342] The first thin-film transistor TR1 is turned on by a scan signal SS provided to the gate line GL to transmit the data voltage Vdata provided to the data line DL to the gate G2 of the second thin-film transistor TR2.

[0343] The third thin-film transistor TR3 is connected to the reference line RL, thereby being turned on or off by the sensing control signal SCS, and sensing the characteristics of the second thin-film transistor TR2, which is the driving transistor, during the sensing period.

[0344] The fourth thin-film transistor TR4 transmits a driving voltage Vdd to the second thin-film transistor TR2 according to the light emission control signal EM, or shields the driving voltage Vdd. When the fourth thin-film transistor TR4 is turned on, current is supplied to the second thin-film transistor TR2, thereby outputting light from the display element 710.

[0345] In addition to the structure described above, the pixel driving circuit PDC according to another embodiment of the present invention can be formed in various structures. For example, the pixel driving circuit PDC may include five or more thin-film transistors.

[0346] According to the present invention, the following beneficial effects can be obtained.

[0347] The thin-film transistor according to one embodiment of the present invention has a large S-factor and excellent on-current characteristics. Therefore, when using a thin-film transistor, the grayscale rendering capability of a display device can be improved, and the current characteristics of the display device can also be improved.

[0348] It will be apparent to those skilled in the art that the disclosure described above is not limited to the embodiments and drawings described herein; various substitutions, modifications, and variations may be made in this invention without departing from the spirit or scope thereof. Therefore, the scope of this invention is defined by the appended claims, and all variations or modifications derived from the meaning, scope, and equivalent concepts of the claims are intended to fall within the scope of this invention.

Claims

1. A thin-film transistor, comprising: Active layer; as well as A gate that at least partially overlaps with a portion of the active layer. The active layer includes: Channel section; The first connecting portion that contacts one side of the channel portion; and The second connecting portion that contacts the other side of the channel portion, The channel portion includes a first region and a second region, each of the first region and the second region extending from the first connecting portion to the second connecting portion. The thin-film transistor further includes: a first conductive material layer overlapping the channel portion; and a first spacer overlapping the channel portion. The channel portion is disposed between the first conductive material layer and the gate, and also between the first spacer and the gate. The first conductive material layer is connected to the first connecting portion. The first spacer does not overlap with the first area, but the first spacer overlaps with the second area.

2. The thin-film transistor of claim 1, wherein the channel portion further comprises a third region separated from the first region, wherein the second region is interposed between the first region and the third region. The third region extends from at least the first connecting portion to the second connecting portion.

3. The thin-film transistor of claim 1, wherein the channel portion further comprises a fourth region separated from the second region, wherein the first region is interposed between the second region and the fourth region. The fourth region extends from at least the first connecting portion to the second connecting portion.

4. The thin-film transistor of claim 1, wherein the first conductive material layer overlaps with the first region.

5. The thin-film transistor of claim 1, wherein the channel portion further comprises a third region, the third region being separated from the first region and not overlapping with the first spacer.

6. The thin-film transistor of claim 1, wherein the first spacer is disposed between the channel portion and the first conductive material layer.

7. The thin-film transistor of claim 1, wherein the first spacer and the first conductive material layer are disposed on the same layer.

8. The thin-film transistor of claim 1, further comprising a second spacer, the second spacer being separated from the first spacer and overlapping the channel portion.

9. The thin-film transistor of claim 8, wherein the channel portion further comprises a fourth region overlapping with the second spacer.

10. The thin-film transistor of claim 8, wherein the first region overlaps with the gap space between the first spacer and the second spacer.

11. The thin-film transistor of claim 8, wherein the first spacer and the second spacer are disposed between the channel portion and the first conductive material layer.

12. The thin-film transistor of claim 8, wherein the first conductive material layer, the first spacer, and the second spacer are disposed on the same layer. The first conductive material layer is disposed between the first spacer and the second spacer.

13. A thin-film transistor, comprising: Active layer; as well as A gate that at least partially overlaps with a portion of the active layer. The active layer includes: Channel section; The first connecting portion that contacts one side of the channel portion; and The second connecting portion that contacts the other side of the channel portion, The thin-film transistor further includes: A first conductive material layer overlapping the channel portion, wherein the channel portion is disposed between the first conductive material layer and the gate, and the first conductive layer is connected to the first connection portion; and A second conductive material layer is separated from the first conductive material layer and overlaps with the channel portion, wherein the channel portion is disposed between the second conductive material layer and the gate, and the second conductive material layer is connected to the first connection portion. The channel portion includes a first region that overlaps with the first conductive material layer but does not overlap with the second conductive material layer, a second region that does not overlap with the first conductive material layer and the second conductive material layer, and a third region that overlaps with the second conductive material layer but does not overlap with the first conductive material layer, each of the first region, the second region and the third region extending from the first connection portion to the second connection portion.

14. The thin-film transistor of claim 13, further comprising a first spacer located between the first conductive material layer and the second conductive material layer.

15. The thin-film transistor of claim 14, wherein the first conductive material layer, the second conductive material layer, and the first spacer are disposed on the same layer.

16. The thin-film transistor of claim 13, wherein the second region overlaps with the gap space between the first conductive material layer and the second conductive material layer.

17. The thin-film transistor of claim 13, further comprising a conductive pattern separated from the active layer, the first conductive material layer being interposed between the conductive pattern and the active layer.

18. The thin-film transistor of claim 13, further comprising a conductive pattern separated from the active layer by the first conductive material layer and the second conductive material layer, wherein the first conductive material layer and the second conductive material layer are interposed between the conductive pattern and the active layer.

19. The thin-film transistor of claim 13, wherein the active layer comprises an oxide semiconductor material.

20. The thin-film transistor of claim 19, wherein the oxide semiconductor material comprises at least one of IZO (InZnO)-based, IGO (InGaO)-based, ITO (InSnO)-based, IGZO (InGaZnO)-based, IGZTO (InGaZnSnO)-based, GZTO (GaZnSnO)-based, GZO (GaZnO)-based, ITZO (InSnZnO)-based, and FIZO (FeInZnO)-based oxide semiconductor materials.

21. The thin-film transistor of claim 13, wherein the active layer comprises: First oxide semiconductor layer; as well as A second oxide semiconductor layer on top of the first oxide semiconductor layer.

22. The thin-film transistor of claim 21, wherein the active layer further comprises a third oxide semiconductor layer on the second oxide semiconductor layer.

23. A display device comprising a thin-film transistor according to claim 1 or 13.

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