Quadrant alternately switching phase interpolator and phase adjustment method
By designing a quadrant-alternating phase interpolator, and utilizing a multitasking unit, phase interpolator circuit system, and controller circuit system, the high hardware complexity of traditional phase interpolators is solved, achieving higher phase update speed and smoothness, and reducing power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2022-04-21
- Publication Date
- 2026-07-31
AI Technical Summary
Traditional phase interpolators have high hardware complexity, resulting in high power consumption and limited phase update rate. Existing quadrant-switching phase interpolators produce obvious jitter or frequency signal loss during phase switching, affecting system operation.
The quadrant-alternating phase interpolator includes first and second multiplexer circuits, a phase interpolator circuit system, and a controller circuit system. By controlling the quadrant control code and phase control bit, the surge during phase switching is reduced and the smoothness is improved.
The number of phase control bits was reduced, the hardware complexity of the controller circuit system was reduced, the phase update speed and smoothness were improved, and the power consumption and circuit area were reduced.
Smart Images
Figure CN116073800B_ABST
Abstract
Description
Technical Field
[0001] This invention application relates to phase interpolators, and more particularly to quadrant-switching phase interpolators and phase adjustment methods suitable for high-speed applications. Background Technology
[0002] Traditional phase interpolators typically have high hardware complexity. This leads to excessive hardware area and power consumption, and is more likely to generate large parasitic capacitances, limiting the phase update rate. Quadrant-switching phase interpolators have been proposed to improve these problems. However, existing quadrant-switching phase interpolators use multiple pairs of four-way multiplexers and multiple phase buffers to switch the quadrant corresponding to the phase. In existing quadrant-switching phase interpolators, when the current quadrant of the phase needs to be switched to the next quadrant, the output of each of the four pairs of multiplexers must be switched, and the weights of these phase buffers must also be adjusted. This causes significant jitter in the frequency signal output by the quadrant-switching phase interpolator, or even causes the frequency signal to disappear. This will affect the operation of other circuits in the system that receive frequency signals. Summary of the Invention
[0003] In some implementations, the quadrant-alternating phase interpolator includes a first multiplexer circuit, a second multiplexer circuit, a phase interpolator circuit system, and a controller circuit system. The first multiplexer circuit, in response to the first and third bits of the quadrant control code, outputs one of a first frequency signal and a second frequency signal as a first signal, wherein the first frequency signal and the second frequency signal are 180 degrees out of phase. The second multiplexer circuit, in response to the second and fourth bits of the quadrant control code, outputs one of a third frequency signal and a fourth frequency signal as a second signal, wherein the third frequency signal and the fourth frequency signal are 180 degrees out of phase, and the first frequency signal and the third frequency signal are 90 degrees out of phase. The phase interpolator circuit system, in response to the first signal, the second signal, and multiple phase control bits, generates an output frequency signal. The controller circuit system, outputting the quadrant control code and the multiple phase control bits, and shifting the multiple phase control bits to adjust the phase of the output frequency signal.
[0004] In some embodiments, the phase adjustment method includes the following operations: outputting a quadrant control code and a plurality of phase control bits, and shifting the plurality of phase control bits to adjust the phase of the output frequency signal; in response to the first and third bits of the quadrant control code, outputting one of a first frequency signal and a second frequency signal as a first signal, wherein the first frequency signal and the second frequency signal are 180 degrees out of phase; in response to the second and fourth bits of the quadrant control code, outputting one of a third frequency signal and a fourth frequency signal as a second signal, wherein the third frequency signal and the fourth frequency signal are 180 degrees out of phase, and the first frequency signal and the third frequency signal are 90 degrees out of phase; and generating the output frequency signal in response to the first signal, the second signal, and the plurality of phase control bits. Attached Figure Description
[0005] The features, practical operation, and effects of this invention will be described in detail below with reference to the accompanying drawings.
[0006] Figure 1 A schematic diagram of a quadrant-switching phase interpolator is shown for some embodiments of the present invention;
[0007] Figure 2 Drawing according to some embodiments of the present invention Figure 1 A schematic diagram showing the correspondence between the phase of the output frequency signal, multiple phase control bits, and multiple bits in the quadrant control code;
[0008] Figure 3A Drawing according to some embodiments of the present invention Figure 1 A schematic diagram of the controller circuit system;
[0009] Figure 3B Drawing according to some embodiments of the present invention Figure 3A Timing diagram of the middle part of the signal;
[0010] Figure 4A Drawing according to some embodiments of the present invention Figure 1 A schematic diagram of multiple multiplexer circuits in the diagram;
[0011] Figure 4B Drawing according to some embodiments of the present invention Figure 1 A schematic diagram of the phase interpolator circuit system in the image;
[0012] Figure 5 A schematic diagram of a quadrant-switching phase interpolator is provided to illustrate some embodiments of the present invention; and
[0013] Figure 6 A flowchart of a phase adjustment method is provided for some embodiments of the present invention.
[0014] Symbol Explanation
[0015] 100: Quadrant Alternating Phase Interpolator
[0016] 110, 120, 511, 512: Multiplexer circuits
[0017] 130: Phase interpolator circuit system
[0018] 132, 134: Circuit Section
[0019] 132[0]~132
[31] ,134[0]~134
[31] : Inverter circuit
[0020] 140: Controller circuit system
[0021] 310~314, 322: Logic gate circuits
[0022] 320: Periodic Adjustment Circuit
[0023] 321, 331: Flip-Flip Circuit
[0024] 330: State Prediction Circuit
[0025] 332, 351, 352, 410, 411, 420, 421: Inverter circuits
[0026] 340, 350: Shift register circuit
[0027] 500: Quadrant Alternating Phase Interpolator
[0028] 510: Synchronization Circuit
[0029] 513, 514: Latch circuits
[0030] 600: Phase Adjustment Method
[0031] CK[0]~CK[3]、CLK: Frequency signals
[0032] CKO: Output frequency signal
[0033] DN, UP: Phase adjustment signals
[0034] PH[0:3]: Quadrant control code
[0035] PH[0]': First
[0036] PH[1]: Second position
[0037] PH[2]: Third position
[0038] PH[3]: Fourth position
[0039] PH[0]'~PH[3]': Bit PS: Status signal
[0040] PT: Shift trigger signal
[0041] PU: Generates update signal
[0042] S1~S9: Signals
[0043] S610, S620, S630, S640: Operation
[0044] SC1, SC2: Switching signals
[0045] ST[0]~ST
[31] 、ST[0]'~ST
[31] '、ST[0:31]:Phase control bits
[0046] T1, T2: Energizing period Detailed Implementation
[0047] All terms used herein have their common meanings. The definitions of the above terms in commonly used dictionaries, and examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope or meaning of the invention. Similarly, the invention is not limited to the various embodiments shown in this specification.
[0048] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit” can refer to a single system formed by at least one circuit, and the term “circuit” can refer to a device consisting of at least one transistor and / or at least one active and passive component connected in a certain manner to process signals.
[0049] As used herein, the term "and / or" includes any combination of one or more of the listed related items. The terms first, second, third, etc., are used herein to describe and identify individual components. Therefore, a first component may also be referred to as a second component without departing from the spirit of the invention. For ease of understanding, similar components in the various figures will be designated with the same reference numerals.
[0050] Figure 1 A schematic diagram of a quadrant-alternating phase interpolator 100 is shown for some embodiments of the present invention. The quadrant-alternating phase interpolator 100 includes a multiplexer circuit 110, a multiplexer circuit 120, a phase interpolator circuit system 130, and a controller circuit system 140.
[0051] The multiplexer circuit 110 is used to respond to the first PH[0] (hereinafter referred to as bit PH[0]) and the third PH[2] (hereinafter referred to as bit PH[2]) of the quadrant control code PH[0:3] and output one of the frequency signals CK[0] and CK[2] as signal S1. The multiplexer circuit 120 is used to respond to the second PH[1] (hereinafter referred to as bit PH[1]) and the fourth PH[3] (hereinafter referred to as bit PH[3]) of the quadrant control code and output one of the frequency signals CK[1] and CK[3] as signal S2. In some embodiments, the frequency signals CK[0] and CK[2] are 180 degrees out of phase, the frequency signals CK[1] and CK[3] are 180 degrees out of phase, and the frequency signals CK[0] and CK[1] are 90 degrees out of phase. For example, the phase of frequency signal CK[0] is 0 degrees, the phase of frequency signal CK[1] is 90 degrees, the phase of frequency signal CK[2] is 180 degrees, and the phase of frequency signal CK[3] is 270 degrees.
[0052] Through the above configuration, signals S1 and S2 can be switched alternately to control the quadrant corresponding to the phase of the output frequency signal CKO. For example, if the phase of the output frequency signal CKO is in the first quadrant, the multiplexer circuit 110 can output the frequency signal CK[0] as signal S1, and the multiplexer circuit 120 can output the frequency signal CK[1] as signal S2. In this way, the phase of the output frequency signal CKO will be between 0 degrees and 90 degrees (corresponding to the first quadrant). If the phase of the output frequency signal CKO is in the second quadrant, the multiplexer circuit 110 can change the output frequency signal CK[2] to signal S1, and the multiplexer circuit 120 can maintain the output frequency signal CK[1] as signal S2. In this way, the phase of the output frequency signal CKO will be between 90 degrees and 180 degrees (corresponding to the second quadrant).
[0053] As described below, based on the control of the controller circuit system 140, when the phase of the output frequency signal CKO switches from the current quadrant to the next quadrant, only one of the multiplexer circuits 110 and 120 has its output (e.g., signal S1 or signal S2) switched. This reduces the surge caused by phase switching, thereby improving the smoothness of quadrant switching. The operation here will be explained by referring to... Figure 2 Please provide an explanation.
[0054] Phase interpolator circuit system 130 is used to generate an output frequency signal CKO in response to signals S1, S2, and multiple phase control bits ST[0] to ST
[31] . For example, phase interpolator circuit system 130 includes circuit section 132 and circuit section 134. The output of circuit section 132 is coupled to the output of circuit section 134 to generate the output frequency signal CKO. Circuit section 132 generates the output frequency signal CKO in response to signal S1 and multiple phase control bits ST[0] to ST
[31] . Circuit section 134 generates the output frequency signal CKO in response to signal S2 and multiple phase control bits ST[0]' to ST
[31] '. The multiple phase control bits ST[0] to ST
[31] and multiple phase control bits ST[0]' to ST
[31] ' have mutually opposite logic values. For example, if phase control bit ST[0] has a logic value of 0, phase control bit ST[0]' has a logic value of 1. Alternatively, if the phase control bit ST[0] has a logic value of 1, the phase control bit ST[0]' has a logic value of 0.
[0055] The controller circuit system 140 is used to output quadrant control code PH[0:3], multiple phase control bits ST[0]~ST
[31] , and multiple phase control bits ST[0]'~ST
[31] '. In some embodiments, the controller circuit system 140 can be used to shift multiple phase control bits ST[0]~ST
[31] (and / or multiple phase control bits ST[0]'~ST
[31] ') to adjust the phase of the output frequency signal CKO. In some embodiments, such as Figure 2 As shown, the controller circuit system 140 can sequentially switch each of the multiple phase control bits ST[0] to ST
[31] from a first logic value (e.g., logic value 0) to a second logic value (e.g., logic value 1) to adjust the phase of the output frequency signal CKO. Similarly, the controller circuit system 140 can shift multiple bits PH[0] to PH[3] in the limit control code PH[0:3] to switch the phase of the output frequency signal CKO from the current quadrant to the next quadrant.
[0056] Compared to a conventional phase interpolator that does not use quadrant switching, the quadrant-alternating phase interpolator 100 requires fewer phase control bits. For example, for 128 phases, the quadrant-alternating phase interpolator 100 can use 31 phase control bits for switching, while a conventional phase interpolator without quadrant switching requires 128 phase control bits. This reduces the hardware complexity of the controller circuitry 140, resulting in a higher phase update speed.
[0057] Figure 2 Drawing according to some embodiments of the present invention Figure 1A schematic diagram showing the correspondence between the phase of the output frequency signal CKO, multiple phase control bits ST[0]~ST
[31] , and multiple bits PH[0]~PH[3] in the quadrant control code PH[0:3].
[0058] like Figure 2 As shown, the phase of the output frequency signal CKO can be divided into four quadrants. When the quadrant control code PH[0:3] is 1100 (i.e., bits PH[0] and PH[1] are logic 1, and bits PH[2] and PH[3] are logic 0), the phase of the output frequency signal CKO falls into the first quadrant. In the first quadrant, the phase of the output frequency signal CKO can be 0 to 90 degrees. Under this condition, when each of the multiple phase control bits ST[0] to ST
[31] (labeled as ST[0:31]) is logic 0, the phase of the output frequency signal CKO is 0 degrees. When each of the multiple phase control bits ST[0] to ST
[31] is logic 1, the phase of the output frequency signal CKO is 90 degrees.
[0059] When the quadrant control code PH[0:3] is 1100, the controller circuit system 140 can sequentially switch multiple phase control bits ST[0] to ST
[31] (labeled as ST[0:31] in the figure) from multiple logic values of 0 to multiple logic values of 1, so as to adjust the phase of the output frequency signal CKO from 0 degrees to 90 degrees. For example, starting from the first phase control bit ST[0] among the multiple phase control bits ST[0] to ST
[31] , the controller circuit system 140 can sequentially update the multiple phase control bits ST[0] to ST
[31] to logic values of 1. In other words, the controller circuit system 140 can sequentially shift multiple logic values of 1 from the first phase control bit ST[0] to the last phase control bit ST
[31] (i.e., the aforementioned shift bit) until each of the multiple phase control bits ST[0] to ST
[31] has a logic value of 1. During the above switching process, the phase of the output frequency signal CKO will gradually be adjusted from 0 degrees to 90 degrees. Alternatively, the controller circuit system 140 can sequentially shift multiple logic values of 0 from the last phase control bit ST
[31] to the last phase control bit ST[0] (i.e., the aforementioned shift bits) until each of the multiple phase control bits ST[0] to ST
[31] has a logic value of 0. During the above switching process, the phase of the output frequency signal CKO will gradually adjust from 90 degrees to 0 degrees.
[0060] When the quadrant control code PH[0:3] is 0110 (i.e., bits PH[1] and PH[2] are logic 1, and bits PH[0] and PH[3] are logic 0), the phase of the output frequency signal CKO falls into the second quadrant. In the second quadrant, the phase of the output frequency signal CKO is 90 to 180 degrees. Under this condition, when each of the multiple phase control bits ST[0] to ST
[31] is logic 0, the phase of the output frequency signal CKO is 180 degrees. Similarly, the controller circuit system 140 can sequentially switch the multiple phase control bits ST[0] to ST
[31] from multiple logic values 1 to multiple logic values 0 to adjust the phase of the output frequency signal CKO from 90 degrees to 180 degrees. For example, starting from the first phase control bit ST[0] among multiple phase control bits ST[0] to ST
[31] , the controller circuit system 140 can sequentially update multiple phase control bits ST[0] to ST
[31] to the logic value 0. In other words, the controller circuit system 140 can sequentially shift multiple logic values 0 from the first phase control bit ST[0] to the last phase control bit ST
[31] (i.e., the aforementioned shift bit) until each of the multiple phase control bits ST[0] to ST
[31] has the logic value 0. During the above switching process, the phase of the output frequency signal CKO will gradually adjust from 90 degrees to 180 degrees. Alternatively, the controller circuit system 140 can sequentially shift multiple logic values 1 from the last phase control bit ST
[31] to the last phase control bit ST[0] (i.e., the aforementioned shift bit) until each of the multiple phase control bits ST[0] to ST
[31] has the logic value 1. During the switching process described above, the phase of the output frequency signal CKO will gradually adjust from 180 degrees to 90 degrees.
[0061] When the quadrant control code PH[0:3] is 0011 (i.e., bits PH[0] and PH[1] are logic 1, and bits PH[2] and PH[3] are logic 0), the phase of the output frequency signal CKO falls into the third quadrant. In the third quadrant, the phase of the output frequency signal CKO is 180 to 270 degrees. Under this condition, when each of the multiple phase control bits ST[0] to ST
[31] is logic 1, the phase of the output frequency signal CKO is 270 degrees. Based on a similar operation, the controller circuit system 140 can sequentially switch the multiple phase control bits ST[0] to ST
[31] from multiple logic values of 0 to multiple logic values of 1 to adjust the phase of the output frequency signal CKO from 180 degrees to 270 degrees. Alternatively, the controller circuit system 140 can sequentially switch multiple phase control bits ST[0] to ST
[31] from multiple logic values 1 to multiple logic values 0 to adjust the phase of the output frequency signal CKO from 270 degrees to 180 degrees.
[0062] When the quadrant control code PH[0:3] is 1001 (i.e., bits PH[0] and PH[3] are logic 1, and bits PH[1] and PH[2] are logic 0), the phase of the output frequency signal CKO falls into the fourth quadrant. In the fourth quadrant, the phase of the output frequency signal CKO is 270 to 360 degrees (i.e., 0 degrees). Under this condition, when each of the multiple phase control bits ST[0] to ST
[31] is logic 0, the phase of the output frequency signal CKO is 0 degrees. Based on a similar operation, the controller circuit system 140 can sequentially switch the multiple phase control bits ST[0] to ST
[31] from multiple logic values 1 to multiple logic values 0 to adjust the phase of the output frequency signal CKO from 270 degrees to 0 degrees. Alternatively, the controller circuit system 140 can sequentially switch multiple phase control bits ST[0] to ST
[31] from multiple logic values 0 to multiple logic values 1 to adjust the phase of the output frequency signal CKO from 0 degrees to 270 degrees.
[0063] based on Figure 2 It is understandable that the controller circuit system 140 can be used to shift bits of the quadrant control code PH[0:3] to switch the phase of the output frequency signal CKO from the current quadrant to the next quadrant. In one shift, the number of bits that change in multiple bits PH[0] to PH[3] is 2. For example, the controller circuit system 140 can right-shift multiple bits PH[0] to PH[3] to switch the quadrant control code PH[0:3] from 1100 to 0110. In this way, the phase of the output frequency signal CKO can be switched from the first quadrant to the second quadrant, where bits PH[0] and PH[2] change, while bits PH[1] and PH[3] do not change. In other words, during this switching process, Figure 1 The multiplexer circuit 110 responds to bits PH[0] and PH[2] by changing the output frequency signal CK[2] to signal S1, while the multiplexer circuit 120 responds to bits PH[1] and PH[3] by continuously outputting the frequency signal CK[1] to signal S2. In this way, only one set of multiplexer circuit outputs will be switched, which can reduce the surge generated during the switching process and improve the smoothness of quadrant switching.
[0064] Similarly, based on Figure 2It is understood that the controller circuit system 140 can be used to shift multiple phase control bits ST[0] to ST
[31] to adjust the phase of the output frequency signal CKO. In one shift, the number of bits that change in the multiple phase control bits ST[0] to ST
[31] is 1. For example, the controller circuit system 140 can adjust the multiple phase control bits ST[0] to ST
[31] from 000…000 to 100…000, where only bit ST[0] is changed. In this way, the number of circuit switching in the phase interpolator circuit system 130 can be reduced, thereby improving the smoothness and speed of phase switching. The above description of the number of bit changes in one shift is for illustrative purposes only, and the present invention is not limited thereto. The number of bit changes can be adjusted according to different actual needs.
[0065] Figure 3A Drawing according to some embodiments of the present invention Figure 1 A schematic diagram of the controller circuit system 140 is shown. The controller circuit system 140 includes multiple logic gate circuits 310-314, a period adjustment circuit 320, a state prediction circuit 330, a shift register circuit 340, and a shift register circuit 350. The multiple logic gate circuits 310-314 can be used to generate an update signal PU based on the state signal PS, the first phase control bit ST[0] and the last phase control bit ST
[31] among multiple phase control bits ST[0]-ST
[31] , the phase adjustment signal UP, and the phase adjustment signal DN. The state signal PS is used to indicate the current quadrant corresponding to the phase of the output frequency signal CKO. The phase adjustment signal UP is used to indicate that the phase of the output frequency signal CKO will move along the current quadrant. Figure 2 The counter-clockwise adjustment is used in the signal DN. The phase adjustment signal DN is used to indicate that the phase of the output frequency signal CKO will be adjusted along the counter-clockwise direction. Figure 2 The phase adjustment is clockwise. In some embodiments, the phase adjustment signal UP and the phase adjustment signal DN have opposite logic values.
[0066] Specifically, logic gate circuit 310 generates signal S3 based on the last phase control bit ST
[31] and the status signal PS. In some embodiments, logic gate circuit 310 may be a mutually exclusive OR (XOR) gate circuit. Logic gate circuit 311 generates signal S4 based on the first phase control bit ST[0] and the status signal PS. In some embodiments, logic gate circuit 311 may be an anti-mutually exclusive OR (XNOR) gate circuit. Logic gate circuit 312 generates signal S5 based on signal S3 and the phase adjustment signal UP. Logic gate circuit 313 generates signal S6 based on signal S4 and the phase adjustment signal DN. In some embodiments, each of logic gate circuit 312 and logic gate circuit 313 may be an AND gate circuit. Logic gate circuit 314 generates update signal PU based on signals S5 and S6. In some embodiments, logic gate circuit 314 may be an OR gate circuit. The types of logic gate circuits 310 to 314 described above are for illustrative purposes only, and the present invention is not limited thereto. Various logic gates capable of performing similar operations are all within the scope of this invention.
[0067] The period adjustment circuit 320 is used to generate a shift trigger signal PT based on the frequency signal CLK and the update signal PU. In some embodiments, the period adjustment circuit 320 is used to generate a shift trigger signal PT with a default period, wherein the default period is half of the active period of the phase adjustment signal UP (or phase adjustment signal DN). In this way, the state prediction circuit 330 can be triggered during the active period based on the transition edge (e.g., a rising edge) of the shift trigger signal PT to update the state signal PS. In some embodiments, the period adjustment circuit 320 includes a flip-flop circuit 321 and a logic gate circuit 322. The flip-flop circuit 321 is used to output the update signal PU as signal S7 based on the frequency signal CLK. The logic gate circuit 322 generates the shift trigger signal PT based on signal S7 and the frequency signal CLK. In some embodiments, the flip-flop circuit 321 may be a D-type flip-flop circuit, and the logic gate circuit 322 may be an AND gate circuit, but the invention is not limited thereto.
[0068] The state prediction circuit 330 updates the state signal PS according to the shift trigger signal PT. The state prediction circuit 330 can predict the quadrant switching direction of the output frequency signal CKO before the phase switches from the current quadrant to the next quadrant. Specifically, the state prediction circuit 330 includes a flip-flop circuit 331 and an inverter circuit 332. The flip-flop circuit 331 outputs the state signal PS' as the state signal PS according to the shift trigger signal PT. The inverter circuit 332 outputs the state signal PS' according to the state signal PS. In some embodiments, the flip-flop circuit 331 may be a D-type flip-flop circuit, but the invention is not limited thereto.
[0069] In this example, if the current phase corresponds to Figure 2 In the first and third quadrants, the state signal PS is a logic value of 0. If the current phase corresponds to... Figure 2 In the second and fourth quadrants, the status signal PS is at logic value 1. Since the first to fourth quadrants are multiple consecutive quadrants, when the phase of the output frequency signal CKO switches from the first quadrant (or the third quadrant) to the second or fourth quadrant, the status signal PS switches from logic value 0 to logic value 1. Similarly, when the phase of the output frequency signal CKO switches from the second quadrant (or the fourth quadrant) to the first or third quadrant, the status signal PS switches from logic value 0 to logic value 1. In other words, the inverter circuit 332 can pre-generate a status signal PS' corresponding to the next quadrant based on the current status signal PS to update the status signal PS. Equivalently, before the next quadrant switch, the controller circuit system 140 can predict the direction of the quadrant switch through the status signal PS and the inverter circuit 332.
[0070] The shift register circuit 340 is used to store the quadrant control codes PH[0:3]. In some embodiments, the shift register circuit 340 can shift bits according to at least one of the phase adjustment signal UP and the phase adjustment signal DN and the shift trigger signal PT targeting the quadrant control codes PH[0:3]. If the phase adjustment signal UP is logic 1 (i.e., the phase adjustment signal UP is logic 0), it means that the phase of the output frequency signal CKO is adjusted in the counterclockwise direction. Under this condition, the shift register circuit 340 can right-shift the multiple quadrant control bits PH[0] to PH[3] when the shift trigger signal PT has a default bit level. Alternatively, if the phase adjustment signal DN is logic 1 (i.e., the phase adjustment signal UP is logic 0), it means that the phase of the output frequency signal CKO is adjusted in the clockwise direction. Under this condition, the shift register circuit 340 can left-shift the quadrant control codes PH[0:3] when the shift trigger signal PT has a default bit level. In some embodiments, the shift register circuit 340 may also perform shift operations based on the shift trigger signal PT and the target limit control code PH[0:3] associated with at least one of the phase adjustment signals UP and DN (e.g., signals S5 and / or S6), but the present invention is not limited thereto.
[0071] The shift register circuit 350 is used to store multiple phase control bits ST[0] to ST
[31] . In some embodiments, the shift register circuit 350 can shift multiple phase control bits ST[0] to ST
[31] according to at least one of the phase adjustment signal UP and the phase adjustment signal DN, the status signal PS, and the frequency signal CLK, so as to adjust the multiple phase control bits ST[0] to ST
[31] . In this example, each of the multiple phase control bits ST[0] to ST
[31] is defaulted to a logic value of 0. If the phase adjustment signal UP is a logic value of 1 and the status signal PS is a logic value of 1, it means that the phase of the output frequency signal CKO is adjusted in the counterclockwise direction and the current quadrant is the first quadrant or the third quadrant. Under this condition, the shift register circuit 350 is triggered by the frequency signal CLK and sequentially shifts multiple logic values of 1 from the first phase control bit ST[0] to the last phase control bit ST
[31] through the internal inverter circuit 351, so as to gradually adjust the multiple phase control bits ST[0] to ST
[31] . Alternatively, if the phase adjustment signal UP is logic 0 and the status signal PS is logic 1, it means that the phase of the output frequency signal CKO is adjusted in a clockwise direction and the current quadrant is the first or third quadrant. Under this condition, the shift register circuit 350 is triggered by the frequency signal CLK and sequentially shifts multiple logic 0 values from the last phase control bit ST
[31] to the first phase control bit ST[0] through the internal inverter circuit 352, so as to gradually adjust multiple phase control bits ST[0] to ST
[31] . The operation of other quadrants can be deduced in the same way, so it will not be repeated here.
[0072] Figure 3B Drawing according to some embodiments of the present invention Figure 3AThe timing diagram of the middle part of the signal. In this example, the phase of the output frequency signal CKO is in the first quadrant, so the quadrant control code PH[0:3] is 1100, and the status signal PS (not shown) is logic 0. During the enable period T1 of the phase adjustment signal UP, the last phase control bit ST
[31] has a logic value of 1. Under this condition, it means that the phase of the output frequency signal CKO is 90 degrees and is about to enter the second quadrant. In response to the status signal PS and the last phase control bit ST
[31] , the logic gate circuit 310 outputs a signal S3 with a logic value of 1 (corresponding to the high level), and causes the logic gate circuit 314 to output an update signal PU with a high level. During the enable period T2 of the phase adjustment signal UP, the period adjustment circuit 320 outputs a shift trigger signal PT with a high level in response to the frequency signal CLK with a high level. In response to this shift trigger signal PT, the shift register circuit 340 can shift bits of the limit control code PH[0:3] to adjust the phase of the output frequency signal CKO to the second quadrant. Additionally, in response to this shift trigger signal PT, the state prediction circuit 330 can update the state signal PS (not shown) to a logic value of 1.
[0073] Figure 4A Drawing according to some embodiments of the present invention Figure 1 A schematic diagram of multiplexer circuits 110 and 120 is shown. In some embodiments, each of multiplexer circuits 110, 120, and phase interpolator circuit system 130 may be an inverter-based digital circuit. Compared to current-mode logic circuits, this arrangement reduces the number of circuits, area, and internal parasitic capacitance, and avoids the impact of DC common-mode signal jitter on the output frequency signal CKO. This reduces the power consumption and circuit area of the quadrant-alternating phase interpolator 100, while simultaneously increasing the bandwidth of multiplexer circuits 110 and 120.
[0074] In detail, the multiplexer circuit 110 includes an inverter circuit 410 and an inverter circuit 411. The outputs of each of the inverter circuits 410 and 411 are coupled to each other to output signal S1. The inverter circuit 410 is enabled according to bit PH[0] and bit PH[0]' to output signal S1 according to frequency signal CK[0]. The inverter circuit 411 is enabled according to bit PH[2] and bit PH[2]' to output signal S1 according to frequency signal CK[2]. Similarly, the multiplexer circuit 120 includes an inverter circuit 420 and an inverter circuit 421. The outputs of each of the inverter circuits 420 and 421 are coupled to each other to output signal S2. The inverter circuit 420 is enabled according to bit PH[1] and bit PH[1]' to output signal S2 according to frequency signal CK[1]. The inverter circuit 421 is activated based on bit PH[3] and bit PH[3]' to output signal S3 based on frequency signal CK[3]. The corresponding bits of multiple bits PH[0] to PH[3] have opposite logic values to the corresponding bits of multiple bits PH[0]' to PH[3]'. For example, when bit PH[0] is logic 1, bit PH[0]' is logic 0; and vice versa.
[0075] Figure 4B Drawing according to some embodiments of the present invention Figure 1 A schematic diagram of the phase interpolator circuit system 130 is shown. Circuit section 132 includes multiple inverter circuits 132[0] to 132
[31] , and circuit section 134 includes multiple inverter circuits 134[0] to 134
[31] . The outputs of each of the multiple inverter circuits 132[0] to 132
[31] and 134[0] to 134
[31] are coupled to each other to generate an output frequency signal CKO.
[0076] Each of the multiple inverter circuits 132[0] to 132
[31] is enabled according to the corresponding one of the multiple phase control bits ST[0] to ST
[31] and the corresponding one of the multiple phase control bits ST[0]' to ST
[31] ' to generate an output frequency signal CKO according to signal S1. For example, inverter circuit 132[0] is enabled according to phase control bit ST[0] and phase control bit ST[0]' to generate an output frequency signal CKO. Similarly, inverter circuit 132
[31] is enabled according to phase control bit ST
[31] and phase control bit ST
[31] ' to generate an output frequency signal CKO.
[0077] Similarly, each of the multiple inverter circuits 134[0] to 134
[31] is enabled according to the corresponding one of the multiple phase control bits ST[0]' to ST
[31] ' and the corresponding one of the multiple phase control bits ST[0] to ST
[31] to generate an output frequency signal CKO according to signal S2. For example, inverter circuit 134[0] is enabled according to phase control bit ST[0]' and phase control bit ST[0] to generate an output frequency signal CKO. Similarly, inverter circuit 134
[31] is enabled according to phase control bit ST
[31] ' and phase control bit ST
[31] to generate an output frequency signal CKO.
[0078] Figure 5 A schematic diagram of a quadrant-alternating phase interpolator 500 is shown for some embodiments of the present invention. Compared to Figure 1 In this example, the quadrant alternating phase interpolator 500 further includes a synchronization circuit 510. The synchronization circuit 510 can be used to output bits PH[0] and PH[2] to the multiplexer circuit 110 according to the first synchronization signal S8, and to output bits PH[1] and PH[3] to the multiplexer circuit 120 according to the second synchronization signal S9. The first synchronization signal S8 or the second synchronization signal S9 is a signal that has a phase leading the current phase of the output frequency signal CKO by 90 degrees before the phase of the output frequency signal CKO is switched.
[0079] The synchronization circuit 510 can synchronize the operation of multiple frequency signals CK[0] to CK[3] with the controller circuit system 140. In this way, it can be avoided that signal S1 (or signal S2) will have incorrect waveform changes under certain conditions (for example, when the quadrant switching time point is close to the rising edge of the output frequency signal CKO).
[0080] In detail, the synchronization circuit 510 includes a multiplexer circuit 511, a multiplexer circuit 512, a latch circuit 513, and a latch circuit 514. The multiplexer circuit 511 is used to output one of the frequency signals CK[0] and CK[2] as the first synchronization signal S8 according to the switching signal SC1. If the phase of the output frequency signal CK is in the first quadrant or the second quadrant, the switching signal SC1 has a logic value of 0. If the phase of the output frequency signal CK is in the third quadrant or the fourth quadrant, the switching signal SC1 has a logic value of 1. The multiplexer circuit 512 is used to output one of the frequency signals CK[1] and CK[3] as the second synchronization signal S9 according to the switching signal SC2. If the phase of the output frequency signal CK is in the second quadrant or the third quadrant, the switching signal SC2 has a logic value of 0. If the phase of the output frequency signal CK is in the first quadrant or the fourth quadrant, the switching signal SC2 has a logic value of 1.
[0081] Latch circuit 513 is used to output bits PH[0] and PH[2] to multiplexer circuit 110 according to the first synchronization signal S8, wherein the first synchronization signal S8 is input to the inverting input terminal of latch circuit 513. Latch circuit 514 is used to output bits PH[1] and PH[3] to multiplexer circuit 120 according to the second synchronization signal S9, wherein the second synchronization signal S9 is input to the inverting input terminal of latch circuit 514.
[0082] For example, if a switch is to be made from the first quadrant to the second quadrant, it means that the current phase of the output frequency signal CKO is 90 degrees. Under this condition, the multiplexer circuit 511 selects the output frequency signal CK[0] (i.e., a signal with a phase lead of 90 degrees over the output frequency signal CKO) as the first synchronization signal S8, and transmits the first synchronization signal S8 to the inverting input of the latch circuit 513. Thus, the multiplexer circuit 110 can switch in response to bits PH[0] and PH[2] at a specific time point, and this specific time point is different from the time point that is 90 degrees ahead or behind the current phase of the output frequency signal CKO. In other words, in this example, the multiplexer circuit 110 will not switch at the time point that corresponds to the current phase difference (lead or lag) of the output frequency signal CKO.
[0083] Alternatively, if a switch from the second quadrant to the third quadrant is desired, it represents that the current phase of the output frequency signal CKO is 180 degrees. Under this condition, the multiplexer circuit 512 selects the output frequency signal CK[1] (i.e., a signal with a phase lead of 90 degrees over the output frequency signal CKO) as the second synchronization signal S9 and transmits the second synchronization signal S9 to the inverting input of the latch circuit 514. Thus, the multiplexer circuit 120 can switch in response to bits PH[1] and PH[3] at a specific time point, and this specific time point is different from the time point that is 90 degrees ahead or behind the current phase of the output frequency signal CKO. In other words, in this example, the multiplexer circuit 120 will not switch at the time point that corresponds to the current phase difference (lead or lag) of the output frequency signal CKO.
[0084] The above-described configuration of the synchronization circuit 510 is for illustrative purposes only, and the present invention is not limited thereto. Any synchronization circuit 510 used to improve the accuracy of signal waveforms is within the scope of this invention.
[0085] Figure 6A flowchart of a phase adjustment method 600 according to some embodiments of the present invention is provided. In operation S610, a quadrant control code and multiple phase control bits are output, and the multiple phase control bits are shifted to adjust the phase of the output frequency signal. In operation S620, in response to the first and third bits of the quadrant control code, one of a first frequency signal and a second frequency signal is output as a first signal, wherein the phase difference between the first frequency signal and the second frequency signal is 180 degrees. In operation S630, in response to the second and fourth bits of the quadrant control code, one of a third frequency signal and a fourth frequency signal is output as a second signal, wherein the phase difference between the third frequency signal and the fourth frequency signal is 180 degrees, and the phase difference between the first frequency signal and the third frequency signal is 90 degrees. In operation S640, the output frequency signal is generated in response to the first signal, the second signal, and the multiple phase control bits.
[0086] The descriptions of the above operations can be found in the foregoing embodiments, and therefore will not be repeated. The operations of the phase adjustment method 600 described above are merely examples and are not limited to being performed in the order shown in these examples. Without departing from the operation mode and scope of the embodiments of the present invention, the various operations in the phase adjustment method 600 may be appropriately added, replaced, omitted, or performed in a different order (for example, they may be performed simultaneously or partially simultaneously).
[0087] In summary, the quadrant-alternating phase interpolator and phase adjustment method in some embodiments of the present invention can utilize two sets of 2-to-1 multiplexer circuits to alternately switch quadrants and adjust the phase by shifting bits. Furthermore, the multiplexer circuit and interpolation circuit can be implemented using inverter-based digital circuitry. This effectively reduces circuit area and power consumption while increasing the bandwidth of the multiplexer circuit. Consequently, the quadrant-alternating phase interpolator is more suitable for high-speed applications.
[0088] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope defined in the claims of this application.
Claims
1. A quadrant-alternating phase interpolator, characterized by, The quadrant-alternating phase interpolator includes: The first multiplexer circuit is used to output one of a first frequency signal and a second frequency signal as the first signal, responding to the first and third bits of the quadrant control code, wherein the first frequency signal and the second frequency signal are 180 degrees out of phase. The second multiplexer circuit is used to output one of the third frequency signal and the fourth frequency signal as the second signal, in response to the second and fourth bits in the quadrant control code, wherein the third frequency signal and the fourth frequency signal are 180 degrees out of phase, and the first frequency signal and the third frequency signal are 90 degrees out of phase. A phase interpolator circuit system for generating an output frequency signal in response to the first signal, the second signal, and multiple phase control bits; as well as The controller circuit system is used to output the quadrant control code and the plurality of phase control bits, and to shift the plurality of phase control bits to adjust the phase of the output frequency signal.
2. The quadrant alternating phase interpolator as described in claim 1, characterized in that, The first signal and the second signal are switched alternately to control the quadrant corresponding to the phase.
3. The quadrant alternating phase interpolator as described in claim 1, characterized in that, When the phase switches from the first quadrant to the second quadrant, the first multiplexer circuit responds to the first bit and the third bit, and outputs the other of the first frequency signal and the second frequency signal as the first signal; and the second multiplexer circuit responds to the second bit and the fourth bit, and maintains the output of the other of the third frequency signal and the fourth frequency signal as the second signal.
4. The quadrant alternating phase interpolator as described in claim 1, characterized in that, Before the phase switches from the first quadrant to the second quadrant, the controller circuitry is further used to predict the quadrant switching direction of the phase.
5. The quadrant alternating phase interpolator as described in claim 1, characterized in that, The controller circuit system includes: Multiple logic gate circuits are used to generate an update signal based on a first state signal, a first phase control bit and a last phase control bit among the multiple phase control bits, a first phase adjustment signal and a second phase adjustment signal; A periodic adjustment circuit is used to generate a shift trigger signal based on the frequency signal and the update signal; A state prediction circuit is used to update the first state signal according to the shift trigger signal; The first shift register circuit is used to store the quadrant control code and to shift the quadrant control code by bits according to at least one of the first phase adjustment signal and the second phase adjustment signal and the shift trigger signal. as well as The second shift register circuit is used to store the plurality of phase control bits and to shift the plurality of phase control bits according to at least one of the first phase adjustment signal and the second phase adjustment signal, the first state signal and the frequency signal.
6. The quadrant alternating phase interpolator as described in claim 1, characterized in that, The controller circuit system is used to sequentially switch each of the plurality of phase control bits from a first logic value to a second logic value to adjust the phase.
7. The quadrant alternating phase interpolator as described in claim 1, characterized in that, The number of bit changes in the multiple phase control bits in the displacement bit is 1.
8. The quadrant-alternating phase interpolator as described in claim 1, characterized in that, The controller circuit system is used to shift the quadrant control code by bits to switch the phase from the first quadrant to the second quadrant.
9. The quadrant-alternating phase interpolator as described in claim 1, characterized in that, The quadrant-alternating phase interpolator further includes: A synchronization circuit is used to output the first bit and the third bit to the first multiplexer circuit according to a first synchronization signal, and to output the second bit and the fourth bit to the second multiplexer circuit according to a second synchronization signal. The first synchronization signal or the second synchronization signal is a signal whose phase leads the current phase of the output frequency signal by 90 degrees.
10. A phase adjustment method, characterized in that, The phase adjustment method includes: Output quadrant control code and multiple phase control bits, and shift the multiple phase control bits to adjust the phase of the output frequency signal; In response to the first and third bits of the quadrant control code, one of the first frequency signal and the second frequency signal is output as the first signal, wherein the first frequency signal and the second frequency signal are 180 degrees out of phase. In response to the second and fourth bits of the quadrant control code, one of the third and fourth frequency signals is output as the second signal, wherein the third frequency signal and the fourth frequency signal are 180 degrees out of phase, and the first frequency signal and the third frequency signal are 90 degrees out of phase; and The output frequency signal is generated in response to the first signal, the second signal, and the plurality of phase control bits.