Power-on reset circuit, undervoltage lockout circuit, and undervoltage lockout method

Abstract

The application discloses a power-on reset circuit, an under-voltage lock circuit and an under-voltage lock method. The power-on reset circuit comprises a first voltage dividing unit and a first MOS tube. The first voltage dividing unit is electrically connected between a power supply voltage V DD and a ground potential, and outputs a voltage dividing voltage V A at a first voltage dividing node. The gate of the first MOS tube is connected with the first voltage dividing node, the source is connected with the power supply voltage V DD , and the drain is indirectly connected with the ground potential. The output end of the power-on reset circuit is directly or indirectly connected with the drain of the first MOS tube to output a power-on reset signal. The first voltage dividing unit is arranged to adjust the flip point voltage of the power-on reset circuit, so that the problem that the under-voltage lock circuit is flipped for multiple times due to the too low flip voltage of the power-on reset circuit at high temperature FF corner when the flip voltage of the under-voltage lock circuit is low can be avoided.

Description

Technical Field

[0001] This invention belongs to the field of power supply circuit technology, and in particular relates to a power-on reset circuit, an undervoltage lockout circuit, and an undervoltage lockout method. Background Technology

[0002] In some applications, it is required that the output monotonically change with the power supply at different power-up speeds. The output is usually controlled by an undervoltage lockout (UVLO) circuit, which requires that the UVLO be pulled high only once at different power-up speeds.

[0003] In UVLO circuits, conventional power-on reset (POR) circuits typically use an NMOS transistor connected to an input resistor to control the power supply voltage V. DD The voltage is divided, and then the signal is inverted by a set of inverters to output a power-on reset signal to the comparator in the UVLO circuit. After the POR circuit is pulled high, the comparator starts to work normally, and the reference voltage V is input to the positive input terminal of the comparator. REF The inverting input terminal receives the bandgap reference voltage V generated by the bandgap reference circuit. BG When the reference voltage V REF Higher than the bandgap reference voltage V BG When the reference voltage V is high, the UVLO circuit outputs a high level; when the reference voltage V is high, the UVLO circuit outputs a high level. REF Below the bandgap reference voltage V BG When this occurs, the UVLO circuit outputs a low level.

[0004] However, the design of the POR circuit is somewhat limited when the UVLO circuit switching voltage is low. The POR circuit is typically related to the threshold voltage V of the MOSFET. TH Related, V TH The switching voltage of the POR circuit is significantly affected by temperature and corner. It has a high switching point at the low-temperature SS corner and a relatively low switching point at the high-temperature FF corner. Specifically, at the low-temperature SS corner, the switching voltage of the POR circuit cannot exceed the switching voltage of the UVLO circuit, while the switching voltage of a conventional POR circuit is approximately 2V. TH For scenarios where the UVLO circuit has a low switching voltage, significant challenges arise at low-temperature SS corners, necessitating further reductions in the switching voltage of the POR circuit. On the other hand, such as... Figure 1a , 1b As shown, at the high temperature FF corner, the UVLO circuit has multiple switching problems due to the low switching voltage of the POR circuit.

[0005] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a power-on reset circuit, an undervoltage lockout circuit, and an undervoltage lockout method, which solve the problem that the undervoltage lockout circuit has multiple flips due to the low flip voltage of the power-on reset circuit at high temperature FF corner when the undervoltage lockout circuit flips low.

[0007] To achieve the above objectives, embodiments of the present invention provide a power-on reset circuit, the power-on reset circuit comprising:

[0008] The first voltage divider unit is electrically connected to the power supply voltage V. DD Between the voltage and ground potential, the first voltage divider unit outputs a divided voltage V at the first voltage divider node. A ;

[0009] The first MOSFET has its gate connected to the first voltage divider node, and its source connected to the power supply voltage V. DD The drain of the first MOS transistor is connected to the ground potential, and the output terminal of the power-on reset circuit is directly or indirectly connected to the drain of the first MOS transistor to output a power-on reset signal.

[0010] Wherein, the flip point voltage V of the power-on reset signal L2H For V L2H =K*V TH K > 1, V TH This is the threshold voltage of the first MOSFET.

[0011] In one or more embodiments of the present invention, the first voltage divider unit includes components electrically connected to the power supply voltage V. DD The first resistor between the first voltage divider node and the first voltage divider node, and the second resistor electrically connected between the first voltage divider node and the ground potential.

[0012] In one or more embodiments of the present invention, the flip-point voltage V of the power-on reset signal L2H <2V GS V GS This is the gate-source voltage of the first MOSFET.

[0013] In one or more embodiments of the present invention, the first MOS transistor is a PMOS transistor.

[0014] In one or more embodiments of the present invention, a third resistor or current source is connected between the drain of the first MOS transistor and ground potential.

[0015] In one or more embodiments of the present invention, 2N inverters are connected in series between the output terminal of the power-on reset circuit and the drain of the first MOS transistor, where N is a positive integer.

[0016] In one or more embodiments of the present invention, the inverter includes a first inverter and a second inverter. The first inverter includes a third MOS transistor and a fourth MOS transistor, wherein the third MOS transistor is a PMOS transistor and the fourth MOS transistor is an NMOS transistor. The gates of the third MOS transistor and the fourth MOS transistor are connected and then connected to the drain of the first MOS transistor. The drains of the third MOS transistor and the fourth MOS transistor are connected. The source of the third MOS transistor is connected to the power supply voltage V. DD The source of the fourth MOSFET is connected to ground potential;

[0017] The second inverter includes a fifth MOSFET and a sixth MOSFET, wherein the fifth MOSFET is a PMOS transistor and the sixth MOSFET is an NMOS transistor. The gates of the fifth and sixth MOSFETs are connected and then connected to the drains of the third and fourth MOSFETs. The drains of the fifth and sixth MOSFETs are connected and then connected to the output of the power-on reset circuit. The source of the fifth MOSFET is connected to the power supply voltage V. DD The source of the sixth MOSFET is connected to ground.

[0018] In another aspect of the invention, an undervoltage lockout circuit is provided, the undervoltage lockout circuit comprising:

[0019] The power-on reset circuit described above is used to provide a power-on reset signal;

[0020] A reference voltage generation circuit is used to generate a reference voltage V. REF ;

[0021] A bandgap reference circuit is used to generate a bandgap reference voltage V. BG ;

[0022] The comparator is electrically connected between the power-on reset circuit and ground potential. Its first input terminal is connected to the reference voltage generation circuit, its second input terminal is connected to the bandgap reference circuit, and its output terminal is used to output an undervoltage lockout signal.

[0023] In one or more embodiments of the present invention, the bandgap reference circuit includes:

[0024] A bipolar transistor unit, comprising a first bipolar transistor and a second bipolar transistor;

[0025] The matching resistor unit includes a first matching resistor connected to a first bipolar transistor, a second matching resistor connected to a second bipolar transistor, and a third matching resistor connected to the second matching resistor;

[0026] An operational amplifier has a first input terminal and a second input terminal, wherein the first input terminal is connected between a first matching resistor and a first bipolar transistor, and the second input terminal is connected between a second matching resistor and a third matching resistor;

[0027] The second MOSFET is a PMOS transistor, whose gate is connected to the output terminal of the operational amplifier, and whose source is connected to the power supply voltage V. DD The drain of the second MOSFET is connected to the first matching resistor and the second matching resistor, and the drain of the second MOSFET generates a bandgap reference voltage V. BG .

[0028] In one or more embodiments of the present invention, the reference voltage generating circuit includes a second voltage divider unit, the second voltage divider unit being electrically connected to the power supply voltage V. DD The second voltage divider unit outputs a reference voltage V at the second voltage divider node, consisting of a fourth resistor between the second voltage divider node and the second voltage divider node, and a fifth resistor electrically connected between the second voltage divider node and ground potential. REF .

[0029] In one or more embodiments of the present invention, the undervoltage lockout circuit further includes a seventh MOS transistor and an inverter INV. The seventh MOS transistor is an NMOS transistor. The input terminal of the inverter INV is connected to the output terminal of the power-on reset circuit. The output terminal of the inverter is connected to the gate of the seventh MOS transistor. The source of the seventh MOS transistor is connected to ground potential, and the drain is connected to the output terminal of the reference voltage generation circuit.

[0030] In another aspect of the invention, an undervoltage lockout method is also provided, the method comprising:

[0031] During power-on, the power supply voltage V DD Gradually increase, reference voltage V REF With power supply voltage V DD As the bandgap reference voltage V gradually increases, BG With power supply voltage V DD After gradually increasing, it remains stable at the power supply voltage V. DD When the first voltage V1 and the second voltage V2 are used, the reference voltage V REF With bandgap reference voltage V BG equal;

[0032] When the power supply voltage V DD The flip-point voltage V of the power-on reset signal L2HWhen the power-on reset signal flips, the voltage V at the flip point of the power-on reset signal... L2H Satisfying V1 < V L2H <V2.

[0033] Compared with the prior art, the power-on reset circuit, undervoltage lockout circuit, and undervoltage lockout method according to embodiments of the present invention, by setting a first voltage divider unit, can, on the one hand, adjust the switching point voltage of the power-on reset circuit, avoiding the problem of multiple switching of the undervoltage lockout circuit due to excessively low switching voltage of the power-on reset circuit at high temperature FF corner when the switching voltage of the undervoltage lockout circuit is low; on the other hand, it can ensure that the switching point voltage of the power-on reset circuit meets V L2H <2V GS This allows for a further reduction in the switching voltage of the power-on reset circuit under low-temperature SS corner conditions, thus meeting the application scenarios where the switching voltage of the undervoltage lockout circuit is low. Attached Figure Description

[0034] Figure 1a The reference voltage V in the existing technology REF Bandgap reference voltage V BG and the power-on reset signal varies with the power supply voltage V DD A graph showing the changes;

[0035] Figure 1b This is a schematic diagram of the signal flipping in the undervoltage lockout circuit at the high-temperature FF corner in the prior art.

[0036] Figure 2 This is a circuit diagram of the power-on reset circuit in Embodiment 1 of the present invention.

[0037] Figure 3 This is a circuit diagram of the undervoltage lockout circuit in Embodiment 2 of the present invention.

[0038] Figure 4 This is a circuit diagram of the bandgap reference circuit in Embodiment 2 of the present invention.

[0039] Figure 5 This is a circuit diagram of the undervoltage lockout circuit in Embodiment 3 of the present invention.

[0040] Figure 6a The reference voltage V in Embodiment 2 of the present invention REF Bandgap reference voltage V BG and the power-on reset signal varies with the power supply voltage V DD A graph showing the changes;

[0041] Figure 6b This is a schematic diagram of the undervoltage lockout circuit signal flipping at the high temperature FF corner in Embodiment 2 of the present invention. Detailed Implementation

[0042] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0043] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0044] It should be understood that, in the following description, "circuit" may include single or combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by the programmable circuit. When an element or circuit is said to be "connected to" or "connected to" another element, or when an element / circuit is said to be "connected" between two nodes, it may be directly coupled to or connected to the other element, or there may be intermediate elements; the connection between elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.

[0045] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0046] Example 1

[0047] like Figure 2 As shown, this embodiment discloses a power-on reset circuit that can be applied to any other undervoltage lockout (UVLO) circuit using a PMOS transistor bandgap reference circuit.

[0048] Specifically, the power-on reset circuit in this embodiment includes:

[0049] The first voltage divider unit is electrically connected to the power supply voltage V. DD Between the voltage and ground potential, the first voltage divider unit outputs a divided voltage V at the first voltage divider node A. A ;

[0050] The first MOSFET M1 has its gate connected to the first voltage divider node A, and its source connected to the power supply voltage V. DD The drain of the first MOSFET M1 is connected to the ground potential, and the output terminal of the power-on reset circuit is directly or indirectly connected to the drain of the first MOSFET M1 to output the power-on reset signal POR.

[0051] In this embodiment, the first voltage divider unit includes components electrically connected to the power supply voltage V. DD The first resistor R1 connected to the first voltage divider node A, and the second resistor R2 electrically connected between the first voltage divider node A and ground potential, and the voltage divider voltage V on the first voltage divider node A.A = V DD * r2 / (r1 + r2), where r1 and r2 are the resistances of the first resistor R1 and the second resistor R2 respectively.

[0052] The first MOS transistor M1 in this embodiment is a PMOS transistor. When the gate-source voltage V of the first MOS transistor M1 GS is greater than its threshold voltage V TH the power-on reset circuit pulls up. The flip point voltage of the power-on reset circuit is V L2H = K * V TH , where K > 1 and K = (r1 + r2) / r1.

[0053] By setting the first resistor R1 and the second resistor R2, on the one hand, the flip point voltage of the power-on reset circuit can be adjusted to avoid the problem that when the flip voltage of the under-voltage lockout circuit is relatively low, the flip voltage of the power-on reset circuit is too low at high temperature FF corner, resulting in multiple flips of the under-voltage lockout circuit. On the other hand, the flip point voltage of the power-on reset circuit can be made to satisfy V L2H < 2V GS , realizing further reducing the flip voltage of the power-on reset circuit in the low temperature SS corner state to meet the application scenario when the flip voltage of the under-voltage lockout circuit is relatively low.

[0054] Preferably, a third resistor R3 is connected between the drain of the first MOS transistor M1 and the ground potential in this embodiment. The third resistor R3 functions as a current limiting resistor. In some embodiments, the third resistor R3 can also be replaced by a current source.

[0055] Further, 2N groups of inverters are connected in series between the output terminal of the power-on reset circuit and the drain of the first MOS transistor M1, where N is a positive integer.

[0056] Refer Figure 2 As shown, the inverter in this embodiment includes a first inverter and a second inverter, where:

[0057] The first inverter includes a third MOS transistor M3 and a fourth MOS transistor M4. The third MOS transistor M3 is a PMOS transistor and the fourth MOS transistor M4 is an NMOS transistor. The gates of the third MOS transistor M3 and the fourth MOS transistor M4 are connected and then connected to the drain of the first MOS transistor M1. The drains of the third MOS transistor M3 and the fourth MOS transistor M4 are connected. The source of the third MOS transistor M3 is connected to the power supply voltage V DD and the source of the fourth MOS transistor M4 is connected to the ground potential;

[0058] The second inverter includes a fifth MOSFET M5 and a sixth MOSFET M6, where the fifth MOSFET M5 is a PMOS transistor and the sixth MOSFET M6 is an NMOS transistor. The gates of the fifth MOSFET M5 and the sixth MOSFET M6 are connected and then connected to the drains of the third MOSFET M3 and the fourth MOSFET M4. The drains of the fifth MOSFET M5 and the sixth MOSFET M6 are connected and then connected to the output of the power-on reset circuit. The source of the fifth MOSFET M5 is connected to the power supply voltage V. DD The source of the sixth MOSFET M6 is connected to ground.

[0059] Thus, by continuously setting two sets of inverters, on the one hand, the signal waveform output from the drain of the first MOS transistor M1 can be shaped to make the waveform steeper; on the other hand, it also plays a role in balancing signal delay.

[0060] It should be understood that this embodiment uses two sets of inverters as an example for illustration. In other embodiments, inverters may not be set or multiple sets (2N, N>1) of inverters may be set, which can also output a power-on reset signal.

[0061] Example 2

[0062] like Figure 3 As shown, this embodiment discloses an undervoltage lockout circuit, including:

[0063] Power-on reset circuit 100 is used to provide a power-on reset signal;

[0064] Reference voltage generation circuit 200 is used to generate reference voltage V. REF ;

[0065] Bandgap reference circuit 300 is used to generate bandgap reference voltage V. BG ;

[0066] The comparator Comp is electrically connected between the power-on reset circuit 100 and ground potential. Its first input terminal is connected to the reference voltage generation circuit 200, its second input terminal is connected to the bandgap reference circuit 300, and its output terminal is used to output an undervoltage lockout signal.

[0067] The power-on reset circuit 100 in this embodiment is exactly the same as the power-on reset circuit in Embodiment 1, and will not be described again here.

[0068] The reference voltage generating circuit 200 in this embodiment specifically includes a second voltage divider unit, which includes components electrically connected to the power supply voltage V. DD The second voltage divider unit outputs a reference voltage V at the second voltage divider node B via a fourth resistor R4 connected to the second voltage divider node B and a fifth resistor R5 electrically connected between the second voltage divider node B and ground potential. REFDuring power-on, the power supply voltage V DD Gradually increase, reference voltage V REF With power supply voltage V DD Gradually increase.

[0069] like Figure 4 As shown, the bandgap reference circuit 300 in this embodiment includes:

[0070] A bipolar transistor unit includes a first bipolar transistor Q1 and a second bipolar transistor Q2;

[0071] The matching resistor unit includes a first matching resistor R6 connected to the first bipolar transistor Q1, a second matching resistor R7 connected to the second bipolar transistor Q2, and a third matching resistor R8 connected to the second matching resistor R7.

[0072] Operational amplifier OP1 has a first input terminal and a second input terminal. The first input terminal is connected between a first matching resistor R6 and a first bipolar transistor Q1, and the second input terminal is connected between a second matching resistor R7 and a third matching resistor R8.

[0073] The second MOSFET M2 is a PMOS transistor. Its gate is connected to the output terminal of operational amplifier OP1, and its source is connected to the power supply voltage V. DD The drain of the second MOSFET M2 is connected to the first matching resistor R6 and the second matching resistor R7. The drain of the second MOSFET M2 generates a bandgap reference voltage V. BG .

[0074] When the undervoltage lockout circuit is activated, the power supply voltage V DD When the voltage is less than the threshold voltage of the second MOSFET M2, the second MOSFET M2 is turned off, and the bandgap reference voltage V... BG Pull down to 0. When the power supply voltage V DD When the voltage is gradually increased to exceed the threshold voltage of the second MOSFET M2, the bandgap reference voltage V BG Gradually increase until the bandgap reference voltage V BG Approximate power supply voltage V DD Power supply voltage V DD The bandgap reference voltage V continues to rise. BG It has reached a stable state and no longer follows the power supply voltage V. DD rise.

[0075] In this embodiment, the first MOS transistor M1 used in the power-on reset circuit 100 and the second MOS transistor M2 used in the bandgap reference circuit 300 can form a process compensation to avoid the comparator Comp of the undervoltage lockout circuit being mistakenly triggered when the flip-point voltage of the power-on reset circuit is low, thus preventing the generation of an incorrect flip-point signal.

[0076] In this embodiment, the undervoltage lockout circuit operates under the following conditions during power-on: the power supply voltage V... DD Gradually increase, reference voltage V REF With power supply voltage V DD As the bandgap reference voltage V gradually increases, BG With power supply voltage V DD It gradually increases and then stabilizes. As shown in Figure 6, at the power supply voltage V... DD When the first voltage V1 and the second voltage V2 are used, the reference voltage V REF With bandgap reference voltage V BG Equal, at this time, the flip-point voltage V of the power-on reset signal is equal. L2H Satisfying V1 < V L2H <V2, thus avoiding multiple flips of the undervoltage lockout circuit signal.

[0077] Specifically, such as Figure 6a The reference voltage V is shown. REF With bandgap reference voltage V BG The curves of the change of the power supply voltage V intersect at points C and D, respectively, and the power supply voltage V at point C is... DD Let V1 be the first voltage, and V be the power supply voltage at point D. DD This is the second voltage V2. The power-on reset signal flips between points C and D, meaning the voltage V at the flip point of the power-on reset signal is... L2H Satisfying V1 < V L2H <V2.

[0078] like Figure 6b This indicates that when the power-on reset signal flips at the voltage V... L2H Satisfying V1 < V L2H When the voltage is less than V2, the undervoltage lockout circuit signal flips, thus avoiding the problem of the undervoltage lockout circuit flipping multiple times due to the low flip voltage of the power-on reset circuit at high temperature FF corner.

[0079] Example 3

[0080] like Figure 5 As shown, the undervoltage lockout circuit in this embodiment is largely the same as the undervoltage lockout circuit in Embodiment 2, except that it also includes a seventh MOS transistor M7 and an inverter INV. The seventh MOS transistor M7 is an NMOS transistor. The input terminal of the inverter INV is connected to the output terminal of the power-on reset circuit 100. The output terminal of the inverter is connected to the gate of the seventh MOS transistor M7. The source of the seventh MOS transistor M7 is connected to ground potential, and the drain is connected to the output terminal of the reference voltage generation circuit 200.

[0081] By configuring the seventh MOSFET M7 and the inverter INV, the voltage can be adjusted before the power-on reset signal flips (V). DD <V L2HWhen the power-on reset signal POR is inverted, it drives the seventh MOSFET M7 to conduct, thereby turning on the reference voltage V generated by the reference voltage generation circuit 200. REF Pull down to ground potential.

[0082] Example 4

[0083] This embodiment discloses an undervoltage lockout method, including the following steps:

[0084] During power-on, the power supply voltage V DD Gradually increase, reference voltage V REF With power supply voltage V DD As the bandgap reference voltage V gradually increases, BG With power supply voltage V DD After gradually increasing, it remains stable at the power supply voltage V. DD When the first voltage V1 and the second voltage V2 are used, the reference voltage V REF With bandgap reference voltage V BG equal;

[0085] When the power supply voltage V DD The flip-point voltage V of the power-on reset signal L2H When the power-on reset signal flips, the voltage V at the flip point of the power-on reset signal... L2H Satisfying V1 < V L2H <V2.

[0086] Specifically, such as Figure 6a As shown, the reference voltage V REF With bandgap reference voltage V BG The curves of the change of the power supply voltage V intersect at points C and D, respectively, and the power supply voltage V at point C is... DD Let V1 be the first voltage, and V be the power supply voltage at point D. DD This is the second voltage V2. The power-on reset signal flips between points C and D, meaning the voltage V at the flip point of the power-on reset signal is... L2H Satisfying V1 < V L2H <V2.

[0087] like Figure 6b As shown, when the power-on reset signal flips at the voltage V... L2H Satisfying V1 < V L2H When the voltage is less than V2, the undervoltage lockout circuit signal flips, thus avoiding the problem of the undervoltage lockout circuit flipping multiple times due to the low flip voltage of the power-on reset circuit at high temperature FF corner.

[0088] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments of the invention, as well as various different choices and variations. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. An undervoltage lockout circuit, characterized in that, The undervoltage lockout circuit includes: The power-on reset circuit is used to provide a power-on reset signal; A reference voltage generation circuit is used to generate a reference voltage V. REF ; The bandgap reference circuit includes a second MOSFET, the source of which is connected to the power supply voltage V. DD When connected, the drain generates a bandgap reference voltage V. BG ; The comparator is electrically connected between the power-on reset circuit and ground potential. Its first input is connected to a reference voltage generation circuit, its second input is connected to a bandgap reference circuit, and its output is used to output an undervoltage lockout signal. The power-on reset circuit includes: The first voltage divider unit is electrically connected to the power supply voltage V. DD Between the voltage and ground potential, the first voltage divider unit outputs a divided voltage V at the first voltage divider node. A ; The first MOSFET has its gate connected to the first voltage divider node, and its source connected to the power supply voltage V. DD The drain of the first MOSFET is connected to the ground potential, and the output terminal of the power-on reset circuit is directly or indirectly connected to the drain of the first MOSFET to output a power-on reset signal. The first MOSFET and the second MOSFET form a process compensation. Wherein, the flip point voltage V of the power-on reset signal L2H For V L2H =K*V TH K > 1, V TH The threshold voltage of the first MOSFET is V. During power-on, the power supply voltage V... DD Gradually increase, reference voltage V REF With power supply voltage V DD As the bandgap reference voltage V gradually increases, BG With power supply voltage V DD After gradually increasing, it remains stable at the power supply voltage V. DD When the first voltage V1 and the second voltage V2 are used, the reference voltage V REF With bandgap reference voltage V BG Equal, when the power supply voltage V DD The flip-point voltage V of the power-on reset signal L2H When the power-on reset signal flips, the voltage V at the flip point of the power-on reset signal... L2H Satisfying V1 < V L2H <V2.

2. The undervoltage lockout circuit as described in claim 1, characterized in that, The bandgap reference circuit includes: A bipolar transistor unit, comprising a first bipolar transistor and a second bipolar transistor; The matching resistor unit includes a first matching resistor connected to a first bipolar transistor, a second matching resistor connected to a second bipolar transistor, and a third matching resistor connected to the second matching resistor; An operational amplifier has a first input terminal and a second input terminal, wherein the first input terminal is connected between a first matching resistor and a first bipolar transistor, and the second input terminal is connected between a second matching resistor and a third matching resistor; The second MOSFET is a PMOS transistor, whose gate is connected to the output terminal of the operational amplifier, and whose source is connected to the power supply voltage V. DD The drain of the second MOSFET is connected to the first matching resistor and the second matching resistor, and the drain of the second MOSFET generates a bandgap reference voltage V. BG .

3. The undervoltage lockout circuit as described in claim 1, characterized in that, The reference voltage generating circuit includes a second voltage divider unit, which is electrically connected to the power supply voltage V. DD The second voltage divider unit outputs a reference voltage V at the second voltage divider node, consisting of a fourth resistor between the second voltage divider node and the second voltage divider node, and a fifth resistor electrically connected between the second voltage divider node and ground potential. REF .

4. The undervoltage lockout circuit as described in claim 1, characterized in that, The undervoltage lockout circuit also includes a seventh MOS transistor and an inverter INV. The seventh MOS transistor is an NMOS transistor. The input terminal of the inverter INV is connected to the output terminal of the power-on reset circuit. The output terminal of the inverter is connected to the gate of the seventh MOS transistor. The source of the seventh MOS transistor is connected to ground potential, and the drain is connected to the output terminal of the reference voltage generation circuit.

5. The undervoltage lockout circuit as described in claim 1, characterized in that, The first voltage divider unit includes components electrically connected to the power supply voltage V. DD The first resistor between the first voltage divider node and the first voltage divider node, and the second resistor electrically connected between the first voltage divider node and the ground potential.

6. The undervoltage lockout circuit as described in claim 1, characterized in that, The flip-point voltage V of the power-on reset signal L2H <2V GS V GS This is the gate-source voltage of the first MOSFET.

7. The undervoltage lockout circuit as described in claim 1, characterized in that, The first MOS transistor is a PMOS transistor.

8. The undervoltage lockout circuit as described in claim 1, characterized in that, A third resistor or current source is connected between the drain of the first MOS transistor and ground potential.

9. The undervoltage lockout circuit as described in claim 1, characterized in that, The output terminal of the power-on reset circuit is connected in series with the drain of the first MOS transistor via 2N inverters, where N is a positive integer.

10. The undervoltage lockout circuit as described in claim 9, characterized in that, The inverter includes a first inverter and a second inverter. The first inverter includes a third MOSFET and a fourth MOSFET, wherein the third MOSFET is a PMOS transistor and the fourth MOSFET is an NMOS transistor. The gates of the third and fourth MOSFETs are connected and then connected to the drain of the first MOSFET. The drains of the third and fourth MOSFETs are connected. The source of the third MOSFET is connected to the power supply voltage V. DD The source of the fourth MOSFET is connected to ground potential; The second inverter includes a fifth MOSFET and a sixth MOSFET, wherein the fifth MOSFET is a PMOS transistor and the sixth MOSFET is an NMOS transistor. The gates of the fifth and sixth MOSFETs are connected and then connected to the drains of the third and fourth MOSFETs. The drains of the fifth and sixth MOSFETs are connected and then connected to the output of the power-on reset circuit. The source of the fifth MOSFET is connected to the power supply voltage V. DD The source of the sixth MOSFET is connected to ground.

11. An undervoltage lockout method, based on the undervoltage lockout circuit according to any one of claims 1 to 10, characterized in that, The method includes: During power-on, the power supply voltage V DD Gradually increase, reference voltage V REF With power supply voltage V DD As the bandgap reference voltage V gradually increases, BG With power supply voltage V DD After gradually increasing, it remains stable at the power supply voltage V. DD When the first voltage V1 and the second voltage V2 are used, the reference voltage V REF With bandgap reference voltage V BG equal; When the power supply voltage V DD The flip-point voltage V of the power-on reset signal L2H When the power-on reset signal flips, the voltage V at the flip point of the power-on reset signal... L2H Satisfying V1 < V L2H <V2.

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