Gapped clock再生成电路及再生成方法
By periodically counting and differentiating the gap clock signal, and adjusting the frequency using a control module and digital filters, the fast convergence and low jitter performance of the gap clock regeneration circuit are achieved, solving the problems of slow generation loop and poor jitter in the existing technology.
CN116073822BActive Publication Date: 2026-07-173PEAK INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 3PEAK INC
- Filing Date
- 2022-12-31
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
Existing gapped clock regeneration circuits have slow loop convergence speed and poor jitter performance of the locked clock signal.
Method used
The first counting module periodically counts the gap clock signal, the control module generates a control signal, the second counting module processes the count value, the first digital filter processes the difference, and the clock generation module feeds back a signal to the second counting module to achieve fast convergence and reduce jitter.
Benefits of technology
It improves the convergence speed of the clock signal frequency, and the locked clock signal has lower jitter performance and higher frequency accuracy.
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Figure CN116073822B_ABST
Abstract
本发明公开了一种Gapped clock再生成电路及再生成方法，Gapped clock再生成电路包括：第一计数模块、控制模块、第二计数模块、第一数字滤波器以及时钟生成模块。根据本发明的Gapped clock再生成电路，通过第一计数模块对缺口时钟信号进行计数而获得表征计数周期完成的指示信号；通过控制模块接收指示信号产生控制信号；通过第二计数模块基于控制信号对时钟信号进行计数获得计数值，控制模块产生计数值与第一预设值的差值；通过第一数字滤波器对差值进行处理而获得分频信号；通过时钟生成模块基于分频信号获得时钟信号，从而能够快速收敛时钟信号的频率，得到抖动性能更低以及频率精度更高的时钟信号。
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