System for testing electronic circuits comprising digital-to-analog converters and corresponding method

Abstract

Embodiments of the present disclosure relate to systems and corresponding methods for testing electronic circuits including digital-to-analog converters. A digital-to-analog converter (DAC) includes a switching network and a built-in self-test (BIST) circuit. In operation, the DAC generates an analog output signal in response to an input code of a set of input codes of the DAC. The BIST circuit applies codes of a determined subset of codes of the set of input codes in sequence to test a plurality of switches. The codes of the determined subset of codes are fewer than the codes of the set of input codes. The BIST circuit detects a switch fault of the plurality of switches based on a response of the DAC to the applied codes. In response to detecting the switch fault, the BIST generates a signal indicating a switching network fault.

Description

Technical Field

[0001] Embodiments of this disclosure relate to techniques for testing electronic circuits, and more specifically to techniques for testing integrated circuits including digital-to-analog (DAC) circuits. Background Technology

[0002] The costs associated with test time, the complexity of actual integrated circuit designs, and the resulting increase in costs have forced the exploration of new testing methods to simplify testing activities and improve efficiency.

[0003] The development of new technology nodes has led to increased design complexity (e.g., circuits with high configuration levels), higher quality requirements, and increased costs associated with test time activities.

[0004] This cost can be reduced by improving the design architecture and testing methods.

[0005] Testing costs are one of the main factors affecting the overall manufacturing cost of integrated circuits. Increased circuit configurability directly increases the number of tests required to cover all possible configurations.

[0006] Circuits including digital-to-analog converters (DACs) are affected by the problem that high configurability means testing a large number of bits and a large number of input codes.

[0007] Typically, testing the input-output characteristics of a DAC involves selecting all possible input codes and using an external automated test instrument (ATE) to read all relevant output variables (e.g., current or voltage). As the number of bits n increases, 2... n Each test has a significant impact on testing time and cost.

[0008] Furthermore, there may be dozens of DACs inside an integrated circuit, so the impact on testing costs needs to be multiplied by the number of DACs.

[0009] More specifically, a digital-to-analog converter (DAC) circuit is a circuit that converts digital codes into analog current or voltage. The input of a DAC ranges from 0 to 2. n-1 The code is given by n, where n is the number of bits as described above. The output of the DAC is represented by voltage (or current), ranging from -VFS to +VFS (or –IFS to +IFS), where VFS (or IFS) is a full-scale voltage value (or a double IFS is a full-scale current value).

[0010] Whenever the code at the DAC input changes, the output voltage changes accordingly, forming a definite relationship, which can be linear, exponential, or other similar.

[0011] Because random silicon defects during manufacturing can affect the operation of a DAC converter, it is important to examine all combinations of input code-output variables. For example, if the output does not change when the input code changes, or if the output may change in a different relationship than expected (e.g., not linear), this could be because silicon defects have affected the DAC's input-output characteristics.

[0012] Assuming that the DAC design is determined to behave in accordance with design predictions / expectations (e.g., no system design errors), only silicon defects are considered to be the cause of DAC characteristic problems.

[0013] To detect and analyze problems that may be related to silicon defects, known DAC test solutions use automated test instruments (ATE) to examine the relationship between the DAC's input codes and the DAC's output variables (e.g., output analog voltage) for all possible input combinations.

[0014] exist Figure 1 The diagram schematically illustrates a solution for test architecture 10, where 11 indicates electronic circuitry, specifically an integrated circuit, including a digital-to-analog converter (DAC) 111, which is coupled to a supply voltage VDD for power and to a reference voltage VREF. Electronic circuitry 11 includes logic modules or control circuitry 112, such as dedicated control logic, which may include, for example, a microprocessor or network of logic gates that transmits n-bit input digital codes DC at the input of DAC 111. Electronic circuitry includes an input / output interface 113, which includes an output terminal 113a at which the analog output voltage VDAC from the output of DAC 111 is provided. Input / output interface 113 also includes an input terminal 113b. Electronic circuitry 11 represents the circuit under test, while test architecture 10 also includes an automated test instrument (ATE) 12.

[0015] Such an ATE 12 includes a voltmeter 121, which is coupled to the input voltage terminal 123a of a corresponding input / output interface 123 of the ATE 12. The input / output interface 123 is coupled to the output terminal 113a of the electronic circuit 11, providing an analog output voltage VDAC thereon. Furthermore, the ATE 12 includes a digital output terminal 123b, which provides test data TD and is coupled to the input terminal 113b representing the input of the logic module 112. Therefore, the command module or circuit 122 in the ATE 12 may include a microprocessor that generates an OR mode test data TD as an input to the logic module 112, which generates a corresponding digital code DC, where n bits are used for the input in the DAC 11. The voltmeter 121 measures the corresponding analog voltage VDAC at the output.

[0016] The tests performed by ATE 12 can therefore follow this sequence:

[0017] ATE 12 communicates with integrated circuit 11 via digital interface 123 and requests that the input digital code DC be changed to logic 112;

[0018] ATE 12 reads the output variable on the dedicated pin VDAC using voltmeter 121 (or ammeter, if the DAC output is current);

[0019] ATE 12 repeats this operation 2 n Repeat once for each input code DC allowed by DAC 11;

[0020] Based on the communication frequency, the duration T of each new digital code DC communication by ATE 12 is... COMM It typically takes several microseconds (e.g., up to 10 microseconds). A change in the input code DC via the DAC 11 requires a settling time T. SETTL Typically 1µs. Each ATE 12 reading T at voltmeter 121. READ The duration is typically 1ms.

[0021] Considering the 10-bit DAC, the total test time for the DAC is... TOTAL TEST TIME The following formula can be used to calculate:

[0022]

[0023] Therefore, testing the input / output characteristics of a DAC requires extensive testing to screen out random silicon defects in the architecture. Since testing time costs correlate with IC manufacturing costs, these costs increase with circuit complexity (e.g., the number of bits in the DAC), meaning that as technology becomes increasingly complex, these testing costs will also rise.

[0024] Once a defect is detected, it is difficult to locate it inside the integrated circuit, and a costly (resource- and time-consuming) failure analysis is required to identify the root cause.

[0025] Figure 2 It shows Figure 1 An embodiment of the test architecture 10 shown.

[0026] As shown in the figure, the DAC 111 in the example electronic circuit 11 is a 3-bit (n=3) resistive DAC. It includes a ladder-shaped analog reference voltage Va, which is provided in this example by a non-inverting operational amplifier 111a. This power supply is indicated by VDD and receives a reference voltage VREF at one input. The other input receives a feedback voltage from the output via a feedback resistor R2 and is coupled to ground GND via a resistor R1, such that Va = VREF. 1+R2 / R1. The output of amplifier 111a, which provides a stepped analog reference voltage Va, is coupled to multiplexer circuit 111b, which includes the output of amplifier 111a (indicated by terminal or node N2). n 2 in series between ) and ground GND (indicated as node N1) n-1 A resistor ladder with resistors R (e.g., 7 resistors), in the example of 8 nodes, n=3, with N terminals for each i-th resistor R. i N i+1 The corresponding selection switches SW2 are coupled to voltage buffers 111c to 2n. n …The input to SW1, in this example, is that the corresponding selection switch is controlled by the corresponding code DC from binary 111 to binary 000. Therefore, whenever module 112 inputs the corresponding test data TD (with the given i-th switch SW…)… i Correspondingly, i=2 n …1) When the digital code DC transmitted under control is received, such a switch closes, connecting the input of buffer 111c to the highest (code DC=111, switch SW2) input. n For example, SW8 is closed, and then a resistor in a series of resistors is connected to the lowest (code DC=000, switch SW1 is closed, coupling the input of buffer 111c to ground). The other switches divide the output voltage by the corresponding ratio.

[0027] According to the solution described herein, a possible test sequence includes the following: after ATE 12 sends test data TD corresponding to the n-bit digital input code DC digital word, this is converted into an analog signal, such as voltage VDAC, by DAC 111. DAC 111 can be used as the output of buffer 111c, which is coupled to terminal 113a. Once the analog signal (voltage VDAC) is established, e.g., stabilized, ATE 12 reads the analog signal (voltage VDAC) using voltmeter 112. ATE 12 compares the read analog signal VDAC with the expected signal. If the difference is within the expected range (e.g., ±1 / 2 LSB), the test is successful, and new test data DC / input code DC is sent to IC DAC 111. Otherwise, if the difference exceeds the expected range, the test fails, and the test stream stops.

[0028] This architecture requires 2 3 This test, total test time DAC TOTAL TEST TIME for:

[0029]

[0030] This is a simple DAC, so the test time can increase significantly as the number of bits increases.

[0031] Figure 3 A graph showing the typical DAC step function in the presence of fault condition PF is shown. The horizontal axis is the input code DC, and the vertical axis is the DAC output voltage VDAC read at ATE 12.

[0032] For a given digital input code DC, the analog signal read by ATE is not the expected signal, therefore a fault condition PF occurs for that input code DC value.

[0033] In this situation, it is difficult to determine the cause of the problem, thus implying which component is causing the IC failure. Summary of the Invention

[0034] In one embodiment, the device includes a digital-to-analog converter (DAC) and a built-in self-test (BIST) circuit. The DAC has a switching network, and in operation, the DAC generates an analog output signal in response to input codes in its set of input codes. The BIST circuit is coupled to the DAC and, in self-test operating mode, sequentially applies codes from a subset of codes determined from the set of input codes to test multiple switches. The determined subset of codes contains fewer codes than the set of input codes. The BIST circuit detects switch failures in the multiple switches based on the DAC's response to the applied codes. In response to the detection of a switch failure, the BIST circuit generates a signal indicating a fault in the switching network.

[0035] In one embodiment, the system includes an automated test instrument (ATE), an interface, and a digital-to-analog converter (DAC) coupled to the ATE via the interface. The DAC generates an analog output signal in response to input codes in its input code set. The DAC includes a switch network with multiple switches and a built-in self-test (BIST) circuit coupled to the switch network. In the DAC's self-test operating mode, the BIST circuit sequentially applies codes from a determined subset of codes in the input code set to test the multiple switches. The determined subset of codes contains fewer codes than the input code set. The BIST circuit detects switch failures in the multiple switches based on the DAC's response to the applied codes. In response to the detection of a switch failure, the BIST circuit generates a signal indicating a fault in the switch network.

[0036] In one embodiment, the method includes using a built-in self-test (BIST) circuit of the DAC to sequentially apply codes from a determined subset of codes in the DAC's input code set to a digital-to-analog converter (DAC). The determined subset of codes has fewer codes than the DAC's input code set. Based on the DAC's response to the codes applied in the determined subset of codes, the BIST circuit detects switching faults in multiple switches of the DAC's switching network. In response to the detection of multiple switching faults, the BIST circuit generates an indication of a fault in the DAC's switching network.

[0037] In one embodiment, the content of a non-transitory computer-readable medium causes the built-in self-test (BIST) circuitry of a digital-to-analog converter (DAC) to execute a method. The method includes using the DAC's BIST circuitry to sequentially apply codes from a determined subset of codes in the DAC's input code set to the DAC. The determined subset of codes contains fewer codes than the DAC's input code set. Based on the DAC's response to the applied codes in the determined subset, the BIST circuitry detects switching faults in multiple switches of the DAC's switching network. In response to the detection of multiple switching faults, the BIST circuitry generates an indication of a fault in the DAC's switching network. Attached Figure Description

[0038] Embodiments of this disclosure will now be described with reference to the accompanying drawings, which are provided purely by way of non-limiting example, and in which:

[0039] Figures 1 to 3 As described above;

[0040] Figure 4 This is a schematic block diagram of a test system according to one embodiment;

[0041] Figure 5 This is a circuit diagram of a test system according to one embodiment during a first test phase, wherein the electronic circuitry includes a resistive converter;

[0042] Figure 6A This indicates the first test phase in a fault-free closed switch scenario, and Figure 6B This represents the first test phase in a fault-closed switch scenario according to one embodiment;

[0043] Figure 7A This indicates the second test phase in a fault-free closed switch scenario, and Figure 7B This represents the second test phase of a fault disconnect switch scenario according to one embodiment;

[0044] Figure 8 This is a circuit diagram of a test system according to one embodiment in a second test phase, wherein the electronic circuitry includes a resistive converter;

[0045] Figures 9-10 This is a circuit diagram of a test system according to an embodiment in a second test phase and a first test phase, wherein the electronic circuit includes a multi-stage resistive converter;

[0046] Figure 11 This is a circuit diagram of a test system according to an embodiment during a first test phase, wherein the electronic circuitry includes a current-directing converter;

[0047] Figure 12 This is a circuit diagram of a test system according to one embodiment in a second test phase, wherein the electronic circuitry includes a current-directing converter;

[0048] Figure 13 This is a flowchart of one embodiment of a method for operating the system described herein. Detailed Implementation

[0049] In the following description, numerous specific details are set forth to provide a thorough understanding of the embodiments. The embodiments may be practiced without one or more of these specific details, or may be implemented using other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring various aspects of the embodiments.

[0050] Throughout this specification, references to "an embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0051] The headings provided in this document are for informational purposes only and do not explain the scope or meaning of the embodiments.

[0052] The solution described here is to detect the presence of silicon defects (which can cause unexpected behavior in DAC input / output characteristics), providing a partitioning method for such detection of the basic blocks of the digital-to-analog converter. In fact, a typical digital-to-analog converter might consist of the following parts:

[0053] Circuit components (e.g., resistors, current sources, capacitors, etc.) are specifically arranged in network and circuit layouts to provide analog voltage scaling, depending on their configuration.

[0054] A multiplexing network is a network in which circuit components are configured according to the input digital code to be converted.

[0055] The proposed solution was tested on the circuit components and the multiplexing network separately, thus verifying that there are no silicon defects in the overall DAC architecture.

[0056] Therefore, the solution described herein provides a method for testing DAC converters, which includes a first test of the circuit components and a second test of the multiplexing network, which is different from the first test.

[0057] The first test of a circuit element or network of electronic components involves taking analog readings of the DAC's analog output (voltage or current). As mentioned earlier, depending on the DAC architecture, the circuit element can be a resistor, capacitor, current, etc.

[0058] The second test of the multiplexed network (which is typically a common test for all DAC architectures and includes the arrangement of switches (e.g., CMOS transistors)) includes a built-in self-test.

[0059] exist Figure 4 The diagram shows a schematic representation of an embodiment of the proposed solution, which essentially corresponds to Figure 1 The block diagram shows that, however, the system 10' used for testing includes electronic circuitry 11', where the DAC 111 is shown as including blocks 111n corresponding to circuit elements and blocks 111m corresponding to multiplexing or switching networks. The arrangement of the architecture is then compared with... Figure 1 Similarly, test data TD is provided from ATE 12, and the analog output, specifically the analog voltage VDAC, is read through voltmeter 121 of ATE 12. However, the multiplexing network 111m additionally sends a feedback signal FB to IC logic module 112, which is configured to perform a first test under the control of ATE 12 (test data TD) and a second test as a built-in self-test (BIST). The built-in self-test (BIST) is therefore fully integrated into IC logic 112 (ATE 12 does not need to provide test data as input, nor does it need to receive the DAC output during the second test). Control logic 112 may include logic gates, processors and memory, state machines, etc., and various combinations thereof. Similarly, control logic 122 may include logic gates, processors and memory, state machines, etc., and various combinations thereof.

[0060] This testing strategy is particularly suitable for production purposes, where testing time is critical to IC manufacturing costs for IC development, and the duration of the test plan may not affect manufacturing costs. Conversely, short-duration testing is required when development is completed and production begins.

[0061] The testing method described here can therefore include two phases:

[0062] In the first testing phase of a circuit element or assembly of components, logic 122 of ATE 12 assigns a digital data TD to DAC 111 for conversion into an analog signal. A measuring instrument (e.g., voltmeter 122) reads the corresponding analog-to-digital conversion signal VDAC, and the measured value is compared to an acceptable range to determine a pass / fail indicator. If the result is "pass," there is no defect on the underlying component;

[0063] The second test phase of the multiplexing network 111m, managed by electronic circuitry (specifically integrated circuit 10', particularly logic module or control circuitry 112), enables it to perform a built-in self-test. Typically, this second test phase may include logic module 112 being configured to automatically provide input codes DC to the multiplexing network 111m, corresponding to a specific configuration of switches in the multiplexing network 111b, and then wait as feedback signals FB for the multiplexing network 111m to output a digital state (which could be logic 0 or logic 1). Based on the state of the feedback signal FB, logic module 112 is configured to determine whether a fault has occurred within the multiplexing network 111m. At the end of the built-in test, logic 112 writes the test results into a register. If, in the built-in self-test sequence provided by logic 112, all output states FB for all different input codes DC (e.g., switch network configurations) are the expected states, then logic 112 considers the test "passed". Otherwise, if at least one of the states FB stored in the register does not match the expected states, then logic 112 considers the test "failed". In addition, the register status can be checked based on the register address storing the mismatch result to find out which path of the multiplexer 115m failed.

[0064] This solution allows for the measurement of all relevant test parameters within integrated circuit 11', and then, for example, comparison with expected values ​​within integrated circuit 11'. The final result of the comparison (pass / fail) is sent to automated test instrument 12' via a high-speed communication interface. Figure 4 (Not shown in the image).

[0065] Figure 5 The implementation of the solution described in the first test of the reference circuit element is shown, and the solution is similar to... Figure 2 The solution features a 3-bit resistive DAC architecture. Figure 5 The representation of basically corresponds to Figure 2 Since the first test uses the same hardware, but amplifier 111a is not shown, only the trapezoidal reference analog voltage Va at the input of the resistor step is shown, the resistor step is coupled between the trapezoidal reference analog voltage Va and ground GND.

[0066] Therefore, the first test may include:

[0067] Logic 122 sets the digital test data TD to be converted into an analog signal (in Figure 5 In the example shown, the logical value is 100).

[0068] After internal logic 112 receives data TD and provides the corresponding digital code DC, DAC 111 provides the corresponding analog signal VDAC (in the example, switch SW4 corresponding to DC code 100 is closed, other switches are open, VDAC=Va). 4 / 7);

[0069] The output analog signal VDAC is measured using an external voltmeter 121 provided by ATE 12;

[0070] The reading of external voltmeter 121 is compared with a predefined range. If the reading is within the range, the test of the basic component is considered successful. Conversely, if the reading is outside the range, the test is considered to have failed.

[0071] The number of analog readings performed by ATE 12 to conduct the initial tests on the circuit components may vary depending on the DAC architecture used. For example, in Figure 5 In the example implementation shown, there are three variables in the architecture: the ladder reference analog voltage Va, the ground voltage GND, and the resistor step ratio. Therefore, three reads can be performed to test the arrangement of the circuit elements (resistors R in this case).

[0072] Specifically regarding Figure 5 In the first test phase of the circuit, the multiplexing network 111b is used to draw signals from multiple available inputs (e.g., terminal N2). n … Select a single signal from N1, for example, voltage divided by a certain step ratio. For example, in the general i-th node N i At that point, a voltage Va is formed. i / (2) n -1). Therefore, the multiplexing network 111b typically includes multiple inputs (e.g., terminal N2). n … N1), a bit selector with n bits (which controls the connection to terminal N2). n … N1 is associated with the switch set SW2 n … The open and closed states of SW1, each switch is associated with a command to close it via the corresponding n header (in the example n=3), and a digital code DC (used to transmit the analog quantity (e.g., voltage) of the corresponding branch to a single output of the multiplexing network 111b).

[0073] For the second test phase of the switch multiplexing network, the main component tested is the switch SW2 driven by an n-bit selector. n … SW1, an n-bit selector, selects switch SW2 based on the n-bit binary value decoded from the digital code DC. n … The open and closed states of the corresponding switches in SW1.

[0074] For example, multiplexing networks like the 111b are commonly used in DAC architectures because they allow, during normal operation, multiple digital codes (DCs) driving an n-bit selector at terminal N2. n … Different input voltages at N1 are carried to the output.

[0075] Affecting switches (such as SW2) n … The most common defects of SW1 are open fault (the switch is never closed) and closed fault (the switch is always closed).

[0076] These defects may degrade DAC characteristics and deviate from expected behavior.

[0077] Therefore, the second testing phase typically includes the following steps:

[0078] The determined DAC 111 code DC is enforced, which corresponds to the required test configuration of the switch, and additionally includes test signals (e.g., signals that enable operation of circuit elements dedicated to the test (such as a current generator), such as the enable signal En below).

[0079] Logic module 112 waits for DAC 111 to stabilize in order to have a stable output;

[0080] At logic module 112, the feedback signal FB from DAC 111 is evaluated and compared with the expected result. The feedback FB can be obtained directly from the output of the DAC, or it can be obtained using a feedback network that derives the feedback signal FB from the DAC output signal.

[0081] If the feedback signal FB is correct, for example, matching the expected result of a specific code DC (logic 112) determined at the input, and if another code DC is to be executed during the test, then another configuration exists to test, change the DAC input code DC, and begin the next check. If an error exists, for example, the feedback signal FB does not match the expected result, then in this embodiment, the corresponding digital code DC and the fault can be reported to ATE 12 via a communication interface, while in other embodiments, particularly if multiple digital code DCs are sent, the corresponding feedback signal value can be stored, and the result of the multiplexing network test is evaluated and then executed on the stored value (e.g., in a register of logic 112). Then, after reporting the result related to a single DAC input code DC or storing it, also in this case, logic 112 can begin the next check or stop the test. If there is only one digital code DC and one configuration (as follows) Figure 6A If all the switches shown are turned off, the correct or incorrect results can also be reported or stored.

[0082] The second testing phase of the multiplexing network 111b ends when all combinations of the n bits of the digital code DC required for the test (e.g., BIST test) are checked or an error is detected.

[0083] Using self-test within integrated circuit 11 reduces the conversion delay between one code DC and another code, thereby shortening the test time for multiplexed networks.

[0084] exist Figure 6A The diagram schematically illustrates a closed-loop fault test under fault-free conditions, e.g., a good result. The objective of this test is to detect faults in switch SW2 of a multiplexing network. n … Defects in SW1 and dedicated logic (such as bit selectors).

[0085] Therefore, in Figure 6A In the middle, the multiplexing network consists of switch SW2 n …SW1 indicates that, for simplicity, these switches are coupled to ground (GND) at one terminal of the multiplexing network; however, in the case of a resistive DAC, they are actually coupled to ground via a voltage divider of the corresponding resistor R (or a pull-down operation of the trapezoidal resistor network shown in the variant embodiment of DAC current steering, as illustrated in the figure below). The other terminal is coupled to the input of threshold comparator 111d, and the other input is coupled to the threshold voltage VREFT. A pull-up current generator 111e is coupled between the input of threshold comparator 111d, coupled to the multiplexing network, and the supply voltage VDD, injecting current into node VS of threshold comparator 111d. The output of threshold comparator 111d is coupled to logic 112, which operates state machine 112b based on the input logic value of threshold comparator 111d.

[0086] Figure 6A The closed-loop fault test is shown under the condition of good results.

[0087] Here, the switches are forcibly turned off, and all switches are in a high-impedance state.

[0088] The implementation of testing for closure faults using a multiplexed network that executes switches may include the following steps:

[0089] The pull-up current of pull-up current generator 111e is enabled by the enable signal En provided by logic 112;

[0090] Logic module 112 forces all switches SW2 n … SW1 is in the off state;

[0091] If all switches SW2 n … If all SW1s are turned off, there is an open circuit between node VS and ground.

[0092] Given that VREFT = VDD / 2, the pull-up current of generator 111e will pull node VS up to the supply voltage VDD, and the output of comparator 111d will go high;

[0093] The test results were good because all switches were forced to the off state, and all switches SW2... n … SW1 results in a high impedance state.

[0094] All switches SW2 n … SW1 is placed in parallel, and only one test is needed to verify all switches SW2. n … Whether SW1 can be in a disconnected state to ensure good manufacturing.

[0095] The test is executed very quickly (on the order of microseconds) because it is performed internally within integrated circuit 11'. No interaction with external instruments such as ATE 12 is required.

[0096] Figure 6B The same closure fault test is shown under fault conditions, for example, when all switches SW2 n … SW1 is forced to the off state, but not all switches result in a high impedance state.

[0097] The implementation of testing for closure faults in a multiplexed network of switches may include the following steps:

[0098] The pull-up current of generator 111e is enabled by the enable signal En provided by logic 112;

[0099] Logic 112 forces all switches SW2 n … SW1 is in the off state;

[0100] Due to a defect in the multiplexer network 111b, one or more switches are in the ON state (SW1 in the example shown) even though they are forced to the OFF state. Therefore, a low impedance exists between node VS and ground GND, for example, a low impedance path.

[0101] As a result, the pull-up current generator 111e is unable to pull node VS up to a voltage greater than the reference voltage VREFT, and the output of comparator 111d remains low;

[0102] The test results were poor because the switch was forced to be off, but at least a low impedance path still exists as indicated by the output of comparator 111d remaining low.

[0103] Figure 7A The diagram schematically illustrates a disconnection fault test of a multiplexed network under fault-free conditions.

[0104] Here, the switches are forced into the ON state one by one, and all combinations should be in a low-impedance state to provide a pass or fault-free result.

[0105] The implementation of a multiplexing network for switches may include the following steps:

[0106] The pull-up current of generator 111e is enabled by the enable signal En provided by logic 112;

[0107] All switches SW2 n …SW1 is forced into the ON state iteratively by logic 112. N iterations are used, and the number of switches is N; in this embodiment, N=2. n Because a DAC multiplexer consists of a single stage of parallel switches, but in the case of multiple stages, the number of switches may be less than 2. n .

[0108] For each iteration, one switch is on, and all other switches are off. Therefore, if all switches follow the command of logic 112 in this test, a low-impedance path must exist between node VS and ground;

[0109] Therefore, the pull-up current generator 111e is unable to pull node VS up to the supply voltage VDD value, and the output of comparator 111d remains logic low;

[0110] The test results were evaluated as good, for example, passed, because when the comparator 111d was forced into the ON state on each individual switch, the output remained logic low, indicating the presence of a low impedance path.

[0111] The disconnection fault test employs N iterations, with N switches. It can be executed in a short time (each iteration is on the order of microseconds) because it runs internally within integrated circuit 11 and does not require interaction with external devices.

[0112] Figure 7B This demonstrates a disconnection fault test of a multiplexed network under fault conditions.

[0113] This figure illustrates a disconnection failure test performed under unfavorable conditions, such as failure or malfunction. Here, the switches are forced on one by one, and it is detected that not all such switch combinations output a low impedance state at node VS.

[0114] The implementation of disconnection fault testing in a multiplexed network that executes the switch may include the following steps:

[0115] The pull-up current of generator 111e is enabled by the enable signal En provided by logic 112;

[0116] All switches SW2 n … SW1 is forced into the ON state iteratively by logic 112. This process involves N iterations, with N switches in total.

[0117] For each iteration, logic 112 commands one switch to close, while commanding all other switches to open. If a switch is damaged (SW2 in the example shown), a high-impedance path exists between node VS and ground;

[0118] In this case, the pull-up current generator 111e pulls node VS up to the power supply VDD value, and the output of comparator 111d goes high (VS > the voltage at VREFT).

[0119] The test results were not good. For example, the test passed because each switch was forced to be on, but a high impedance path was found, and the output of comparator 111d was checked with a high logic value.

[0120] exist Figure 8 An embodiment of a complete test architecture for a resistive DAC is shown, indicating the circuit elements (block T1) used in the first test phase of the electronic components and the circuit elements (block T2) used in the second test phase of the switching multiplexing network.

[0121] A switch SW is provided to switch the input of the voltage divider between the analog voltage Va (block T1) for the first test phase and the ground GND for the second test phase (block T2).

[0122] Figure 5 and Figures 6A-7B The inputs of buffer 111c and comparator 111d shown are both coupled to the output of the multiplexing network, for example, to node VS.

[0123] Therefore, as Figure 8 The resistive DAC test shown includes:

[0124] The first testing phase of the electronic components involves ATE 12 transmitting a digital data to be converted. DAC 11, in which a resistive voltage divider's high-side word is coupled to an analog voltage Va, specifically selectively coupled between the analog voltage Va and the high-side word of the voltage divider grounded GND via a switch SW. See reference... Figure 5 As shown, the voltage divider converts it into an analog signal, and voltmeter 121 reads the analog VDAC. ATE 12 compares this result to a defined range (which can be predefined) to determine the pass / fail metric. This test includes the internal structure of the voltage divider and buffer 111c;

[0125] The second test phase of the switch multiplexing network involves enabling the pull-up current generator 111e (signal En) and coupling the high-side of the resistive voltage divider to ground GND; then, a closure fault test (such as...) is performed. Figure 6A and Figure 6B (As shown) is executed. Logic 112 keeps all switches in the off state. If the output of comparator 111d goes high, the test result is good, for example, the test passes; subsequently, the disconnect fault test begins. Then the disconnect fault test is executed (as shown). Figure 7A and Figure 7B(As shown). All switches are forced to the ON state one by one, while all other switches remain OFF. If the output of comparator 111d is low, the test result is good; otherwise, a fault exists. At the end of the test, logic 112 writes the result to a register, such as the resistor in logic 112.

[0126] Logic 112, as shown in the figure, includes a logic state machine 112b. This state machine operates the second test phase based on the output of comparator 111d, thereby commanding the digital front end and decoder 112a. Decoder 112a generates the digital code DC requested by state machine 112a. In the first test phase, as referenced... Figure 5 As shown, logic 112 uses decoder 112a to set the digital test data TD to be converted into an analog signal one by one in order to test the analog voltage VDAC.

[0127] exist Figure 9 The image shows an example using a DAC 111 (6-bit distributed DAC): the structure consists of two voltage dividers connected by a set of switches.

[0128] The first voltage divider, DV1, is similar to... Figure 5 The voltage divider 111b in the circuit includes, and therefore includes, a series resistor R controlled by the most significant bit (MSB), via the associated switch SW1. … SW2n-1 can access the series nodes. Switch SW1 … The resistance of SW2n-1 is negligible compared to the values ​​of other resistors in the architecture (such as R and Rsw shown below);

[0129] The second voltage divider, DV2, consists of a resistive switch SWR network with resistors RSW (starting from the output node of the DAC), a tree structure comprising multiple stages (each stage including multiple branches with resistive switches SWR), and a negligible resistance switch starting from the first stage SG1. This branch is coupled to the node of the first voltage divider DV1 to reach the first stage SG1 coupled to the output node of the DAC via stages with fewer branches / forks. The DAC has two branches to select the upper or lower part of the network, where the resistance of the two switches is negligible. Stages SG1, SG2, SG3, and SG4 are connected in series, some always closed, while others can be configured by the input code DC. The associated switches are controlled by the least significant bit (LSB).

[0130] The state of all switches is controlled by a decoder (e.g., decoder 112a), which translates the input code into control signals.

[0131] Configuration switches SWT1 and SWT2 have been added to enable multiplexer self-test; with Figure 5In the circuit, switch SW corresponds to SWT1, which selectively couples Va and GND, while switch SWT2 selectively couples the upper part of the DAC 111' network, the downstream of the fourth stage SG1, and the lower part.

[0132] Figure 10 This demonstrates how to perform the first test using an external device (ATE) 12.

[0133] Test execution in the first testing phase:

[0134] Switch SWT2 is closed, and SWT1 is connected to the analog reference voltage Va.

[0135] ATE 12 sends a digital data TD to be converted (110101 in this example).

[0136] The decoder 112a of DAC 111” commands the switch to turn on / off according to the value of the digital data TD to be converted, and brings the corresponding voltage to the output VDAC;

[0137] ATE 12 uses voltmeter 121 to read the analog signal VDAC and compares it with a defined range (which can be predefined) to assess whether it is within or outside such a range;

[0138] Using three measurements (lower limit code 000000 and upper limit code 111111 plus the intermediate code between these limits), the entire physical structure of the first and second voltage dividers DV1 and DV2 is covered.

[0139] Figure 9 The second test phase is shown, for example, testing a multiplexed network (BIST) (second test phase), such as DAC 111', which is a 6-bit distributed DAC, where the second test phase has two sub-tests: closure fault test and open fault test.

[0140] Closed-loop fault testing includes:

[0141] Switch SWT1 is coupled to ground GND, and switch SWT2 is closed to couple the upper and lower branches;

[0142] Pull-up current 111e and comparator 111d are enabled.

[0143] By turning off the switch of the level under test and turning on all other switches, each level SG1 … SG4 is tested sequentially. For example, the switch of the fourth-stage SG4 remains off, while all other switches are closed. If the switches are not damaged, the comparator output goes high, so the test result is good;

[0144] The second and third stage SG3 switches remain off, while all other switches remain on. If the switches are not damaged, the output of comparator 111d will go high, therefore the test result is good;

[0145] For Level 2 SG2 and Level 1 SG1, the test is repeated in the same manner.

[0146] Disconnection fault tests include:

[0147] Switch SWT1 is coupled to ground (GND), and SW2 is open, thus separating the upper and lower branches. Pull-up current and the comparator are enabled. Each switch is tested by closing each path between the output analog voltage VDAC and the first resistor divider DV1. If all programmed switches are closed correctly, the divider will force the output analog voltage VDC to ground, and the comparator output will be low. This indicates that there is no fault.

[0148] For example, to test the fourth stage SG4, the first, second, and third stage switches remain on, while the fourth stage switch is closed one by one. If the output of comparator 111d is still low, the test result is good.

[0149] For example, the disconnection fault test on the third stage SG3: SWT2 disconnects, and SG1, SG2, and SG4 stages are all closed. SG3 switches close one at a time. If the output of comparator 111d remains low, the test result is good.

[0150] Similar tests can be performed for SG1 and SG2 levels.

[0151] Another embodiment could be a current-directing DAC architecture.

[0152] Figure 11 This illustrates a possible implementation of the basic test components, such as performing the first test phase in a 2-bit current-directed DAC architecture 111′′′.

[0153] The illustrated current-direction unary (i.e., all generators transmit the same current I) architecture includes three current generators GI1, GI2, and GI3, i.e., 2 n-1 n is the number of bits, thus providing a defined current I, which is selectively coupled to the analog current output Idac through corresponding switches iSW1, iSW2, iSW3. The three current generators GI1, GI2, GI3 are obtained as parallel current mirrors (e.g., as transistors, particularly MOSFET transistors), which are coupled through their gates to the gate of the same mirror transistor (e.g., a diode connected in a mirror current diagram). Figure 11The transistors and current mirrors are not shown, but a mirror current generator MI for a diode-connected MOSFET is shown, with geometric parameters such that multiplying the current (reference current Iref) by an integer factor M = 2. n-1 In mirror image, the diode-connected MOSFET is coupled to terminal 113a for measurement by ammeter 121'. Therefore, in Figure 11 In the middle, the mirror current generator MI can drive a value of 3. The reference current Iref is I. Thus, when switches iSW1, iSW2, and iSW3 are all closed, the mirror current generator MI can be driven to a value of 3. The reference current Iref is measured by ammeter 121'. In the presence of another configuration, the smaller reference current Iref will be mirrored into ammeter 121'. The analog current output Idac is a scaled version of the reference current Iref; therefore, for testing purposes, it is sufficient to measure the reference current rather than selecting the output as in a resistor divider, since the reference current represents a scaled measurement of the analog current output Ida.

[0154] Therefore, the first test may include:

[0155] Under the control of ATE logic 122, logic 112 will switch to enable a reference current generator in the DAC current branch;

[0156] Use ATE 12' to read the analog reference current Iref using ammeter 122';

[0157] ATE 12' compares the analog current Iref reading with a preset current range. If the reference current Iref is within the expected range, the basic component passes the test successfully. If the reference current Iref exceeds the preset current range, a fault is asserted via logic.

[0158] The number of ATE 12' measurements required for the test circuit elements in the first test depends on the architecture used. For example, in this implementation, there is only one variable in the architecture: the mirror reference current IREF. As mentioned above, the output current IDAC is simply a scaled version of the mirror reference current IREF, so it does not need to be measured. Therefore, only one reading is required.

[0159] Figure 12 The overall test architecture of the 3-bit current-directing DAC is shown, which is basically the same as... Figure 11 Corresponding to the architecture in [the previous section], this one has more current generators, where the number of bits n is 3. This architecture includes components for the first and second test phases. In the case shown, there are 2 [units / parts]. n-1 (For example, seven) current generators GI1 … GI7 utilizes the corresponding switch iSW1… ISW7 supplies current I, and these switches selectively couple the corresponding current generators to the output node of the DAC labeled VS. Furthermore, in this case, the current generators GI1…GI7, although not explicitly shown, are obtained through current mirrors connected in parallel with the corresponding switches in iSW1…ISW7, while on the other side is a mirror generator MI, such as a diode-connected MOSFET, whose size can provide a current mirror equal to M. The reference current Iref of I, for example, is 7 in this case. The output of DAC VS is coupled to comparator 111d, which is similar to... Figures 6A-7B The comparators used for testing the network, for example, have the node VS terminal coupled to the input of threshold comparator 11d, and another input coupled to the threshold voltage VREFT. This is because the pull-up current generator UG, which provides half a current I to node VS (e.g., half the current I of the DAC current generator), is coupled in parallel with the load RL between VS and VDD, and is coupled to node VS via the load decoupling switch SWL. The corresponding pull-down generator DG, which provides half a current I to ground, is coupled in parallel with the DAC current generators GI1…GI7 between node VS and ground. The two generators UG and DG, as well as the mirror generator MI, are operated via the enable signal En provided by logic 122.

[0160] The output of threshold comparator 111d is coupled to logic 112, which runs state machine 112b based on the output logic value of threshold comparator 111d and includes decoder 112a to provide code for commanding switches.

[0161] The tests for this embodiment include:

[0162] The first testing phase verifies the basic analog components. Logic 122 enables (signal En) the reference current Iref of its internal current branch (e.g., a generator coupled to a current mirror). The reference current is read from an external ammeter. The read value is compared to the expected range. If the value is within the expected range, the test result is good.

[0163] Second testing phase: Multiplexing network testing;

[0164] First, a fault closure test is performed. The pull-up current generator (DU) is enabled, and the pull-down generator (DG) is disabled. The pull-up current value is I / 2, which is half of the single current generator unit, because the pull-down current must be greater than the pull-up current in the event of a fault. The logic keeps all switches off. If the output of comparator 111d goes high, the test is considered successful.

[0165] Next, the fault disconnection test begins. All switches iSW1…iSW7 are sequentially forced into the ON state, while all other switches are in the OFF state. If the output of comparator 111d is low, the test result is good;

[0166] A third test phase can also be performed: testing the decoupling switch SWL from the load RL;

[0167] First, a closure fault test is performed. A pull-down current (e.g., generator DG) is enabled, and generator UG is disabled. The pull-down current value is I / 2. Logic 112b keeps switch SWL in the off state. If the output of comparator 111d goes low, the test result is good.

[0168] Next, the fault disconnect test begins. Pull-down current is enabled, and UG (generator DG) is disabled. Logic 112b keeps switch SWL on. If the output of comparator 111d goes high, the test is successful.

[0169] When the test is complete, the logic writes the test results into the register.

[0170] Figure 13 A flowchart illustrating a possible embodiment of the second testing phase (i.e., testing of the switching network) is shown.

[0171] In fact, the second testing phase of the switching network distinguishes between fault disconnection testing (e.g., testing whether some switches in the network cannot disconnect) and fault closure testing (e.g., testing whether some switches in the network cannot close).

[0172] In fault disconnect test ( Figure 13 In 310), each switch in the switch network is individually disconnected, and the output is checked to see if it matches the expected output.

[0173] In fault closure test ( Figure 13 In step 320), all switches belonging to the DAC stage are forcibly disconnected, for example, put in the off state, and the output is checked to ensure it matches the expected output. If the DAC includes multiple stages, such as... Figure 10 As shown, each level is controlled by different bits or bit groups of a digital code DC starting from the MSB to the LSB, and the same operation is performed sequentially in the next level. For example, in one embodiment, when a level is being tested and its switch is forcibly opened, all switches in other levels are closed.

[0174] therefore, Figure 13 The flowchart of Example 300 for the second testing phase is shown in the figure.

[0175] The 305 indication begins after the completion of the first test phase indicated by phase 200. The first test phase 200 typically involves sending a given digital data TD from an automated test instrument 12 as input to a digital-to-analog converter (e.g., 111'), and measuring the analog output of the digital-to-analog converter 111' using a measuring instrument. For example, in the automated test instrument, a voltmeter or ammeter checks whether the measured value matches the expected conversion value of the given digital data TD based on the electrical quantity output as the digital-to-analog converter. As previously mentioned, test phase 200 may include sending multiple data TDs and performing corresponding multiple measurements or reads using a measuring instrument; the number and reads of such digital data TDs are related to the DAC architecture.

[0176] 310 indicates a disconnect fault test, which typically involves forcing the 311 digital code DC into DAC 111 (or 111' or 111"'), where the digital code DC corresponds to a given digital input value corresponding to a given switch SWi or iSWi.

[0177] 312 indicates whether the given settling time has elapsed.

[0178] If the condition is positive, step 313, checked by comparator 111d, will execute the output of DAC 111 (or 111' or 111). Otherwise, step 312 is forced.

[0179] In step 314, it is verified whether the output of comparator 111d matches the expected logic value.

[0180] If the result is positive, step 315 checks whether all switches have been tested in sequence. If the result is negative, the exponent i is incremented, for example, by 1, and then step 311 is executed for the next switch.

[0181] In the affirmative case, control is passed to the closure fault test 320, which typically involves forcing 321 to input a digital code DC to DAC 111 (or 111' or 111), the digital code DC being configured to force the same state (e.g., open) for the switches of a given stage (SGj, where j is the index of that stage). If other stages exist, the digital code DC is configured with values ​​that hold them in relative states, such as closed states.

[0182] 322 indicates whether the given settling time has elapsed.

[0183] If the condition is positive, step 323, which checks the output of DAC 111 (or 111' or 111), will be executed. Otherwise, step 312 is forced.

[0184] In step 324, it is verified whether the output of comparator 111d matches the expected logic value.

[0185] If the result is positive, step 325 checks whether all levels have been tested in sequence. If the result is negative, index i is incremented in step 326, for example, by 1, and step 321 is performed for the next level.

[0186] Obviously, for Figure 5 or Figure 11 The circuit shown only has one stage, so it only performs one iteration.

[0187] If the result is negative during steps 314 and 324 (e.g., a fault exists), then step 330 (report error) is executed, and the test ends in step 340. If for all levels (e.g., ...) Figure 10 If steps 321-324 are executed for DV1 and SG1 to SG4, then the end step 340s also follows step 326.

[0188] Therefore, the system 10', 10" or 10" used for testing includes an electronic circuit to be tested, such as 11', 11" or 11"', and an automated test instrument 12, 12', wherein the electronic circuit to be tested 11', 11" or 11"' includes a digital-to-analog converter, such as 111', 111" or 111"', and the automated test instrument 12, 12' includes:

[0189] An assembly of electronic components, such as resistor R and current generator I, and resistive switch Rsw, which is specifically arranged in a network and coupled to an analog reference voltage or analog reference current, and

[0190] A multiplexing network of switch 111b, coupled to the electronic component set and configured to select a path in the electronic component set R, I based on the digital value DC at the input of the digital-to-analog converters 111', 111'', which are provided by a logic control module 112 consisting of the electronic circuits 11', 11'', 11"'.

[0191] The electronic circuits 11', 11" and 11"' to be tested include input data links, such as 113b and 123b, between automatic test instruments 12 and 12' and logic control module 112.

[0192] The test system is configured to perform tests on an electronic component assembly, wherein automated test instruments 12, 12' are configured to send digital data TD to control logic module 112 to input digital code DC into digital-to-analog converters 111', 111'' and measure the analog output of digital-to-analog converters 111', 111'' using measuring instruments (e.g., voltmeter 122 or ammeter 122'), which are coupled to the output (e.g., VDAC, Vin) of electronic circuits 10', 10"', 10"' in the automated test instruments 12, 12'. The measured values ​​are then checked to see if they match the expected conversion value of the given digital data TD.

[0193] The tests on the digital-to-analog converters 111', 111"', and 111"' include further testing of the multiplexing network of switch 111b, wherein...

[0194] The logic module 112 is configured to execute a built-in test sequence, such as in embodiment 300, including a digital code sequence DC provided by the logic module 112, to force a given switch of the multiplexing network of the switch (111b) to be in a determined open or closed state.

[0195] The electronic circuits 11', 11”, 11”' include a feedback circuit, which is essentially a comparator 111d, for providing a feedback signal FB to the logic module 112, which is configured to control the execution flow of the built-in test sequence 300 and perform verification based on the feedback signal FB, such as in operations 324, 314, verifying whether the feedback signal FB matches the expected value of the corresponding digital code DC in the digital code sequence.

[0196] Regarding the reduction in test time, as mentioned earlier, referring to the test time of a 10-bit DAC, the ATE 12 uses a voltmeter or ammeter to read the output 2. n Second-rate:

[0197] The duration of each communication depends on the communication frequency. It usually takes a few microseconds (up to 10 microseconds).

[0198] Integrated circuit code changes require stabilization time. Typically, it is 1 microsecond;

[0199] Duration of each ATE read It usually takes 1ms.

[0200] therefore:

[0201]

[0202] Testing of basic components

[0203] The test duration and the number of simulated readouts for the basic components (N) read ) and the time required for ATE to read (T) COMM +T SETTL +T read Related:

[0204] In the case of a resistive DAC, the minimum number of reads N required to test the basic components is... read There are three readouts: one for checking the voltage reference (maximum code), one for checking the ground reference (minimum code), and another for checking the resistor divider ratio to select the intermediate conversion value (intermediate code). The total time required to test the basic components is:

[0205]

[0206] In the case of a current-directed DAC, the minimum number of reads N required to test the basic components is... read 1: Readout of the current reference. The total time required to test the basic components is:

[0207]

[0208] The duration of the multiplexing network test is related to the number of stages in the DAC architecture (denoted by G), the number of bits per stage m, l, and k for each resistor. x The selected number of wires and the time T required for one self-test cycle. cycle Relevant. This formula can provide a good estimate of the calculations required for doubling network test:

[0209]

[0210]

[0211] Total DAC test time: First embodiment

[0212] Consider a 3-bit resistive DAC and T cycle =2.375us:

[0213]

[0214]

[0215] Total DAC test time: Second embodiment

[0216] consider Figure 9 The 6-bit distributed DAC 111' in the middle has 2 wires for the first stage test and 1 wire for the second stage, T cycle =2.375us:

[0217]

[0218]

[0219] Total DAC test time: Third embodiment

[0220] Consider 3-bit current-directing DAC and T cycle =2.375us:

[0221]

[0222]

[0223] Total DAC test time: 10-bit resistive DAC

[0224] Consider a 10-bit resistive DAC with one stage (worst-case test time with multiplication network), T cycle =2.375us, the total test time will be:

[0225]

[0226]

[0227] Test time comparison: known solutions vs. proposed solutions

[0228] In summary, even in the worst-case scenario, for each DAC, the proposed solution reduces the test time by approximately three orders of magnitude compared to known solutions. Considering the assumptions presented earlier, for a 10-bit DAC:

[0229]

[0230]

[0231] Compared with existing technical solutions, the solution can therefore have several advantages.

[0232] The proposed solution is used to test and measure DAC circuits, thereby reducing testing costs by better screening for manufacturing defects and reducing the time required to perform tests.

[0233] The described solution allows for built-in self-testing to avoid interaction with external instruments. Furthermore, the self-test is highly configurable by the user (the number of switches to be tested, speed, and other parameters can be configured).

[0234] The described solution allows for the provision of detailed information to better pinpoint the discovered defects.

[0235] Of course, without prejudice to the principles of this disclosure, the details of the construction and embodiments may vary considerably from those described and illustrated herein by way of example only, without departing from the scope of this disclosure as defined by the appended claims.

[0236] A test system may be summarized as including an electronic circuit under test (11; 11'; 11”; 11”') and an automated test instrument (12; 12'), wherein the electronic circuit under test (11; 11'; 11”; 11”') includes a digital-to-analog converter (111; 111'; 111"), the digital-to-analog converter including an electronic component set (R; I) specifically arranged in a network and coupled to an analog reference voltage or analog reference current; and a multiplexing switch network (111b) coupled to the electronic component set (R; I) and configured to be based on the logic included in the electronic circuit (11; 11'; 11”; 11”'). The control module (112) provides digital values ​​(DC) at the input of the digital-to-analog converter (111; 111'; 111") to select a path in the electronic component set (R), the electronic circuit under test (11; 11'; 11"; 11"') including an input data link (113b; 123b) between an automatic test instrument (20; 20'; 20") and the logic control module (112), the test system being configured to perform tests on the electronic component set (R; I), wherein the automatic test instrument (20; 20'; 20") is configured to send digital data (TD) to control the logic module (112) at the input of the digital-to-analog converter (111; 111'; 111") to select a path in the electronic component set (R); The digital-to-analog converter (111; 111'; 111") is input with a digital code (DC) and the analog output of the digital-to-analog converter (111; 111'; 111") is measured by a measuring instrument (122; 122') coupled to the output of the electronic circuit (10; 10'; 10''') in the automatic test instrument (12; 12'), and then the measured value is checked to see if it matches the expected conversion value of the given digital data (TD). The test of the digital-to-analog converter (111; 111'; 111") includes further testing of the multiplexing switch network (111b), wherein the logic module (112) is configured to execute a built-in test sequence (300). The column (300) includes a digital code sequence (DC) provided by the logic module (112) to force a given switch of the multiplexing network of the switch (111b) to a determined open or closed state. The electronic circuit (11'; 11”; 11”') includes a feedback circuit (111d) for providing a feedback signal (FB) to the logic module (112). The logic module (112) is configured to control the execution flow of the built-in test sequence (300) based on the feedback signal (FB) and to verify (324; 325) whether the feedback signal (TB) matches the expected value of the corresponding digital code (DC) in the digital code sequence.

[0237] The feedback circuit (111d) may include a comparator (111d) configured to receive the analog output of a digital-to-analog converter (111; 111'; 111'') as input and compare it with a given comparator threshold to provide the feedback signal (FB) as a logic signal. The logic module (112) is configured to check whether the logic value at the output of the comparator (111d) of the feedback signal (FB) matches the expected logic value of the corresponding digital code (DC) in the digital code sequence.

[0238] The test system can be configured to perform tests (200) on the electronic component set (R;I), wherein the logic module (122) of the automatic test instrument (12) can be configured to set one or more digital test data (TD) to be converted into corresponding expected analog signals (VDAC) and sent to the logic module (112); the logic module (112) of the electronic circuit (11'; 11"; 11"') is configured to receive the digital test data (TD) and provide the corresponding digital test data to the input analog converter (111; 111'; 111") The measuring instruments (122; 122') of the automatic test instrument (12), particularly voltage or current measuring instruments, can be configured to measure the output analog signal (VDAC); the automatic test instrument (12) can be configured to compare the measured value of the measuring instrument (122; 122') with the expected range of the output analog signal (VDAC) of the corresponding digital code (DC), and if the measured value is within the expected range, the corresponding result is evaluated as passing the corresponding digital code (DC) test, otherwise it is evaluated as failing the test.

[0239] The further testing of the multiplexed network of the switch may include performing an open fault test (310) and a closed fault test (320).

[0240] The disconnection fault test (310) may include testing the fault corresponding to a given switch (SW). i iSW i The corresponding digital code DC forcing (311) of the given digital input value is fed into the digital-to-analog converter (111; 111'; 111''), and the comparator (111d) checks (313) whether (312) the given settling time has elapsed. The feedback signal (FB) output of the comparator (111d) is verified (314) to match the expected logic value. If yes, all switches (SW) of the multiplexed switch network (111b) are checked (315). i iSW iWhether the test has been performed in sequence is determined. If not, the check is performed on the next switch in sequence (313). If yes, control is passed to the next step (specifically, a closure fault test (320)) or the closure fault test (310) ends. The closure fault test may include inputting a digital code DC (321) into a digital-to-analog converter (111; 111'; 111''). The digital code DC may be configured to force the same state (specifically, closure) on the switches of a given stage (SGj) of the multiplexed switch network (111b). If the multiplexed switch network (111b) may include other stages, the digital code (DC) is configured with a value that will affect the other stages. The switch is kept in a relative state, specifically a closed state, and the comparator (111d) of the output of the digital-to-analog converter (111; 111'; 111'') checks (323) in particular whether (322) a given settling time has elapsed, verifies (324) whether the feedback signal (FB) output of the comparator (111d) matches the expected logic value, and if yes, checks (325) whether all stages of the multiplexed switch network (111b) have been tested in sequence, and if no (325), the checks (323) are performed on the next stage in sequence, and if yes, the control proceeds to the next step, specifically a disconnect fault test (310), or proceeds to the end of the disconnect fault test (320).

[0241] A pull-up current generator (111e) can be coupled between a power supply (VDD) and the input node (VS) of a comparator (111d), which can be coupled to the output of a digital-to-analog converter (111; 111'; 111"). The pull-up current generator (111e) is enabled by the logic circuit (112) at the start of the open fault test (310) and the closed fault test (320). The pull-up current generator (111e) is configured to pull up the input node (111e) above a threshold voltage if the multiplexed switch network (111b) is an open circuit relative to ground (GND) to change the logic state of the feedback signal (FB) relative to the switch network (111b) which is set to a low impedance ground path (GND) under the control of the digital code (DC).

[0242] The digital-to-analog converter (111; 111'; 111) may include a resistive digital-to-analog converter.

[0243] The digital-to-analog converter (111; 111'; 111) may include a resistive digital-to-analog converter with multiple stages.

[0244] The digital-to-analog converter (111; 111'; 111) may include a current-directing digital-to-analog converter.

[0245] If the feedback signal (TB) matches the expected value of the corresponding digital code (DC) in the digital code sequence, the logic module (112) can be configured to send the result of the verification steps (324; 325) to the automated test instrument (12), particularly when the built-in sequence is completed. Specifically, the logic module (112) may include registers for storing the result during the execution of the built-in sequence and is configured to evaluate whether the result stored at the end of the test of the circuit multiplexing network of the switch (111b) passes the test.

[0246] The electronic circuit to be tested can be summarized as including being configured to operate in the system.

[0247] A method of operating a test system can be summarized as follows: when an automatic test instrument (20; 20'; 20") sends digital data (TD) to control a logic module (112) to input digital code (DC) into a digital-to-analog converter (111; 111'; 111") and measures (122; 122') the analog output of the digital-to-analog converter (111; 111'; 111") in the automatic test instrument (12), a test is performed on an electronic component set (R; I), and then the measured value is checked to see if it matches the expected conversion value of the given digital data (TD), wherein the test of the digital-to-analog converter (111; 111'; 111") is performed. Further testing of the multiplexed switch network (111b) includes executing a built-in test sequence (300) at the logic module (112), the built-in test sequence (300) including providing a digital code sequence (DC) to force a given switch in the multiplexed network of the switch (111b) to a determined open or closed state, providing a feedback signal (FF) to the logic module (112) based on the feedback signal (FB), controlling the execution flow of the built-in test sequence (300), and verifying (324; 325) whether the feedback signal (TB) matches the expected value of the corresponding digital code (DC) in the digital code sequence.

[0248] The method may include comparing the analog output of the digital-to-analog converter (111; 111'; 111") with a given comparator threshold to provide the feedback signal (FB) as a logic signal, and checking (112) whether the logic value of the feedback signal (FF) matches the expected logic value of the corresponding digital code (DC) in the digital code sequence.

[0249] The method may include performing a test (200) of the electronic component set (R;I), including: setting one or more digital test data (TD) to be converted into a corresponding expected analog signal (VDAC) at the logic module (122) of the automatic test instrument (12) and sending it to the logic module (112); receiving the digital test data (TD) at the logic module (112) of the electronic circuit (10) and providing a corresponding digital code (DC) to the input of the analog-to-digital converter (111; 111'; 111''); measuring (122; 122') (specifically voltage or current measurement) the output analog signal (VDAC) by the measuring instrument of the automatic test instrument (12); comparing the measured value of the measuring instrument (122; 122') with the expected value range of the output analog signal (VDAC) of the corresponding digital code (DC) at the automatic test instrument (12), and evaluating the corresponding result as passing the test for the corresponding digital code (DC) if the measured value is within the expected value range, otherwise evaluating it as a test failure.

[0250] The further testing of the multiplexed switch network (111b) may include performing an open fault test (310) and a closed fault test (320).

[0251] The disconnection fault test (310) may include testing the fault corresponding to a given switch (SW). i iSW i The corresponding digital code DC forcing (311) of the given digital input value is fed into the digital-to-analog converter (111; 111'; 111''). The comparator (111d) at the output of the digital-to-analog converter (111; 111'; 111'') checks (313) whether (312) the given settling time has elapsed. It verifies (314) whether the feedback signal (FB) at the output of the comparator (111d) matches the expected logic value. If yes, it checks (315) all switches (SW) of the multiplexed switch network (111b). i iSW iWhether the test has been performed in sequence is determined. If not, the check is performed on the next switch in sequence (313). If yes, control is passed to the next step (specifically, a closure fault test (320)) or the open fault test (310) ends. The closure fault test may include inputting a digital code DC (321) into a digital-to-analog converter (111; 111'; 111''). The digital code DC may be configured to force the same state (specifically, open) on the switches of a given stage (SGj) of the multiplexed switch network (111b). If the multiplexed switch network (111b) may include other stages, the digital code (DC) is configured with a value that will affect the open state of the other stages. The switch is kept in a relative state, specifically a closed state. The comparator (111d) of the output of the digital-to-analog converter (111; 111'; 111'') checks (323) whether (322) a given settling time has elapsed. The feedback signal (FB) output of the comparator (111d) is verified (324) to match the expected logic value. If yes, all stages of the multiplexed switch network (111b) are checked (325) to see if they have been tested in sequence. If no (325), the checks (323) are performed on the next stage in sequence. If yes, the control proceeds to the next step, specifically a disconnect fault test (310), or to the end of the disconnect fault test (320).

[0252] A computer program product that can be loaded into the memory of at least one computer and can be summarized as including software code that, when the product is run on at least one computer, enables the execution of steps of a method.

[0253] In one embodiment, a device includes: a digital-to-analog converter (DAC) having a switching network, wherein the DAC generates an analog output signal in operation in response to input codes in an input code set of the DAC; and a built-in self-test (BIST) circuit coupled to the DAC, wherein the BIST circuit, in a self-test operating mode: sequentially applies codes from a determined subset of codes in the input code set to test a plurality of switches, the determined subset of codes being less than the input code set; detects switch failures of the plurality of switches based on the DAC's response to the applied codes; and generates a signal indicating a switch network failure in response to the detection of a switch failure. In one embodiment, the BIST circuit, in the self-test operating mode: controls the sequential application of codes from the determined subset of codes based on the DAC's response to the applied codes. In one embodiment, the BIST circuit, in the self-test operating mode: stops applying codes from the determined subset of codes in response to detecting a switch failure based on the response to the applied codes. In one embodiment, the BIST circuit, in self-test operation mode, performs an open fault test on a plurality of switches. The open fault test includes: applying a determined subset of codes to the DAC to open all switches in the plurality of switches; detecting a switch fault that opened in response to the applied codes; and generating a fault indication for the open fault test in response to the detection of a switch fault that opened in response to the applied codes. In another embodiment, the BIST circuit, in self-test operation mode, performs a closed fault test on a plurality of switches. The closed fault test includes: sequentially, for one or more switches in the plurality of switches, applying a determined subset of codes to the DAC to close a switch in the plurality of switches and open the other switches in the plurality of switches; detecting a switch fault that closed in response to the applied codes; and generating a fault indication for the closed fault test in response to the detection of a switch fault that closed in response to the applied codes. In one embodiment, the BIST circuit, in self-test operation mode, performs an open fault test on a plurality of switches, the open fault test comprising: applying a determined subset of codes to the DAC to open all switches in the plurality of switches; detecting a switch fault that opened in response to the applied codes in the plurality of switches; and generating a fault indication for the open fault test in response to the detection of a switch fault that opened in response to the applied codes in the plurality of switches; and performs a close fault test on a plurality of switches, the close fault test comprising, for one or more switches in the plurality of switches, sequentially: applying a determined subset of codes to the DAC to close a switch in the plurality of switches, and opening other switches in the plurality of switches; detecting a switch fault that closed in response to the applied codes; and generating a fault indication for the close fault test in response to the detection of a switch fault that closed in response to the applied codes in the plurality of switches.In one embodiment, the BIST circuit, in self-test operation mode, performs an open fault test before performing a closure fault test. In another embodiment, the BIST circuit, in self-test operation mode, performs an open fault test on a plurality of switches, the open fault test comprising: applying a determined subset of codes to the DAC to open all switches in the plurality of switches; detecting a switch fault that opened in response to the applied codes; and generating a fault indication for the open fault test in response to the detection of a switch fault that opened in response to the applied codes; and selectively performing a closure fault test on the plurality of switches based on the result of the open fault test, the closure fault test comprising, for one or more switches in the plurality of switches, sequentially: applying a determined subset of codes to the DAC to close a switch in the plurality of switches and open the other switches in the plurality of switches; detecting a switch fault that closed in response to the applied codes; and generating a fault indication for the closure fault test in response to the detection of a switch fault that closed in response to the applied codes. In one embodiment, the BIST circuit includes: a comparator that, in operation, compares a threshold with the analog response of the DAC to an applied code; and generates a logic signal based on the comparison result of the threshold and the analog response of the DAC, wherein the BIST circuit, in operation, detects a switching fault of a plurality of switches in response to a difference between the value of the logic signal and the expected value of the logic signal corresponding to the applied code. In one embodiment, the BIST circuit includes: a current generator coupled between a power supply voltage node and an input node of the comparator, the input node of the comparator being coupled to an analog output of the DAC, wherein the BIST circuit selectively enables the current generator in BIST operating mode. In one embodiment, the device includes: an interface coupled to the DAC and the BIST circuit, wherein, in operation: the BIST circuit receives digital test data via the interface and applies a test code to the DAC based on the received digital test data; and the DAC generates an analog result based on the applied test code and outputs the analog result via the interface. In one embodiment, in operation, the interface couples the device to an automated test instrument, receives digital test data from the automated test instrument, and outputs an analog result to the automated test instrument. In one embodiment, the DAC includes a resistive DAC. In one embodiment, the DAC includes a current-directing DAC. In one embodiment, the switch network includes multiple levels, and each level includes corresponding switches of multiple switches.In one embodiment, the BIST circuit, in self-test operation mode, performs an open fault test on the switches of a stage in a plurality of stages. The open fault test includes: applying a determined subset of codes to the DAC to: close all switches of other stages in the plurality of stages; and open all switches of a stage in the plurality of stages; detect a switch fault in a stage that is open in response to the applied codes; and generate a fault indication for the open fault test in response to the detection of a switch fault in a stage that is open in response to the applied codes. In one embodiment, the BIST circuit, in self-test operation mode, performs a closed fault test on the switches of a stage in a plurality of stages. The closed fault test includes, sequentially for one or more switches of a stage, applying a determined subset of codes to the DAC to: close all switches of other stages in the plurality of stages; close the switches of the stage; open other switches of the stage; detect a switch fault that is closed in response to the applied codes; and generate a fault indication for the closed fault test in response to the detection of a plurality of switches that are closed in response to the applied codes.

[0254] In one embodiment, the system includes: an automated test instrument (ATE); an interface; and a digital-to-analog converter (DAC) coupled to the ATE via the interface, wherein the DAC generates an analog output signal in operation in response to input codes of an input code set of the DAC. The DAC includes: a switch network having multiple switches; and a built-in self-test (BIST) circuit coupled to the switch network, wherein in the DAC's self-test operation mode, the BIST circuit: sequentially applies codes from a determined subset of codes in the input code set to test the multiple switches, the determined subset of codes having fewer codes than the input code set; detects switch failures of the multiple switches based on the DAC's response to the applied codes; and generates a signal indicating a switch network failure in response to the detection of a switch failure. In one embodiment, the BIST circuit, in the self-test operation mode, controls the sequential application of codes from the determined subset of codes based on the DAC's response to the applied codes. In one embodiment, the BIST circuit includes: a comparator that, in operation, compares a threshold with an analog response of the DAC to an applied code; and generates a logic signal based on the comparison result of the threshold and the analog response of the DAC, wherein the BIST circuit, in operation, detects a switch failure of a plurality of switches in response to a difference between the value of the logic signal and the expected value of the logic signal corresponding to the applied code. In one embodiment, in operation: the BIST circuit receives digital test data from the ATE via an interface and applies a test code to the DAC based on the received digital test data; and the DAC generates an analog result based on the applied test code and outputs the analog result via an interface. In one embodiment, in operation, the BIST circuit generates a test result signal indicating the test result of a plurality of switches and outputs the test result signal to the ATE via an interface. In one embodiment, the switch network includes multiple stages, each stage including a corresponding switch among a plurality of switches. In one embodiment, the BIST circuit, in self-test operation mode, performs a disconnection fault test on the switches of multiple stages. The disconnection fault test includes: applying a determined subset of codes to the DAC to: close all switches of other stages in the multiple stages; and open all switches of stages in the multiple stages; detect a switch fault in a stage that is open in response to the applied codes; and generate a fault indication for the disconnection fault test in response to the detection of a switch fault in a stage that is open in response to the applied codes.In one embodiment, the BIST circuit, in self-test operation mode, performs a closure fault test on the switches of a level among multiple levels. The closure fault test includes, sequentially for one or more switches of a level, applying a determined subset of codes to the DAC to: close all switches of other levels among the multiple levels; close the switches of the level; and open the other switches of the level; detect a switch fault that closes in response to the applied codes; and generate a fault indication for the closure fault test in response to the detection of a switch fault that closes multiple switches in response to the applied codes.

[0255] In one embodiment, a method includes: using a built-in self-test (BIST) circuit of a DAC, sequentially applying codes from a determined subset of codes in the input code set of the DAC to a digital-to-analog converter (DAC), wherein the determined subset of codes is less than the input code set of the DAC; detecting switching faults of multiple switches in a DAC switching network using the BIST circuit based on the DAC's response to the applied codes in the determined subset of codes; and generating a fault indication of the DAC switching network using the BIST circuit in response to the detection of switching faults in the multiple switches. In one embodiment, the method includes: controlling the sequential application of codes from the determined subset of codes based on the DAC's response to the applied codes. In one embodiment, fault detection includes: comparing a threshold with the DAC's analog response to the applied codes to generate a logic signal; and detecting switching faults in the multiple switches in response to a logic signal value that differs from an expected value of the logic signal corresponding to the applied codes. In one embodiment, the method includes: receiving digital test data from an automated test instrument (ATE) via the BIST circuit; applying test codes to the DAC based on the received digital test data via the BIST circuit; generating a simulation result by the DAC based on the applied test codes; and comparing the simulation result with an expected simulation result via the ATE. In one embodiment, the switch network includes multiple levels, each level including a corresponding switch among multiple switches. In one embodiment, the method includes: performing an open fault test on the switches of a level of the multiple levels, the open fault test including: applying codes from a determined subset of codes to a DAC to: close all switches of other levels in the multiple levels; open all switches of a level in the multiple levels; detect a switch fault in a level that is open in response to the applied codes; and generate a fault indication for the open fault test in response to the detection of a switch fault in a level that is open in response to the applied codes. In one embodiment, the method includes: performing a close fault test on the switches of a level of the multiple levels, the close fault test including, sequentially for one or more switches of a level: applying codes from a determined subset of codes to a DAC to: close all switches of other levels in the multiple levels; close the switches of the level; open other switches of the level; detect a close switch fault in response to the applied codes; and generate a fault indication for the close fault test in response to the detection of a switch fault in a plurality of switches that are closed in response to the applied codes. In one embodiment, the method includes: determining the determined subset of codes.

[0256] In one embodiment, the content of a non-transitory computer-readable medium causes a built-in self-test (BIST) circuit of a digital-to-analog converter (DAC) to execute a method comprising: sequentially applying codes of a determined subset of codes in the DAC's input code level to the inputs of the DAC, the determined subset of codes being less than the DAC's input code set; detecting switching faults of a plurality of switches in a DAC switching network based on the DAC's response to the applied codes in the determined subset of codes; and generating a fault indication of the DAC's switching network in response to the detection of switching faults of the plurality of switches. In one embodiment, the method comprises: controlling the sequential application of codes of the determined subset of codes based on the DAC's response to the applied codes. In one embodiment, fault detection comprises: comparing a threshold with an analog response of the DAC to the applied codes to generate a logic signal; and detecting switching faults of the plurality of switches in response to a difference between the logic signal value and an expected value of the logic signal corresponding to the applied codes. In one embodiment, the content comprises instructions executed by the BIST.

[0257] Some embodiments may take the form of or include a computer program product. For example, according to one embodiment, a computer-readable medium is provided, which includes a computer program adapted to perform one or more of the methods or functions described above. The medium may be a physical storage medium, such as a read-only memory (ROM) chip, or a disk, such as a digital multifunction disk (DVD-ROM), optical disk (CD-ROM), hard disk, memory, network, or a portable media article that can be read by a suitable drive or via a suitable connection (including one or more barcodes or other related codes stored on one or more such computer-readable media and readable by a suitable card reader device).

[0258] Furthermore, in some embodiments, some or all of the methods and / or functions may be implemented or provided in other ways (such as at least in part in firmware and / or hardware), including but not limited to one or more application-specific integrated circuits (ASICs), digital signal processors, discrete circuits, logic gates, standard integrated circuits, controllers (e.g., by executing appropriate instructions, and including microcontrollers and / or embedded controllers), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), and devices employing RFID technology and various combinations thereof.

[0259] The various embodiments described above can be combined to provide further embodiments. As needed, aspects of the embodiments can be modified to utilize concepts from various patents, applications, and publications to provide further embodiments.

[0260] Based on the detailed description above, these and other modifications can be made to the embodiments. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the scope of all equivalents claimed by such claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A device for testing, comprising: A digital-to-analog converter (DAC) having a switching network, wherein the DAC generates an analog output signal in operation in response to an input code in the DAC's input code set; as well as A built-in self-test BIST circuit device coupled to the DAC, wherein the BIST circuit device is in self-test operation mode: Multiple switches are tested by sequentially applying the codes of a subset of codes determined from the input code set, wherein the determined subset of codes has fewer codes than the input code set; The switching failure of the plurality of switches is detected based on the DAC's response to the applied code. as well as In response to the detection of a switch fault, a signal indicating a fault in the switch network is generated.

2. The device according to claim 1, wherein the BIST circuit device in the self-test operation mode: Based on the DAC's response to the applied code, the order of application of the code in the determined subset of code is controlled.

3. The device according to claim 2, wherein the BIST circuit device in the self-test operation mode: In response to a detected switch failure based on the response to the applied code, the application terminates the set of code determined by the application.

4. The device according to claim 1, wherein the BIST circuit device in the self-test operation mode: Perform a disconnection fault test on one of the plurality of switches, the disconnection fault test including: The code of the determined subset of codes is applied to the DAC to disconnect all of the plurality of switches; Detecting switch malfunctions among the plurality of switches that open in response to the applied code; as well as In response to the detection of a switch failure in which one of the plurality of switches is disconnected in response to an applied code, a fault indication for the disconnection fault test is generated.

5. The device according to claim 1, wherein the BIST circuit device in the self-test operation mode: Perform a closure fault test on one of the plurality of switches, the closure fault test including: For one or more of the plurality of switches, sequentially: The code of the determined subset of codes is applied to the DAC to close one of the plurality of switches and open the other of the plurality of switches; Detects faulty switches that close in response to the applied code; as well as In response to the detection of a switch failure among a plurality of switches that closed in response to an applied code, a fault indication for the closure failure test is generated.

6. The device according to claim 1, wherein the BIST circuit device in the self-test operation mode: Perform a disconnection fault test on one of the plurality of switches, the disconnection fault test including: The code of the determined subset of codes is applied to the DAC to disconnect all of the plurality of switches; Detecting switch malfunctions among the plurality of switches that open in response to the applied code; as well as In response to the detection of a switch failure in which one of the plurality of switches is disconnected in response to an applied code, a fault indication for the disconnection fault test is generated; as well as Perform a closure fault test on one or more of the plurality of switches, the closure fault test comprising, sequentially: The code of the determined subset of codes is applied to the DAC to close one of the plurality of switches and open the other switches among the plurality of switches; Detects faulty switches that close in response to the applied code; as well as In response to the detection of a switch failure in which one of the plurality of switches closes in response to an applied code, a fault indication for the closure failure test is generated.

7. The device of claim 6, wherein the BIST circuitry performs the open fault test before performing the closure fault test in the self-test operation mode.

8. The device according to claim 1, wherein the BIST circuit device in the self-test operation mode: Perform a disconnection fault test on one of the multiple switches, the disconnection fault test including: The code of the determined subset of codes is applied to the DAC to disconnect all of the plurality of switches; Detecting switch malfunctions among the plurality of switches that open in response to the applied code; as well as In response to the detection of a switch failure in which one of the plurality of switches is disconnected in response to an applied code, a fault indication for the disconnection fault test is generated; as well as Based on the results of the disconnection fault test, a closure fault test is selectively performed on the plurality of switches. The closure fault test includes, for one or more of the plurality of switches, sequentially: The code of the determined subset of codes is applied to the DAC to close one of the plurality of switches and open the other of the plurality of switches; Detects faulty switches that close in response to the applied code; as well as In response to the detection of a switch failure in which one of the plurality of switches closes in response to an applied code, a fault indication for the closure failure test is generated.

9. The device of claim 1, wherein the BIST circuitry comprises: The comparator, in operation: The threshold is compared with the simulated response of the DAC to the applied code; as well as A logic signal is generated based on a comparison between the threshold and the analog response of the DAC, wherein the value of the logic signal in operation differs from the expected value of the logic signal corresponding to the applied code, and the BIST circuitry detects a switching fault in the plurality of switches.

10. The device of claim 9, wherein the BIST circuitry comprises: A current generator is coupled between a power supply voltage node and an input node of the comparator, the input node of which is coupled to the analog output of the DAC, wherein the BIST circuitry selectively enables the current generator in the BIST operating mode.

11. The device according to claim 1, comprising: An interface, coupled to the DAC and the BIST circuitry, wherein in operation: The BIST circuitry receives digital test data via the interface and applies test codes to the DAC based on the received digital test data; and The DAC generates simulation results based on the applied test code and outputs the simulation results via the interface.

12. The device of claim 11, wherein in operation, the interface couples the device to an automated test instrument, receives the digital test data from the automated test instrument, and outputs the simulation results to the automated test instrument.

13. The device of claim 1, wherein the DAC comprises a resistive DAC.

14. The device of claim 1, wherein the DAC comprises a current-driven DAC.

15. The device of claim 1, wherein the switch network comprises a plurality of levels, each of the plurality of levels comprising a corresponding switch among the plurality of switches.

16. The device of claim 15, wherein the BIST circuitry in the self-test operation mode: Perform a disconnection fault test on the switch of one of the multiple levels, the disconnection fault test including: The code of the determined subset of codes is applied to the DAC so that: Close all switches in the other stages of the plurality of stages; as well as Disconnect all switches in one of the plurality of levels; Detect switch failures in the stage where the switch is disconnected in response to the applied code; as well as In response to the detection of a switch failure in the level that is disconnected in response to the applied code, a fault indication for the disconnection failure test is generated.

17. The device of claim 15, wherein the BIST circuitry in the self-test operation mode: Perform a closure fault test on the switches of one or more of the multiple levels, the closure fault test comprising sequentially performing the following on one or more switches of the level: The code of the determined subset of codes is applied to the DAC so that: Close all switches in the other stages of the plurality of stages; Close the switch of the stage; Disconnect the other switches in the stage; Detects faulty switches that close in response to the applied code; as well as In response to the detection of a switch failure in which one of the plurality of switches closes in response to an applied code, a fault indication for the closure failure test is generated.

18. A system for testing, comprising: Automated Test Instruments (ATE); interface; as well as A digital-to-analog converter (DAC) coupled to the ATE via the interface, wherein the DAC generates an analog output signal in operation in response to input codes of the DAC's input code set, the DAC comprising: A switching network having multiple switches; and A built-in self-test BIST circuit is coupled to the switching network, wherein the BIST circuit is configured in the DAC's self-test operation mode. The multiple switches are tested by sequentially applying the codes of a subset of codes determined from the input code set, wherein the determined subset of codes contains fewer codes than the input code set. The switching failure of the plurality of switches is detected based on the DAC's response to the applied code; and In response to the detection of the switch fault, a signal indicating a fault in the switch network is generated.

19. The system of claim 18, wherein the BIST circuitry in the self-test operation mode: Based on the DAC's response to the applied code, the sequential application of code in the determined subset of code is controlled.

20. The system of claim 18, wherein the BIST circuitry comprises: The comparator, in operation: The threshold is compared with the simulated response of the DAC to the applied code; as well as A logic signal is generated based on a comparison between the threshold and the analog response of the DAC, wherein the value of the logic signal in operation differs from the expected value of the logic signal corresponding to the applied code, and the BIST circuitry detects switching faults of the plurality of switches.

21. The system of claim 18, wherein in operation: The BIST circuitry receives digital test data from the ATE via the interface and applies test codes to the DAC based on the received digital test data; and The DAC generates simulation results based on the applied test code and outputs the simulation results to the ATE via the interface.

22. The system of claim 21, wherein in operation, The BIST circuit device generates a test result signal indicating the result of the test on the plurality of switches and outputs the test result signal to the ATE via the interface.

23. The system of claim 22, wherein the switch network comprises a plurality of levels, each of the plurality of levels comprising a corresponding switch among the plurality of switches.

24. The system of claim 23, wherein the BIST circuitry in the self-test operation mode: Perform a disconnection fault test on the switch of one of the multiple levels, the disconnection fault test including: The code of the determined subset of codes is applied to the DAC so that: Close all switches in the other stages of the plurality of stages; as well as Disconnect all switches in one of the plurality of levels; Detect switch failures in the stage where the switch is disconnected in response to the applied code; as well as In response to the detection of a switch failure in the level that is disconnected in response to the applied code, a fault indication for the disconnection failure test is generated.

25. The system of claim 23, wherein the BIST circuitry in the self-test operation mode: Perform a closure fault test on the switches of one or more of the multiple levels, the closure fault test comprising sequentially: The code of the determined subset of codes is applied to the DAC so that: Close all switches in the other stages of the plurality of stages; Close the switch of the stage; as well as Disconnect the other switches in the stage; Detects faulty switches that close in response to the applied code; as well as In response to the detection of a switch failure in which one of the plurality of switches closes in response to an applied code, a fault indication for the closure failure test is generated.

26. A method for testing, comprising: Using the built-in self-test BIST circuit of the digital-to-analog converter (DAC), the codes of a subset of codes determined in the input code set of the DAC are sequentially applied to the DAC, wherein the codes of the determined subset of codes are less than the input code set of the DAC. Based on the DAC's response to the applied code of the determined subset of codes, the BIST circuitry is used to detect switching failures of multiple switches in the DAC's switching network. as well as In response to the detection of a switch failure in the plurality of switches, a fault indication of the switch network of the DAC is generated using the BIST circuit.

27. The method of claim 26, comprising: Based on the DAC's response to the applied code, the order of application of the code in the determined subset of code is controlled.

28. The method of claim 26, wherein the fault detection comprises: The threshold is compared with the analog response of the DAC to the applied code to generate a logic signal; as well as A switching fault is detected in the plurality of switches in response to the fact that the value of the logic signal is different from the expected value of the logic signal corresponding to the applied code.

29. The method of claim 28, comprising: The BIST circuitry receives digital test data from the automated test instrument ATE. The BIST circuitry device applies test codes to the DAC based on the received digital test data. The DAC generates simulation results based on the applied test code; as well as The simulation results are compared with the expected simulation results using the ATE.

30. The method of claim 26, wherein the switch network comprises a plurality of levels, each of the plurality of levels comprising a corresponding switch among the plurality of switches.

31. The method of claim 30, comprising: Perform a disconnection fault test on the switches of the multiple levels, the disconnection fault test including: The code of the determined subset of codes is applied to the DAC so that: Close all switches in the other stages of the plurality of stages; Disconnect all switches of the aforementioned levels; Detect a switch failure in the stage that is disconnected in response to an applied code; and generate a fault indication for the disconnection failure test in response to the detection of a switch failure in the stage that is disconnected in response to an applied code.

32. The method of claim 30, comprising: Perform a closure fault test on the switches of one or more of the multiple levels, the closure fault test comprising sequentially performing the following on one or more switches of the level: Apply the code of the determined subset of codes to the DAC, so as to: Close all switches in the other stages of the plurality of stages; Close the switch of the stage; Disconnect the other switches in the stage; Detect switch failures that respond to the closing of the applied code; as well as In response to the detection of a switch failure in which one of the plurality of switches closes in response to an applied code, a fault indication for the closure failure test is generated.

33. The method of claim 26, comprising: Determine the subset of code that has been identified.

34. A non-transitory computer-readable medium having contents that cause a built-in self-testing BIST circuit of a digital-to-analog converter (DAC) to perform a method, the method comprising: The codes of a subset of codes determined from the input code set of the DAC are sequentially applied to the input of the DAC, wherein the determined subset of codes has fewer codes than the input code set of the DAC; Based on the DAC's response to the code applied in the determined code subset, the switching faults of multiple switches in the DAC's switching network are detected. as well as In response to the detection of a switch failure in the plurality of switches, a fault indication of the switch network of the DAC is generated.

35. The non-transitory computer-readable medium of claim 34, wherein the method comprises: Based on the DAC's response to the applied code, the order of application of the code in the determined subset of code is controlled.

36. The non-transitory computer-readable medium of claim 34, wherein fault detection comprises: The threshold is compared with the analog response of the DAC to the applied code to generate a logic signal; as well as The system detects switching faults in multiple switches by responding to a difference between the value of the logic signal and the expected value of the logic signal corresponding to the applied code.

37. The non-transitory computer-readable medium of claim 34, wherein the content includes instructions executed by the BIST.

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