A centralized interrupt control method, an interrupt control system and a chip
By centrally managing interrupts through the processor, using interrupt receivers and synthesizers to identify and buffer interrupt signals, and having the processor query and respond to interrupts, the problem of inflexible interrupt design in large-scale on-chip systems is solved, and interrupt management efficiency is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- STREAM COMPUTING INC
- Filing Date
- 2021-11-08
- Publication Date
- 2026-07-21
Smart Images
Figure CN116089026B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of interrupt control technology, and in particular to a centralized interrupt control method, interrupt control system, chip, computer equipment, and medium. Background Technology
[0002] In the initial design of large-scale System-on-Chip (SoC) and Network-on-Chip (NoC) architectures, interrupt requirements are often not determined at once. Especially when the usage scenarios are not very certain, the design of centralized interrupt management becomes particularly important. This is especially true for large chips, which have dozens to hundreds of interrupt data lines. How to flexibly design interrupts to meet uncertain usage requirements has become an urgent technical problem to be solved. Summary of the Invention
[0003] To address at least one of the aforementioned problems, a first embodiment of the present invention provides a centralized interruption control method, comprising:
[0004] The processor controls the interrupt receiver to receive a first interrupt signal sent by one or more interrupt sources, such that the interrupt receiver determines whether the first interrupt signal is a valid interrupt signal based on a preset interrupt mask and the first interrupt signal. If the first interrupt signal is a valid interrupt signal, the processor generates a second interrupt signal and transmits it to the processor. The first interrupt signal is a level signal.
[0005] After receiving the second interrupt signal, the processor queries the one or more interrupt sources to determine the interrupt corresponding to the valid interrupt signal;
[0006] The processor responds to the interrupt corresponding to the valid interrupt signal and clears the valid interrupt signal.
[0007] This embodiment centrally manages and controls interrupts through the processor. The interrupt receiver receives the first interrupt signal in the form of a level and determines the validity of the first interrupt signal according to the preset interrupt mask. The valid first interrupt signal is then reported to the processor. The processor queries the interrupt source for the received first interrupt signal to determine and respond to the interrupt, and clears the interrupt. Thus, through the process of "receiving and judging the interrupt - querying the interrupt - responding to the interrupt and clearing the interrupt", flexible management, control and response to each interrupt are achieved, which effectively simplifies the complex interrupt management and control process in the prior art.
[0008] In an optional embodiment, the interrupt control method further includes: setting the interrupt mask in response to user operation or a pre-set configuration file;
[0009] The interrupt receiver includes an interrupt synthesizer, and the interrupt control method further includes:
[0010] The interrupt receiver receives a first interrupt signal sent by one or more interrupt sources connected to multiple interrupt interfaces.
[0011] The interrupt receiver performs an AND operation based on the first interrupt signal and the corresponding interrupt mask to determine whether the first interrupt signal is a valid signal.
[0012] If the first interrupt signal is a valid interrupt signal, then the second interrupt signal is generated by the interrupt synthesizer.
[0013] This embodiment allows for flexible setting and modification of the required interrupt signals by setting an interrupt mask, and completes the interrupt judgment and interrupt reporting process through an interrupt receiver with AND gates and an interrupt synthesizer.
[0014] In an optional embodiment, the interrupt receiver further includes a register slice disposed at the back end of the interrupt synthesizer, and the interrupt control method further includes:
[0015] The register slice buffers and delays the signal transmitted by the interrupt synthesizer, wherein the signal transmitted by the interrupt synthesizer includes at least the second interrupt signal generated by the interrupt synthesizer.
[0016] This embodiment uses register slicing to buffer and delay the first interrupt signal to facilitate interrupt timing management and backend hardware design.
[0017] In an optional embodiment, the plurality of interrupt interfaces include a plurality of interrupt groups, and the interrupt synthesizer thereby includes a plurality of first interrupt synthesizers and a second interrupt synthesizer corresponding one-to-one with the interrupt groups. The register slice thereby includes a plurality of first register slices corresponding one-to-one with the first interrupt synthesizers and disposed at the back end of each first interrupt synthesizer, and a second register slice disposed at the back end of the second interrupt synthesizer. The first interrupt synthesizer receives a plurality of valid first interrupt signals received by the interrupt interface of the corresponding interrupt group, and the second interrupt synthesizer receives signals output by the plurality of first register slices.
[0018] The interrupt control method further includes:
[0019] The first interrupt synthesizer synthesizes the valid first interrupt signal to generate a first interrupt synthesized signal, and buffers the first interrupt synthesized signal into the first register slice;
[0020] The second interrupt synthesizer synthesizes the first interrupt signals buffered in each of the first register slices to generate a second interrupt signal, and buffers the second interrupt signal in the second register slice.
[0021] This embodiment further buffers the first interrupt signal by setting up a two-level "interrupt synthesizer-register slice" structure to facilitate the design of interrupt management and control for large-scale on-chip system communication architecture and on-chip network.
[0022] In an optional embodiment, after receiving the second interrupt signal, the processor queries the one or more interrupt sources to determine the interrupt corresponding to the valid interrupt signal, which further includes: the processor queries all interrupt sources corresponding to the interrupt mask according to the second interrupt signal to determine the interrupt to be responded to corresponding to the valid first interrupt signal;
[0023] The processor responding to the interrupt corresponding to the valid interrupt signal and clearing the valid interrupt signal further includes: the processor responding to each interrupt according to the priority of at least one interrupt and clearing the valid interrupt signal corresponding to each interrupt.
[0024] In this embodiment, the processor queries the interrupt source using a preset interrupt mask and determines the interrupt. It then responds to the interrupts to be responded to according to their priority based on the queryed interrupts and clears the valid interrupt signals to complete the interrupt handling.
[0025] In an optional embodiment,
[0026] After receiving the second interrupt signal, the processor queries the one or more interrupt sources to determine the interrupt corresponding to the valid interrupt signal. This further includes: the processor queries the interrupt status register corresponding to the interrupt mask according to the second interrupt signal to determine the interrupt corresponding to the valid interrupt signal; wherein, each interrupt interface is connected to a corresponding interrupt status register for storing the first interrupt signal received by the interrupt interface.
[0027] The processor responding to the interrupt corresponding to the valid interrupt signal and clearing the valid interrupt signal further includes: the processor responding to each interrupt according to the priority of at least one interrupt, clearing the valid interrupt signal and clearing the interrupt status register.
[0028] This embodiment stores each first interrupt signal in an interrupt status register located at the back end of each interrupt interface. This allows the processor to quickly determine the interrupt source by querying the terminal status register, identify the interrupt based on the interrupt source, respond to each first interrupt signal according to the interrupt priority, and clear the first interrupt signal to complete the interrupt handling, effectively improving the efficiency of interrupt management and control.
[0029] In an optional embodiment, the processor queries the interrupt status registers corresponding to the interrupt mask according to the second interrupt signal to determine the interrupt corresponding to the valid interrupt signal, which further includes: after receiving the second interrupt signal, the processor queries all interrupt status registers corresponding to the interrupt mask through a query channel to determine the interrupt corresponding to the valid interrupt signal; wherein, the query channel is connected to the processor and each interrupt status register.
[0030] This embodiment further accelerates the processor's interrupt query speed by setting up a query channel that directly connects the processor and each interrupt status register, thereby improving the efficiency of interrupt management and control.
[0031] In an optional embodiment, there are multiple processors and multiple interrupt receivers, with each processor and interrupt receiver corresponding to one another, and each interrupt receiver connected to all interrupt interfaces;
[0032] The processor responding to the interrupt corresponding to the valid interrupt signal and clearing the valid interrupt signal further includes: the processor responding to the received interrupt to be responded to according to its processing capability and clearing the corresponding interrupt signal.
[0033] This embodiment sets up multiple "processor-interrupt receiver" interrupt management and control channels, and each interrupt management and control channel covers all interrupt sources to realize flexible management and control of interrupts sent by different processors to each interrupt source. In particular, it uses processors with different processing capabilities to respond to interrupts based on the processing characteristics of different processors, thereby realizing the design of interrupt management and control for large-scale on-chip system communication architecture and on-chip network.
[0034] A second embodiment of the present invention provides an interrupt control system, including an interrupt interface, at least one processor, and interrupt receivers corresponding to each processor, wherein...
[0035] The interrupt receiver is used to receive a first interrupt signal sent by one or more interrupt sources connected to multiple interrupt interfaces, determine whether the first interrupt signal is a valid interrupt signal according to a preset interrupt mask and the first interrupt signal, and generate a second interrupt signal and transmit it to the processor if the first interrupt signal is a valid interrupt signal. The first interrupt signal is a level signal.
[0036] The processor is configured to query the one or more interrupt sources based on the received second interrupt signal to determine the interrupt corresponding to the valid interrupt signal, respond to the interrupt corresponding to the valid interrupt signal, and clear the valid interrupt signal.
[0037] This embodiment achieves centralized management and control of interrupts through an interrupt handling system. Specifically, it achieves flexible management, control, and response to each interrupt through "interrupt receiver receiving and judging interrupts - processor querying interrupts - processor responding to interrupts and clearing interrupts", effectively simplifying the complex interrupt management and control process in the prior art.
[0038] In an optional embodiment, the interrupt receiver includes an inverter for receiving interrupt masks corresponding to each of the first interrupt signals, an interrupt determiner, and an interrupt synthesizer, wherein...
[0039] The interrupt detector is used to determine whether the first interrupt signal is a valid interrupt signal based on the first interrupt signal and the interrupt mask inverted by the inverter. If the first interrupt signal is a valid interrupt signal, it is transmitted to the interrupt synthesizer.
[0040] The interrupt synthesizer is used to generate the second interrupt signal from the valid first interrupt signal and transmit it to the processor.
[0041] This embodiment allows for flexible setting and modification of required interrupt signals by pre-setting an interrupt mask in the processor, and completes the interrupt judgment and interrupt reporting process through an interrupt receiver with AND gates and an interrupt synthesizer.
[0042] In an optional embodiment, the interrupt receiver further includes a register slice disposed at the back end of the interrupt synthesizer for buffering and delaying signals transmitted by the interrupt synthesizer, the signals transmitted by the interrupt synthesizer including at least the second interrupt signal generated by the interrupt synthesizer.
[0043] This embodiment uses register slicing to buffer and delay the second interrupt signal to facilitate interrupt timing management and backend hardware design.
[0044] In an optional embodiment, the interrupt control system further includes an interrupt status register disposed at the back end of each interrupt interface for storing the first interrupt signal, so that the processor can query and determine the interrupt corresponding to the first interrupt signal.
[0045] This embodiment speeds up the processor's polling speed by setting the interrupt status register.
[0046] In an optional embodiment, the interrupt control system includes multiple processors, and each processor is provided with an interrupt receiver, all interrupt receivers being connected to an interrupt interface;
[0047] For each processor, it is used to respond to the received interrupts according to its processing capabilities and clear the corresponding interrupt signal.
[0048] This embodiment sets up different "processor-interrupt receiver" interrupt management and control channels, and each interrupt management and control channel covers all interrupt sources to realize flexible management and control of interrupts sent by different processors to each interrupt source. In particular, it uses processors with different processing capabilities to respond to interrupts based on the processing characteristics of different processors, thereby realizing the design of interrupt management and control for large-scale on-chip system communication architecture and on-chip network.
[0049] A third embodiment of the present invention provides a chip including the interrupt control system described in the second embodiment.
[0050] The chip in this embodiment includes the aforementioned interrupt control system. By "receiving and judging interrupts - querying interrupts - responding to interrupts and clearing interrupts", it can achieve flexible management, control and response to each interrupt, effectively simplifying the complex interrupt management and control process in the prior art.
[0051] A fourth embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the interrupt control method described in the first embodiment.
[0052] The fifth embodiment of the present invention provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the interrupt control method described in the first embodiment.
[0053] The beneficial effects of this invention are as follows:
[0054] This invention addresses existing problems by providing a centralized interrupt control method, system, chip, computer device, and medium. It involves receiving a first interrupt signal in a voltage level form via an interrupt receiver, determining its validity based on a pre-set interrupt mask, and then reporting valid first interrupt signals to a processor. The processor queries the interrupt source based on the received first interrupt signal to identify, respond to, and clear the interrupt. This process of "receiving and judging interrupts—querying interrupts—responding to interrupts and clearing interrupts" enables flexible management, control, and response to each interrupt. It effectively simplifies the complex interrupt management and control process in existing technologies, significantly improves interrupt management and control efficiency, and has practical application value. Attached Figure Description
[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0056] Figure 1A flowchart illustrating an embodiment of the interrupt control method of the present invention is shown;
[0057] Figure 2 This diagram illustrates the structure of an interrupt control system according to an embodiment of the present invention.
[0058] Figure 3 A schematic diagram of the interrupt control system according to another embodiment of the present invention is shown;
[0059] Figure 4 A schematic diagram of the interrupt control system according to another embodiment of the present invention is shown;
[0060] Figure 5 A schematic diagram of the interrupt control system according to another embodiment of the present invention is shown;
[0061] Figure 6 A schematic diagram of the interrupt control system according to another embodiment of the present invention is shown;
[0062] Figure 7 A schematic diagram of the structure of a computer device according to another embodiment of the present invention is shown. Detailed Implementation
[0063] To more clearly illustrate the present invention, the following description, in conjunction with preferred embodiments and accompanying drawings, further explains the invention. Similar components in the drawings are indicated by the same reference numerals. Those skilled in the art should understand that the specific description below is illustrative rather than restrictive and should not be construed as limiting the scope of protection of the present invention.
[0064] In existing technologies, interrupt controllers typically receive and temporarily store secondary interrupt signals from interrupt sources, generate and select high-priority primary interrupt signals, then temporarily store the primary interrupt signals and report them to the corresponding interrupt handling device to respond to and clear the interrupt. There is a one-to-one correspondence between the interrupt controller and the interrupt handling device, thus managing and controlling interrupts in this way. In other words, existing technologies set up interrupt controllers based on interrupt requirements and use these controllers to manage and control interrupts. Whenever interrupt requirements change, the interrupt controller needs to be modified or expanded, resulting in cumbersome interrupt control and difficulties in modification or expansion.
[0065] In response to the above situation, the inventors, after extensive research and experimentation, proposed that the reason for the shortcomings of interrupt control management is that the interrupt controller is set according to the interrupt requirements, which is not easy to modify. At the same time, the interrupt controller controls the processing flow of each interrupt, which is cumbersome. For example, the interrupt controller controls the interrupt to report to the processor for processing based on the priority of each interrupt.
[0066] Based on the above problems and the causes of these problems, such as Figure 1As shown, one embodiment of the present invention provides a centralized interrupt control method, comprising:
[0067] The processor controls the interrupt receiver to receive a first interrupt signal sent by one or more interrupt sources. The interrupt receiver determines whether the first interrupt signal is a valid interrupt signal based on a preset interrupt mask and the first interrupt signal itself. If the first interrupt signal is valid, it generates a second interrupt signal and transmits it to the processor. The first interrupt signal is a level signal. The interrupt receiver can receive first interrupt signals from multiple interrupt sources. If the interrupt receiver determines that a valid interrupt signal exists among the received first interrupt signals, it generates a second interrupt signal to inform the processor that an interrupt needs to be responded to. The valid interrupt signal refers to the valid first interrupt signal, and the interrupt corresponding to the valid first interrupt signal is an interrupt that requires a processor response.
[0068] After receiving the second interrupt signal, the processor queries the one or more interrupt sources to determine the interrupt corresponding to the valid interrupt signal. The interrupt source requests an interrupt by sending a first interrupt signal, and each interrupt source may issue multiple first interrupt signals to request multiple interrupts. After issuing a first interrupt signal, each interrupt source stores the issued first interrupt signal, so that the processor can find out which interrupt sources issued valid first interrupt signals after receiving the second interrupt signal.
[0069] The processor responds to the interrupt corresponding to the valid interrupt signal and clears the valid interrupt signal.
[0070] In this embodiment, interrupts are centrally managed and controlled by a processor, which can be a CPU, a GPU, or other control device capable of handling interrupt events.
[0071] First, the processor controls the interrupt receiver to receive the first interrupt signal from each interrupt source connected to the interrupt interface. The interrupt receiver determines whether the received first interrupt signal is valid based on the preset interrupt mask and the first interrupt signal, and generates a second interrupt signal based on the valid first interrupt signal and transmits it to the processor so that the processor can control and manage the interrupt.
[0072] It is worth noting that this embodiment includes multiple interrupt interfaces, each of which is connected to one or more interrupt sources to receive the first interrupt signal sent by each interrupt source. Furthermore, the first interrupt signal in this embodiment is a level signal, meaning the interrupt signal sent by the interrupt source is either a high-level signal or a low-level signal, so that the interrupt receiver can receive the first interrupt signal. Additionally, the second interrupt signal can be generated by a first interrupt signal triggered by one interrupt, or by multiple first interrupt signals triggered by multiple interrupts.
[0073] Secondly, after receiving the second interrupt signal reported by the interrupt receiver, the processor queries each interrupt source to obtain the interrupt corresponding to each first interrupt signal.
[0074] It is worth noting that the second interrupt signal in this embodiment is used to notify the processor that an interrupt has been reported. It does not involve the specific interrupt name, interrupt type and interrupt priority. The processor queries each interrupt source based on the received second interrupt signal to determine the interrupt corresponding to each first interrupt signal. For example, it queries the interrupt flag in the interrupt register of each interrupt source to determine the interrupt name, interrupt type and interrupt priority of the interrupt corresponding to the first interrupt signal issued by that interrupt source.
[0075] Finally, the processor responds to the interrupt and clears it.
[0076] In this embodiment, the processor includes an interrupt server that responds to interrupts. For example, the interrupt server responds to interrupts to complete interrupt tasks, clears the interrupt flag in the interrupt register corresponding to the interrupt in the interrupt source, and clears the first interrupt signal that the processor has responded to.
[0077] It is worth noting that the interrupt clearing in this embodiment includes clearing the first interrupt signal that the processor has responded to, as well as other interrupt identifiers related to the interrupt, such as clearing the flag bit in the interrupt register of the interrupt source. Those skilled in the art should clear the interrupt according to actual needs so that the interrupt can be triggered again next time.
[0078] In summary, this embodiment manages and processes interrupts through the processor control interrupt management process. It achieves flexible management, control, and response to each interrupt through the process of "processor controlling interrupt receiver to receive, judge, and report interrupts - processor processing and querying interrupts - processor responding to and clearing interrupts", which effectively simplifies the complex interrupt management and control process in the prior art.
[0079] In an optional embodiment, before the processor controls the interrupt receiver to receive at least one first interrupt signal sent by one or more interrupt sources, the interrupt control method further includes: setting the interrupt mask in response to a user operation or a pre-set configuration file;
[0080] The interrupt receiver includes an interrupt synthesizer, and the interrupt control method further includes:
[0081] The interrupt receiver receives a first interrupt signal sent by one or more interrupt sources connected to multiple interrupt interfaces.
[0082] The interrupt receiver performs an AND operation based on the first interrupt signal and the corresponding interrupt mask to determine whether the first interrupt signal is a valid signal.
[0083] If the first interrupt signal is a valid interrupt signal, then the second interrupt signal is generated by the interrupt synthesizer.
[0084] In this embodiment, to facilitate flexible setting or modification of interrupt requirements, setting commands can be sent to configure or modify interrupt requirements. For example, the required interrupts can be directly selected or modified through the processor's external interface. It is worth noting that in large SoCs and NoCs including multiple processors, each processor is configured with a corresponding interrupt receiver. The interrupt mask of each processor's interrupt receiver can be set by sending setting commands to any processor through an external interface. For example, with two processors, a first processor and its corresponding first interrupt receiver, and a second processor and its corresponding second interrupt receiver, the interrupt masks of the first and second interrupt receivers can be set through the external interface via the first processor. Alternatively, interrupt requirements can be set or modified by configuring a configuration file. For example, the required interrupts can be set by configuring an interrupt configuration file during the processor's initialization process. This configuration file can be flexibly modified according to requirements, allowing the processor to clearly define the interrupts it needs to receive and configure the interrupt receivers accordingly.
[0085] Specifically, for example, by configuring the interrupt mask corresponding to the interrupt that needs to be responded to in the interrupt receiver to 0, and then inverting the interrupt mask to limit the required interrupts; for example, by using an AND gate to determine whether the first interrupt signal is valid, where one input of the AND gate is the first interrupt signal and the other input of the AND gate is the inverted interrupt mask, the validity of the first interrupt signal is determined by performing an AND operation on the first interrupt signal in level format and the inverted interrupt mask; at the same time, for multiple first interrupt signals that may exist at the same time, an OR gate can be used as an interrupt synthesizer to perform an OR operation on each valid first interrupt signal and generate a second interrupt signal to be sent to the processor for subsequent interrupt management control process.
[0086] In a specific example, such as Figure 2As shown, the interrupt sources include interrupt source 0, interrupt source 1, interrupt source 2 and interrupt source 3, and the interrupt receiver includes inverter 100, judge 200 and interrupt synthesizer 300. The interrupt interface includes interrupt interface port0 corresponding to interrupt source 0, interrupt interface port1 corresponding to interrupt source 1, interrupt interface port2 corresponding to interrupt source 2, and interrupt interface port3 corresponding to interrupt source 3. Interrupt source 0 sends interrupt 0, and the interrupt mask of the interrupt receiver corresponding to interrupt 0 is Int0_mask0; interrupt source 1 sends interrupt 1, and the interrupt mask of the interrupt receiver corresponding to interrupt 1 is Int1_mask0; interrupt source 2 sends interrupt 2, and the interrupt mask of the interrupt receiver corresponding to interrupt 2 is Int2_mask0; interrupt source 3 sends interrupt 3, and the interrupt mask of the interrupt receiver corresponding to interrupt 3 is Int3_mask0. Inverter 100 inverts the interrupt mask, that is, the interrupt mask of the required interrupt is set to 0, and after inversion by the inverter, it becomes 1 and is transmitted to the judge 200; the judge 200 is an AND gate, and the interrupt synthesizer 300 is an OR gate.
[0087] Specifically, interrupt source 0 sends a high-level first interrupt signal int0 to interrupt interface port0. The first interrupt signal int0, after being connected to the interrupt interface, is transmitted to one end of the judgment unit 200. The interrupt mask Int0_mask0 corresponding to interrupt 0 is inverted by an inverter and transmitted to the other end of the judgment unit 200. The judgment unit 200 performs an AND operation on the two input signals. If interrupt 0, corresponding to the first interrupt signal int0, is an interrupt that does not need to be connected to the processor, then the interrupt mask Int0_mask0 is set to 1. After inversion, the AND gate judgment unit determines that the first interrupt signal int0 sent by interrupt source 0 is invalid. If interrupt 0 is an interrupt that needs to be connected to the processor, then the first interrupt signal int0 is high-level and the interrupt mask Int0_mask0 is set to 0. After inversion, the interrupt mask Int0_mask0 is 1, then the first interrupt signal int0 is a valid signal and is transmitted to the interrupt synthesizer 300. The specific process of interrupt sources 1 through 3 sending the first interrupt signal is similar to that of interrupt source 0 and will not be repeated here. The first interrupt signal received by each interrupt interface is used by the interrupt synthesizer 300 to generate a second interrupt signal and transmit it to the processor. In other words, after the interrupt receiver determines at least one valid first interrupt signal, the interrupt synthesizer generates a second interrupt signal from the at least one valid first interrupt signal to notify the processor that an interrupt has been reported.
[0088] It is worth noting that this embodiment is described with each interrupt source including one interrupt (i.e., the interrupt source issues a first interrupt signal), but this embodiment is not limited to this. When the interrupt source includes multiple interrupts, that is, each interrupt source can issue multiple first interrupt signals, and the first interrupt signal triggered by each interrupt is transmitted to the interrupt receiver through the interrupt interface.
[0089] In summary, this embodiment can flexibly set and modify the required interrupt signals by pre-setting the interrupt mask, and complete the interrupt judgment process and interrupt reporting process respectively by using an interrupt receiver with AND gates and an interrupt synthesizer.
[0090] Considering the possibility of multiple interrupt sources simultaneously sending multiple interrupts, in an optional embodiment, the interrupt receiver further includes a register slice located at the back end of the interrupt synthesizer. The step of transmitting the first interrupt signal to the interrupt synthesizer to generate the second interrupt signal if the first interrupt signal is a valid signal further includes: the register slice buffering and delaying the signal transmitted by the interrupt synthesizer, wherein the signal transmitted by the interrupt synthesizer includes at least the second interrupt signal generated by the interrupt synthesizer.
[0091] In this embodiment, as Figure 3 As shown, the interrupt receiver also includes a register slice 400, which is used to buffer and delay the input signal. In this embodiment, the register slice 400 is a D flip-flop, used to buffer and delay the signal output by the interrupt synthesizer and transmit the second interrupt signal generated after the delay to the processor. This embodiment uses a register slice to buffer the second interrupt signal to facilitate interrupt timing management and to benefit the design and routing of backend hardware.
[0092] It is worth noting that this application does not require the specific form of the register slice, which can be other devices with buffering and delay functions. Those skilled in the art should select appropriate devices to implement the buffering and delay functions according to the actual application requirements, which will not be elaborated here.
[0093] Considering the large number of interrupts in large-scale on-chip system communication architectures and on-chip networks, in an optional embodiment, the multiple interrupt interfaces are divided into multiple interrupt groups. The interrupt synthesizer thus includes multiple first interrupt synthesizers and second interrupt synthesizers corresponding one-to-one with each interrupt group. The register slice thus includes multiple first register slices corresponding one-to-one with each first interrupt synthesizer and located at the back end of each first interrupt synthesizer, and second register slices located at the back end of each second interrupt synthesizer. The first interrupt synthesizer receives multiple valid first interrupt signals received through the interrupt interfaces of the corresponding interrupt group, and the second interrupt synthesizer receives signals output from the multiple first register slices. During the synthesis of the second interrupt signal, the first interrupt synthesizer synthesizes the valid first interrupt signals to generate a first interrupt synthesized signal and buffers the first interrupt synthesized signal in the first register slice. This first interrupt synthesized signal is the intermediate signal generated by the interrupt synthesizer. The second interrupt synthesizer synthesizes the first interrupt synthesized signals buffered in each first register slice to generate a second interrupt signal and buffers the second interrupt signal in the second register slice.
[0094] In a specific example, such as Figure 4 As shown, the interrupt sources include interrupt source 0 to interrupt source 11, and each interrupt source includes one interrupt, i.e., interrupt 0 to interrupt 11. The interrupt interface includes interrupt interface port0 to port11 corresponding to interrupt 0 to 11 respectively. The interrupt receiver includes: inverter 100, judge 200, first interrupt synthesizer 300, first register slice 400, second interrupt synthesizer 500, and second register slice 600 corresponding to each interrupt. The interrupt interface is divided into multiple interrupt groups, each of which includes multiple interrupt interfaces. For example, in this embodiment, interrupt interfaces port0-port3 form one interrupt group, interrupt interfaces port4-port7 form another, and interrupt interfaces port8-port11 form yet another. The interrupt masks corresponding to interrupts 0-11 are Int0_mask0-Int11_mask0, respectively. Inverter 100 inverts the interrupt masks; that is, an interrupt mask set to 0 indicates a required interrupt, and after inversion, it becomes 1 and is transmitted to the judge 200. The judge 200 is an AND gate, the first interrupt synthesizer 300 is an OR gate, the first register slice 400 is a D flip-flop, the second interrupt synthesizer 500 is an OR gate, and the second register slice 600 is a D flip-flop. In other words, this embodiment includes a two-level "interrupt synthesizer-register slice" structure.
[0095] Specifically, one or more of interrupts 0-11 send a first interrupt signal and transmit it to interrupt interfaces port0-port12. Each first interrupt signal is transmitted to one end of the judgment unit 200 via the corresponding interrupt interface. The first interrupt signal is ANDed with the inverted interrupt mask transmitted to the other end of the judgment unit 200 and a valid first interrupt signal is output. Valid first interrupt signals belonging to the same interrupt group are transmitted to the corresponding first interrupt synthesizer 300 to generate a first interrupt synthesized signal, and then to the first register slice 400 to generate a first interrupt synthesized register slice signal. The first interrupt synthesized register slice signals output by each interrupt group are transmitted to the second interrupt synthesizer 500 to generate a second interrupt synthesized signal, and then to the second register slice 600 to generate a second interrupt signal and transmit it to the processor. That is, the second interrupt signal is output through the two-level "interrupt synthesizer-register slice" structure, and the processor is notified of an interrupt report through the second interrupt signal.
[0096] In summary, this embodiment further buffers the first interrupt signal by setting up a two-level "interrupt synthesizer-register slice" structure to facilitate the design of interrupt management and control for large-scale on-chip system communication architecture and on-chip network.
[0097] It should be noted that register slices are used to buffer and delay interrupt signals. Those skilled in the art should understand that a single-level or multi-level "interrupt synthesizer-register slice" structure can be adopted depending on the actual scale of the SoC and NoC, which will not be elaborated here.
[0098] Considering the redundancy in interrupt source lookup when the processor receives the second interrupt signal and queries each interrupt source, in an optional embodiment, the processor querying the one or more interrupt sources based on the second interrupt signal to determine the interrupt corresponding to the first interrupt signal further includes: the processor querying the one or more interrupt sources to determine the interrupt corresponding to the valid interrupt signal after receiving the second interrupt signal further includes: the processor querying all interrupt sources corresponding to the interrupt mask based on the second interrupt signal to determine the interrupt to be responded to corresponding to the valid first interrupt signal.
[0099] The processor responding to the interrupt corresponding to the valid interrupt signal and clearing the valid interrupt signal further includes: the processor responding to each interrupt according to the priority of at least one interrupt and clearing the first interrupt signal corresponding to each interrupt.
[0100] In this embodiment, the processor further queries the allowed interrupts based on the interrupt mask set in the interrupt receiver, thereby speeding up the processor's query speed and avoiding querying for unauthorized interrupt sources.
[0101] Meanwhile, in this embodiment, after the processor finds at least one interrupt corresponding to a first interrupt signal, the processor responds to the interrupt according to the priority of each interrupt. For example, the processor's interrupt server responds to the interrupts in priority order and clears the interrupt flag, thereby realizing the processor's management and control of the processing flow of each interrupt.
[0102] Considering the problem that the processor has a long query path and a long cycle when querying each interrupt source after receiving the second interrupt signal, the processor querying the one or more interrupt sources according to the second interrupt signal to determine the interrupt corresponding to the first interrupt signal further includes: the processor querying the interrupt status register corresponding to the interrupt mask according to the second interrupt signal to determine the interrupt corresponding to the valid interrupt signal; wherein, each interrupt interface is connected to a corresponding interrupt status register to store the first interrupt signal received by the interrupt interface.
[0103] The processor responding to the interrupt corresponding to the first interrupt signal and clearing the first interrupt signal further includes: the processor responding to each interrupt according to the priority of the at least one interrupt, clearing the first interrupt signal, and clearing the interrupt status register.
[0104] In this embodiment, as Figure 5 As shown, each interrupt interface (port0-port11) is equipped with an interrupt status register (R0-R11). This register stores the corresponding first interrupt signal. When the processor queries the interrupt source based on the second interrupt signal, it can determine the interrupt corresponding to each first interrupt signal by checking the first interrupt signal stored in the interrupt status register. It should be noted that an interrupt source may include one or more interrupts. When each interrupt corresponds to only one interrupt event, the interrupt can be determined by checking the cached data in the interrupt status register. For example, the interrupt status register caches 8 bits or 16 bits of data, with different bits representing different interrupts. The processor can determine the interrupt source, interrupt, and interrupt event by checking the interrupt status register at the end of the interrupt interface. When there is an interrupt involving multiple interrupt events, the processor can determine the interrupt by checking the interrupt status register at the end of the interrupt interface, and then further check the interrupt status register of the interrupt source to determine the specific interrupt event. In summary, by setting the interrupt status register at the back end of the interrupt interface, the speed at which the processor queries each first interrupt signal can be improved, effectively reducing the cycle time taken by the processor to query the interrupt status register of each interrupt source; and the processor responds to the interrupt according to the priority of each interrupt and clears the interrupt flag and interrupt status register of the interrupt source to complete the interrupt processing, thereby realizing the processor's management and control of each interrupt and the processing flow, effectively improving the efficiency of interrupt management and control.
[0105] To further accelerate the processor's query for the interrupts corresponding to each first interrupt signal, the processor queries the interrupt status registers corresponding to the interrupt mask according to the second interrupt signal to determine the interrupt corresponding to the valid interrupt signal. This further includes: after receiving the second interrupt signal, the processor queries all interrupt status registers corresponding to the interrupt mask through a query channel to determine the interrupt corresponding to the valid interrupt signal; wherein, the query channel connects the processor and each interrupt status register.
[0106] This embodiment further accelerates the processor's interrupt query speed by setting up a query channel that directly connects the processor and each interrupt status register, thereby improving the efficiency of interrupt management and control.
[0107] Considering the presence of multiple processors in large-scale system-on-chip (SoC) communication architectures and on-chip networks, in an optional embodiment, there are multiple processors and multiple interrupt receivers. Each processor and interrupt receiver are in one-to-one correspondence, with each processor covering all interrupt interfaces; that is, each processor has one corresponding interrupt receiver, and all interrupt receivers are connected to the interrupt interfaces. Furthermore, different processors may have different processing capabilities. Each processor responds to received interrupts according to its different processing capabilities and clears the signals corresponding to those interrupts.
[0108] This embodiment addresses the scenario with multiple processors by configuring a corresponding interrupt receiver for each processor, thereby forming different "processor-interrupt receiver" interrupt management and control channels. Each processor covers the interrupt interface, meaning that each processor can handle all interrupts. Furthermore, different processing capabilities are configured for different processors based on their hardware resources and functions.
[0109] Specifically, such as Figure 6 As shown, it includes a first processor 1 and a second processor 2. Each processor is configured with a corresponding interrupt receiver. Each interrupt receiver receives the first interrupt signal sent by all interrupts from all interrupt sources. Each interrupt receiver includes an interrupt mask corresponding to each interrupt. For example, the interrupt mask of the interrupt receiver corresponding to the first processor 1 is Int0_mask0-Int11_mask0, and the interrupt mask of the interrupt receiver corresponding to the second processor 2 is Int0_mask1-Int11_mask1.
[0110] In a specific example, the interrupt source is a serial port. When the amount of data received by the serial port exceeds the 2KB storage threshold, a first interrupt signal is sent. The first processor 1 includes a first interrupt server for responding to interrupts, and the second processor 2 includes a second interrupt server for responding to interrupts. If the first processor is used for data transmission, the first interrupt server corresponding to the serial port interrupt of the first processor can transmit 2KB of data each time. If the second processor is used for computing functions, the second interrupt server corresponding to the serial port interrupt of the second processor can only transmit 0.5KB of data each time. By setting interrupt servers with different processing capabilities for processors with different hardware resources and functions, the management and control of interrupts can be flexibly set, changed, and expanded while ensuring the normal operation of the main functions of each processor. This enables flexible design of interrupt management and control for large-scale on-chip system communication architecture and on-chip network.
[0111] Corresponding to the interrupt control method provided in the above embodiments, an embodiment of this application also provides an interrupt control system that implements the above interrupt control method. Since the interrupt control system provided in this application corresponds to the interrupt control method provided in the above embodiments, the previous embodiments are also applicable to the interrupt control system provided in this embodiment, and will not be described in detail in this embodiment.
[0112] An embodiment of this application also provides an interrupt control system that implements the above-described interrupt control method, such as... Figures 2-6 As shown, the interrupt control system includes an interrupt interface, at least one processor, and interrupt receivers corresponding to each processor.
[0113] The interrupt receiver is used to receive a first interrupt signal sent by one or more interrupt sources connected to the interrupt interface, determine whether the first interrupt signal is a valid interrupt signal according to a preset interrupt mask and the first interrupt signal, and generate a second interrupt signal and transmit it to the processor if the first interrupt signal is a valid interrupt signal. The first interrupt signal is a level signal.
[0114] The processor is configured to query the one or more interrupt sources based on the received second interrupt signal to determine the interrupt corresponding to the valid interrupt signal, respond to the interrupt corresponding to the valid interrupt signal, and clear the first interrupt signal.
[0115] This embodiment achieves centralized management and control of interrupts through an interrupt handling system. Specifically, it achieves flexible management, control, and response to each interrupt through the process of "interrupt receiver receiving and judging interrupts—processor querying interrupts—processor responding to interrupts and clearing interrupts," effectively simplifying the complex interrupt management and control process in the prior art. For specific implementation details, please refer to the foregoing embodiment, which will not be repeated here.
[0116] In an optional embodiment, the interrupt receiver includes: an inverter for receiving interrupt masks corresponding to each of the first interrupt signals, an interrupt determiner, and an interrupt synthesizer, wherein...
[0117] The interrupt detector is used to determine whether the first interrupt signal is a valid interrupt signal based on the first interrupt signal and the interrupt mask inverted by the inverter. If the first interrupt signal is a valid interrupt signal, it is transmitted to the interrupt synthesizer.
[0118] The interrupt synthesizer is used to generate the second interrupt signal from the valid first interrupt signal and transmit it to the processor.
[0119] This embodiment allows for flexible setting and modification of required interrupt signals by pre-setting an interrupt mask in the processor, and completes the interrupt judgment and interrupt reporting processes respectively through an interrupt receiver equipped with AND gates and an interrupt synthesizer. For detailed implementation methods, please refer to the foregoing embodiments, which will not be repeated here.
[0120] In an optional embodiment, the interrupt receiver further includes a register slice disposed at the back end of the interrupt synthesizer for buffering and delaying signals transmitted by the interrupt synthesizer, the signals transmitted by the interrupt synthesizer including at least the second interrupt signal generated by the interrupt synthesizer.
[0121] This embodiment uses register slicing to buffer the second interrupt signal to facilitate interrupt timing management and backend hardware design. For detailed implementation, please refer to the foregoing embodiment; further details will not be repeated here.
[0122] In an optional embodiment, the plurality of interrupt interfaces are divided into a plurality of interrupt groups, the interrupt synthesizer includes a plurality of first interrupt synthesizers corresponding one-to-one with the interrupt groups, and a second interrupt synthesizer, the register slice includes a plurality of first register slices corresponding one-to-one with the first interrupt synthesizer and disposed at the back end of each first interrupt synthesizer, and a second register slice disposed at the back end of the second interrupt synthesizer, wherein the first interrupt synthesizer receives a valid first interrupt signal received by the corresponding interrupt group, and the second interrupt synthesizer receives a signal output by the plurality of first register slices;
[0123] The first interrupt synthesizer synthesizes the valid first interrupt signal to generate a first interrupt synthesized signal, and buffers the first interrupt synthesized signal into the first register slice;
[0124] The second interrupt synthesizer synthesizes the first interrupt signals buffered in each of the first register slices to generate a second interrupt signal, and buffers the second interrupt signal in the second register slice.
[0125] This embodiment further buffers the first interrupt signal by setting up a two-level "interrupt synthesizer-register slice" structure to facilitate the design of interrupt management and control for large-scale on-chip system communication architecture and on-chip network. For specific implementation details, please refer to the foregoing embodiments, which will not be repeated here.
[0126] In an optional embodiment, the interrupt control system further includes an interrupt status register disposed at the back end of each interrupt interface for storing the first interrupt signal so that the processor can query it to determine the interrupt corresponding to the first interrupt signal.
[0127] This embodiment stores the status of each first interrupt signal in an interrupt status register located at the back end of each terminal interface. The processor can then quickly identify the interrupt by querying the terminal status register, respond to each first interrupt signal according to its priority, and clear the interrupt flag to complete the interrupt handling, effectively improving the efficiency of interrupt management and control. For specific implementation details, please refer to the foregoing embodiment; they will not be repeated here.
[0128] In an optional embodiment, the interrupt control system further includes a polling channel directly connected to the processor and each interrupt status register.
[0129] The processor queries all interrupt status registers corresponding to the interrupt mask through the query channel according to the second interrupt signal to determine at least one interrupt corresponding to the at least one first interrupt signal.
[0130] This embodiment further accelerates the processor's interrupt lookup speed by setting up a query channel that directly connects the processor and each interrupt status register, thereby improving the efficiency of interrupt management and control. For detailed implementation methods, please refer to the foregoing embodiments, which will not be repeated here.
[0131] In an optional embodiment, for an interrupt control system that includes multiple processors,
[0132] The interrupt control system includes multiple processors, and each processor is provided with an interrupt receiver. All interrupt receivers are connected to an interrupt interface.
[0133] For each processor, it is used to respond to the received interrupts according to its processing capabilities and clear the corresponding interrupt signal.
[0134] This embodiment achieves flexible management and control of interrupts sent by different processors to different interrupt sources by setting up different "processor-interrupt receiver" interrupt management and control channels, and each interrupt management and control channel covers all interrupt sources. In particular, it uses interrupt servers with different processing capabilities to respond to interrupts based on the processing characteristics of different processors, thereby realizing the design of interrupt management and control for large-scale on-chip system communication architecture and on-chip network. For specific implementation methods, please refer to the foregoing embodiments, which will not be repeated here.
[0135] Based on the above-described interrupt control system, one embodiment of this application also provides a chip including the above-described interrupt control system.
[0136] The chip in this embodiment includes the aforementioned interrupt control system. By "receiving and judging interrupts - querying interrupts - responding to interrupts and clearing interrupts", it can achieve flexible management, control and response to each interrupt, effectively simplifying the complex interrupt management and control process in the prior art and improving interrupt management efficiency.
[0137] Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When executed by a processor, the program performs the following: the processor controls an interrupt receiver to receive a first interrupt signal from one or more interrupt sources, such that the interrupt receiver determines whether the first interrupt signal is a valid interrupt signal based on a preset interrupt mask and the first interrupt signal; if the first interrupt signal is a valid interrupt signal, it generates a second interrupt signal and transmits it to the processor, wherein the first interrupt signal is a level signal; the processor queries the one or more interrupt sources based on the second interrupt signal to determine the interrupt corresponding to the first interrupt signal; the processor responds to the interrupt corresponding to the first interrupt signal and clears the interrupt flag in the interrupt register of the interrupt source corresponding to the first interrupt signal.
[0138] In practical applications, the computer-readable storage medium can be any combination of one or more computer-readable media. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. For example, a computer-readable storage medium can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this embodiment, the computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.
[0139] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.
[0140] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.
[0141] Computer program code for performing the operations of this invention can be written in one or more programming languages or a combination thereof, including object-oriented programming languages such as Java, Smalltalk, and C++, as well as conventional procedural programming languages such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).
[0142] like Figure 7As shown, another embodiment of the present invention provides a structural schematic diagram of a computer device. Figure 7 The computer device 12 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of the present invention.
[0143] like Figure 7 As shown, the computer device 12 is represented in the form of a general-purpose computing device. The components of the computer device 12 may include, but are not limited to: one or more processors or processing units 16, system memory 28, and a bus 18 connecting different system components (including system memory 28 and processing unit 16).
[0144] Bus 18 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. For example, these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.
[0145] Computer device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by computer device 12, including volatile and non-volatile media, removable and non-removable media.
[0146] System memory 28 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write non-removable, non-volatile magnetic media (…). Figure 7 Not shown; usually referred to as a "hard drive"). Although Figure 7 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disk drive for reading and writing to a removable non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media) may be provided. In these cases, each drive may be connected to bus 18 via one or more data media interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.
[0147] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 42 typically perform the functions and / or methods described in the embodiments of the present invention.
[0148] Computer device 12 can also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), and with one or more devices that enable a user to interact with the computer device 12, and / or with any device that enables the computer device 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). This communication can be performed through input / output (I / O) interface 22. Furthermore, computer device 12 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) through network adapter 20. Figure 7 As shown, network adapter 20 communicates with other modules of computer device 12 via bus 18. It should be understood that, although... Figure 7 As not shown, it can be used in conjunction with computer device 12 with other hardware and / or software modules, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.
[0149] The processor unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing a centralized control interrupt control method provided in the embodiments of the present invention.
[0150] This invention addresses existing problems by providing a centralized interrupt control method, system, chip, computer device, and medium. It involves receiving a first interrupt signal in a voltage level form via an interrupt receiver, determining its validity based on a pre-set interrupt mask, and then reporting valid first interrupt signals to a processor. The processor queries the interrupt source based on the received first interrupt signal to identify, respond to, and clear the interrupt. This process of "receiving and judging interrupts—querying interrupts—responding to interrupts and clearing interrupts" enables flexible management, control, and response to each interrupt. It effectively simplifies the complex interrupt management and control process in existing technologies, significantly improves interrupt management and control efficiency, and has practical application value.
[0151] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. For those skilled in the art, other variations or modifications can be made based on the above description. It is impossible to exhaustively list all the implementation methods here. All obvious variations or modifications derived from the technical solutions of the present invention are still within the protection scope of the present invention.
Claims
1. A centralized interrupt control method, characterized in that, include: Each of the multiple processors is configured with a one-to-one interrupt receiver, and each interrupt receiver is connected to all interrupt interfaces. Each interrupt interface corresponds to one or more interrupt sources, and each interrupt receiver is configured with a one-to-one interrupt mask. The processor controls the corresponding interrupt receiver to receive the first interrupt signal sent by each interrupt source connected to the interrupt interface, so that the interrupt receiver determines whether the first interrupt signal is a valid interrupt signal according to the preset interrupt mask and the first interrupt signal. If the first interrupt signal is a valid interrupt signal, a second interrupt signal is generated and transmitted to the processor. The first interrupt signal is a level signal. After receiving the second interrupt signal, the processor queries the one or more interrupt sources to determine the interrupt corresponding to the valid interrupt signal; The processor responds to the interrupt corresponding to the valid interrupt signal and clears the valid interrupt signal.
2. The interrupt control method according to claim 1, characterized in that, The interrupt control method further includes: setting the interrupt mask in response to user operation or a pre-set configuration file; The interrupt receiver includes an interrupt synthesizer, and the interrupt control method further includes: The interrupt receiver receives a first interrupt signal sent by one or more interrupt sources connected to multiple interrupt interfaces. The interrupt receiver performs an AND operation based on the first interrupt signal and the corresponding interrupt mask to determine whether the first interrupt signal is a valid signal. If the first interrupt signal is a valid interrupt signal, then the second interrupt signal is generated by the interrupt synthesizer.
3. The interrupt control method according to claim 2, characterized in that, The interrupt receiver also includes a register slice located at the back end of the interrupt synthesizer, and the interrupt control method further includes: The register slice buffers and delays the signal transmitted by the interrupt synthesizer, wherein the signal transmitted by the interrupt synthesizer includes at least the second interrupt signal generated by the interrupt synthesizer.
4. The interruption control method according to claim 3, characterized in that, The plurality of interrupt interfaces include a plurality of interrupt groups, and the interrupt synthesizer thereby includes a plurality of first interrupt synthesizers and a second interrupt synthesizer corresponding one-to-one with the interrupt groups. The register slice thereby includes a plurality of first register slices corresponding one-to-one with the first interrupt synthesizers and disposed at the back end of each first interrupt synthesizer, and a second register slice disposed at the back end of the second interrupt synthesizer. The first interrupt synthesizer receives a plurality of valid first interrupt signals received by the interrupt interface of the corresponding interrupt group, and the second interrupt synthesizer receives signals output by the plurality of first register slices. The interrupt control method further includes: The first interrupt synthesizer synthesizes the valid first interrupt signal to generate a first interrupt synthesized signal, and buffers the first interrupt synthesized signal into the first register slice; The second interrupt synthesizer synthesizes the first interrupt signals buffered in each of the first register slices to generate a second interrupt signal, and buffers the second interrupt signal in the second register slice.
5. The interruption control method according to any one of claims 2 to 4, characterized in that, After receiving the second interrupt signal, the processor queries the one or more interrupt sources to determine the interrupt corresponding to the valid interrupt signal. This further includes: the processor queries all interrupt sources corresponding to the interrupt mask according to the second interrupt signal to determine the interrupt to be responded to corresponding to the valid first interrupt signal. The processor responding to the interrupt corresponding to the valid interrupt signal and clearing the valid interrupt signal further includes: the processor responding to each interrupt according to the priority of at least one interrupt and clearing the valid interrupt signal corresponding to each interrupt.
6. The interruption control method according to any one of claims 2 to 4, characterized in that, After receiving the second interrupt signal, the processor queries the one or more interrupt sources to determine the interrupt corresponding to the valid interrupt signal. This further includes: the processor queries the interrupt status register corresponding to the interrupt mask according to the second interrupt signal to determine the interrupt corresponding to the valid interrupt signal; wherein, each interrupt interface is connected to a corresponding interrupt status register for storing the first interrupt signal received by the interrupt interface. The processor responding to the interrupt corresponding to the valid interrupt signal and clearing the valid interrupt signal further includes: the processor responding to each interrupt according to the priority of at least one interrupt, clearing the valid interrupt signal and clearing the interrupt status register.
7. The interrupt control method according to claim 6, characterized in that, The processor further includes querying the interrupt status registers corresponding to the interrupt mask according to the second interrupt signal to determine the interrupt corresponding to the valid interrupt signal. This further includes: after receiving the second interrupt signal, the processor queries all interrupt status registers corresponding to the interrupt mask through a query channel to determine the interrupt corresponding to the valid interrupt signal; wherein, the query channel is connected to the processor and each interrupt status register.
8. An interrupt control system, characterized in that, It includes interrupt interfaces, at least one processor, and interrupt receivers corresponding to each processor. Each interrupt receiver is connected to all interrupt interfaces. Each interrupt interface corresponds to one or more interrupt sources. Each interrupt receiver is configured with an interrupt mask that corresponds to it. The interrupt receiver is used to receive the first interrupt signal sent by each interrupt source connected to each interrupt interface, and determine whether the first interrupt signal is a valid interrupt signal according to the preset interrupt mask and the first interrupt signal. If the first interrupt signal is a valid interrupt signal, a second interrupt signal is generated and transmitted to the processor. The first interrupt signal is a level signal. The processor is configured to query the one or more interrupt sources based on the received second interrupt signal to determine the interrupt corresponding to the valid interrupt signal, respond to the interrupt corresponding to the valid interrupt signal, and clear the valid interrupt signal.
9. The interrupt control system according to claim 8, characterized in that, The interrupt receiver includes an inverter for receiving the interrupt mask corresponding to each of the first interrupt signals, an interrupt detector, and an interrupt synthesizer, wherein... The interrupt detector is used to determine whether the first interrupt signal is a valid interrupt signal based on the first interrupt signal and the interrupt mask inverted by the inverter. If the first interrupt signal is a valid interrupt signal, it is transmitted to the interrupt synthesizer. The interrupt synthesizer is used to generate the second interrupt signal from the valid first interrupt signal and transmit it to the processor.
10. The interrupt control system according to claim 9, characterized in that, The interrupt receiver also includes a register slice located at the back end of the interrupt synthesizer for buffering and delaying signals transmitted by the interrupt synthesizer, wherein the signals transmitted by the interrupt synthesizer include at least the second interrupt signal generated by the interrupt synthesizer; and / or The interrupt control system also includes an interrupt status register located at the back end of each interrupt interface, used to store the first interrupt signal so that the processor can query and determine the interrupt corresponding to the first interrupt signal.
11. The interrupt control system according to any one of claims 8-10, characterized in that, The interrupt control system includes multiple processors, and each processor is provided with an interrupt receiver. All interrupt receivers are connected to an interrupt interface. For each processor, it is used to respond to the received interrupts according to its processing capabilities and clear the corresponding interrupt signal.
12. A chip, characterized in that, Including the interrupt control system as described in any one of claims 8-11.