Method of manufacturing a multilayer chip card and multilayer chip card

Abstract

A method of manufacturing a multilayer chip card and a multilayer chip card are disclosed. A core layer structure (2) having a front surface and a rear surface is provided, the core layer structure (2) comprising contact pads (20) on the front surface, further comprising an IC chip (10) and a conductor pattern, the IC chip (10) and the contact pads (20) not overlapping as seen in the front-rear direction; a front layer structure (1) is provided on the front surface of the core layer structure (2), the front layer structure having a through hole (5) whose cross-sectional shape substantially corresponds in size and position to the outer contour of the contact pads (20); a rear layer structure (3) is provided on the rear surface of the core layer structure (2); a label (50) is provided between the rear layer structure (3) and the core layer structure (2), the label (50) overlapping the contact pads (20) as seen in the front-rear direction and preferably having an outer contour which substantially corresponds in size and position to the outer contour of the contact pads (20); the stacked front layer structure, core layer structure and rear layer structure and label are laminated by applying heat and pressure to the stack.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a multilayer chip card (also known as an integrated circuit card or smart card), and a multilayer chip card, particularly a dual-interface chip card. A dual-interface chip card is a chip card that integrates an integrated circuit chip (IC chip), a metal contact pad for conductive communication with the IC chip, and an antenna for non-contact communication with the IC chip in its card structure. Background Technology

[0002] Typically, the IC chip and contact pads are provided as a chip module, in which they are mounted on opposite sides of a carrier substrate. Contact between the IC chip and the contact pads is achieved through the carrier substrate that supports them. The chip module is mounted within a cavity of the card body, such that its contact pads are flush with the outer surface of the card body, and the IC chip is concealed within this cavity. The antenna of a dual-interface chip card typically takes the form of an antenna coil embedded within the card body, with two antenna contact areas exposed within the cavity of the card body. When the chip module is mounted within the cavity, these contact areas make contact with corresponding contact areas on the underside of the chip module, thereby electrically connecting to the IC chip within the chip module.

[0003] EP 3 384 434 B1 discloses a dual-interface smart card in which an IC chip, contact pads, and an antenna are all disposed on the same flexible polyethylene terephthalate (PET) carrier substrate, which forms the core layer of the card body. The front layer has through-holes and is disposed on the front side of the core layer, so that the contact pads are accommodated in the through-holes. The rear layer has a cavity and is mounted on the rear side of the core layer, so that the IC chip is accommodated in the cavity. The IC chip and the contact pads are electrically connected to a conductor pattern on the core layer, and they do not overlap when viewed in the front-to-back direction.

[0004] According to EP 3 384 434 B1, firstly, in a hot-pressing stage, the core layer and the back layer are laminated into a stack at a temperature of at least 80°C and a pressure of 2 MPa for approximately 30 minutes. Then, in a cold-pressing stage, the core layer and the back layer are laminated at a temperature not exceeding 30°C and a pressure of 2 MPa for approximately 20 minutes. During lamination, the back layer softens, and the IC chip, which is disposed as a flip chip on the core layer, is extruded and embedded into the softened back layer. Next, after cooling, this laminated structure is laminated onto the front layer under the same conditions, wherein contact pads on the core layer protrude through vias in the front layer, thus forming a continuous flat plane with the front surface of the final laminated structure. Alternatively, the contact pads and the IC chip are disposed on the same side of the core layer, in which case the cavity for accommodating the IC chip is located on the rear side of the front layer. Summary of the Invention

[0005] The object of the present invention is to improve the appearance of the outer surface of a chip card including the core layer structure described above, wherein the chip card includes a core layer having at least one contact pad and an IC chip disposed thereon in a non-overlapping manner, and the core layer is laminated into the other layers of the chip card.

[0006] This objective is achieved by a method and a multilayer chip card as claimed in the appended independent claims. Preferred embodiments and specific features of the invention are defined in the dependent claims.

[0007] A first aspect of the present invention relates to a method for manufacturing a multilayer chip card, wherein the chip card comprises:

[0008] - A core layer structure having a front surface and a rear surface, wherein the core layer structure includes contact pads on the front surface, and also includes an IC chip and a conductor pattern, wherein the IC chip and the contact pads are conductively connected to the conductor pattern, and, viewed in the front-to-back direction, they do not overlap.

[0009] - A front layer structure disposed on the front surface of the core layer structure, wherein the front layer structure has a through-hole whose cross-sectional shape substantially corresponds in size and location to the outer contour of the contact pad on the front surface of the core layer structure.

[0010] - The rear layer structure set on the rear surface of the core layer structure, and

[0011] - A label positioned between the back layer and the core layer, wherein, viewed in the front-to-back direction, the label and the contact pad completely overlap or at least largely overlap.

[0012] Then, the stacked front layer structure, core layer structure, and back layer structure, as well as the label located between the core layer structure and the back layer structure, are laminated by applying heat and pressure to the stack. Since the cross-sectional shape of the through-holes substantially corresponds to the outer contour of the contact pads in terms of size and location, the contact pads pass through the through-holes during lamination and are preferably flush with the outer surface of the laminated stack.

[0013] A second aspect of the invention relates to a multilayer chip card having a corresponding structure. When the chip card to be manufactured is a dual-interface chip card, the core layer structure may further include an antenna, such as an antenna coil, conductively connected to the IC chip. Preferably, the IC chip and the contact pads are disposed on a common substrate, more preferably on opposite sides of the common substrate. Specifically, the IC chip and the contact pads may be laterally spaced from each other.

[0014] The label positioned between the back layer and the core layer structure functions to compensate for any unevenness that may occur on the front and / or back sides of the laminate. During lamination, the label generates localized pressure on the back side of the core layer structure, forcing the core layer structure, along with its front contact pad, into the through-holes of the front layer structure. That is, the contact pad is thinner than the front layer structure, and it should protrude through the front layer structure to be flush with the outer surface of the laminate. Therefore, the label material partially compensates for the lack of material in the through-holes.

[0015] Preferably, the outer contour of the label substantially corresponds in size and position to the outer contour of the contact pad on the front surface of the core layer structure. This ensures that the pressure generated by the label during lamination is evenly distributed across the entire area of ​​the contact pad.

[0016] Furthermore, the label thickness is preferably chosen to be the same as or greater than the thickness of the preceding layer structure. For example, the label thickness can be chosen to be 5% to 15% greater than the thickness of the preceding layer structure. As mentioned above, the volume of the label should compensate for the lack of material in the through-holes of the preceding layer structure. Overcompensation is better than undercompensation because the excess material will flow and distribute evenly between the layers. In a preferred embodiment, the thickness of the preceding layer structure is chosen to be 0.3 mm or slightly less, and the thickness of the label is chosen to be 0.3 mm or slightly greater.

[0017] Preferably, the label is made of ethylene glycol-modified polyethylene terephthalate (PETG) because of its low viscosity.

[0018] In a preferred embodiment, the core layer structure is formed by a first layer on which an IC chip is mounted and a second layer having an aperture, such that the IC chip on the first layer is accommodated within the aperture of the second layer. This reduces the force applied to the IC chip during lamination. More specifically, the aperture size is preferably larger than the IC chip size, so that when these two layers are laminated together with the remaining layers of the multilayer structure, the IC chip is accommodated within the aperture without bearing any force.

[0019] In one embodiment, the aperture in the second layer of the core structure may be in the form of a through-hole, and an adhesive is provided in the region of the through-hole to achieve an adhesive connection between the IC chip housed in the through-hole and the back layer structure when the second layer of the core structure comes into contact with the back layer structure.

[0020] Further preferably, at least one of the front and back layer structures is formed of at least two, preferably three, layers. For example, its inner layers may have properties that facilitate contact with the first layer of the aforementioned carrier contact pad or the aforementioned second layer of the IC chip housing. One or two of the inner layers may contain adhesive to improve adhesion to the core layer structure. The outer layers of the front and / or back layer structures provide good protection and / or scratch resistance. One layer (e.g., an intermediate layer) of the front and / or back layer structures may have good print quality and carry one or more printed patterns. For example, at least one layer of the front and / or back layer structures may be white, and / or at least one layer of the front and / or back layer structures may have printed patterns visible from the outside of the stack.

[0021] To further improve the appearance of the outer surface of the laminated stack, a release liner can be applied to one or both of the front and rear surfaces of the stack before the lamination step, preferably at least on the front surface, and removed after the lamination step. For this purpose, the release liner may comprise polyethylene terephthalate (PET), or is preferably made of PET. This release liner serves to protect the laminate from indentation, which could otherwise occur due to vias in the front layer structure. In summary, the appearance of the front and rear surfaces of the stack, and the final chip card, is improved.

[0022] Regarding the lamination process, it is preferable that the front layer structure, core layer structure, and rear layer structure are stacked and laminated together in a single lamination process. More preferably, when one or more of these layer structures include more than one layer, all layers of all layer structures are stacked and laminated together in a single lamination process.

[0023] The lamination process includes a first heating step at a first heating temperature and a second heating step at a second heating temperature higher than the first heating temperature, followed by a cooling step. This avoids the formation of air bubbles and the exposure of the antenna (if present). The first heating temperature can be set in the range of 120°C to 130°C, for example, 125°C, and the second heating temperature can be set in the range of 140°C to 150°C, for example, 145°C. Preferably, the first heating step is performed in a first laminator, and the second heating step is performed in a separate second laminator. Cooling can be performed, for example, at a temperature as low as 20°C. Cooling can be performed in the second laminator.

[0024] According to a preferred embodiment, the pressure increases during a first heating step, further increases during a second heating step, and preferably increases even further during a cooling step. For example, during the first heating step, the pressure may increase continuously or gradually from 3 bar to 15 bar, for example, through three sub-steps of 3 bar, 10 bar, and 15 bar. Similarly, during the second heating step, the pressure may increase continuously or gradually from 25 bar to 35 bar, for example, through two sub-steps of 25 bar and 35 bar. During the cooling step, the pressure may further increase continuously or gradually from 50 bar to 60 bar, for example, through two sub-steps of 50 bar and 60 bar.

[0025] The appropriate duration of the heating and cooling steps and sub-steps can be selected according to specific circumstances, especially depending on the material and thickness of the layers. The lamination temperatures and pressures described above have proven useful when most layers are made of polyvinyl chloride (PVC) and other layers are made of polyethylene terephthalate (PET), but they have also proven useful in other cases. Attached Figure Description

[0026] Figure 1 Multiple layers are shown in a decomposed diagram. Detailed Implementation

[0027] Preferred embodiments of the present invention will now be described with reference to the accompanying drawings, wherein... Figure 1 It is the only diagram that shows multiple layers 1.1 to 3.3 in an exploded view, which will be laminated together to form a multi-layer chip card, more specifically a dual-interface chip card.

[0028] In one embodiment, a first layer structure 1, also known as a front layer structure, is provided, which has through-holes 5 and consists of three layers 1.1, 1.2, and 1.3 in total. The front layer structure 1 may include more or fewer layers, and includes at least one layer.

[0029] The second layer structure 2 (also known as the core layer structure) includes at least layer 2.1, which carries contact pads 20 on its front surface and IC chip 10 on its rear surface. Antenna coils for antenna 30 are also provided on the front and rear surfaces. The conductor pattern on layer 2.1, which the IC chip 10 conductively connects to the contact pads 20 and antenna 30 (not shown in the figure), is used for electrical connections. Layer 2.1 may be made of polyethylene terephthalate (PET). The IC chip 10 can be mounted and connected to layer 2.1 and embedded in the polymer matrix using wire bonding technology, or mounted and connected using flip-chip technology. The conductor pattern (not shown), antenna 30, and contact pads 20 may be etched from an aluminum coating covering layer 2.1.

[0030] In the illustrated embodiment, the core layer structure further includes a second layer 2.2 having an aperture 40 in which the IC chip 10 is housed. The second layer 2.2 can be attached to the first layer 2.1 using an adhesive G, preferably disposed on the second layer 2.2. The aperture 40 can be in the form of a notch in layer 2.2, or it can be formed as a through-hole, as is currently the case. When these layers are stacked together, adhesive is filled into the aperture 40, thereby bonding the IC chip 10 to the next adjacent layer. The second layer 2.2 of the core layer structure 2 serves to protect the IC chip 10.

[0031] The third layer structure 3 (also known as the rear layer structure) comprises three layers 3.1, 3.2, and 3.3. The rear layer structure may include more or fewer layers, and includes at least one layer. The thickness and material of layers 3.1, 3.2, and 3.3 may correspond to the thickness and material of the corresponding layers 1.1, 1.2, and 1.3 of the front layer structure 1. The inner surfaces of the front layer structure 1 and the rear layer structure 3 are coated with adhesive G to achieve a strong bond with the core layer structure 2.

[0032] Furthermore, printed patterns P1 and / or P2 may be provided in one or both of the front layer structure 1 and the rear layer structure 3. For example, the central layers 1.2 and 3.2 of the front layer structure 1 and the rear layer structure 3 may be made of polyethylene terephthalate (PET), which may be colorless (i.e., transparent) and have printed patterns P2, P1 on either of its surfaces, or preferably white (i.e., opaque) and have printed patterns P2, P1 on the corresponding outer surfaces, as shown in the figure. Alternatively, one or both of the inner layers 1.3 and 3.3 may have printed patterns. Preferably, the inner layers 1.3 and 3.3 are made of polyvinyl chloride (PVC), more preferably of colorless (i.e., opaque) PVC. Finally, the outer layers 1.1 and 3.1 of the front layer structure 1 and the rear layer structure 3 may be colorless, and preferably also made of PVC. These layers are used to protect the layers and printed patterns within the multilayer structure. The aforementioned printed patterns are visible from the outside (i.e., visible to the user of the final chip card).

[0033] In embodiments where the core layer structure 2 comprises only a first layer 2.1 on which electronic components are mounted, the aperture 40 may be disposed in an adjacent rear layer structure 3, more specifically, in its layer 3.3. If the IC chip 10 is mounted together with the contact pad 20 on the front side of layer 2.1, the aperture 40 may be disposed in the front layer structure 1, more specifically, in its layer 1.3.

[0034] A label 50 is also provided. Viewed in the forward direction, the label 50 is precisely located behind the contact pad 20. That is, the contact pad 20 has an outer contour that substantially or precisely corresponds to the cross-sectional shape of the through hole 5, and the label 50 also has an outer contour that substantially or precisely corresponds to the outer contour of the contact pad. When layers 1.1 to 3.3 are stacked together, the contact pad 20 is pressed through the through hole 5, thereby becoming flush with the outer surface of the entire stack, and the label 50 behind the contact pad 20 supports this process.

[0035] Label 50 is made of PETG, a material with a low melting temperature and low viscosity, which allows it to flow easily when melted.

[0036] Layers 1.1 to 3.3 can be stacked in groups and spot-welded together before stacking and laminating to improve positioning accuracy. For example, layers 1.1 to 1.3 of the front layer structure 1 can be stacked into a first group and spot-welded together, for example, using a soldering iron. Through-holes 5 are then punched from the spot-welded stack of layers 1.1 to 1.3. Similarly, after punching holes 40 in layer 2.2 of the core layer structure 2, layers 2.1 and 2.2 of the core layer structure 2 can be stacked with layer 3.3 of the rear layer structure 3, with a label 50 positioned correctly between layers 2.2 and 3.3 to cover the contact pad 20. Layers 3.2 and 3.1 of the front layer structure are then stacked and spot-welded together to form a third group of spot-welded layers. The first and second groups of spot-welded layers are then stacked and transferred to a laminator, where all layers are laminated together to form a single multilayer structure.

[0037] It is obvious that the dimensions shown in the attached figures are not drawn to scale and should be understood only schematically. However, the thickness proportions of the individual layers are drawn to scale. That is, PVC layers 1.3, 2.2, and 3.3 may have a thickness of 150 micrometers, PVC layers 1.1 and 3.1 may have a thickness of 80 micrometers, PET layers 1.2 and 3.2 may have a thickness of 100 micrometers, and PET layer 2.1 with electronic components (also known as the "intercalation") may have a thickness of 40 micrometers, resulting in a total thickness of approximately 850 micrometers for the final laminated stack. The PETG label 50 may have a thickness of 300 micrometers, slightly larger than the combined thickness of layers 1.1 to 1.3 in the preceding layer structure 1.

[0038] The exposed surface of the back layer 3 can support other components, such as anti-counterfeiting element 60 (e.g., hologram), signature plate 70, magnetic strip 80, etc. The signature plate and magnetic strip can be applied to the exposed surface of layer 3.1 of the back layer 3 before the lamination step, while the hologram 60 can be applied after lamination, for example, during hot stamping.

[0039] The lamination process is carried out on two sequentially arranged laminators to minimize manufacturing time on a continuous production line. In the first laminator, the laminate is subjected to a temperature of 125°C for 480 seconds, 120 seconds, and 420 seconds at successively increasing pressures of 3 bar, 10 bar, and 15 bar, respectively. In the second laminator, the laminate is subjected to an even higher temperature of 145°C for 300 seconds and 720 seconds at successively increasing pressures of 25 bar and 35 bar, respectively. Finally, the laminate is subjected to a cooling step for 300 seconds and 720 seconds at successively increasing pressures of 50 bar and 60 bar and a temperature of 20°C, respectively. This avoids the formation of air bubbles and the exposure of the antenna 30. The cooling step can be carried out in the second laminator or a third laminator.

[0040] During the lamination step, a release liner (not shown) is provided at least on the front surface of the stack (i.e., on the outer surface of the front layer structure 1), preferably on both the front and rear surfaces of the stack before the lamination step, and removed after the lamination step. The release liner comprises polyethylene terephthalate (PET), or is preferably made of PET. The release liner may have a thickness of 0.05 mm.

[0041] It should be understood that these layers are typically provided in the form of large sheets on which corresponding electronic components, holes and apertures are arranged multiple times in a matrix (e.g., a 3×8 matrix), and finally individual chip cards are stamped out from the stack of sheets in an appropriate format (e.g., the ID-1 format specified in ISO 7810).

[0042] In addition to the visible printed patterns mentioned above (e.g., printed patterns P1 and P2), processing marks may also be provided on certain layers, which can also be provided in the form of printed patterns. For example, a printed pattern P2.2 may be provided on the second layer 2.2 of the core structure 2, and this printed pattern P2.2 may have the function of facilitating the identification of the location of the orifice 40 to be produced (e.g., produced by stamping). More specifically, as shown, the printed pattern P2.2 may completely cover the second layer 2.2 except for the area where the orifice 40 is to be produced, or it may be provided only partially, that is, precisely around the orifice 40. Alternatively, the printed pattern P2.2 may be precisely provided only in the area of ​​the orifice 40.

[0043] Similarly, for the printed pattern P2.2 on the second layer 2.2 of the core structure 2, a printed pattern P3.3 may be provided on the inner surface of the inner layer 3.3 of the third layer structure 3, and the printed pattern P3.3 may have the function of facilitating identification of the location where the label 50 will be placed before lamination. More specifically, as shown, the printed pattern P3.3 may completely cover the inner layer 3.3 except for the area where the label 50 is to be placed, or it may be provided only partially, that is, precisely around the area where the label 50 is to be placed. Alternatively, the printed pattern P3.3 may be provided only on the inner layer 3.3 and precisely in the area of ​​the label 50.

[0044] Finally, the printed pattern P1 can even serve to facilitate the identification of the location where the through-hole 5 will be generated in the first layer structure 2 (e.g., by stamping). More specifically, the printed pattern P1 can completely or partially cover the central layer 1.2, precisely leaving the area where the through-hole 5 will be generated, as shown in the figure.

[0045] Preferred embodiments of the invention are summarized in paragraphs 1 to 26 below:

[0046] 1. A method for manufacturing a multilayer chip card, comprising the following steps:

[0047] - A core structure (2) having a front surface and a rear surface is provided, wherein the core structure (2) includes a contact pad (20) on the front surface, and also includes an IC chip (10) and a conductor pattern, wherein the IC chip (10) and the contact pad (20) are electrically connected to the conductor pattern, and, viewed in the front-to-back direction, they do not overlap.

[0048] - A front layer structure (1) is provided on the front surface of the core layer structure (2), wherein the front layer structure (1) has a through hole (5) whose cross-sectional shape corresponds substantially to the outer contour of the contact pad (20) on the front surface of the core layer structure (2) in terms of size and location.

[0049] -Provide a back layer structure (3) on the back surface of the core layer structure (2),

[0050] - A label (50) is provided between the back layer structure (3) and the core layer structure (2), wherein, viewed in the front-to-back direction, the label (50) and the contact pad (20) completely overlap or at least largely overlap; and

[0051] - A front layer structure (1), a core layer structure (2), and a back layer structure (3) are laminated by applying heat and pressure to the laminate, and a label (50) is located between the core layer structure (2) and the back layer structure (3).

[0052] 2. The method as described in paragraph 1, wherein the outer contour of the label (50) substantially corresponds in size and position to the outer contour of the contact pad (20) on the front surface of the core structure (2).

[0053] 3. The method as described in paragraph 1 or 2, wherein the thickness of the label (50) is selected to be equal to or greater than the thickness of the preceding structure (1).

[0054] 4. The method as described in paragraph 3, wherein the thickness of the label (50) is selected to be 5% to 15% greater than the thickness of the preceding layer structure (1).

[0055] 5. The method as described in paragraph 3 or 4, wherein the thickness of the front layer structure (1) is selected to be 0.3 mm or less, and the thickness of the label (50) is selected to be 0.3 mm or greater.

[0056] 6. The method as described in any of paragraphs 1 to 5, wherein the label (50) is made of ethylene glycol-modified polyethylene terephthalate (PETG).

[0057] 7. The method as described in any of paragraphs 1 to 6, comprising the step of forming a core layer structure (2) from a first layer (2.1) on which an IC chip (10) is mounted and a second layer (2.2) having an aperture (40), such that the IC chip (10) on the first layer (2.1) is accommodated in the aperture (40) of the second layer (2.2).

[0058] 8. The method as described in paragraph 7, wherein the aperture (40) in the second layer (2.2) of the core structure (2) is a through-hole, and wherein the method further comprises the step of providing an adhesive in the region of the through-hole, thereby forming an adhesive bond between the IC chip (10) housed in the through-hole and the back layer structure (3) when the second layer (2.2) of the core structure (2) contacts the back layer structure (3).

[0059] 9. The method as described in any of paragraphs 1 to 8, comprising the step of forming at least one of a front layer structure (1) and a back layer structure (3) from a plurality of layers (1.1, 1.2, 1.3, 3.1, 3.2, 3.3).

[0060] 10. The method as described in paragraph 9, wherein, preferably, at least one layer (1.3, 3.3) of the front or rear layer structure is white, and one layer (1.2, 3.3) of the front or rear layer structure is provided with a printed pattern (P) visible from the outside of the stack.

[0061] 11. The method as described in any of paragraphs 1 to 10, comprising the steps of providing a release film on the front and rear surfaces of the stack prior to the lamination step and removing the release film after the lamination step.

[0062] 12. The method as described in paragraph 11, wherein the separator comprises polyethylene terephthalate (PET) or is made of PET.

[0063] 13. The method as described in any of paragraphs 1 to 12, wherein the front layer structure (1), the core layer structure (2), and the rear layer structure (3) are laminated together by a single lamination process.

[0064] 14. The method as described in paragraph 13, wherein one or more of the front layer structure (1), the core layer structure (2) and the rear layer structure (3) comprises more than one layer, and all layers (1.1, 1.2, 1.3, 2.1, 2.2, 3.1, 3.2, 3.3) of all layer structures (1, 2, 3) are laminated together by a single lamination process.

[0065] 15. The method as described in any of paragraphs 1 to 14, wherein the lamination step comprises a first heating step at a first heating temperature and a second heating step at a second heating temperature above the first heating temperature, followed by a cooling step.

[0066] 16. The method as described in paragraph 15, wherein the first heating temperature is set in the range of 120°C to 130°C, and the second heating temperature is set in the range of 140°C to 150°C.

[0067] 17. The method as described in paragraph 15 or 16, wherein the first heating step is performed in a first laminator and the second heating step is performed in a separate second laminator.

[0068] 18. The method as described in any of paragraphs 15 to 17, wherein the pressure increases during the first heating step, increases further during the second heating step, and increases even further during the cooling step.

[0069] 19. A multi-layer chip card, comprising:

[0070] - A core layer structure (2) having a front surface and a rear surface, wherein the core layer structure (2) includes a contact pad (20) on the front surface, and also includes an IC chip (10) and a conductor pattern, wherein the IC chip (10) and the contact pad (20) are electrically connected to the conductor pattern, and, viewed in the front-to-back direction, they do not overlap.

[0071] - A front layer structure (1) on the front surface of the core layer structure (2), wherein the front layer structure (1) has a through hole (5) whose cross-sectional shape corresponds substantially to the outer contour of the contact pad (20) on the front surface of the core layer structure (2) in terms of size and location.

[0072] -The rear layer structure (3) on the rear surface of the core layer structure (2), and

[0073] - A label (50) between the back layer structure (3) and the core layer structure (2), wherein, when viewed in the front-to-back direction, the label (50) and the contact pad (20) completely overlap or at least largely overlap.

[0074] 20. The multilayer chip card as described in paragraph 19, wherein the outer contour of the tag (50) substantially corresponds in size and position to the outer contour of the contact pad (20) on the front surface of the core structure (2).

[0075] 21. The multilayer chip card as described in paragraph 19 or 20, wherein the tag (50) is made of ethylene glycol-modified polyethylene terephthalate (PETG).

[0076] 22. The multilayer chip card as described in any of paragraphs 19 to 21, wherein the core structure (2) comprises a first layer (2.1) on which an IC chip (10) is mounted and a second layer (2.2) having an aperture (40) in which the IC chip (10) on the first layer (2.1) is accommodated.

[0077] 23. The multilayer chip card as described in any of paragraphs 19 to 22, wherein the core structure (2) includes an antenna (30) electrically connected to the IC chip (10).

[0078] 24. The multilayer chip card as described in paragraph 23, wherein the IC chip (10) and the contact pad (20) are disposed on a common substrate (2.1).

[0079] 25. The multilayer chip card as described in paragraph 24, wherein the IC chip (10) and the contact pad (20) are disposed on opposite sides of the common substrate (2.1).

[0080] 26. A multilayer chip card as described in any of paragraphs 19 to 25, wherein the IC chip (10) and the contact pad (20) are arranged laterally spaced from each other.

Claims

1. A method for manufacturing a multilayer chip card, comprising the following steps: - A core structure (2) having a front surface and a rear surface is provided, wherein the core structure (2) includes a contact pad (20) on the front surface, and also includes an IC chip (10) and a conductor pattern, wherein the IC chip (10) and the contact pad (20) are electrically connected to the conductor pattern, and, viewed in the front-to-back direction, they do not overlap. - A front layer structure (1) is provided on the front surface of the core layer structure (2), wherein the front layer structure (1) has a through hole (5) whose cross-sectional shape corresponds substantially to the outer contour of the contact pad (20) on the front surface of the core layer structure (2) in terms of size and location. -Provide a back layer structure (3) on the back surface of the core layer structure (2), - A label (50) is provided between the back layer structure (3) and the core layer structure (2), the thickness of the label (50) being selected to be equal to or greater than the thickness of the front layer structure (1), wherein, viewed in the front-to-back direction, the label (50) and the contact pad (20) completely overlap or at least largely overlap, wherein the label (50) is made of ethylene glycol-modified polyethylene terephthalate (PETG); and - A front layer structure (1), a core layer structure (2), and a back layer structure (3) are laminated by applying heat and pressure to the laminate, and a label (50) is located between the core layer structure (2) and the back layer structure (3).

2. The method as described in claim 1, wherein, The outer contour of the label (50) corresponds substantially to the outer contour of the contact pad (20) on the front surface of the core structure (2) in terms of size and position.

3. The method as described in claim 1 or 2, wherein, The thickness of the label (50) is selected to be 5% to 15% greater than the thickness of the front layer structure (1), and / or the thickness of the front layer structure (1) is selected to be 0.3 mm or less, and the thickness of the label (50) is selected to be 0.3 mm or greater.

4. The method as claimed in claim 1 or 2, comprising the step of forming a core layer structure (2) from a first layer (2.1) on which an IC chip (10) is mounted and a second layer (2.2) having an aperture (40), such that the IC chip (10) on the first layer (2.1) is accommodated in the aperture (40) of the second layer (2.2), and wherein the method further comprises the step of providing an adhesive in the region of the via, thereby forming an adhesive bond between the IC chip (10) accommodated in the via and the back layer structure (3) when the second layer (2.2) of the core layer structure (2) contacts the back layer structure (3).

5. The method of claim 4, wherein, The aperture (40) in the second layer (2.2) of the core structure (2) is a through hole.

6. The method of claim 1 or 2, comprising the step of forming at least one of a front layer structure (1) and a back layer structure (3) from a plurality of layers.

7. The method of claim 6, wherein, At least one layer of the front or back structure is white, and one layer of the front or back structure has a printed pattern visible from the outside of the stack.

8. The method of claim 1 or 2, comprising the steps of providing a release film on the front surface and the rear surface of the stack before the lamination step and removing the release film after the lamination step.

9. The method of claim 8, wherein, The separator membrane comprises polyethylene terephthalate (PET) or is made of PET.

10. The method as claimed in claim 1 or 2, wherein, The front layer structure (1), the core layer structure (2), and the rear layer structure (3) are laminated together in a single lamination process.

11. The method of claim 10, wherein, In cases where one or more of these layered structures comprise more than one layer, all layers of all the layered structures are laminated together in a single lamination process.

12. The method as claimed in claim 1 or 2, wherein, The lamination process includes a first heating step at a first heating temperature and a second heating step at a second heating temperature higher than the first heating temperature, followed by a cooling step.

13. The method of claim 12, wherein, The first heating temperature is set in the range of 120°C to 130°C, the second heating temperature is set in the range of 140°C to 150°C, and / or the first heating step is performed in the first laminator, and the second heating step is performed in a separate second laminator.

14. The method of claim 12, wherein, The pressure increases during the first heating step, increases further during the second heating step, and increases even more during the cooling step.

15. A multi-layer chip card, comprising: - A core layer structure (2) having a front surface and a rear surface, wherein the core layer structure (2) includes a contact pad (20) on the front surface, and also includes an IC chip (10) and a conductor pattern, wherein the IC chip (10) and the contact pad (20) are electrically connected to the conductor pattern, and, viewed in the front-to-back direction, they do not overlap. - A front layer structure (1) on the front surface of the core layer structure (2), wherein the front layer structure (1) has a through hole (5) whose cross-sectional shape corresponds substantially to the outer contour of the contact pad (20) on the front surface of the core layer structure (2) in terms of size and location. -The rear layer structure (3) on the rear surface of the core layer structure (2), and - A label (50) between the back layer structure (3) and the core layer structure (2), the thickness of the label (50) being selected to be equal to or greater than the thickness of the front layer structure (1), wherein, viewed in the front-back direction, the label (50) and the contact pad (20) completely overlap or at least largely overlap, wherein the label (50) is made of ethylene glycol modified polyethylene terephthalate (PETG).

16. The multilayer chip card as described in claim 15, wherein, The outer contour of the label (50) substantially corresponds in size and position to the outer contour of the contact pad (20) on the front surface of the core structure (2), and / or the label (50) is made of ethylene glycol-modified polyethylene terephthalate (PETG).

17. The multilayer chip card as described in claim 15 or 16, wherein, The core structure (2) includes a first layer (2.1) on which an IC chip (10) is mounted and a second layer (2.2) having an aperture (40) in which the IC chip (10) on the first layer (2.1) is housed.

18. The multilayer chip card as described in claim 15 or 16, wherein, The core structure (2) includes an antenna (30) that is electrically connected to the IC chip (10).

19. The multilayer chip card as described in claim 18, wherein, The IC chip (10) and the contact pad (20) are disposed on a common substrate.

20. The multilayer chip card as described in claim 19, wherein, The IC chip (10) and the contact pad (20) are disposed on opposite sides of the common substrate.

21. The multilayer chip card as described in claim 15 or 16, wherein, The IC chip (10) and the contact pad (20) are arranged laterally spaced from each other.

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