Method for manufacturing a semiconductor device and semiconductor device
By injecting nitrogen into the gate layer of the DRAM device and gradually reducing its concentration to lower the work function value, the gate-induced drain leakage problem was solved, and the electrical performance of the device was maintained.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2021-11-02
- Publication Date
- 2026-08-04
AI Technical Summary
Gate-induced drain leakage (GIDL) is a serious problem in existing DRAM devices, affecting device performance and being difficult to reduce effectively.
Nitrogen is injected into the gate layer, and its concentration is gradually reduced from the top down. The electric field strength in the overlapping region of the gate layer with the source and drain is reduced by adjusting the work function value of the gate layer.
It effectively reduces the electric field strength in the overlapping region of the gate layer and drain, improves the GIDL phenomenon, and does not increase the gate layer resistance, thus maintaining other electrical properties of the device.
Smart Images
Figure CN116092927B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a semiconductor device and the semiconductor device thereof. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device. Its memory cells consist of one transistor and one capacitor, a 1T1C structure. In the transistor, the gate electrode is connected to the word line, one end of the source / drain region is connected to the bit line, and the other end is connected to the DRAM's storage capacitor.
[0003] In DRAM transistors, gate layers are incorporated. Fabricating these gate layers can easily lead to gate-induced drain leakage (GIDL) current, a major pathway causing leakage in DRAM. Therefore, effectively reducing GIDL without affecting other performance characteristics of semiconductor devices remains a challenge.
[0004] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention
[0005] This disclosure provides a method for fabricating a semiconductor device that can improve gate-induced drain leakage, and the process is simple and does not affect other electrical properties of the semiconductor device.
[0006] This disclosure also provides a semiconductor device that can effectively improve gate-induced drain leakage and has stable other electrical properties.
[0007] According to one aspect of this disclosure, a method for fabricating a semiconductor device is provided, comprising: providing a semiconductor substrate; etching the semiconductor substrate to form a gate trench; forming a gate layer in the gate trench; implanting nitrogen into the gate layer; wherein the concentration of nitrogen in the gate layer gradually decreases from the top of the gate layer downwards.
[0008] According to an exemplary embodiment of this disclosure, the implantation of nitrogen into the gate layer is performed using an ion implantation process, wherein the ion implantation energy is 3–10 keV and the implantation dose is 7.0e+15–3.0e+16 atoms / cm². 2 .
[0009] According to an exemplary embodiment of the present disclosure, the semiconductor substrate includes a substrate of a first doping type and an active region of a second doping type. Etching the semiconductor substrate to form a gate trench includes: etching from the active region toward the substrate to form the gate trench; after etching the semiconductor substrate to form the gate trench, the method further includes: filling the gate trench with a dielectric layer.
[0010] According to an exemplary embodiment of the present disclosure, before implanting nitrogen into the gate layer, the method further includes: depositing an implantation barrier layer on the surface of the active region.
[0011] According to an exemplary embodiment of this disclosure, the thickness of the injection barrier layer is 50–70 nm.
[0012] According to an exemplary embodiment of this disclosure, the implantation barrier layer and the dielectric layer are both made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.
[0013] According to an exemplary embodiment of the present disclosure, after implanting nitrogen into the gate layer, the method further includes: filling the gate trench with an insulating capping layer; and removing the implantation barrier layer and the insulating capping layer located above the active region.
[0014] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a semiconductor substrate, a gate trench, and a gate layer. The gate trench is disposed within the semiconductor substrate; the gate layer is located within the gate trench, and at least a portion of the gate layer is doped with nitrogen, wherein the concentration of nitrogen gradually decreases downwards from the top of the gate layer.
[0015] According to an exemplary embodiment of the present disclosure, the semiconductor substrate includes a substrate of a first doping type and an active region of a second doping type, the active region being disposed on the substrate; wherein the gate trench extends from the active region toward the substrate.
[0016] According to an exemplary embodiment of the present disclosure, within a first preset depth range of the gate layer, the work function of the gate layer gradually increases from the top down; within a range of the gate layer from the maximum value of the first preset depth to the bottom of the gate layer, the work function of the gate layer is the same, and is 0.3 to 0.6 eV greater than the work function of the gate layer located within the first preset depth range.
[0017] According to an exemplary embodiment of this disclosure, the first preset depth range is 0 to 20 nm.
[0018] According to an exemplary embodiment of this disclosure, the gate layer is made of TiN. xWhere x represents a numerical value, and within the first preset depth range, x is greater than 1 and gradually decreases from the top of the gate layer downwards; within the range from the maximum value of the first preset depth to the bottom of the gate layer, x = 1.
[0019] According to an exemplary embodiment of the present disclosure, the gate layer includes a first gate material layer and a second gate material layer, wherein the first gate material layer is located on the second gate material layer; wherein the first gate material layer is doped with nitrogen, and the second gate material layer is not doped with nitrogen.
[0020] According to an exemplary embodiment of the present disclosure, the first gate material layer is made of TiN. x The material of the second gate material layer is W; where x represents a value, x is greater than 1, and x gradually decreases from the top of the first gate material layer downwards.
[0021] According to an exemplary embodiment of the present disclosure, the semiconductor device further includes a dielectric layer disposed on the inner wall of the gate trench; and a transition layer disposed between the dielectric layer and the second gate material layer.
[0022] According to an exemplary embodiment of this disclosure, the transition layer is made of TiN.
[0023] According to an exemplary embodiment of the present disclosure, the semiconductor device further includes an insulating capping layer covering the gate layer.
[0024] As can be seen from the above technical solution, this disclosure possesses at least one of the following advantages and positive effects:
[0025] In this embodiment, by injecting nitrogen into the gate layer, the amount of nitrogen doped in the gate layer gradually decreases from the top of the gate layer downwards, which can effectively reduce the work function value of the gate layer, thereby reducing the electric field strength in the overlapping region of the gate layer with the source and drain, improving the GIDL phenomenon. The process is simple, and it does not increase the resistance of the gate layer or affect other electrical properties of the semiconductor device. Attached Figure Description
[0026] The above and other features and advantages of this disclosure will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.
[0027] Figure 1 A method for fabricating a semiconductor device according to an exemplary embodiment of this disclosure;
[0028] Figure 2 This is a schematic diagram of a semiconductor substrate according to an exemplary embodiment of the present disclosure;
[0029] Figure 3This is a schematic diagram of forming a gate trench on a semiconductor substrate, which is an exemplary embodiment of the present disclosure;
[0030] Figure 4 This is a schematic diagram of forming a dielectric layer and an implantation barrier layer on a semiconductor substrate, which is an exemplary embodiment of the present disclosure.
[0031] Figure 5 This is a schematic diagram of filling a gate material on a semiconductor substrate according to an exemplary embodiment of the present disclosure;
[0032] Figure 6 This is a schematic diagram illustrating the formation of a gate layer by etching back the gate material of a semiconductor substrate, as an exemplary embodiment of the present disclosure.
[0033] Figure 7 This is a schematic diagram of nitrogen implantation into the gate layer, which is an exemplary embodiment of the present disclosure.
[0034] Figure 8 This is a schematic diagram of forming an insulating capping layer on a semiconductor substrate, which is an exemplary embodiment of the present disclosure;
[0035] Figure 9 This is a schematic diagram of a semiconductor device with the injection barrier layer and the insulating capping layer located above the active region removed, as an exemplary embodiment of the present disclosure.
[0036] Figure 10 This is a schematic diagram of a semiconductor device according to another exemplary embodiment of the present disclosure;
[0037] Figure 11 This is a test result diagram of nitrogen doping in the gate layer, which is an exemplary embodiment of this disclosure.
[0038] Explanation of reference numerals in the attached figures:
[0039] 1. Semiconductor substrate; 11. Substrate; 12. Active region; 13. Shallow trench isolation; 2. Gate trench; 3'. Gate material; 3. Gate layer; 31. First gate material layer; 32. Second gate material layer; 33. Transition layer; 4. Dielectric layer; 5. Implantation barrier layer; 6. Insulating cap layer; d. Thickness of implantation barrier layer; A. Overlapping region. Detailed Implementation
[0040] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.
[0041] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and not as numerical limitations on the object.
[0042] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.
[0043] In addition, in the description of this disclosure, "multiple" means at least two, such as two, three, etc., unless otherwise expressly and specifically limited.
[0044] During the study of GIDL (Glass Injection Drainage), it was discovered that one of the causes of GIDL leakage is the intensity of the electric field in the overlapping region between the gate layer and the source / drain electrodes. The greater the electric field intensity in this overlapping region, the more severe the GIDL. This overlapping region can be understood as follows: the semiconductor substrate includes a substrate and an active region, with the active region located above the substrate. The difference between the active region and the substrate lies in their different doping types, resulting in different electrical properties. The active region contains source / drain regions. The gate layer is typically formed within the substrate and the active region; for example, the gate layer can be a buried gate. Therefore, the gate layer located in the active region will have a vertical overlap with the source / drain electrodes located in the active region.
[0045] To reduce the electric field strength in the overlapping region, related technologies use polysilicon, which has a lower work function, to replace part of the gate layer, which has a higher work function, thus improving the GIDL situation. However, since the resistivity of polysilicon is about two orders of magnitude higher than that of the gate layer, the more polysilicon there is, the greater the resistance of the gate layer, resulting in a decrease in the transistor's turn-on speed. This leads to a series of problems. For example, to ensure the transistor's turn-on speed, the length of the gate layer must be shortened, but a shorter gate layer limits the size of the memory array, affecting the chip area. Furthermore, when the gate layer contains tungsten (W), the polysilicon and tungsten react at high temperatures, forming WSi at the interface, affecting interface quality and further increasing resistance.
[0046] Further research has led to the provision of a method for fabricating a semiconductor device. For example... Figures 1 to 11 As shown, where, Figure 1 This disclosure illustrates a method for fabricating a semiconductor device according to an embodiment of the present disclosure. Figures 2 to 8 The diagram shows the structure of semiconductor substrate 1 at different stages of the fabrication process. Figure 9 and Figure 10 Schematic diagrams of the semiconductor devices in different embodiments are shown. Figure 11 The diagram shows a test result of nitrogen doping in the gate layer according to an embodiment of this disclosure. The method for fabricating a semiconductor device according to an embodiment of this disclosure includes:
[0047] Step S200: Provide semiconductor substrate 1.
[0048] Step S400: Etch semiconductor substrate 1 to form gate trench 2.
[0049] Step S600: Form a gate layer 3 within the gate trench 2.
[0050] Step S800: Nitrogen element is implanted into the gate layer 3. The concentration of nitrogen element in the gate layer 3 gradually decreases from the top of the gate layer 3 downwards.
[0051] The semiconductor device fabrication method of this disclosure, by injecting nitrogen element into the gate layer 3, so that the nitrogen element doped in the gate layer 3 gradually decreases from the top of the gate layer 3 downwards, can effectively reduce the work function value of the gate layer 3, thereby reducing the electric field strength in the overlapping region of the gate layer 3 and the drain, improving the GIDL phenomenon. The process is simple, and at the same time, it does not increase the resistance of the gate layer 3 and does not affect other electrical properties of the semiconductor device.
[0052] The method for fabricating a semiconductor device according to embodiments of this disclosure will now be described in detail.
[0053] Step S200: Provide semiconductor substrate 1.
[0054] like Figure 2 As shown, the semiconductor substrate 1 includes a substrate 11 of a first doped type and an active region 12 of a second doped type, with the active region 12 formed on the substrate 11. In fact, the active region 12 and the substrate 11 are integral, both being part of the semiconductor substrate 1. By implanting different dopant particles, the substrate 11 and the active region 12 have different doping characteristics, and therefore different electrical properties. The active region 12 includes source / drain regions. The substrate 11 is of the first doped type, such as P-type, formed by implanting P-type dopant ions, for example, implanting B; the active region 12 is of the second doped type, such as n-type, formed by implanting N-type dopant ions, for example, implanting P or As. Of course, this is not a limitation; the doping types of the substrate 11 and the active region 12 can be changed according to actual needs. To distinguish the substrate 11 and the active region 12, a dashed line is drawn on the semiconductor substrate 1 in the accompanying drawings of this disclosure as a boundary separating the two. The area above the dashed line is the active region 12, and the area below the dashed line is the substrate 11. (Reference) Figure 9 Since the source / drain regions are located in the active region 12, the overlapping region A of the gate layer 3 and the active region 12 is the overlapping region of the gate layer and the source and drain mentioned above. The fabrication method of this embodiment can reduce the electric field strength of the overlapping region of the semiconductor device.
[0055] In one embodiment, the semiconductor substrate 1 of this disclosure may be made of silicon, silicon carbide, silicon nitride, silicon-on-insulator, silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, silicon-germanium-on-insulator, or germanium-on-insulator.
[0056] Continue to refer to Figure 2 A shallow trench isolation 13 is formed on the semiconductor substrate 1, which separates each adjacent active region 12. The shallow trench isolation 13 can be made of silicon nitride or silicon oxide to achieve electrical isolation between multiple active regions 12.
[0057] It should be noted that in the embodiments of this disclosure, "above" or "below" refers to the relative positional relationship between different components in a semiconductor device. In the embodiments of this disclosure, the active region 12 is located above the substrate 11, which can be understood as the direction from the active region 12 toward the substrate 11 being from top to bottom. The use of the above-mentioned technical terms representing relative positions is merely for ease of explanation and is not intended to be limiting.
[0058] Step S400: Etch semiconductor substrate 1 to form gate trench 2.
[0059] like Figure 3As shown, a gate trench 2 is formed by etching from the active region 12 of the semiconductor substrate 1 towards the substrate 11, i.e., the gate trench 2 extends from the active region 12 towards the substrate 11. Of course, the gate trench 2 is not only formed in the active region 12, but can also be formed in the shallow trench isolation 13, such as... Figure 3 As shown, the gate trenches 2 located on the left and right sides are formed by etching shallow trench isolation 13. From Figure 3 As can be seen, the depth of the gate trench 2 formed by etching the shallow trench isolation 13 is greater than the depth of the gate trench 2 formed by etching the active region 12. This is mainly due to the different etching selectivity of the etchant for different materials. The difference in the depth of the gate trench 2 does not affect the formation of the gate layer 3.
[0060] The gate trench 2 can be formed using either a dry etching process or a wet etching process. A dry etching process can be a plasma etching process. The etching gas used in a plasma etching process can be chlorine gas. By controlling the amount of etching gas used, the etching degree can be controlled, thereby controlling the depth and critical dimensions of the gate trench 2. A wet etching process can use concentrated sulfuric acid and hydrogen peroxide as etchants. By adjusting the concentration of the etchant, the etching degree can also be controlled, thereby controlling the depth and critical dimensions of the gate trench 2. Those skilled in the art can choose the above etching process according to the actual situation; no special limitations are made here.
[0061] In some embodiments, such as Figure 4 As shown, after the gate trench 2 is formed, a dielectric layer 4 can be filled inside the gate trench 2. That is, a dielectric layer 4 is formed on the inner wall of the gate trench 2.
[0062] The dielectric layer 4 can be made of at least one of silicon oxide, silicon nitride, and silicon oxynitride. The dielectric layer 4 can be formed by an oxidation process such as wet or dry oxidation in an environment including oxides, water vapor, nitric oxide, or combinations thereof, or by an in-situ steam generation (ISSG) process in an environment including oxygen, water vapor, nitric oxide, or combinations thereof, or by chemical vapor deposition (CVD) using tetraethyl orthosilicate (TEOS) and oxygen as precursors, or by an atomic layer deposition process.
[0063] In some embodiments, such as Figure 4As shown, while forming the dielectric layer 4, the same process can be used to form an implantation barrier layer 5 on the surface of the active region 12. The material of the implantation barrier layer 5 can be the same as that of the dielectric layer 4, such as silicon oxide, silicon nitride, and silicon oxynitride. In subsequent processes, since nitrogen will be implanted into the gate layer 3, the implantation barrier layer 5 can prevent the nitrogen from being implanted into the active region 12, thus avoiding changes in the electrical properties of the active region 12 due to nitrogen doping. Furthermore, forming the implantation barrier layer 5 simultaneously with the dielectric layer 4 allows for the formation of two layers using the same process, simplifying the manufacturing process.
[0064] Of course, the dielectric layer 4 and the injection barrier layer 5 can also be formed using different processes, and their materials can also be different. The choice can be made based on the actual situation; no special restrictions are imposed here.
[0065] In some other embodiments, the implantation barrier layer 5 may be formed on the surface of the active region 12 after the dielectric layer 4 is formed. That is, the implantation barrier layer 5 can be formed as long as it is formed before nitrogen is implanted. Those skilled in the art can determine the timing of the formation of the implantation barrier layer 5 according to the actual process conditions, and no special limitation is made here.
[0066] In some embodiments, the thickness d of the implantation barrier layer 5 is 50–70 nm. In some embodiments, the thickness d of the implantation barrier layer 5 can be 55 mm, 60 mm, or 65 mm, without particular limitation. Within this thickness range, nitrogen elements can be effectively blocked from being implanted into the active region 12, thus avoiding affecting the electrical performance of the active region 12.
[0067] Step S600: Form a gate layer 3 within the gate trench 2.
[0068] like Figure 5 As shown, in some embodiments, a deposition process can be used to fill the gate trench 2 with gate material 3'. This gate material 3' can fill above the active region 12. For example... Figure 6 As shown, the gate material 3' is etched back to a predetermined depth according to the required gate layer 3 size to form the gate layer 3 in the gate trench 2.
[0069] The gate material 3' can be etched back using a dry etching method, such as plasma etching. By controlling the amount of etching gas, the thickness of the gate layer 3 can be precisely controlled. In some embodiments, the gate material 3' can be TiN, and the deposition process can be atomic deposition or chemical vapor deposition; no special limitation is made here.
[0070] In other embodiments, such as Figure 10As shown, the gate layer 3 may include a first gate material layer 31, a second gate material layer 32, and a transition layer 33. The gate layer 3 is formed as follows: a transition layer 33 is formed on the dielectric layer 4 using a deposition process; then, a second gate material layer 32 with a predetermined height is deposited upwards from the bottom of the space enclosed by the transition layer 33, the second gate material layer 32 not filling the gate trench 2; subsequently, a first gate material layer 31 of the required height is deposited on the second gate material layer 32. In some embodiments, the material of the first gate material layer 31 may be TiN as described in the above embodiments, the second gate material layer 32 may be tungsten (W), the transition layer 33 may be TiN, or the material of the transition layer 33 may be the same as that of the first gate material layer 31.
[0071] Since the first gate material layer 31 is located on the upper part of the gate layer 3, in subsequent processes, the first gate material layer 31 can be additionally doped with nitrogen to effectively reduce the work function value at the top of the gate layer 3, thereby reducing the electric field strength in the overlapping region of the gate layer 3 with the source and drain, improving the GIDL phenomenon, and without increasing the resistance. The second gate material layer 32 is located on the lower part of the gate layer 3. It is not doped with nitrogen and uses tungsten metal with low resistivity, which can further ensure that this part of the gate layer 3 has good conductivity and ensure that the transistor can be turned on quickly. Since grain boundary dislocations or stress are prone to occur at the junction of the metal W and the dielectric layer 4, the junction of the gate layer 3 and the dielectric layer 4 is unstable and prone to defects. To overcome this problem, a transition layer 33 is provided between the dielectric layer 4 and the second gate material layer 32. The transition layer 33 can better bond with the dielectric layer 4 and also better bond with the second gate material layer 32, making the formed gate layer 3 more stable and overcoming the above-mentioned defects.
[0072] Step S800: Nitrogen element is implanted into the gate layer 3. The concentration of nitrogen element in the gate layer 3 gradually decreases from the top of the gate layer 3 downwards.
[0073] like Figure 7 As shown, nitrogen is implanted from the surface of gate layer 3. Nitrogen implantation can be performed using ion implantation, a conventional technique in this field, and its specific execution process will not be detailed here. In the ion implantation process of the embodiments of this disclosure, the ion implantation energy can be 3–10 keV, for example, 5 keV, 7 keV, 8 keV, or 9 keV, and the implantation dose can be 7.0e+15–3.0e+16 atoms / cm². 2 For example, the injection dose could be 9.0e+15 atoms / cm. 2 1.0e+16 atoms / cm 2 2.0e+16 atoms / cm2 2.5e+16 atoms / cm 2 The implantation dose can be understood as the amount of nitrogen element implanted as set by the ion implantation device. Tests have shown that when the concentration of nitrogen doped in gate layer 3 is greater than 1.0e+21cm... -3 When the work function of the gate layer 3 can be changed, those skilled in the art can set the parameters of the ion implantation device within the above range according to the actual situation, without any special limitation.
[0074] By adjusting the injection energy and injection dose within the above range, nitrogen can be additionally doped into the gate layer 3 at the required depth, and the nitrogen doping concentration can be gradually reduced from the top of the gate layer 3 downwards. This not only avoids GIDL leakage but also ensures that other electrical properties of the gate layer 3 function normally.
[0075] like Figure 8 As shown, in some embodiments, after doping the gate layer 3 with nitrogen, the method of this disclosure may further include:
[0076] Step S1000: Fill the gate trench 2 with insulating capping layer 6.
[0077] like Figure 8 As shown, an insulating capping layer 6 is filled into the gate trench 2 using a deposition process to cover the gate layer 3, and the insulating capping layer 6 at least fills the gate trench 2 so that the top of the gate layer 3 is electrically isolated from other semiconductor devices located above it.
[0078] In some embodiments, the insulating capping layer 6 can be formed by atomic deposition or chemical vapor deposition. The insulating capping layer 6 can be made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.
[0079] Step S1200: Remove the injection barrier layer 5 and the insulating capping layer 6 located above the active region 12.
[0080] like Figure 9 As shown, the implantation barrier layer 5 and the insulating capping layer 6 located above the active region 12 can be removed using a chemical mechanical polishing process. In some embodiments, the area above the active region 12 can be ground flat so that the insulating capping layer is flush with the surface of the active region 12, so as to facilitate the formation of other semiconductor devices above the active region 12, which is beneficial for process planarization.
[0081] In the preparation method of this embodiment, by additionally injecting nitrogen element into the gate layer 3, the nitrogen element doped in the gate layer 3 gradually decreases from the top of the gate layer 3 downwards, which can effectively reduce the work function value at the top of the gate layer 3, thereby reducing the electric field strength in the overlapping region of the gate layer 3 and the drain, improving the GIDL phenomenon. The process is simple, and it does not increase the resistance of the gate layer 3, nor does it affect other electrical properties of the semiconductor device.
[0082] According to another aspect of this disclosure, a semiconductor device is provided, which is fabricated using the fabrication method described in the above embodiments. For example... Figure 9 and Figure 10 As shown, the semiconductor device in this embodiment includes a semiconductor substrate 1, a gate trench 2, and a gate layer 3. The gate trench 2 is disposed within the semiconductor substrate 1. The gate layer 3 is formed in the gate trench 2, and at least a portion of the gate layer 3 is doped with nitrogen, with the nitrogen concentration gradually decreasing from the top of the gate layer 3 downwards.
[0083] like Figure 9 As shown, the semiconductor substrate 1 includes a substrate 11 of a first doping type and an active region 12 of a second doping type, with the active region 12 disposed on the substrate 11. A gate trench 2 extends from the active region 12 toward the substrate 11. In some embodiments, the first doping type can be P-type, formed by implanting P-type dopant ions, such as implanting B; the second doping type can be N-type, formed by implanting N-type dopant ions, such as implanting As.
[0084] In some embodiments, within a first preset depth range of the gate layer 3, the work function of the gate layer 3 gradually increases from the top downwards. From the maximum value of the gate layer 3 (i.e., the maximum depth within the first preset depth range) to the bottom of the gate layer 3, the work function of the gate layer 3 is the same, and is 0.3 to 0.6 eV greater than the work function of the gate layer 3 located within the first preset depth range. Alternatively, the work function of the gate layer 3 within this first preset depth range can be considered to be 0.3 to 0.6 eV lower than the work function of the gate layer 3 at a deeper location (depth greater than the first preset depth). The aforementioned first preset depth refers to the distance downwards from the top surface of the gate layer 3, or the distance from the top surface of the gate layer 3 towards the substrate 11. Furthermore, the work function of the gate layer 3 increases as the concentration of doped nitrogen decreases. That is, the higher the concentration of doped nitrogen, the greater the decrease in the work function of the gate layer 3. Therefore, in the nitrogen-doped portion of the gate layer 3, the work function increases with the increase in the depth of the gate layer 2.
[0085] In some embodiments, the first preset depth range is 0–20 nm. Within this range, the first preset depth of the gate layer 3 can be 0.1 nm, 0.5 nm, 1 nm, 5 nm, 10 nm, 15 nm, and 20 nm, and the work function of the gate layer 3 can correspondingly decrease by 0.6 eV, 0.5 eV, 0.4 eV, and 0.3 eV. Of course, these values and their corresponding relationships are only one case. This example only illustrates the change in the work function of the nitrogen-doped gate layer 3. Different processes may have different corresponding relationships, but the rule that the nitrogen concentration gradually decreases with the increase of the depth of the gate layer 3 remains the same.
[0086] The gate layer 3 is made of TiN. x Where x represents a numerical value, within the first preset depth range, x is greater than 1 and gradually decreases downwards from the top of the gate layer 3; within the range from the maximum value of the first preset depth to the bottom of the gate layer 3, x = 1. That is, within the range of the gate layer located below the first preset depth, the material of the gate layer is TiN.
[0087] refer to Figure 10 The diagram illustrates a semiconductor device according to other embodiments of the present disclosure. The gate layer 3 includes a first gate material layer 31 and a second gate material layer 32, with the first gate material layer 31 situated on the second gate material layer 32. The first gate material layer 31 is doped with nitrogen, while the second gate material layer 32 is not doped with nitrogen.
[0088] In some embodiments, the first gate material layer 31 may be made of TiN as described in the above embodiments. x In this context, x represents a numerical value, greater than 1, and x gradually decreases downwards from the top of the first gate material layer 31, indicating that the nitrogen concentration gradually decreases from the top of the first gate material layer 31 downwards. The second gate material layer 32 can be tungsten (W). The first gate material layer 31 is doped with nitrogen, and the nitrogen concentration gradually decreases with increasing depth of the gate layer 3 to effectively reduce the work function value at the upper end of the gate layer 3, thereby reducing the electric field strength in the overlap region between the gate layer 3 and the drain, improving the GIDL phenomenon, and without increasing the resistance. The tungsten metal in the second gate material layer 32 is located in the lower part of the gate layer 3 and is not doped with nitrogen. Furthermore, due to the low resistivity of tungsten, this part of the gate layer 3 has good conductivity, ensuring that the transistor can be turned on quickly.
[0089] In some embodiments, such as Figure 9 and Figure 10 As shown, the semiconductor device may further include a dielectric layer 4 and a transition layer 33. The dielectric layer 4 is disposed on the inner wall of the gate trench 2, and the transition layer 33 is disposed between the dielectric layer 4 and the second gate material layer 32.
[0090] The dielectric layer 4 is disposed between the gate layer 3 and the inner wall of the gate trench 2. The dielectric layer 4 can be made of at least one of silicon oxide, silicon nitride and silicon oxynitride.
[0091] A transition layer 33 is formed between the gate layer 3 and the dielectric layer 4. In some embodiments, the material of the transition layer 33 can be the same as that of the first gate material layer 31, for example, the transition layer 33 is made of TiN, and the first gate material layer 31 is also made of TiN. Since grain boundary dislocations or stress are prone to occur at the junction of the metal W and the dielectric layer 4, the bonding between the gate layer 3 and the dielectric layer 4 becomes unstable and prone to defects. To overcome this problem, the transition layer 33 is provided between the dielectric layer 4 and the second gate material layer 32. The transition layer 33 can better bond with the dielectric layer 4 and also better bond with the second gate material layer 32, making the formed gate layer 3 more stable and overcoming the aforementioned defects. Simultaneously, the material of the transition layer 33 is the same as that of the first gate material layer 31, allowing for better bonding between the first gate material layer 31 and the transition layer 33, further increasing the stability of the gate layer 3.
[0092] In some embodiments, such as Figure 9 and Figure 10 As shown, the semiconductor device may further include an insulating capping layer 6 covering the gate layer 3, and the insulating capping layer 6 at least fills the gate trench 2 so that the top of the gate layer 3 is electrically isolated from other semiconductor devices located above it.
[0093] like Figure 11 The figure shows a schematic diagram of the results of nitrogen doping in the gate layer 3 of the semiconductor device according to an embodiment of the present disclosure. It can be seen from the figure that the nitrogen doping concentration is relatively high within a first predetermined depth range of 0–20 nm in the gate layer 3. This can be understood as the nitrogen injected into the gate layer 3 reducing the work function of the gate layer 3 within this first predetermined depth range. Tests showed that the work function (WF) of the gate layer 3 within this 0–20 nm depth range is 4.0–4.3 eV, while the work function of the gate layer 3 beyond a depth of 20 nm is 4.5–4.8 eV. The work function of the gate layer 3 in the nitrogen-doped region decreased by at least 0.5 eV. These test results demonstrate that the work function of the gate layer 3 of the semiconductor device prepared by the fabrication method of the present disclosure embodiment is effectively reduced.
[0094] In summary, in the semiconductor device of this disclosure embodiment, the nitrogen element doped in the gate layer 3 gradually decreases from the top of the gate layer 3 downwards, which can effectively reduce the work function value of the gate layer 3, improve the GIDL phenomenon, and at the same time not affect other electrical properties of the semiconductor device.
[0095] It should be understood that this disclosure is not limited to the detailed structure and arrangement of the components presented in this specification. This disclosure is capable of other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this disclosure. It should be understood that this disclosure, as disclosed and defined in this specification, extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of this disclosure. The embodiments described in this specification illustrate the best known mode for implementing this disclosure and will enable those skilled in the art to utilize this disclosure.
Claims
1. A method of manufacturing a semiconductor device, characterized by, include: Provide semiconductor substrates; Etching the semiconductor substrate forms a gate trench; A gate layer is formed within the gate trench; Nitrogen element is implanted into the gate layer; The concentration of nitrogen in the gate layer gradually decreases from the top of the gate layer downwards. The nitrogen element is implanted into the gate layer using an ion implantation process. The semiconductor substrate includes a substrate of a first doping type and an active region of a second doping type. Etching the semiconductor substrate to form a gate trench includes etching from the active region toward the substrate to form the gate trench. After etching the semiconductor substrate to form a gate trench, the method further includes filling the gate trench with a dielectric layer; The method of forming the gate layer includes: A transition layer is formed on the dielectric layer using a deposition process; Then, in the space enclosed by the transition layer, a second gate material layer with a predetermined height is deposited from the bottom of the space upwards, and the second gate material layer does not fill the gate trench; Then, a first gate material layer of the required height is deposited on the second gate material layer; Wherein, the first gate material layer is doped with nitrogen, while the second gate material layer is not doped with nitrogen; The first gate material layer is made of TiN, the second gate material layer is made of tungsten, and the transition layer is made of the same material as the first gate material layer.
2. The method of claim 1, wherein, in, The ion implantation energy is 3-10 keV, and the implantation dose is 7.0e+15-3.0e+16 atoms / cm 2 .
3. The method of claim 1, wherein, Before injecting nitrogen into the gate layer, the method further includes depositing an injection barrier layer on the surface of the active region.
4. The method according to claim 3, wherein the thickness of the injection barrier layer is 50~70nm.
5. The method of claim 3, wherein, The injection barrier layer and the dielectric layer are both made of at least one of silicon oxide, silicon nitride, and silicon oxynitride.
6. The method of claim 3, wherein, After implanting nitrogen into the gate layer, the process further includes: Fill the gate trench with an insulating capping layer; Remove the injection barrier layer and the insulating capping layer located above the active region.
7. A semiconductor device produced by the production method according to claim 1, characterized by include: Semiconductor substrate; A gate trench is disposed within the semiconductor substrate; A gate layer, located in the gate trench, is at least partially doped with nitrogen, and the concentration of nitrogen gradually decreases from the top of the gate layer downwards.
8. The semiconductor device of claim 7, wherein, The semiconductor substrate includes a substrate of a first doping type and an active region of a second doping type, the active region being disposed on the substrate; wherein the gate trench extends from the active region toward the substrate.
9. The semiconductor device of claim 8, wherein, Within a first preset depth range of the gate layer, the work function of the gate layer gradually increases from the top down; within a range from the maximum value of the gate layer above the first preset depth to the bottom of the gate layer, the work function of the gate layer is the same, and is 0.3 to 0.6 eV greater than the work function of the gate layer located within the first preset depth range.
10. The semiconductor device of claim 9, wherein, The first preset depth range is 0~20nm.
11. The semiconductor device of claim 10, wherein, The material of the gate layer is TiN x ; Where x represents a numerical value, x is greater than 1 within the first preset depth range and gradually decreases from the top of the gate layer downwards; x = 1 within the range from the maximum value of the first preset depth to the bottom of the gate layer.
12. The semiconductor device according to claim 7, characterized in that, The gate layer includes a first gate material layer and a second gate material layer, wherein the first gate material layer is located on the second gate material layer; wherein the first gate material layer is doped with nitrogen, and the second gate material layer is not doped with nitrogen.
13. The semiconductor device of claim 12, wherein, The material of the first gate material layer is TiN x The material of the second gate material layer is W Where x represents a numerical value, x is greater than 1, and x gradually decreases from the top of the first gate material layer downwards.
14. The semiconductor device of claim 13, wherein, Also includes A dielectric layer is disposed on the inner wall of the gate trench; A transition layer is disposed between the dielectric layer and the second gate material layer.
15. The semiconductor device of claim 14, wherein, The transition layer is made of TiN.
16. The semiconductor device of claim 7, wherein It also includes an insulating capping layer covering the gate layer.