A shallow trench isolation annealing method

Abstract

This invention provides a shallow trench isolation annealing method, comprising: etching multiple equally spaced strip-shaped protrusions on a substrate; forming a thin STI oxide layer covering the strip-shaped protrusions on the substrate; etching multiple STI trenches on the substrate; forming an ALD thin oxide layer covering the multiple strip-shaped protrusions and STI trenches on the substrate; covering the substrate with a dielectric layer to fill the STI trenches; immersing the substrate and the multiple strip-shaped protrusions, STI thin oxide layer, ALD thin oxide layer, and dielectric layer on the substrate with deionized water; annealing to transform the dielectric layer into a silicon oxide layer; and planarizing the top of the silicon oxide layer. This invention adds a deionized water immersion step before the water vapor oxidation annealing of FCVD deposition. Water vapor oxidation uses a lower temperature and shorter reaction time, thereby reducing fin consumption and increasing the process window.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for shallow trench isolation annealing. Background Technology

[0002] In the advanced manufacturing nodes of logic chip manufacturing, FinFET technology is widely adopted, making the size of the FinCD a major concern. The process of filling FCVD in the Fin process plays a crucial role. This paper describes an annealing method to reduce FinCD loss: after Fin etching, an STI liner oxide layer is first grown, followed by an ALD oxide layer, then FCVD is deposited to fill the high aspect ratio trenches. Finally, steam oxidation annealing completely converts the FCVD into SiO2.

[0003] The problem with existing technology is that the conversion of FCVD requires a long Steam OX process. Although the long Steam OX process can completely convert FCVD, it also increases the consumption of FIN and reduces the process window. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a shallow tank isolation annealing method to solve the problem that the oxidation process required to complete FCVD in the prior art is very long, which increases the consumption of Fin and reduces the process window.

[0005] To achieve the above and other related objectives, the present invention provides a shallow trench isolation annealing method, comprising at least:

[0006] Step 1: Etch multiple equally spaced strip-shaped protrusions onto the substrate;

[0007] Step 2: Form a thin STI oxide layer on the substrate to cover the strip-shaped protrusions;

[0008] Step 3: Etch multiple STI trenches on the substrate;

[0009] Step 4: Form a thin ALD oxide layer on the substrate covering the plurality of strip protrusions and the STI trenches;

[0010] Step 5: Cover the substrate with a dielectric layer to fill the STI trench;

[0011] Step 6: Soak the substrate and the multiple strip-shaped protrusions, STI thin oxide layer, ALD thin oxide layer, and dielectric layer on the substrate in deionized water;

[0012] Step 7: Perform annealing to convert the dielectric layer into a silicon oxide layer;

[0013] Step 8: Planarize the top of the silicon oxide layer.

[0014] Preferably, the plurality of strip-shaped protrusions in step one are arranged laterally on the substrate.

[0015] Preferably, the method for forming the STI thin oxide layer in step two is the ISSG method.

[0016] Preferably, the STI trench in step three is formed by cutting and etching the substrate with a plurality of transversely arranged strip-shaped protrusions.

[0017] Preferably, the STI trench in step three is formed by cutting and etching the substrate with a plurality of transversely arranged strip-shaped protrusions.

[0018] Preferably, in step five, a dielectric layer is coated onto the substrate using the FCVD method to fill the STI trench.

[0019] Preferably, the soaking time of the substrate in step six is ​​15 minutes.

[0020] Preferably, the temperature at which the substrate is immersed in step six is ​​60–100°C.

[0021] Preferably, the annealing method in step seven is steam oxidation annealing.

[0022] Preferably, the annealing temperature of the steam oxidation annealing method in step seven is 650°C.

[0023] Preferably, the planarization method in step eight is chemical mechanical polishing.

[0024] As described above, the shallow tank isolation annealing method of the present invention has the following beneficial effects: The present invention adds a deionized water soaking step before the steam oxidation annealing of FCVD deposition. Steam oxidation employs a lower temperature and shorter reaction time. This reduces fin consumption and increases the process window. Attached Figure Description

[0025] Figure 1 The diagram shown is a flowchart of the shallow trench isolation annealing method of the present invention.

[0026] Figure 2 The diagram shows a schematic representation of the structure of multiple strip protrusions formed on the substrate in this invention.

[0027] Figure 3 The diagram shows a structural schematic of the STI trenches formed by etching in this invention.

[0028] Figure 4The diagram shows a schematic of the STI trench covered with a dielectric layer in this invention.

[0029] Figure 5 The diagram shows a structural schematic of the medium layer soaked in deionized water in this invention.

[0030] Figure 6 The diagram shows the structure of the dielectric layer transformed into a silicon oxide layer after annealing in this invention.

[0031] Figure 7 The diagram shows the structure of the silicon oxide layer after planarization in this invention. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0033] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0034] This invention provides a shallow trench isolation annealing method, such as... Figure 1 As shown, Figure 1 The diagram shown illustrates a shallow trench isolation annealing method according to the present invention, which includes at least the following steps:

[0035] Step 1: Etch multiple equally spaced strip-shaped protrusions onto the substrate; such as... Figure 2 As shown, Figure 2 The diagram shows a schematic representation of multiple strip-shaped protrusions formed on a substrate in this invention. In step one, multiple strip-shaped protrusions 02 arranged at equal intervals are etched onto the substrate 01. The multiple strip-shaped protrusions 02 in this invention are Fin structures, i.e., Fin structures in fin transistors. Further, in step one of this embodiment, the multiple strip-shaped protrusions are arranged laterally on the substrate.

[0036] Step 2: Form a thin STI oxide layer on the substrate covering the strip-shaped protrusions; such as Figure 2As shown, in step two, a thin STI oxide layer 03 covering the strip-shaped protrusions is formed on the substrate 01. Further, in this embodiment, the method for forming the STI thin oxide layer in step two is the ISSG method.

[0037] Step 3: Etch multiple STI trenches on the substrate; such as Figure 3 As shown, Figure 3 The diagram shows a schematic of the STI trenches formed by etching in this invention. Step three involves etching the plurality of STI trenches 03 onto the substrate 01. Further, in this embodiment, the STI trenches in step three are formed by cutting and etching the substrate with a plurality of laterally arranged strip-shaped protrusions.

[0038] Step 4: Form a thin ALD oxide layer on the substrate covering the plurality of strip-shaped protrusions and the STI trenches; as shown below. Figure 4 As shown, Figure 4 The diagram shows a schematic of the STI trench covered with a dielectric layer in this invention. Figure 4 The ALD thin oxide layer is not shown in the diagram. Further, in step four of this embodiment, the ALD thin oxide layer is formed by deposition.

[0039] Step 5: Cover the substrate with a dielectric layer to fill the STI trench; as shown Figure 4 As shown, step five involves covering the substrate with a dielectric layer 04 to fill the STI trench 03. Further, in this embodiment, step five uses the FCVD method to cover the substrate with a dielectric layer to fill the STI trench.

[0040] Step Six: Immerse the substrate and its multiple strip-shaped protrusions, STI thin oxide layer, ALD thin oxide layer, and dielectric layer in deionized water; as shown. Figure 5 As shown, Figure 5 The diagram shows a schematic of the dielectric layer being soaked in deionized water according to the present invention. Step six involves soaking the substrate and the multiple strip-shaped protrusions (Fin structures) on the substrate 01, the STI thin oxide layer 03, the ALD thin oxide layer, and the dielectric layer 04 in deionized water (DI water). Further, in this embodiment, the soaking time for the substrate in step six is ​​15 minutes. Further, in this embodiment, the soaking temperature for the substrate in step six is ​​60–100°C.

[0041] Step 7: Perform annealing to convert the dielectric layer into a silicon oxide layer; such as Figure 6 As shown, Figure 6 The diagram shows the structure of the dielectric layer transformed into a silicon oxide layer after annealing in this invention. Step seven involves annealing to transform the dielectric layer into a silicon oxide layer 05.

[0042] Furthermore, in this embodiment, the annealing method in step seven is steam oxidation annealing. The annealing temperature in step seven is 650°C.

[0043] Step 8: Planarize the top of the silicon oxide layer. For example... Figure 7 As shown, Figure 7 The diagram shows the structure of the silicon oxide layer after planarization in this invention. Step eight involves planarizing the top of the silicon oxide layer. Further, in this embodiment, the planarization method in step eight is chemical mechanical polishing.

[0044] In summary, this invention adds a deionized water soaking step before the steam oxidation annealing of FCVD deposition. The steam oxidation utilizes a lower temperature and shorter reaction time, thereby reducing fin consumption and increasing the process window. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0045] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for shallow trench isolation annealing, characterized in that, At least including: Step 1: Etch multiple equally spaced strip-shaped protrusions onto the substrate; Step 2: Form a thin STI oxide layer on the substrate to cover the strip-shaped protrusions; Step 3: Etch multiple STI trenches on the substrate; Step 4: Form a thin ALD oxide layer on the substrate covering the plurality of strip protrusions and the STI trenches; Step 5: Cover the substrate with a dielectric layer to fill the STI trench; Step 6: Soak the substrate and the multiple strip protrusions, STI thin oxide layer, ALD thin oxide layer, and dielectric layer on the substrate in deionized water; Step 7: Perform annealing to convert the dielectric layer into a silicon oxide layer; Step 8: Planarize the top of the silicon oxide layer.

2. The shallow trench isolation annealing method according to claim 1, characterized in that: The multiple strip-shaped protrusions mentioned in step one are arranged laterally on the substrate.

3. The shallow trench isolation annealing method according to claim 1, characterized in that: The method for forming the STI thin oxide layer in step two is the ISSG method.

4. The shallow trench isolation annealing method according to claim 2, characterized in that: The STI trench described in step three is formed by cutting and etching the substrate with multiple transversely arranged strip-shaped protrusions.

5. The shallow trench isolation annealing method according to claim 1, characterized in that: In step four, the thin oxide layer of ALD is formed by deposition.

6. The shallow trench isolation annealing method according to claim 1, characterized in that: Step 5: A dielectric layer is applied to the substrate using the FCVD method to fill the STI trench.

7. The shallow trench isolation annealing method according to claim 1, characterized in that: The soaking time for the substrate in step six is ​​15 minutes.

8. The shallow trench isolation annealing method according to claim 1, characterized in that: In step six, the temperature for immersing the substrate is 60–100°C.

9. The shallow trench isolation annealing method according to claim 1, characterized in that: The annealing method in step seven is steam oxidation annealing.

10. The shallow trench isolation annealing method according to claim 1, characterized in that: The annealing temperature for the steam oxidation annealing method in step seven is 650℃.

11. The shallow trench isolation annealing method according to claim 1, characterized in that: The planarization method in step eight is chemical mechanical polishing.

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