Gate structure of semiconductor device and method of forming the same

Abstract

The present disclosure relates to gate structures of semiconductor devices and methods of forming the same. A semiconductor device and a method of forming the same are provided. The method includes forming a fin extending from a substrate. A dummy gate is formed over the fin. The dummy gate extends along sidewalls and a top surface of the fin. The dummy gate is removed to form a recess. A replacement gate is formed in the recess. Forming the replacement gate includes forming an interface layer along sidewalls and a bottom of the recess. A dipole layer is formed over the interface layer. The dipole layer includes metal atoms. Fluorine atoms are introduced into the dipole layer. The fluorine atoms and the metal atoms from the dipole layer are driven into the interface layer. The dipole layer is removed.

Description

Technical Field

[0001] This disclosure generally relates to the gate structure of semiconductor devices and methods for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] According to one aspect of this disclosure, a method of forming a semiconductor device is provided, comprising: forming a fin extending from a substrate; forming a dummy gate over the fin, the dummy gate extending along a sidewall and a top surface of the fin; removing the dummy gate to form a recess; and forming a replacement gate in the recess, wherein forming the replacement gate comprises: forming an interface layer along a sidewall and a bottom of the recess; forming a dipole layer over the interface layer, the dipole layer comprising metal atoms; introducing fluorine atoms into the dipole layer; driving the fluorine atoms and the metal atoms from the dipole layer into the interface layer; and removing the dipole layer.

[0005] According to another aspect of this disclosure, a method of forming a semiconductor device is provided, comprising: patterning a substrate to form a fin; forming a dummy gate on the fin, the dummy gate extending along a sidewall and a top surface of the fin; etching the dummy gate to form a recess; and forming a replacement gate in the recess, wherein forming the replacement gate comprises: depositing an interface layer along the sidewall and bottom of the recess; depositing a dipole layer on the interface layer, the dipole layer comprising metal atoms; performing a fluorine immersion process on the dipole layer to form a doped dipole layer, the doped dipole layer comprising fluorine atoms; performing an annealing process to drive the fluorine atoms and the metal atoms from the doped dipole layer into the interface layer and form a doped interface layer; etching the doped dipole layer to expose the doped interface layer; depositing a gate dielectric layer on the doped interface layer; and depositing a gate electrode layer on the gate dielectric layer.

[0006] According to another aspect of this disclosure, a semiconductor device is provided, comprising: a fin extending from a substrate; an isolation structure on the substrate and adjacent to the fin, wherein a top surface of the fin is higher than a top surface of the isolation structure; and a gate stack extending along the top surface and sidewalls of the fin and the top surface of the isolation structure, wherein the gate stack includes: an interface layer along the top surface and sidewalls of the fin, the interface layer comprising a dielectric material doped with atoms of a first metal element and fluorine atoms, wherein the interface between the interface layer and the fin comprises F-Si bonds; and a gate dielectric layer on the interface layer, the gate dielectric layer comprising atoms of a second metal element, wherein the interface between the interface layer and the gate dielectric layer comprises bonds between some atoms of the second metal element and some of the fluorine atoms. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0008] Figure 1 An example of FinFET according to some embodiments is shown in a 3D view.

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 21D, Figure 22A , Figure 22B , Figure 23A and Figure 23B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET device according to some embodiments.

[0010] Figure 14 This is a flowchart illustrating a method for forming a gate stack according to some embodiments.

[0011] Figure 17 This is a flowchart illustrating a method for forming a dipole layer according to some embodiments.

[0012] Figure 24A and Figure 24B This is a cross-sectional view of a FinFET device according to some embodiments.

[0013] Figure 25A and Figure 25B This is a cross-sectional view of an NSFET device according to some embodiments.

[0014] Figure 26A and Figure 26B This is a cross-sectional view of an NSFET device according to some embodiments. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] In addition, this document may use spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) to facilitate the description of the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the accompanying drawings. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0017] Embodiments will be described with reference to a specific context (i.e., the gate structure of a semiconductor device and methods of its formation). The various embodiments presented herein are discussed in the context of FinFET devices formed using a gate-last process. In other embodiments, a gate-first process may be used. However, instead of FinFETs or combinations thereof, various embodiments can be applied to dies including other types of transistors, such as planar FETs, gate-all-around (GAA) transistors (e.g., nanostructure (e.g., nanosheets, nanowires, etc.) field-effect transistors (NSFETs), etc. The various embodiments discussed herein allow for increasing (or decreasing) the threshold voltage (V) of the semiconductor device. t This reduces interface trap density, improves reliability, and reduces or eliminates gate leakage. In some embodiments, the threshold voltage (V) of the semiconductor device t This can be improved by forming a dipole layer (including metal atoms) on top of the interface layer, performing a fluorine introduction process on the dipole layer, and performing an annealing process to drive the metal and fluorine atoms from the dipole layer to the interface layer.

[0018] Figure 1 An example of a FinFET according to some embodiments is shown in a three-dimensional view. The FinFET includes fins 52 located on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are disposed in the substrate 50, and the fins 52 protrude above adjacent isolation regions 56. Although the isolation regions 56 are described / shown as separate from the substrate 50, as used herein, the term "substrate" can be used to refer only to a semiconductor substrate or to a semiconductor substrate including the isolation regions. Furthermore, although the fins 52 are shown as being a single continuous material with the substrate 50, the fins 52 and / or the substrate 50 may comprise a single material or multiple materials. In this context, fin 52 refers to the portion extending between adjacent isolation regions 56.

[0019] A gate dielectric layer 98 runs along the sidewall of fin 52 and is located above the top surface of fin 52, and a gate electrode 100 is located above the gate dielectric layer 98. Source / drain regions 82 are disposed on the opposite sides of fin 52 with respect to the gate dielectric layer 98 and the gate electrode 100. One or more source / drain regions may individually or collectively refer to the source or drain depending on the context. Figure 1Reference cross sections used in the following figures are also shown. Cross section AA is along the longitudinal axis of the gate electrode 100 and in a direction perpendicular to, for example, the direction of current flow between the source / drain regions 82 of the FinFET. Cross section BB is perpendicular to cross section AA and along the longitudinal axis of the fin 52 in the direction of current flow between, for example, the source / drain regions 82 of the FinFET. Cross section CC is parallel to cross section AA and extends through the source / drain regions 82 of the FinFET. These reference cross sections are referenced in subsequent figures for clarity.

[0020] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 22A , Figure 22B , Figure 23A and Figure 23B This is a cross-sectional view of an intermediate stage in the fabrication of a FinFET device according to some embodiments. Figures 2-7 , Figures 8A-13A , Figure 15A , Figure 16A and Figures 18A-23A It shows along Figure 1 The cross-sectional view of the reference section AA shown differs in that it has multiple fins / FinFETs. Figures 8B-13B , Figure 15B , Figure 16B , Figures 18B-23B , Figure 21C and Figure 21D It shows along Figure 1The cross-sectional view of the reference section BB shown is different in that it has multiple fins / FinFETs. Figure 10C and Figure 10D It shows along Figure 1 The cross-sectional view of the reference section CC shown is different in that it has multiple fins / FinFETs.

[0021] exist Figure 2 A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and can be doped (e.g., doped with p-type or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer or a silicon oxide layer. The insulating layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0022] Substrate 50 has region 50N and region 50P. Region 50N can be used to form an n-type device, such as an NMOS transistor, like an n-type FinFET. Region 50P can be used to form a p-type device, such as a PMOS transistor, like a p-type FinFET. Region 50N can be physically separated from region 50P (as shown by separator 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be formed between region 50N and region 50P.

[0023] exist Figure 3 In this embodiment, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in substrate 50 by etching trenches in substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), combinations thereof, etc. The etching process can be anisotropic.

[0024] Fin 52 can be formed by any suitable method. For example, fin 52 can be formed using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as a mask to form fin 52.

[0025] exist Figure 4 An insulating material 54 is formed on the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide (e.g., silicon oxide), a nitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition and post-curing in a remote plasma system to transform it into another material (e.g., oxide)), or a combination thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material 54 is formed such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) can be formed first along the surfaces of the substrate 50 and the fins 52. A filler material as discussed above can then be formed on the liner.

[0026] exist Figure 5 In this process, a removal process is applied to the insulating material 54 to remove excess portions of the insulating material 54 above the fin 52. In some embodiments, a planarization process may be used, such as a chemical mechanical polishing (CMP) process, an etch-back process, or a combination thereof. The planarization process exposes the fin 52 such that, after the planarization process is completed, the top surface of the fin 52 and the top surface of the insulating material 54 are flush within the process variations of the planarization process.

[0027] exist Figure 6 In the middle, insulating material 54 (see Figure 5The insulating material 54 is recessed to form isolation region 56. Isolation region 56 may also be referred to as shallow trench isolation (STI) region. The insulating material 54 is recessed such that the upper portion of the fin 52 in regions 50N and 50P protrudes between adjacent isolation regions 56. Furthermore, the top surface of the STI region 56 may have a flat surface (as shown), a convex surface, a concave surface (e.g., dish-shaped), or a combination thereof. The top surface of the isolation region 56 may be formed as flat, convex, and / or concave by appropriate etching. The isolation region 56 may be recessed using an acceptable etching process, such as an etching process selective for the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than etching the material of the fin 52). For example, chemical oxide removal may be used, which utilizes an appropriate etching process using, for example, dilute hydrofluoric acid (dHF).

[0028] about Figures 2 to 6 The described process is merely one example of how fin 52 can be formed. In some embodiments, the fin can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoethelic structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoethelic structure protrudes from the dielectric layer to form the fin. Furthermore, in some embodiments, heteroethelic structures can be used for the fin. For example, Figure 5 The fin 52 can be recessed, and a different material can be epitaxially grown on the recessed fin 52. In such an embodiment, the fin includes a recessed material and an epitaxial growth material disposed on the recessed material. In a further embodiment, a dielectric layer can be formed on the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trenches using a material different from that of the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structure protrudes from the dielectric layer to form the fin. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, the epitaxial growth material can be doped in situ during growth, which avoids prior and subsequent implantation, but in-situ doping and implantation doping can be used together.

[0029] Furthermore, it may be advantageous to epitaxially grow a material different from that in region 50P in region 50N. In various embodiments, the upper portion of fin 52 may be made of silicon-germanium (Si). x Ge 1-xThe semiconductor can be formed from materials such as silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, or II-VI compound semiconductors, where x can be in the range of 0 to 1. For example, materials that can be used to form III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, and GaP.

[0030] In addition, Figure 6 In this process, suitable wells (not shown) can be formed in fin 52 and / or substrate 50. In some embodiments, a P-well can be formed in region 50N and an N-well can be formed in region 50P. In some embodiments, either a P-well or an N-well is formed in both region 50N and region 50P. In embodiments with different well types, different implantation steps for regions 50N and 50P can be implemented using photoresist or other masks (not shown). For example, a first photoresist can be formed over fin 52 and isolation region 56 in both regions 50N and 50P. The first photoresist is patterned to expose region 50P of substrate 50. The first photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the first photoresist is patterned, n-type impurity implantation is performed in region 50P, and the remainder of the first photoresist serves as a mask to substantially prevent n-type impurities from being implanted into region 50N. n-type impurities can be phosphorus, arsenic, antimony, etc., injected into the region, with a dose equal to or less than 10. 15 cm -2 For example, in about 10 12 cm -2 To about 10 15 cm -2 Within the range. In some embodiments, n-type impurities can be implanted at an implantation energy of about 1 keV to about 10 keV. After implantation, the first photoresist is removed, for example, by an acceptable ashing process (followed by a wet cleaning process).

[0031] Following implantation in region 50P, a second photoresist is formed over fin 52 and isolation region 56 in both regions 50P and 50N. The second photoresist is patterned to expose region 50N of the substrate 50. The second photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the second photoresist is patterned, p-type impurity implantation can be performed in region 50N, and the remaining portion of the second photoresist serves as a mask to substantially prevent p-type impurities from being implanted into region 50P. The p-type impurity can be boron, BF2, indium, etc., implanted into the region at a dose equal to or less than 10. 15 cm -2 For example, in about 10 12 cm -2 To about 10 15 cm -2 Within the range. In some embodiments, p-type impurities can be implanted at an implantation energy of about 1 keV to about 10 keV. After implantation, the second photoresist can be removed, for example, by an acceptable ashing process (followed by a wet cleaning process).

[0032] After implantation into regions 50N and 50P, an annealing process can be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be doped in situ during growth, which avoids implantation; however, in-situ doping and implantation doping can be used together.

[0033] exist Figure 7In this process, a dummy dielectric layer 60 is formed on fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, or a combination thereof, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized using, for example, a CMP process. After the planarization process, the mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive material and can be selected from the group consisting of amorphous silicon, polysilicon, polycrystalline silicon germanium (polycrystalline SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques known in the art for depositing conductive materials. The dummy gate layer 62 may be made of other materials that have high etch selectivity relative to the material of the isolation region 56. The mask layer 64 may include, for example, one or more layers of silicon oxide, SiN, SiON, combinations thereof, etc. In some embodiments, the mask layer 64 may include a silicon nitride layer and a silicon oxide layer on top of the silicon nitride layer. In some embodiments, a single dummy gate layer 62 and a single mask layer 64 are formed across regions 50N and 50P. Note that, for illustrative purposes only, the dummy dielectric layer 60 is shown as covering only the fin 52. In some embodiments, the dummy dielectric layer 60 may be deposited such that the dummy dielectric layer 60 covers the isolation region 56, extending between the dummy gate layer 62 and the isolation region 56.

[0034] Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 22A , Figure 22B , Figure 23A and Figure 23B Various additional steps in the fabrication of a FinFET device according to some embodiments are illustrated. Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 22A , Figure 22B , Figure 23A and Figure 23B Features in either region 50N or region 50P are shown. For example, Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 22A , Figure 22B , Figure 23A and Figure 23B The structures shown can be applied to both Region 50N and Region 50P. The structural differences between Region 50N and Region 50P are described (if any) in the accompanying text for each figure.

[0035] exist Figure 8A and Figure 8B In this process, acceptable photolithography and etching techniques can be used to process mask layer 64 (see...). Figure 7 The mask 74 is patterned to form a mask 74. In some embodiments, the etching technique may include one or more anisotropic etching processes, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. The pattern of the mask 74 can then be transferred to the dummy gate layer 62 (see [link to documentation]). Figure 7 A dummy gate 72 is formed by etching a mask 74. In some embodiments, the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using an acceptable etching technique. The dummy gate 72 covers the channel region 58 of the fin 52. Each dummy gate 72 can be physically separated from adjacent dummy gates using the pattern of the mask 74. The dummy gate 72 may also have a length direction substantially perpendicular to the length direction of the respective fin 52. As described in more detail below, the dummy gate 72 is a sacrificial gate and is subsequently replaced by a replacement gate. Therefore, the dummy gate 72 may also be referred to as a sacrificial gate. In other embodiments, some dummy gates 72 are not replaced and remain in the final structure of the resulting FinFET device.

[0036] In addition, Figure 8A and Figure 8B In this process, a gate sealing spacer 80 can be formed on the exposed surfaces of the dummy gate 72, mask 74, and / or fin 52. The gate sealing spacer 80 can be formed by thermal oxidation or deposition (followed by anisotropic etching). The gate sealing spacer 80 may include silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, combinations thereof, etc. After forming the gate sealing spacer 80, implantation for lightly doped source / drain (LDD) regions (not explicitly shown) can be performed. In embodiments with different device types, similar to the above... Figure 6The implantation discussed earlier can involve forming a mask (e.g., photoresist) over region 50N while exposing region 50P, and implanting an impurity of an appropriate type (e.g., p-type) into the exposed fins 52 in region 50P. The mask can then be removed. The n-type impurity can be any n-type impurity discussed earlier, and the p-type impurity can be any p-type impurity discussed earlier. The lightly doped source / drain regions can have approximately 10... 12 cm -2 To about 10 16 cm -2 The dosage of impurities. In some embodiments, suitable impurities may be injected with an injection energy of about 1 keV to about 10 keV. Annealing may be used to activate the injected impurities.

[0037] exist Figure 9A and Figure 9B In this embodiment, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacer 86 may include silicon oxide, silicon nitride, SiCN, SiOC, SiOCN, or combinations thereof. In some embodiments, the gate spacer 86 may include multiple layers (not shown) such that these layers comprise different materials. In some embodiments, the gate spacer 86 and the gate sealing spacer 80 comprise the same material. In other embodiments, the gate spacer 86 and the gate sealing spacer 80 comprise different materials.

[0038] Note that the above disclosure generally describes the process for forming the spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, and different step sequences can be used (e.g., the gate seal spacer 80 may not be etched before forming the gate spacer 86, resulting in an "L-shaped" gate seal spacer, the spacers can be formed and removed, etc.). Furthermore, n-type and p-type devices can be formed using different structures and steps. For example, the LDD region of an n-type device can be formed before forming the gate seal spacer 80, while the LDD region of a p-type device can be formed after forming the gate seal spacer 80.

[0039] exist Figure 10A and Figure 10BIn the process, epitaxial source / drain regions 82 are formed in fin 52 to apply stress in each channel region 58, thereby improving device performance. The epitaxial source / drain regions 82 are formed in fin 52 such that each dummy gate 72 is disposed between adjacent pairs of corresponding epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 may extend into fin 52 and may also penetrate fin 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 82 do not short-circuit the subsequently formed gate of the resulting FinFET device.

[0040] The epitaxial source / drain region 82 in region 50N can be formed by masking region 50P and etching the source / drain region of fin 52 in region 50N to form a recess in fin 52. The epitaxial source / drain region 82 in region 50N is then epitaxially grown in the recess. The epitaxial source / drain region 82 can include any acceptable material, such as materials suitable for n-type FinFETs. For example, if fin 52 comprises silicon, the epitaxial source / drain region 82 in region 50N can include a material for applying tensile strain in channel region 58, such as silicon, SiC, SiCP, SiP, or combinations thereof. The epitaxial source / drain region 82 in region 50N can have a surface protruding from the corresponding surface of fin 52 and can have facets.

[0041] The epitaxial source / drain region 82 in region 50P can be formed by masking region 50N and etching the source / drain region of fin 52 in region 50P to form a recess in fin 52. The epitaxial source / drain region 82 in region 50P is then epitaxially grown in the recess. The epitaxial source / drain region 82 can include any acceptable material, such as materials suitable for p-type FinFETs. For example, if fin 52 comprises silicon, the epitaxial source / drain region 82 in region 50P can include a material for applying compressive strain in channel region 58, such as SiGe, SiGeB, Ge, GeSn, or combinations thereof. The epitaxial source / drain region 82 in region 50P can also have a surface protruding from the corresponding surface of fin 52 and can have a facet.

[0042] The epitaxial source / drain regions 82 and / or fins 52 can be implanted with dopants, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the epitaxial source / drain regions 82 can be approximately 10. 19 cm -3 To about 10 21 cm -3The n-type and / or p-type impurities used for the epitaxial source / drain region 82 can be any of the previously discussed impurities. In some embodiments, the epitaxial source / drain region 82 can be doped in situ during growth.

[0043] As a result of the epitaxial process used to form the epitaxial source / drain regions 82 in regions 50N and 50P, the upper surface of the epitaxial source / drain regions has small facets that extend laterally outward beyond the sidewalls of the fin 52. In some embodiments, these small facets cause adjacent epitaxial source / drain regions 82 of the same FinFET to merge, such as... Figure 10C As shown. In other embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 82 remain separated, as shown. Figure 10D As shown. In Figure 10C and Figure 10D In the illustrated embodiment, the gate spacer 86 is formed to cover a portion of the sidewall of the fin 52 that extends above the isolation region 56, thereby blocking epitaxial growth. In other embodiments, the spacer etching used to form the gate spacer 86 may be adjusted to remove spacer material from the sidewall of the fin 52 to allow the epitaxial growth region to extend to the surface of the isolation region 56.

[0044] exist Figure 11A and Figure 11B In the middle, the first interlayer dielectric (ILD) 88 is deposited on Figure 10A and Figure 10B The structure shown is above the first ILD 88. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, combinations thereof, etc. The dielectric material can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can also be used. In some embodiments, a contact etch stop layer (CESL) 87 is disposed between the first ILD 88 and the epitaxial source / drain region 82, mask 74, and gate spacer 86. CESL 87 can include a dielectric material having an etch rate different from that of the first ILD 88 described above, such as silicon nitride, silicon oxide, silicon oxynitride, or combinations thereof.

[0045] exist Figure 12A and Figure 12B In this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 88 flush with the dummy gate 72 or mask 74 (see...). Figure 11A and Figure 11BThe top surface of the dummy gate 72 is flush with the top surface of the first ILD 88. The planarization process also removes the mask 74 on the dummy gate 72, as well as portions of the gate sealing spacers 80 and 86 along the sidewalls of the mask 74. After the planarization process, the top surfaces of the dummy gate 72, gate sealing spacers 80, gate spacers 86, and the first ILD 88 are flush with each other within the process variations of the planarization process. Therefore, the top surface of the dummy gate 72 is exposed through the first ILD 88. In some embodiments, the mask 74 may be retained, in which case the planarization process flushes the top surface of the first ILD 88 with the top surface of the mask 74.

[0046] exist Figure 13A and Figure 13B In the middle, a dummy gate 72 and a mask 74 are set (see Figure 11A and Figure 11B The dummy gate 72 (if present) is removed in one or more etching steps to form an opening 90. A portion of the dummy dielectric layer 60 in the opening 90 may also be removed. In some embodiments, only the dummy gate 72 is removed and the dummy dielectric layer 60 remains and is exposed by the opening 90. In some embodiments, the dummy dielectric layer 60 is removed from the opening 90 in a first region of the die (e.g., a core logic region) and remains in the opening 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactive gases that selectively etch the dummy gate 72 without etching the first ILD 88 or the gate spacer 86. Each opening 90 exposes the channel region 58 of the corresponding fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 82. During removal, the dummy dielectric layer 60 may serve as an etch stop layer as the dummy gate 72 is etched. Then, the dummy dielectric layer 60 can be optionally removed after the dummy gate 72 is removed.

[0047] Figure 14 This illustrates the formation of a gate stack 102 according to some embodiments (see [link]). Figures 21A-21D The flowchart of method 200. Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C and Figure 21DThis is a cross-sectional view of an intermediate stage in the fabrication of gate stack 102 according to method 200. Gate stack 102 may also be referred to as replacement gate stack or metal gate stack.

[0048] refer to Figure 14 , Figure 15A and Figure 15B In step 202, an interface layer 92 is formed along the sidewalls and bottom of the opening 90 and over the first ILD 88. The interface layer 92 may include silicon oxide and may be formed using a chemical deposition process such as ALD or CVD, or an oxidation process. In some embodiments, when the interface layer 92 is formed using a deposition process, the interface layer 92 extends along the exposed surfaces of the fin 52, the isolation region 56, and the gate sealing spacer 80. In some embodiments, when the interface layer 92 is formed using an oxidation process, the interface layer 92 extends along the exposed surface of the fin 52 and does not extend along the exposed surfaces of the isolation region 56 and the gate sealing spacer 80. In some embodiments, the thickness of the interface layer 92 is approximately... to approximately between.

[0049] refer to Figure 14 , Figure 16A and Figure 16B In step 204, a dipole layer 94 is formed over the interface layer 92 in the opening 90. In some embodiments, in region 50N (see...) Figure 2 In this embodiment, the dipole layer 94 comprises a metal oxide material such as lanthanum oxide (La₂O₃), yttrium oxide (Y₂O₃), or combinations thereof, and can be formed using ALD, CVD, or combinations thereof. In such embodiments, the dipole layer 94 may also be referred to as an n-dipole layer. In some embodiments, in region 50P (see...) Figure 2 In this embodiment, the dipole layer 94 comprises a metal oxide material such as zinc oxide (ZnO), aluminum oxide (Al2O3), gallium oxide (Ga2O or Ga2O3), or combinations thereof, and can be formed using ALD, CVD, or combinations thereof. In such embodiments, the dipole layer 94 may also be referred to as a p-dipole layer. In some embodiments, during the deposition process, some metal atoms of the dipole layer 94 diffuse into the interface layer 92 to form a metal-doped interface layer 92'. In some embodiments, the diffused metal atoms form a dipole at the interface between the metal-doped interface layer 92' and the subsequently formed gate dielectric layer, and change the threshold voltage of the resulting FinFET device. In some embodiments, the diffusion into the interface layer 92 can be increased by increasing the thickness of the dipole layer 94 (see [link to documentation]). Figure 15A and Figure 15B The amount of metal atoms in ). In some embodiments, the thickness of the dipole layer 94 is approximately to approximately between.

[0050] Figure 17 This illustrates the formation of a dipole layer 94 according to some embodiments (see [link]). Figure 16A and Figure 16B A flowchart of method 300. In some embodiments, method 300 may be implemented as step 204 of method 200 (see...). Figure 14 In the illustrated embodiment, method 300 includes an ALD process. Method 300 includes performing an ALD cycle 302 once or more. In some embodiments, the ALD cycle 302 is performed N2 times. In some embodiments, N2 can be between 1 and 100. In some embodiments, method 300 is performed at a temperature between about 150°C and about 650°C. In some embodiments, method 300 can be performed at a pressure between about 0.1 Torr and about 70 Torr.

[0051] In some embodiments, ALD loop 302 may include execution step 304, wherein at interface layer 92 (see...) Figure 15A and Figure 15B A metal-containing precursor is introduced onto the interface layer 92. In some embodiments, the metal-containing precursor is adsorbed onto the exposed surface of the interface layer 92. In some embodiments, the metal-containing precursor may be introduced over a time period of about 0.1 seconds to about 60 seconds. In some embodiments, the flow rate of the metal-containing precursor may be between about 200 sccm and about 5000 sccm.

[0052] In step 306, a non-reactive gas (e.g., N2, Ar, or combinations thereof) is used to purge the unadsorbed portion containing the metal precursor. In some embodiments, the purging is performed for a period between 0.1 seconds and 60 seconds. In some embodiments, the flow rate of the non-reactive gas can be between about 200 sccm and about 5000 sccm.

[0053] In step 308, an oxygen-containing precursor is introduced onto the adsorption portion of the metal-containing precursor. The oxygen-containing precursor reacts with the adsorption portion of the metal-containing precursor to form a metal oxide material of dipole layer 94. In some embodiments, the oxygen-containing precursor may include H2O, O2, O3, or combinations thereof. In some embodiments, the oxygen-containing precursor is introduced over a period of 0.1 seconds to about 60 seconds. In some embodiments, the flow rate of the oxygen-containing precursor may be between about 200 sccm and about 5000 sccm.

[0054] In step 310, a non-reactive gas (e.g., N2, Ar, or combinations thereof) is used to purge the reaction byproducts of step 308. In some embodiments, the purging is performed for a period between 0.1 seconds and 60 seconds. In some embodiments, the flow rate of the non-reactive gas can be between about 200 sccm and about 5000 sccm.

[0055] In some embodiments, when the dipole layer 94 comprises aluminum oxide (Al2O3), the metal-containing precursor comprises TMA (Al2(CH3)6), and the oxygen-containing precursor comprises H2O, the method 300 is performed at a temperature between about 250°C and about 550°C and a pressure between about 0.5 Torr and about 40 Torr.

[0056] In some embodiments, when the dipole layer 94 comprises lanthanum oxide (La2O3), the metal-containing precursor comprises La(fAMD)3, and the oxygen-containing precursor comprises H2O, the method 300 is performed at a temperature between about 100°C and about 450°C and a pressure between about 0.01 Torr and about 50 Torr.

[0057] In some embodiments, when the dipole layer 94 comprises yttrium oxide (Y2O3), the metal-containing precursor comprises Y(DPfAMD)3, and the oxygen-containing precursor comprises H2O, the method 300 is performed at a temperature between about 100°C and about 450°C and a pressure between about 0.01 Torr and about 50 Torr.

[0058] In some embodiments, when the dipole layer 94 comprises zinc oxide (ZnO), the metal-containing precursor comprises DEZn, and the oxygen-containing precursor comprises O3, the method 300 is performed at a temperature between about 100°C and about 450°C and a pressure between about 0.01 Torr and about 50 Torr.

[0059] In some embodiments, when the dipole layer 94 comprises gallium oxide (Ga2O or Ga2O3), the metal-containing precursor comprises TDMAGa, and the oxygen-containing precursor comprises O3, the method 300 is performed at a temperature between about 100°C and about 450°C and a pressure between about 0.1 Torr and about 50 Torr.

[0060] refer to Figure 14 , Figure 18A and Figure 18B In step 206, for dipole layer 94 (see...) Figure 16A and Figure 16B Perform a fluorine immersion process to form a fluorine-doped dipole layer 94'. In some embodiments, the fluorine immersion process includes... Figure 16A and Figure 16B The structure is immersed in a fluorinated chemical. The fluorinated chemical may include WF6, NF3, etc., or combinations thereof. In some embodiments, the fluorine immersion process includes a vapor-phase process, and Figure 16A and Figure 16BThe structure is immersed in a gas containing fluorine molecules 96 of a fluorinated chemical. In some embodiments, the fluorine molecules 96 are adsorbed onto the dipole layer 94 (see...). Figure 16A and Figure 16B Fluorine atoms from fluorine-containing molecules 96 diffuse into the dipole layer 94 on the exposed surface of the fluorine-doped dipole layer 94' to form a fluorine-doped dipole layer 94'. In other embodiments, the fluorine immersion process includes a liquid-phase process. In some embodiments, during the fluorine immersion process, some metal atoms of the fluorine-doped dipole layer 94' further diffuse into the metal-doped interface layer 92'.

[0061] In some embodiments, the fluorine immersion process is performed at a temperature between about 250°C and about 550°C. In some embodiments, the fluorine immersion process is performed at a pressure between about 0.5 Torr and about 40 Torr. In some embodiments, the fluorine concentration in the fluorine-doped dipole layer 94' can be increased by increasing the duration of the fluorine immersion process. In some embodiments, the fluorine immersion process is performed for a time between about 0.1 seconds and about 1800 seconds. In some embodiments, the fluorine concentration in the fluorine-doped dipole layer 94' is between about 0.01 at% and about 25 at%.

[0062] refer to Figure 14 , Figure 19A and Figure 19B In step 208, for Figure 18A and Figure 18B The structure is subjected to an annealing process. In some embodiments, the annealing process drives some fluorine and metal atoms from the fluorine-doped dipole layer 94' to the metal-doped interface layer 92' (see [link to documentation]). Figure 18A and Figure 18B In some embodiments, when the fluorine-doped dipole layer 94' is a fluorine-doped lanthanum oxide (La₂O₃) layer, the metal atom is lanthanum (La) atom. In some embodiments, when the fluorine-doped dipole layer 94' is a fluorine-doped yttrium oxide (Y₂O₃) layer, the metal atom is yttrium (Y) atom. In some embodiments, when the fluorine-doped dipole layer 94' is a fluorine-doped zinc oxide (ZnO) layer, the metal atom is zinc (Zn) atom. In some embodiments, when the fluorine-doped dipole layer 94' is a fluorine-doped... In the case of an aluminum oxide (Al₂O₃) layer, the metal atom is aluminum (Al) atom. In some embodiments, when the fluorine-doped dipole layer 94' is a fluorine-doped gallium oxide (Ga₂O or Ga₂O₃) layer, the metal atom is gallium (Ga) atom. In some embodiments, the annealing process is performed at a temperature between about 450°C and about 1100°C. In some embodiments, the annealing process is performed for a time between about 0.1 seconds and about 30 seconds. In some embodiments, steps 206 and 208 are performed N₁ times. N₁ can be between about 1 and about 5.

[0063] In some embodiments, the diffusion depth of fluorine and metal atoms within the metal / fluorine-doped interface layer 92” can be increased by increasing the temperature and / or duration of the annealing process. In some embodiments, fluorine and metal atoms diffuse to the upper surface of the metal / fluorine-doped interface layer 92” when the annealing process is performed for a time between about 0.1 seconds and about 1800 seconds. In such embodiments, the upper surface of the metal / fluorine-doped interface layer 92” has a fluorine concentration between about 0.001 at% and about 20 at%. Furthermore, in some embodiments, when the fluorine-doped dipole layer 94” comprises fluorine-doped lanthanum oxide (La2O3), the upper surface of the metal / fluorine-doped interface layer 92” has a lanthanum concentration between about 0.001 at% and about 15 at%.

[0064] In some embodiments, fluorine and metal atoms diffuse to the interface between the metal / fluorine-doped interface layer 92” and the corresponding fin 52 during the annealing process, which is performed for a time between about 0.1 seconds and about 1800 seconds. In such embodiments, the upper surface of the metal / fluorine-doped interface layer 92” has a fluorine concentration between about 0.001 at% and about 20 at%; the interior of the metal / fluorine-doped interface layer 92” has a fluorine concentration between about 0.001 at% and about 20 at%; and the interface between the metal / fluorine-doped interface layer 92” and the corresponding fin 52 has a fluorine concentration between about 0.001 at% and about 20 at%. Furthermore, in some embodiments, when the fluorine-doped dipole layer 94' comprises fluorine-doped lanthanum oxide (La2O3), the upper surface of the metal / fluorine-doped interface layer 92" has a lanthanum concentration between about 0.001 at% and about 15 at%, the interior of the metal / fluorine-doped interface layer 92" has a lanthanum concentration between about 0.001 at% and about 15 at%, and the interface between the metal / fluorine-doped interface layer 92" and the corresponding fin 52 has a lanthanum concentration between about 0.001 at% and about 15 at%.

[0065] In some embodiments, metal atoms diffused into the interface layer 92” may introduce energy states near the conduction band edge, which could lead to leakage paths and reliability weaknesses in the resulting gate stack. In some embodiments, fluorine atoms diffused into the interface layer 92” can remove energy states near the conduction band edge, improving gate stack reliability and reducing or eliminating gate leakage.

[0066] refer to Figure 14 , Figure 20A and Figure 20B In step 210, the fluorine-doped dipole layer 94' is removed (see...). Figure 19A and Figure 19B To expose the metal / fluorine-doped interface layer 92". In some embodiments, the removal process may include wet etching processes, such as dilute hydrofluoric acid (dHF) etching, SC1 process, SC2 process, etc., or combinations thereof.

[0067] refer to Figure 14 , Figure 21A and Figure 21B In step 212, at opening 90 (see...) Figure 20A and Figure 20B A gate dielectric layer 98 is formed on top of a metal / fluorine-doped interface layer 92”. In some embodiments, the gate dielectric layer 98 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 98 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 98 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric layer 98 may include molecular beam deposition (MBD), ALD, PECVD, or combinations thereof. In some embodiments, the gate dielectric layer 98 comprises atoms of a first metal element, while the metal / fluorine-doped interface layer 92” comprises atoms of a second metal element different from the first metal element.

[0068] Further reference Figure 14 , Figure 21A and Figure 21B In step 214, the gate electrode layer 100 is deposited on the gate dielectric layer 98 and fills the opening 90 (see [reference]). Figure 20A and Figure 20B The remainder of ). Although in Figure 21A and Figure 21B The diagram shows a single-layer gate electrode layer 100, but the gate electrode layer 100 may include any number of liner layers 100A, any number of work function adjustment layers 100B, and conductive fill layers 100C, such as... Figure 21C As shown, Figure 21C It shows Figure 21BA detailed view of region 104. Liner layer 100A may include TiN, TiO, TaN, TaC, combinations thereof, or multiple layers thereof, and may be formed using PVD, CVD, ALD, or combinations thereof. In region 50N, work function adjustment layer 100B may include Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations thereof, or multiple layers thereof, and may be formed using PVD, CVD, ALD, or combinations thereof. In region 50P, work function adjustment layer 100B may include TiN, WN, TaN, Ru, Co, combinations thereof, or multiple layers thereof, and may be formed using PVD, CVD, ALD, or combinations thereof. In some embodiments, the conductive filler layer 100C may include Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, or multilayers thereof, and may be formed using PVD, CVD, ALD, electroplating, or combinations thereof.

[0069] In filling opening 90 (see) Figure 20A and Figure 20B Following this, a planarization process such as CMP can be performed to remove excess portions of the gate dielectric layer 98, gate electrode layer 100, and / or metal / fluorine-doped interface layer 92”, which lie above the top surface of the first ILD 88. The remaining portions of the gate dielectric layer 98, gate electrode layer 100, and metal / fluorine-doped interface layer 92” thus form the gate stack 102 of the resulting FinFET. The gate stack 102 may extend along the sidewalls of the channel region 58 of the fin 52.

[0070] Figure 21D It shows Figure 21C A detailed view of region 106. In some embodiments, fluorine atoms within the metal / fluorine-doped interface layer 92" diffuse into the corresponding fin 52 and the corresponding gate dielectric layer 98, forming various bonds at the interfaces between the metal / fluorine-doped interface layer 92" and the corresponding fin 52, and at the interfaces between the metal / fluorine-doped interface layer 92" and the corresponding gate dielectric layer 98. In some embodiments, fluorine atoms form F-Si bonds at the interfaces between the metal / fluorine-doped interface layer 92" and the corresponding fin 52, and at the interfaces between the metal / fluorine-doped interface layer 92" and the corresponding gate dielectric layer 98. In some embodiments, when the gate dielectric layer 98 is made of hafnium oxide (HfO2), fluorine atoms form Hf-F bonds at the interfaces between the metal / fluorine-doped interface layer 92" and the corresponding gate dielectric layer 98. The F-Si and Hf-F bonds form strong bonds at the interfaces and improve the reliability of the gate stack 102.

[0071] In some embodiments, some metal atoms within the metal / fluorine doped interface layer 92 diffuse into the corresponding gate dielectric layer 98 and the corresponding fin 52. In some embodiments, when the gate dielectric layer 98 is made of hafnium oxide (HfO2) and the metal atoms are lanthanum (La) atoms, the ratio of lanthanum (La) concentration to hafnium (Hf) concentration in the gate dielectric layer 98 is between about 0.014 and about 0.4. In some embodiments, when the gate dielectric layer 98 is made of hafnium oxide (HfO2), the ratio of fluorine (F) concentration to hafnium (Hf) concentration in the gate dielectric layer 98 is between about 0.014 and about 0.4.

[0072] The formation of the gate dielectric layer 98 in regions 50N and 50P can occur simultaneously, such that the gate dielectric layer 98 in each region is formed of the same material. In other embodiments, the gate dielectric layer 98 in each region can be formed using different processes, such that the gate dielectric layer 98 in different regions can be formed of different materials. The formation of the conductive fill layer 100C in regions 50N and 50P can occur simultaneously, such that the conductive fill layer 100C in each region is formed of the same material. In other embodiments, the conductive fill layer 100C in each region can be formed using different processes, such that the conductive fill layer 100C in different regions can be formed of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0073] exist Figure 22A and Figure 22B In this process, after forming the gate stack 102, a second ILD 110 is deposited on top of the first ILD 88 and the gate stack 102. In some embodiments, the second ILD 110 is formed using similar materials and methods to the first ILD 88, and will not be described again here. In some embodiments, the first ILD 88 and the second ILD 110 comprise the same material. In other embodiments, the first ILD 88 and the second ILD 110 comprise different materials.

[0074] In some embodiments, prior to the formation of the second ILD 110, the gate stack 102 is recessed, thereby forming a recess between the gate stack 102 directly above and the opposing portion of the gate sealing spacer 80. A gate mask 108 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, combinations thereof, etc.) is filled into the recess, followed by a planarization process to remove excess dielectric material extending above the first ILD 88. The gate contact 112 is subsequently formed (see...). Figure 23A and Figure 23BIt penetrates the corresponding gate mask 108 to contact the top surface of the corresponding recessed gate electrode layer 100.

[0075] According to some embodiments, in Figure 23A and Figure 23B In this configuration, gate contact 112 and source / drain contact 114 are formed through the second ILD 110 and the first ILD 88. An opening for the source / drain contact 114 is formed through the first ILD 88, the second ILD 110, and CESL 87, and an opening for the gate contact 112 is formed through the second ILD 110 and the gate mask 108. These openings can be formed using acceptable photolithography and etching techniques. After forming the openings for the source / drain contact 114, a silicide layer 116 is formed through the openings for the source / drain contact 114. In some embodiments, a metal material is deposited in the openings for the source / drain contact 114. This metal material may include Ti, Co, Ni, NiCo, Pt, NiPt, Ir, PtIr, Er, Yb, Pd, Rh, Nb, or combinations thereof, and can be formed using PVD, sputtering, or combinations thereof. Subsequently, an annealing process is performed to form a silicide layer 116. In some embodiments where the epitaxial source / drain region 82 includes silicon, the annealing process reacts the metal material with the silicon to form a silicide of the metal material at the interface between the metal material and the epitaxial source / drain region 82. After the silicide layer 116 is formed, an appropriate removal process (e.g., an appropriate etching process) is used to remove unreacted portions of the metal material.

[0076] Subsequently, a liner (e.g., a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the openings for the source / drain contacts 114 and the openings for the gate contacts 112. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, combinations thereof, etc. The conductive material may include copper, copper alloys, silver, gold, tungsten, cobalt, aluminum, nickel, combinations thereof, etc. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD 110. The remaining portion of the liner and conductive material forms the source / drain contacts 114 and the gate contact 112 in the openings. The source / drain contacts 114 are electrically coupled to the corresponding epitaxial source / drain regions 82, and the gate contact 112 is electrically coupled to the corresponding gate electrode layer 100. The source / drain contacts 114 and the gate contact 112 may be formed using different processes or the same process. Although each of the source / drain contact 114 and the gate contact 112 is shown to be formed in the same cross section, it should be understood that each of the source / drain contact 114 and the gate contact 112 may be formed in different cross sections, which can avoid short circuits in the contacts.

[0077] Figure 24A and Figure 24B This is a cross-sectional view of a FinFET device according to some embodiments. Figure 24A It shows along Figure 1 The cross-sectional view of reference section AA shown in the figure. Figure 24B It shows along Figure 1 The cross-sectional view of reference section BB shown. In some embodiments, Figure 24A and Figure 24B The FinFET device shown is... Figure 23A and Figure 23B The FinFET devices shown are similar, with similar features denoted by similar reference numerals, and descriptions of similar features will not be repeated herein. In some embodiments, Figure 24A and Figure 24B The FinFET device shown can be used with the above reference. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 10C , Figure 10D , Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 21C , Figure 21D , Figure 22A , Figure 22B , Figure 23A and Figure 23B The process steps described are similar to those used in the formation process, and will not be repeated here. Figure 24A and Figure 24B In the embodiment shown, the interface layer 92” is formed using an oxidation process, such that the interface layer 92” extends along the surface of the fin 52 and does not extend along the top surface of the isolation region 56 and the sidewall of the gate sealing spacer 80.

[0078] The disclosed FinFET embodiments can also be applied to gate all-around (GAA) devices, such as nanostructured (e.g., nanosheets, nanowires, etc.) field-effect transistors (NSFETs). In NSFET embodiments, the fins are replaced by nanostructures formed by patterning an alternating stack of channel and sacrificial layers. The dummy gate stack and source / drain regions are formed in a manner similar to the embodiments described above. After the dummy gate stack is removed, the sacrificial layer can be partially or completely removed in the channel region. The replacement gate structure is formed in a manner similar to the embodiments described above, and the replacement gate structure can partially or completely fill the opening left by removing the sacrificial layer, and the replacement gate structure can partially or completely surround the channel layer in the channel region of the NSFET device. The ILD and contacts for the replacement gate structure and source / drain regions can be formed in a manner similar to the embodiments described above. Nanostructured devices can be formed as disclosed in U.S. Patent No. 9,647,071, which is incorporated herein by reference in its entirety. Such NSFET embodiments are described below. Figure 25A , Figure 25B , Figure 26A and Figure 26B As shown in the image.

[0079] Figure 25A and Figure 25B This is a cross-sectional view of an NSFET device according to some embodiments. Figure 25A It shows along Figure 1 The cross-sectional view of reference section AA shown in the figure. Figure 25B It shows along Figure 1 The cross-sectional view of the reference section BB shown. Figure 25A and Figure 25B The structure shown is similar to Figure 23A and Figure 23B The structures shown are illustrated, with similar features indicated by similar reference numerals, and descriptions of similar features will not be repeated here. Instead of fin 52 (see...),... Figure 23A and Figure 23B ), Figure 25A and Figure 25BThe structure shown includes a nanostructure 118 such that a portion of the gate stack 102 surrounds the nanostructure 118. In some embodiments, the portion of the gate stack 102 surrounding the nanostructure 118 is isolated from adjacent epitaxial source / drain regions 82 by spacers 120. In some embodiments, the nanostructure 118 may be formed using a material similar to that of the substrate 50, and will not be described again here. In some embodiments, the nanostructure 118 and the substrate 50 comprise the same material. In other embodiments, the nanostructure 118 and the substrate 50 comprise different materials. The spacers 120 may comprise a material such as silicon nitride or silicon oxynitride, but any suitable material may be used, such as a low dielectric constant (low-k) material with a k value less than about 3.5.

[0080] Figure 26A and Figure 26B This is a cross-sectional view of an NSFET device according to some embodiments. Figure 26A It shows along Figure 1 The cross-sectional view of reference section AA shown in the figure. Figure 26B It shows along Figure 1 The cross-sectional view of the reference section BB shown. Figure 26A and Figure 26B The structure shown is similar to Figure 24A and Figure 24B The structures shown are illustrated, with similar features indicated by similar reference numerals, and descriptions of similar features will not be repeated here. Instead of fin 52 (see...),... Figure 24A and Figure 24B ), Figure 26A and Figure 26B The structure shown includes a nanostructure 118 such that a portion of the gate stack 102 surrounds the nanostructure 118. In some embodiments, the portion of the gate stack 102 surrounding the nanostructure 118 is isolated from adjacent epitaxial source / drain regions 82 by spacers 120. In some embodiments, the nanostructure 118 may be formed using a material similar to that of the substrate 50, and will not be described again here. In some embodiments, the nanostructure 118 and the substrate 50 comprise the same material. In other embodiments, the nanostructure 118 and the substrate 50 comprise different materials. The spacers 120 may comprise a material such as silicon nitride or silicon oxynitride, but any suitable material may be used, such as a low dielectric constant (low-k) material with a k value less than about 3.5.

[0081] The embodiments can achieve several advantages. By doping the interface layer with metal and fluorine atoms as described above, the threshold voltage (V) of the semiconductor device is improved (or reduced). t This improves the reliability of the gate stack and reduces or eliminates gate leakage.

[0082] According to one embodiment, a method includes forming a fin extending from a substrate. A dummy gate is formed over the fin. The dummy gate extends along the sidewalls and top surface of the fin. The dummy gate is removed to form a recess. A replacement gate is formed in the recess. Forming the replacement gate includes forming an interface layer along the sidewalls and bottom of the recess. A dipole layer is formed over the interface layer. The dipole layer includes metal atoms. Fluorine atoms are introduced into the dipole layer. Fluorine atoms and metal atoms from the dipole layer are driven into the interface layer. The dipole layer is removed. In one embodiment, the dipole layer includes a metal oxide material. In one embodiment, introducing fluorine atoms into the dipole layer includes immersing the dipole layer in a fluorinated chemical. In one embodiment, the fluorinated chemical includes WF6 or NF3. In one embodiment, driving fluorine atoms and metal atoms from the dipole layer into the interface layer includes performing an annealing process. In one embodiment, removing the dipole layer includes etching the dipole layer. In one embodiment, forming the dipole layer includes performing an atomic layer deposition (ALD) process.

[0083] According to another embodiment, a method includes patterning a substrate to form a fin. A dummy gate is formed on the fin. The dummy gate extends along the sidewalls and top surface of the fin. The dummy gate is etched to form a recess. A replacement gate is formed in the recess. Forming the replacement gate includes depositing an interface layer along the sidewalls and bottom of the recess. A dipole layer is deposited on the interface layer. The dipole layer includes metal atoms. A fluorine immersion process is performed on the dipole layer to form a doped dipole layer. The doped dipole layer includes fluorine atoms. An annealing process is performed to drive fluorine atoms and metal atoms from the doped dipole layer into the interface layer and form a doped interface layer. The doped dipole layer is etched to expose the doped interface layer. A gate dielectric layer is deposited on the doped interface layer. A gate electrode layer is deposited on the gate dielectric layer. In one embodiment, the dipole layer includes lanthanum oxide, yttrium oxide, zinc oxide, aluminum oxide, or gallium oxide. In one embodiment, the annealing process drives some fluorine atoms and some metal atoms to the interface between the doped interface layer and the fin. In one embodiment, the interface layer includes silicon oxide. In one embodiment, the fluorine immersion process and the annealing process are performed two or more times. In one embodiment, performing a fluorine immersion process on the dipole layer includes immersing the dipole layer in WF6 or NF3. In one embodiment, the metal atom is lanthanum, yttrium, zinc, aluminum, or gallium.

[0084] According to another embodiment, a device includes a fin extending from a substrate and an isolation structure on the substrate and adjacent to the fin. The top surface of the fin is higher than the top surface of the isolation structure. The device also includes a gate stack extending along the top surface and sidewalls of the fin and the top surface of the isolation structure. The gate stack includes an interface layer along the top surface and sidewalls of the fin, and a gate dielectric layer above the interface layer. The interface layer includes a dielectric material doped with atoms of a first metal element and fluorine atoms. The interface between the interface layer and the fin includes F-Si bonds. The gate dielectric layer includes atoms of a second metal element. The interface between the interface layer and the gate dielectric layer includes bonds between some atoms of the second metal element and some fluorine atoms. In one embodiment, the first metal element is lanthanum, yttrium, zinc, aluminum, or gallium. In one embodiment, the dielectric material includes silicon oxide. In one embodiment, the first metal element is different from the second metal element. In one embodiment, the gate dielectric layer includes hafnium oxide (HfO2), and the interface between the interface layer and the gate dielectric layer includes Hf-F bonds. In one embodiment, the gate dielectric layer is a metal / fluorine doped layer.

[0085] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0086] Example 1. A method of forming a semiconductor device, comprising: forming a fin extending from a substrate; forming a dummy gate over the fin, the dummy gate extending along a sidewall and a top surface of the fin; removing the dummy gate to form a recess; and forming a replacement gate in the recess, wherein forming the replacement gate comprises: forming an interface layer along a sidewall and a bottom of the recess; forming a dipole layer over the interface layer, the dipole layer comprising metal atoms; introducing fluorine atoms into the dipole layer; driving the fluorine atoms and the metal atoms from the dipole layer into the interface layer; and removing the dipole layer.

[0087] Example 2. The method according to Example 1, wherein the dipole layer comprises a metal oxide material.

[0088] Example 3. The method according to Example 1, wherein introducing the fluorine atoms into the dipole layer comprises immersing the dipole layer in a fluorinated chemical.

[0089] Example 4. The method according to Example 3, wherein the fluorinated chemical comprises WF6 or NF3.

[0090] Example 5. The method according to Example 1, wherein driving the fluorine atoms and the metal atoms from the dipole layer into the interface layer includes performing an annealing process.

[0091] Example 6. The method according to Example 1, wherein removing the dipole layer includes etching the dipole layer.

[0092] Example 7. The method according to Example 1, wherein forming the dipole layer includes performing an atomic layer deposition (ALD) process.

[0093] Example 8. A method of forming a semiconductor device, comprising: patterning a substrate to form a fin; forming a dummy gate over the fin, the dummy gate extending along a sidewall and a top surface of the fin; etching the dummy gate to form a recess; and forming a replacement gate in the recess, wherein forming the replacement gate comprises: depositing an interface layer along the sidewall and bottom of the recess; depositing a dipole layer over the interface layer, the dipole layer comprising metal atoms; performing a fluorine immersion process on the dipole layer to form a doped dipole layer, the doped dipole layer comprising fluorine atoms; performing an annealing process to drive the fluorine atoms and the metal atoms from the doped dipole layer into the interface layer and form a doped interface layer; etching the doped dipole layer to expose the doped interface layer; depositing a gate dielectric layer over the doped interface layer; and depositing a gate electrode layer over the gate dielectric layer.

[0094] Example 9. The method according to Example 8, wherein the dipole layer comprises lanthanum oxide, yttrium oxide, zinc oxide, aluminum oxide, or gallium oxide.

[0095] Example 10. The method according to Example 8, wherein the annealing process drives some of the fluorine atoms and some of the metal atoms to the interface between the doped interface layer and the fin.

[0096] Example 11. The method according to Example 8, wherein the interface layer comprises silicon oxide.

[0097] Example 12. The method according to Example 8, wherein the fluorine immersion process and the annealing process are performed two or more times.

[0098] Example 13. The method according to Example 8, wherein performing the fluorine immersion process on the dipole layer includes immersing the dipole layer in WF6 or NF3.

[0099] Example 14. The method according to Example 8, wherein the metal atom is a lanthanum atom, a yttrium atom, a zinc atom, an aluminum atom, or a gallium atom.

[0100] Example 15. A semiconductor device comprising: a fin extending from a substrate; an isolation structure on the substrate and adjacent to the fin, wherein a top surface of the fin is higher than a top surface of the isolation structure; and a gate stack extending along the top surface and sidewalls of the fin and the top surface of the isolation structure, wherein the gate stack comprises: an interface layer along the top surface and sidewalls of the fin, the interface layer comprising a dielectric material doped with atoms of a first metal element and fluorine atoms, wherein the interface between the interface layer and the fin comprises F-Si bonds; and a gate dielectric layer on the interface layer, the gate dielectric layer comprising atoms of a second metal element, wherein the interface between the interface layer and the gate dielectric layer comprises bonds between some atoms of the second metal element and some of the fluorine atoms.

[0101] Example 16. The device according to Example 15, wherein the first metallic element is lanthanum, yttrium, zinc, aluminum or gallium.

[0102] Example 17. The device according to Example 15, wherein the dielectric material comprises silicon oxide.

[0103] Example 18. The device according to Example 15, wherein the first metal element is different from the second metal element.

[0104] Example 19. The device according to Example 15, wherein the gate dielectric layer comprises hafnium oxide (HfO2), and wherein the interface between the interface layer and the gate dielectric layer comprises Hf-F bonds.

[0105] Example 20. The device according to Example 15, wherein the gate dielectric layer is a metal / fluorine doped layer.

Claims

1. A method for forming a semiconductor device, comprising: Forming fins that extend from the substrate; A dummy gate is formed on the fin, and the dummy gate extends along the sidewall and top surface of the fin; Remove the dummy gate to form a recess; as well as A replacement gate is formed in the recess, wherein forming the replacement gate includes: An interface layer is formed along the sidewalls and bottom of the recess; A dipole layer is formed on the interface layer, the dipole layer comprising metal atoms; Fluorine atoms are introduced into the dipole layer; The fluorine atoms and the metal atoms from the dipole layer are driven into the interface layer; Remove the dipole layer to expose the interface layer; and A gate dielectric layer is deposited on the interface layer, wherein the gate dielectric layer is made of hafnium oxide, and the ratio of fluorine concentration to hafnium concentration in the gate dielectric layer is between 0.014 and 0.

4.

2. The method according to claim 1, wherein, The dipole layer comprises a metal oxide material.

3. The method according to claim 1, wherein, Introducing the fluorine atoms into the dipole layer includes immersing the dipole layer in a fluorine-containing chemical.

4. The method according to claim 3, wherein, The fluorinated chemicals include WF6 or NF3.

5. The method according to claim 1, wherein, Driving the fluorine atoms and the metal atoms from the dipole layer into the interface layer includes performing an annealing process.

6. The method according to claim 1, wherein, Removing the dipole layer includes etching the dipole layer.

7. The method according to claim 1, wherein, Forming the dipole layer includes performing an atomic layer deposition (ALD) process.

8. A method of forming a semiconductor device, comprising: The substrate is patterned to form fins; A dummy gate is formed on the fin, and the dummy gate extends along the sidewall and top surface of the fin; The dummy gate is etched to form a recess; as well as A replacement gate is formed in the recess, wherein forming the replacement gate includes: An interface layer is deposited along the sidewalls and bottom of the recess; A dipole layer is deposited on the interface layer, the dipole layer comprising metal atoms; A fluorine immersion process is performed on the dipole layer to form a doped dipole layer, the doped dipole layer comprising fluorine atoms; An annealing process is performed to drive the fluorine atoms and the metal atoms from the doped dipole layer into the interface layer and form a doped interface layer; Etch the doped dipole layer to expose the doped interface layer; A gate dielectric layer is deposited on the doped interface layer, wherein the gate dielectric layer is made of hafnium oxide, and the ratio of fluorine concentration to hafnium concentration in the gate dielectric layer is between 0.014 and 0.4; and A gate electrode layer is deposited on the gate dielectric layer.

9. The method according to claim 8, wherein, The dipole layer includes lanthanum oxide, yttrium oxide, zinc oxide, aluminum oxide, or gallium oxide.

10. The method according to claim 8, wherein, The annealing process drives some of the fluorine atoms and some of the metal atoms to the interface between the doped interface layer and the fin.

11. The method according to claim 8, wherein, The interface layer comprises silicon oxide.

12. The method according to claim 8, wherein, The fluorine immersion process and the annealing process are performed two or more times.

13. The method according to claim 8, wherein, Performing the fluorine immersion process on the dipole layer includes immersing the dipole layer in WF6 or NF3.

14. The method according to claim 8, wherein, The metal atom is a lanthanum atom, yttrium atom, zinc atom, aluminum atom, or gallium atom.

15. A semiconductor device, comprising: Fins extend from the substrate; An isolation structure, situated on the substrate and adjacent to the fin, wherein the top surface of the fin is higher than the top surface of the isolation structure; and A gate stack extends along the top surface and sidewalls of the fin and the top surface of the isolation structure, wherein the gate stack comprises: An interface layer, extending along the top surface and sidewalls of the fin, comprising a dielectric material doped with atoms of a first metal element and fluorine atoms, wherein the interface between the interface layer and the fin comprises F-Si bonds; and A gate dielectric layer is provided above the interface layer. The gate dielectric layer comprises atoms of a second metal element, wherein the interface between the interface layer and the gate dielectric layer comprises bonds between some atoms of the second metal element and some of the fluorine atoms. The gate dielectric layer is made of hafnium oxide, and the ratio of fluorine concentration to hafnium concentration in the gate dielectric layer is between 0.014 and 0.

4.

16. The device according to claim 15, wherein, The first metallic element is lanthanum, yttrium, zinc, aluminum, or gallium.

17. The device according to claim 15, wherein, The dielectric material includes silicon oxide.

18. The device according to claim 15, wherein, The first metallic element is different from the second metallic element.

19. The device according to claim 15, wherein, The interface between the interface layer and the gate dielectric layer includes Hf-F bonds.

20. The device according to claim 15, wherein, The gate dielectric layer is a metal / fluorine doped layer.

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