Half-bridge intelligent power module based on gallium nitride power chip and preparation method thereof

Abstract

A half-bridge intelligent power module based on a gallium nitride power chip and a preparation method thereof, comprising a gallium nitride chip, a decoupling capacitor, a first driving chip, a second driving chip, a power copper surface, a driving copper surface, a first driving chip peripheral circuit, a second driving chip peripheral circuit and a bottom ceramic substrate; a plurality of power copper surfaces and driving copper surfaces are arranged on the bottom ceramic substrate, the gallium nitride chip and the decoupling capacitor are arranged on the power copper surface, the first driving chip and the second driving chip are arranged on the driving copper surface, and the first driving chip and the second driving chip are respectively connected with the first driving chip peripheral circuit and the second driving chip peripheral circuit; the first driving chip and the second driving chip are used for driving the gallium nitride chip. The application realizes the integration of the driving chip in the module. The power circuit is optimized, the power commutation loop parasitic inductance is less than 2 nH, and the overvoltage and current oscillation in the chip opening and closing process are effectively reduced.

Description

Technical Field

[0001] This invention belongs to the field of intelligent power module technology, and specifically relates to a half-bridge intelligent power module based on gallium nitride power chips and its fabrication method. Background Technology

[0002] Gallium nitride (GaN) power devices, as representatives of wide-bandgap semiconductors, are gradually replacing traditional silicon-based power devices in the power semiconductor market due to their superior characteristics of high frequency and high efficiency. However, most wide-bandgap semiconductors still use the packaging and integration methods of traditional silicon-based semiconductors, which limits the full realization of their superior characteristics and is a bottleneck problem for the application of wide-bandgap semiconductor power devices. Compared with traditional silicon devices, gallium nitride devices have higher switching speeds, and are therefore more sensitive to parasitic parameters during switching. If the chip packaging technology is inappropriate, it can cause serious problems such as overvoltage and electromagnetic interference, resulting in increased losses in power electronic switching devices, decreased device reliability, and even device damage. Summary of the Invention

[0003] The purpose of this invention is to provide a half-bridge intelligent power module based on gallium nitride power chips and its fabrication method, so as to solve the problem that gallium nitride devices are more sensitive to parasitic parameters during switching than traditional silicon devices, which can cause serious overvoltage and electromagnetic interference.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] A half-bridge intelligent power module based on a gallium nitride (GaN) power chip includes a GaN chip, a decoupling capacitor, a first driver chip, a second driver chip, a power copper surface, a driving copper surface, peripheral circuits of the first driver chip, peripheral circuits of the second driver chip, and a bottom ceramic substrate. Several power copper surfaces and driving copper surfaces are disposed on the bottom ceramic substrate. The GaN chip and the decoupling capacitor are disposed on the power copper surfaces. The first and second driver chips are disposed on the driving copper surfaces. The first and second driver chips are respectively connected to the peripheral circuits of the first and second driver chips. The first and second driver chips are used to drive the GaN chip.

[0006] Furthermore, the power copper surface includes a first power copper surface, a second power copper surface, a third power copper surface, and a fourth power copper surface; the driving copper surface includes a first driving copper surface, a second driving copper surface, a third driving copper surface, and a fourth driving copper surface; the gallium nitride power chip is connected to the first power copper surface, the second power copper surface, the third power copper surface, the fourth power copper surface, the first driving copper surface, the second driving copper surface, the third driving copper surface, and the fourth driving copper surface; a top ceramic substrate is disposed on the gallium nitride power chip; a decoupling capacitor is connected to the first power copper surface and the second power copper surface; and a fifth power copper surface is disposed on the back side of the bottom ceramic substrate.

[0007] Furthermore, the peripheral circuit of the first driver chip includes a first driver resistor, a second driver resistor, and a first driver capacitor; the first driver resistor, the second driver resistor, and the first driver capacitor are all connected to the first driver chip.

[0008] Furthermore, the driving copper surface also includes a fifth driving copper surface, a seventh driving copper surface, an eleventh driving copper surface, a twelfth driving copper surface, and a thirteenth driving copper surface; the first driving resistor and the second driving resistor are connected to the first driving copper surface through the eleventh driving copper surface; the first driving resistor and the second driving resistor are connected to the first driving chip through the twelfth driving copper surface and the thirteenth driving copper surface; the first driving capacitor is connected to the first driving chip through the fifth driving copper surface, the seventh driving copper surface, and the first driving chip.

[0009] Furthermore, the peripheral circuit of the second driver chip includes a third driver resistor, a fourth driver resistor, and a second driver capacitor; the third driver resistor, the fourth driver resistor, and the second driver capacitor are all connected to the second driver chip.

[0010] Furthermore, the driving copper surface also includes a fourteenth driving copper surface, a fifteenth driving copper surface, a sixteenth driving copper surface, an eighth driving copper surface, and a tenth driving copper surface; the third driving resistor and the fourth driving resistor are connected to the third driving copper surface through the fourteenth driving copper surface; the third driving resistor and the fourth driving resistor are connected to the second driving chip through the fifteenth driving copper surface, the sixteenth driving copper surface, and the second driving chip; the second driving capacitor is connected to the second driving chip through the eighth driving copper surface, the tenth driving copper surface, and the second driving chip; both the first driving chip and the second driving chip are used to drive the packaged gallium nitride chip.

[0011] Furthermore, the first driver chip is also connected to the sixth driver copper surface; the second driver chip is also connected to the ninth driver copper surface.

[0012] Furthermore, the fifth driving copper surface is connected to the first driving terminal; the sixth driving copper surface is connected to the second driving terminal; the seventh driving copper surface is connected to the third driving terminal; the eighth driving copper surface is connected to the fourth driving terminal; the ninth driving copper surface is connected to the fifth driving terminal; and the tenth driving copper surface is connected to the sixth driving terminal.

[0013] Furthermore, the second power copper surface is connected to the first power terminal, the third power copper surface is connected to the second power terminal, and the fourth power copper surface is connected to the third power terminal.

[0014] Furthermore, the fabrication method of the half-bridge smart power module based on gallium nitride power chips includes the following steps:

[0015] The gallium nitride chip and copper pillars are connected to a temporary carrier board. The upper surface is covered with an insulating layer and patterned. After curing, the surface is polished and thinned until the copper layer on the chip surface is exposed.

[0016] Sputtering a seed adhesion layer, using photoresist as the pattern to be electroplated, electroplating a copper layer, and completing the interconnection between the electrodes on the chip surface;

[0017] Remove the photoresist and etch the sputtered seed adhesion layer; cover and pattern the surface insulating layer, wait for it to cure, then polish and thin it until the electroplated surface copper layer is exposed;

[0018] The seed adhesion layer is sputtered again, and photoresist is used as the pattern to be electroplated. The copper pad terminals corresponding to the half-bridge module are then electroplated.

[0019] Remove the photoresist and etch the sputtered seed adhesion layer; cover and pattern the surface insulating layer, wait for it to cure, then polish and thin it until the electroplated surface copper is exposed;

[0020] The module is flipped over and reconnected to a temporary carrier board; a seed adhesion layer is sputtered, and photoresist is used as the pattern to be electroplated; the connection between the gallium nitride chip substrate and the copper pillar is electroplated.

[0021] Remove the photoresist and etch the sputtered seed adhesion layer; cover and pattern the surface insulating layer, wait for it to cure, then polish and thin it until the electroplated surface copper is exposed, and remove the half-bridge power chip that has completed the Fan-out packaging.

[0022] Soldering material is applied to the surface of the bottom ceramic substrate using a stencil to ensure that the solder can complete the soldering of the terminals without applying too much.

[0023] The driver chip, decoupling capacitor, resistor, packaged power half-bridge chip, power terminals and driver terminals are placed in designated positions on the bottom ceramic substrate using a pick-and-place machine.

[0024] The ceramic substrate is placed in a customized graphite fixture; the graphite fixture has threads, and the height of the adjustable nut is used to fix the chip and terminals.

[0025] The power module is placed in a vacuum welding furnace, and the corresponding temperature profile is set for vacuum welding; residual flux on the module surface is cleaned.

[0026] Apply soldering material to the surface of the top ceramic substrate using a stencil to ensure that the solder can complete the soldering of the terminals without applying too much; then place the module on the top ceramic substrate.

[0027] Place it into a customized graphite fixture, set the corresponding temperature profile in a vacuum welding furnace, and perform vacuum welding; clean the residual flux on the module surface.

[0028] Compared with the prior art, the present invention has the following technical effects:

[0029] This invention relates to a single-phase full-bridge intelligent power module designed based on gallium nitride (GaN) chips. The module features a GaN-based full-bridge layout and integrates the driver chip within the module. The power circuit is optimized, with the parasitic inductance of the power commutation circuit being less than 2nH, effectively reducing overvoltage and current oscillations during chip turn-on and turn-off. Simultaneously, the parasitic inductance of the bonding wire drive circuit is optimized to reduce false turn-on of the GaN chip. A ceramic substrate is used for heat dissipation, reducing the module's thermal resistance.

[0030] This module is suitable for applications requiring high power density and plays an important role in the application of new energy vehicles and energy conservation and emission reduction in home appliances. It can bring significant economic benefits and support the industrialization of gallium nitride modular packaging. Attached Figure Description

[0031] Figure 1 This is the circuit schematic diagram of the entire IPM of this invention;

[0032] Figure 2 This is a split view of the three-dimensional structure of the present invention;

[0033] Figure 3 This is a schematic diagram of the half-bridge topology converter circuit of the present invention.

[0034] Figure 4 This is a flowchart illustrating the processing technology of this invention;

[0035] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0036] in

[0037] 1. Packaged gallium nitride half-bridge chip; 2. Top ceramic substrate; 3. Bottom ceramic substrate; 4. First power copper surface; 5. Second power copper surface; 6. Third power copper surface; 7. Fourth power copper surface; 8. First power terminal; 9. Second power terminal; 10. Third power terminal; 11. Decoupling capacitor; 12. First driving copper surface; 13. Second driving copper surface; 14. Third driving copper surface; 15. Fourth driving copper surface; 16. First driving resistor; 17. Second driving resistor; 18. Third driving resistor; 19. Fourth driving resistor; 20. Second driving chip; 21. Second driving capacitor; 22. First 23. Second drive terminal; 24. Third drive terminal; 25. Fourth drive terminal; 26. Fifth drive terminal; 27. Sixth drive terminal; 28. First drive capacitor; 29. ​​First drive chip; 30. Fifth drive copper surface; 31. Sixth drive copper surface; 32. Seventh drive copper surface; 33. Eighth drive copper surface; 34. Ninth drive copper surface; 35. Tenth drive copper surface; 36. Eleventh drive copper surface; 37. Twelfth drive copper surface; 38. Thirteenth drive copper surface; 39. Fourteenth drive copper surface; 40. Fifteenth drive copper surface; 41. Sixteenth drive copper surface; 42. Fifth power copper surface. Detailed Implementation

[0038] The present invention will be further described below with reference to the accompanying drawings:

[0039] Please see Figures 1 to 4 A half-bridge intelligent power module based on a gallium nitride (GaN) power chip and its fabrication method are described. The packaged GaN power chip 1 is connected to a first power copper surface 4, a second power copper surface 5, a third power copper surface 6, a fourth power copper surface 7, a first driving copper surface 12, a second driving copper surface 13, a third driving copper surface 14, and a fourth driving copper surface 15. A decoupling capacitor 11 is connected to the first power copper surface 4 and the second power copper surface 5. A first power terminal 8 is connected to the second power copper surface 5. A second power terminal 9 is connected to the third power copper surface 6. A third power terminal 10 is connected to the fourth power copper surface 7.

[0040] The first driving resistor 16, the second driving resistor 17, and the first driving capacitor 21 constitute the peripheral circuit of the first driving chip 29; the third driving resistor 18, the fourth driving resistor 19, and the second driving capacitor 28 constitute the peripheral circuit of the second driving chip 20. The first driving resistor 16 and the second driving resistor 17 are connected to copper surface 12 via copper surface 36. The first driving resistor 16 and the second driving resistor 17 are connected to the first driving chip 29 via copper surfaces 37 and 38. The first driving capacitor 21 is connected to the first driving chip 29 via copper surfaces 30 and 32. The third driving resistor 18 and the fourth driving resistor 19 are connected to copper surface 14 via copper surface 39. The third driving resistor 18 and the fourth driving resistor 19 are connected to the second driving chip 20 via copper surfaces 40 and 41. The second driving capacitor 28 is connected to the second driving chip 20 via copper surfaces 33 and 35. Both the first driving chip 29 and the second driving chip 20 are used to drive the packaged gallium nitride half-bridge chip 1.

[0041] The first driving resistor 16 is connected to copper surfaces 36 and 38; the second driving resistor 17 is connected to copper surfaces 36 and 37; the third driving resistor 18 is connected to copper surfaces 39 and 41; and the fourth driving resistor 19 is connected to copper surfaces 39 and 40. The first driving capacitor 21 is connected to copper surfaces 30 and 32; and the second driving capacitor 28 is connected to copper surfaces 33 and 35. The first driving chip 29 is connected to copper surfaces 30, 31, 32, 37, and 38; and the second driving chip 20 is connected to copper surfaces 33, 34, 35, 40, and 41.

[0042] The first drive terminal 22 is connected to the copper surface 30; the second drive terminal 23 is connected to the copper surface 31; the third drive terminal 24 is connected to the copper surface 32; the fourth drive terminal 25 is connected to the copper surface 33; the fifth drive terminal 26 is connected to the copper surface 34; and the sixth drive terminal 27 is connected to the copper surface 35.

[0043] The purpose of this invention is to provide a half-bridge intelligent power module based on a gallium nitride (GaN) power chip that can be used in actual industrial production. The module integrates the drive circuitry while packaging the power chip. This module features low parasitic parameters, high power density, and high reliability. The packaging technology of this module aims to further unleash the superior performance of wide-bandgap devices and leverage the excellent characteristics of GaN high-frequency switching.

[0044] This invention proposes a chip interconnect structure based on Fan-out packaging technology, comprising a gallium nitride power chip and a driver chip forming a smart power module with a half-bridge topology. The packaged module possesses excellent characteristics such as low parasitic parameters, good switching characteristics, and good heat dissipation. Furthermore, this invention presents a complete fabrication process for this power module.

[0045] A smart power module based on Fan-out technology includes a power circuit, a drive circuit, decoupling capacitors, lead terminals, and an insulating and heat-dissipating ceramic substrate. The power circuit consists of a half-bridge circuit formed by two gallium nitride chips and the decoupling capacitors. The half-bridge circuit is connected to the drive chip via a drive circuit. The lead terminals are used for external electrical signal connections. The ceramic substrate on both sides provides insulation and mechanical support.

[0046] The power circuit's baseplate uses a ceramic substrate for superior heat dissipation. The internal topology of the power circuit employs a gallium nitride (GaN)-based half-bridge circuit. The GaN half-bridge chip is packaged using a fan-out process, and the drain, gate, and source pads are brought out. The source of the GaN chip and the substrate are connected via electroplated copper to reduce on-state resistance jumps caused by current collapse. The GaN half-bridge and decoupling capacitors are connected to the copper surface of the top ceramic substrate, providing a commutation path for high-frequency currents. The bottom of the GaN half-bridge is connected to another ceramic substrate, serving as a heat dissipation surface.

[0047] The driver chip is distributed near the power chip to reduce parasitic inductance in the gate circuit. The pads from the gallium nitride half-bridge and the driver pads are connected via conductors on the ceramic surface. Corresponding decoupling capacitors and drive resistors are placed around the driver chip to ensure its proper operation.

[0048] Meanwhile, this invention discloses a fabrication process for a half-bridge smart power module based on a gallium nitride power chip, in order to improve the reliability of power modules fabricated based on gallium nitride power chips.

[0049] To achieve the above objectives, the processing technology requires the following materials and equipment:

[0050] We provide customized ceramic substrates with sintered conductors on both sides, commercially available driver chips and power chips required for the internal power modules, decoupling capacitors and resistors required for the peripheral circuits of the driver chips, a number of customized terminals, stencils for applying solder paste or sintering materials to designated locations on the ceramic substrate, commercially available volatile medium-strong acids and anhydrous ethanol, commercially available vacuum heating furnaces, and a complete set of equipment and packaging materials for commercially available Fan-out packaging processes.

[0051] according to Figure 4 The processing flow shown is as follows:

[0052] The first step involves connecting the gallium nitride chip and copper pillars to a temporary carrier board, covering the upper surface with an insulating layer and patterning it. After curing, the surface is polished to thin it until the copper layer on the chip surface is exposed.

[0053] The second step involves sputtering a seed adhesion layer, using photoresist as the pattern to be electroplated, and then electroplating a copper layer to complete the interconnection between the electrodes on the chip surface.

[0054] The third step involves removing the photoresist and etching the sputtered seed adhesion layer. A surface insulating layer is then applied and patterned, and after curing, it is polished and thinned until the electroplated copper layer is exposed.

[0055] The fourth step is to sputter the seed adhesion layer again, use photoresist as the pattern to be electroplated, and electroplat the copper pad terminals corresponding to the half-bridge module.

[0056] The fifth step involves removing the photoresist and etching the sputtered seed adhesion layer. A surface insulating layer is then applied and patterned. After curing, the surface is polished and thinned until the electroplated copper is exposed.

[0057] Step 6: Flip the module over and reconnect it to the temporary carrier board. Sputter a seed adhesion layer, use photoresist as the pattern to be electroplated, and electroplat the connection between the gallium nitride chip substrate and the copper pillars.

[0058] Step 7: Remove the photoresist and etch the sputtered seed adhesion layer. Cover and pattern the surface insulating layer, allow it to cure, then polish and thin it until the electroplated surface copper is exposed. Remove the half-bridge power chip after completing the fan-out package.

[0059] Step 8: Apply soldering material to the surface of the bottom ceramic substrate using a stencil. The stencil should be of appropriate thickness to ensure that the solder can complete the soldering of the terminals without applying too much.

[0060] The ninth step involves placing the driver chip, decoupling capacitor, resistor, packaged power half-bridge chip, power terminals, and driver terminals at designated positions on the bottom ceramic substrate using a pick-and-place machine.

[0061] Step 10: The ceramic substrate is placed into a customized graphite fixture. The graphite fixture has holes at designated locations for flux evaporation and chip fixation. The graphite fixture also has threads at designated locations for adjusting the height of the nuts to secure the chip and terminals, preventing chip misalignment during the soldering process.

[0062] The eleventh step involves placing the power module in a commercial vacuum welding furnace, setting the corresponding temperature profile, and performing vacuum welding.

[0063] Step 12: Use specialized ultrasonic cleaning equipment to clean residual flux from the module surface.

[0064] Step 13: Apply soldering material to the surface of the top ceramic substrate using a stencil. The stencil should be of appropriate thickness to ensure that the solder can complete the soldering of the terminals without applying too much. Place the module on the top ceramic substrate.

[0065] Step fourteen: Place it in a customized graphite fixture, and perform vacuum welding in a commercial vacuum welding furnace by setting the corresponding temperature profile.

[0066] Step 15: Use specialized ultrasonic cleaning equipment to clean residual flux from the module surface.

[0067] Step sixteen: Conduct a series of module electrical characteristic and reliability tests.

[0068] The power chips, driver chips, peripheral passive components, ceramic substrates, and printed circuit boards used in this module are all commercially available products. The structure of the module mentioned in this application is merely an example of the process and not a limitation. Figures 1-4 The internal structure of the module shown is only for the purpose of illustrating the processing technology and process of this patent design, and is not intended to limit it.

[0069] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0070] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0071] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0072] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0073] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0074] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A half-bridge intelligent power module based on gallium nitride power chips, characterized in that, The system includes a gallium nitride power chip (1), a decoupling capacitor (11), a first driver chip (29), a second driver chip (20), a power copper surface, a driving copper surface, peripheral circuits of the first driver chip, peripheral circuits of the second driver chip, and a bottom ceramic substrate (3). Several power copper surfaces and driving copper surfaces are disposed on the bottom ceramic substrate (3). The gallium nitride power chip (1) and the decoupling capacitor (11) are disposed on the power copper surface. The first driver chip (29) and the second driver chip (20) are disposed on the driving copper surface. The first driver chip (29) and the second driver chip (20) are respectively connected to the peripheral circuits of the first driver chip and the peripheral circuits of the second driver chip. The first driver chip (29) and the second driver chip (20) are used to drive the gallium nitride power chip (1). The power copper surface includes a first power copper surface (4), a second power copper surface (5), a third power copper surface (6), a fourth power copper surface (7), and a fifth power copper surface (42); the driving copper surface includes a first driving copper surface (12), a second driving copper surface (13), a third driving copper surface (14), and a fourth driving copper surface (15); the gallium nitride power chip (1) is connected to the first power copper surface (4), the second power copper surface (5), the third power copper surface (6), the fourth power copper surface (7), the first driving copper surface (12), the second driving copper surface (13), the third driving copper surface (14), and the fourth driving copper surface (15); a top ceramic substrate (2) is disposed on the gallium nitride power chip (1); a decoupling capacitor (11) is connected to the first power copper surface (4) and the second power copper surface (5); the fifth power copper surface (42) is disposed on the back side of the bottom ceramic substrate (3); The peripheral circuit of the first driver chip includes a first driver resistor (16), a second driver resistor (17), and a first driver capacitor (21); the first driver resistor (16), the second driver resistor (17), and the first driver capacitor (21) are all connected to the first driver chip (29). The driving copper surface also includes a fifth driving copper surface (30), a seventh driving copper surface (32), an eleventh driving copper surface (36), a twelfth driving copper surface (37), and a thirteenth driving copper surface (38); a first driving resistor (16) and a second driving resistor (17) are connected to the first driving copper surface (12) through the eleventh driving copper surface (36); the first driving resistor (16) and the second driving resistor (17) are connected to the first driving chip (29) through the twelfth driving copper surface (37), the thirteenth driving copper surface (38); and the first driving capacitor (21) is connected to the first driving chip (29) through the fifth driving copper surface (30), the seventh driving copper surface (32), and the first driving chip (29). The peripheral circuit of the second driver chip includes a third driver resistor (18), a fourth driver resistor (19), and a second driver capacitor (28); the third driver resistor (18), the fourth driver resistor (19), and the second driver capacitor (28) are all connected to the second driver chip (20).

2. The half-bridge intelligent power module based on gallium nitride power chip according to claim 1, characterized in that, The driving copper surface also includes a fourteenth driving copper surface (39), a fifteenth driving copper surface (40), a sixteenth driving copper surface (41), an eighth driving copper surface (33), and a tenth driving copper surface (35); a third driving resistor (18) and a fourth driving resistor (19) are connected to the third driving copper surface (14) through the fourteenth driving copper surface (39); the third driving resistor (18) and the fourth driving resistor (19) are connected to the second driving chip (20) through the fifteenth driving copper surface (40), the sixteenth driving copper surface (41), and the fifth driving chip (20); the second driving capacitor (28) is connected to the second driving chip (20) through the eighth driving copper surface (33), the tenth driving copper surface (35), and the fifth driving chip (20); the first driving chip (29) and the second driving chip (20) are both used to drive the packaged gallium nitride power chip (1).

3. The half-bridge intelligent power module based on gallium nitride power chip according to claim 2, characterized in that, The first driver chip (29) is also connected to the sixth driver copper surface (31); the second driver chip (20) is also connected to the ninth driver copper surface (34).

4. The half-bridge intelligent power module based on gallium nitride power chip according to claim 3, characterized in that, The fifth driving copper surface (30) is connected to the first driving terminal (22); the sixth driving copper surface (31) is connected to the second driving terminal (23); the seventh driving copper surface (32) is connected to the third driving terminal (24); the eighth driving copper surface (33) is connected to the fourth driving terminal (25); the ninth driving copper surface (34) is connected to the fifth driving terminal (26); and the tenth driving copper surface (35) is connected to the sixth driving terminal (27).

5. The half-bridge intelligent power module based on a gallium nitride power chip according to claim 1, characterized in that, The second power copper surface (5) is connected to the first power terminal (8), the third power copper surface (6) is connected to the second power terminal (9), and the fourth power copper surface (7) is connected to the third power terminal (10).

6. A method for fabricating a half-bridge intelligent power module based on a gallium nitride power chip, characterized in that, The half-bridge smart power module based on a gallium nitride power chip according to any one of claims 1 to 5 includes the following steps: The gallium nitride power chip and copper pillars are connected to a temporary carrier board. The upper surface is covered with an insulating layer and patterned. After curing, it is polished and thinned until the copper layer on the chip surface is exposed. Sputtering a seed adhesion layer, using photoresist as the pattern to be electroplated, electroplating a copper layer, and completing the interconnection between the electrodes on the chip surface; Remove the photoresist and etch the sputtered seed adhesion layer; cover and pattern the surface insulating layer, wait for it to cure, then polish and thin it until the electroplated surface copper layer is exposed; The seed adhesion layer is sputtered again, and photoresist is used as the pattern to be electroplated. The copper pad terminals corresponding to the half-bridge module are then electroplated. Remove the photoresist and etch the sputtered seed adhesion layer; cover and pattern the surface insulating layer, wait for it to cure, then polish and thin it until the electroplated surface copper is exposed; The module is flipped over and reconnected to a temporary carrier board; a seed adhesion layer is sputtered, and photoresist is used as the pattern to be electroplated; the connection between the gallium nitride power chip substrate and the copper pillar is electroplated. Remove the photoresist and etch the sputtered seed adhesion layer; cover and pattern the surface insulating layer, wait for it to cure, then polish and thin it until the electroplated surface copper is exposed, and remove the half-bridge power chip that has completed the Fan-out packaging. Soldering material is applied to the surface of the bottom ceramic substrate using a stencil to ensure that the solder can complete the soldering of the terminals without applying too much. The driver chip, decoupling capacitor, resistor, packaged power half-bridge chip, power terminals and driver terminals are placed in designated positions on the bottom ceramic substrate using a pick-and-place machine. The ceramic substrate is placed in a customized graphite fixture; the graphite fixture has threads, and the height of the adjustable nut is used to fix the chip and terminals. The power module is placed in a vacuum welding furnace, and the corresponding temperature profile is set for vacuum welding; residual flux on the module surface is cleaned. Apply soldering material to the surface of the top ceramic substrate using a stencil to ensure that the solder can complete the soldering of the terminals without applying too much; then place the module on the top ceramic substrate. Place it into a customized graphite fixture, set the corresponding temperature profile in a vacuum welding furnace, and perform vacuum welding; clean the residual flux on the module surface.

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