Integrated circuits of thermopile pixel array chips and driving circuit chips

Abstract

This invention provides an integrated circuit comprising a thermopile pixel array chip and a driving circuit chip, comprising: a thermopile pixel array chip including: a first thermocouple and a second thermocouple; the first thermocouple and the second thermocouple are arranged opposite each other in a horizontal direction; a driving circuit chip, wherein the driving circuit and the first thermocouple and the second thermocouple are stacked sequentially in a vertical direction, and the thermopile pixel array chip is electrically connected to the driving circuit chip. This technical solution solves the problem of how to reduce the integrated circuit size of the thermopile pixel array chip and the driving circuit chip; in addition, the design proposed in this invention is fully compatible with CMOS technology and is suitable for mass production.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and more particularly to an integrated circuit of a thermopile pixel array chip and a driving circuit chip. Background Technology

[0002] Traditional thermopile array technology achieves thermal isolation between the thermocouple and the supporting silicon through bottom silicon etching. By etching away the silicon beneath the thermocouple using dry or wet methods, the bottom of the thermocouple is suspended to achieve insulation. However, due to process limitations and ROIC constraints, the silicon substrate left by bottom silicon etching occupies a large area. This area is considered "ineffective" for a single thermopile pixel, which severely limits the miniaturization of thermopile array pixels.

[0003] On the other hand, the placement of individual thermopile pixels alongside IORCs results in a large chip area, which severely limits the miniaturization of thermopile array chips.

[0004] Therefore, developing an integrated structure and fabrication process for thermopile arrays and readout circuits that reduces chip size has become a key technical issue that needs to be addressed by those skilled in the art. Summary of the Invention

[0005] This invention provides an integrated circuit of a thermopile pixel array chip and a driving circuit chip to solve the problem of how to reduce the size of the integrated circuit of the thermopile pixel array chip and the driving circuit chip.

[0006] According to a first aspect of the present invention, an integrated circuit comprising a thermopile pixel array chip and a driving circuit chip is provided, comprising:

[0007] A thermopile pixel array chip includes: a first thermocouple and a second thermocouple; the first thermocouple and the second thermocouple are arranged opposite each other in a horizontal direction;

[0008] The driving circuit chip, wherein the driving circuit and the first thermocouple and / or the second thermocouple are stacked sequentially in a vertical direction, and the thermopile pixel array chip is electrically connected. catch On the aforementioned driving circuit chip.

[0009] Optionally, the driving circuit chip includes: a plurality of first interconnect structures formed on a first side of the driving circuit chip; the first side of the driving circuit chip represents the side of the driving circuit chip closest to the first thermocouple or the second thermocouple;

[0010] The thermopile pixel array chip further includes a plurality of second interconnect structures formed on a first side of the thermopile pixel array chip; the first side of the thermopile pixel array chip represents the side of the thermopile pixel array chip closest to the driving circuit chip;

[0011] The plurality of second interconnect structures are formed on top of the plurality of first interconnect structures, so that the thermopile pixel array chip is electrically connected to the driving circuit chip.

[0012] Optionally, the thermopile pixel array chip further includes:

[0013] A first support post is formed between the first thermocouple and the corresponding second interconnection structure, and connects the first thermocouple and the corresponding second interconnection structure, for transferring the heat of the first thermocouple through the first support post and the driving circuit chip.

[0014] The second support post is formed between the second thermocouple and the corresponding second interconnection structure, and connects the second thermocouple and the corresponding second interconnection structure, for transferring the heat of the second thermocouple to the driving circuit chip through the second support post.

[0015] Optionally, the integrated circuit of the thermopile pixel array chip and the driving circuit chip further includes:

[0016] An insulating dielectric layer is filled in the gap between the second interconnect structure and the first interconnect structure.

[0017] Optionally, the thermopile pixel array chip further includes:

[0018] A release barrier layer is formed at the top of the plurality of second interconnect structures and on the surface of the insulating dielectric layer.

[0019] Optionally, the second interconnect structure includes:

[0020] The system comprises a plurality of first metal layers, a plurality of first metal plugs, and a plurality of first metal interconnect layers; wherein the plurality of first metal layers are formed on the surface of the release barrier layer opposite to the first thermocouple or the second thermocouple; and the plurality of first metal interconnect layers are connected to corresponding first metal layers through corresponding first metal plugs.

[0021] Optionally, the integrated circuit of the thermopile pixel array chip and the driving circuit chip further includes:

[0022] The second metal layer and the third metal layer are respectively formed at both ends of the driving circuit chip away from the plurality of first interconnect structures;

[0023] Several PAD openings are formed on the top of the second metal layer and the third metal layer, respectively, and penetrate the release barrier layer and part of the insulating dielectric layer.

[0024] Optionally, the integrated circuits for the thermopile pixel array chip and the driving circuit chip also include:

[0025] A capped wafer, wherein the center of the capped wafer includes a trench that forms a capping window;

[0026] A plurality of getter structures are sequentially distributed on the surfaces of the release barrier layers on opposite sides of the first thermocouple and the second thermocouple, as well as on the sidewalls, part of the surface, and part of the bottom of the capping window; wherein the plurality of getter structures in the capping window and the plurality of getter structures on the corresponding release barrier layers are arranged opposite to each other along a first direction; the first direction characterizes the stacking direction of the second interconnect structure and the first interconnect structure;

[0027] A plurality of first closed-loop bonding rings and a plurality of second closed-loop bonding rings; the plurality of first closed-loop bonding rings are respectively formed on the surface of the release barrier layer between the first thermocouple and the second thermocouple and the adjacent PAD opening; a plurality of second closed-loop bonding rings are formed on the surface of the capping wafer outside the capping window, and the second closed-loop bonding rings are disposed opposite to the corresponding first closed-loop bonding rings.

[0028] According to a second aspect of the present invention, a method for fabricating an integrated circuit comprising a thermopile pixel array chip and a driving circuit chip is provided, for fabricating an integrated circuit comprising the thermopile pixel array chip and the driving circuit chip as described in any one of the first aspects of the present invention, comprising:

[0029] Form the driving circuit chip;

[0030] A thermopile pixel array chip structure is formed; the thermopile pixel array chip structure includes: the thermopile pixel array chip, a sacrificial layer and a first substrate; wherein, the thermopile pixel array chip includes a first thermocouple and a second thermocouple, the first thermocouple and the second thermocouple are formed on the first substrate; the sacrificial layer fills the gap between the first substrate and the thermopile pixel array chip;

[0031] The driving circuit chip is bonded to the first side of the thermopile pixel array chip;

[0032] Remove the first substrate;

[0033] Release the sacrifice layer.

[0034] Optionally, after removing the first substrate, the process further includes forming the plurality of PAD holes.

[0035] Optionally, forming the thermopile pixel array chip structure specifically includes:

[0036] Provide a first substrate;

[0037] The first thermocouple and the second thermocouple are formed on the first substrate;

[0038] A first support pillar, a second support pillar, a sacrificial layer, and a release barrier layer are formed; wherein, the sacrificial layer is formed on the surfaces of the first substrate, the first thermocouple, and the second thermocouple, and fills the gap between the first support pillar and the second support pillar; the release barrier layer is formed on the surface of the sacrificial layer; the first support pillar is formed on the surface of the first thermocouple and penetrates the release barrier layer and the sacrificial layer; the second support pillar is formed on the surface of the second thermocouple and penetrates the release barrier layer and the sacrificial layer;

[0039] The plurality of second interconnect structures and the insulating dielectric layer are formed: wherein the plurality of second interconnect structures connect the corresponding first thermocouple and the corresponding second thermocouple through the first support post or the second support post; the insulating dielectric layer is formed on the surface of the release barrier layer and fills the gaps between the plurality of first interconnect structures.

[0040] Optionally, forming the plurality of second interconnect structures and the insulating dielectric layer specifically includes:

[0041] A plurality of first metal layers are formed; the plurality of first metal layers are formed on the surface of the release barrier layer, and the first metal layers contact the corresponding first support post or the corresponding second support post;

[0042] A patterned insulating layer is formed; the patterned insulating layer covers a portion of the surface of the release barrier layer and the first metal layer, thereby exposing a portion of the surface of the first metal layer;

[0043] A first metal plug and a first metal interconnect layer are formed; the first metal plug is formed on a portion of the exposed surface of the first metal layer; the first interconnect layer is formed at the top of the first metal plug;

[0044] An insulating layer material is deposited on the surface of the patterned insulating layer and the surface of the first metal interconnect layer.

[0045] Optionally, before forming the plurality of PAD holes, the method further includes:

[0046] A patterned sacrificial layer is formed on the surface of the release barrier layer, and the surface of the release barrier layer on the side of the first thermocouple and the second thermocouple that are opposite to each other is exposed.

[0047] The plurality of getter structures, the first closed-loop bonding ring, the second closed-loop bonding ring, and the capped wafer are formed.

[0048] Remove the graphical sacrifice layer;

[0049] The first closed-loop bonding ring is bonded to the corresponding second closed-loop bonding ring to form the packaged integrated circuit of the thermopile pixel array chip and the driving circuit chip.

[0050] According to a third aspect of the present invention, a sensor is provided, comprising an integrated circuit of a thermopile pixel array chip and a driving circuit chip as described in any of the first aspects of the present invention.

[0051] According to a fourth aspect of the present invention, a method for manufacturing a sensor is provided, comprising a method for manufacturing an integrated circuit of a thermopile pixel array chip and a driving circuit chip as described in any of the second aspects of the present invention.

[0052] This invention provides an integrated circuit of a thermopile pixel array chip and a driving circuit chip. It cleverly connects the driving circuit chip electrically to the bottom of the thermopile pixel array chip, forming a vertically stacked integrated circuit structure. Compared to existing technologies, this design makes efficient use of the space occupied by the suspended silicon at the bottom of the thermopile pixel array chip, maximizing the effective area of ​​the thermopile pixel array chip and reducing its size. Furthermore, because the readout circuit chip is moved to the bottom of the thermopile pixel array chip, rather than being designed side-by-side with it, the chip size is further reduced. Therefore, the technical solution provided by this invention solves the problem of how to reduce the integrated circuit size of the thermopile pixel array chip and the driving circuit chip. In addition, the design proposed in this invention is fully compatible with CMOS processes and suitable for mass production. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of the integrated circuit structure of a thermopile pixel array chip and a driving circuit chip according to an embodiment of the present invention;

[0055] Figure 2 This is a schematic diagram of the integrated circuit packaged thermopile pixel array chip and driving circuit chip according to an embodiment of the present invention;

[0056] Figure 3 This is a schematic flowchart illustrating a method for fabricating an integrated circuit comprising a thermopile pixel array chip and a driving circuit chip according to an embodiment of the present invention.

[0057] Figure 4-7 This is a schematic diagram of the device structure of a thermopile pixel array chip fabricated according to a method for fabricating an integrated circuit of a thermopile pixel array chip and a driving circuit chip, provided in an embodiment of the present invention, showing different process stages.

[0058] Figure 8 This is a schematic diagram of the structure of a driving circuit chip provided in an embodiment of the present invention;

[0059] Figure 9-11 This is a schematic diagram of the device structure at different process stages according to an embodiment of the present invention, which is provided by a method for fabricating an integrated circuit based on a thermopile pixel array chip and a driving circuit chip.

[0060] Figure 12-13 This is a schematic diagram of the device structure at different packaging process stages according to an embodiment of the present invention, based on a method for fabricating an integrated circuit of a thermopile pixel array chip and a driving circuit chip.

[0061] Figure 14 This is a schematic diagram of the encapsulation cover structure provided in an embodiment of the present invention;

[0062] Explanation of reference numerals in the attached figures:

[0063] 101 - First substrate;

[0064] 102 - First thermocouple;

[0065] 103 - Second thermocouple;

[0066] 104 - Sacrifice Layer;

[0067] 105 - Release the blocking layer;

[0068] 106 - First Support Column;

[0069] 107 - Second support column;

[0070] 108 - First metal layer;

[0071] 109 - Graphical insulating layer;

[0072] 110 - First metal interconnect layer;

[0073] 111 - First metal plug;

[0074] 112 - Insulating dielectric layer;

[0075] 113 - Second substrate;

[0076] 114-CMOS device;

[0077] 115 - Second metal plug;

[0078] 116 - Fourth metal layer;

[0079] 117 - Second metal layer;

[0080] 118 - Third metal layer;

[0081] 119 - Third metal plug;

[0082] 120 - Second metal interconnect layer;

[0083] 121-Thermopile Pixel Array Chip;

[0084] 122 - Driver circuit chip;

[0085] 123 - Graphical sacrificial layer;

[0086] 124-getter structure;

[0087] 125 - First closed-loop bonded ring;

[0088] 126 - Capped wafer;

[0089] 127 - Second closed-loop bonding ring;

[0090] 128- Package cover structure. Detailed Implementation

[0091] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0092] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0093] The current mainstream technology for thermopile arrays achieves thermal isolation between the thermocouple and the supporting silicon through bottom silicon etching. Specifically, the silicon beneath the thermocouple is etched away using dry or wet methods, leaving the bottom of the thermocouple suspended to achieve insulation. Individual thermopile pixels are placed side-by-side with the IORC (Input / Output Circuit), meaning the IORC circuit is not located beneath individual pixels in the thermopile; the area beneath the thermopile pixels is simply silicon, resulting in a very large chip area.

[0094] As can be seen, in existing technologies, due to limitations in process and structure, the silicon substrate left by bottom silicon etching technology occupies a large area. This area is considered "ineffective" for a single thermopile pixel, severely limiting the miniaturization of thermopile array pixels. Furthermore, because the ROIC is placed side-by-side with the thermopile pixel and cannot be located under the thermopile pixel, it significantly restricts the miniaturization of the thermopile array chip.

[0095] In view of this, the inventors of this application propose that the thermopile pixel array and the readout ROIC circuit be designed and fabricated separately, and then Hybrid bonding technology is used to bond each thermopile pixel to the corresponding pixel readout circuit interface in situ, so that the thermopile pixel array and the readout ROIC circuit form a vertically stacked structure. This makes reasonable use of the space occupied by the suspended silicon at the bottom of the thermopile pixel array, maximizing the effective area of ​​the thermopile pixels and reducing their size. Simultaneously, the readout circuit is moved below the thermopile pixel array, further reducing the chip size. Specifically, the technical solution provided in this application moves the support portion, driving circuit, and interconnects all below the thermopile pixels. The heat from the thermocouple is transferred away through the support portion, the bottom driving circuit, and the interconnects, eliminating the need for a suspended silicon wafer at the bottom. Furthermore, compared to existing technologies, the readout circuit is moved below the thermopile pixel array, rather than being designed side-by-side with it, thus further reducing the chip size. In addition, the design proposed in this invention is fully compatible with CMOS technology and is suitable for mass production.

[0096] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0097] Please refer to Figures 1-14 According to an embodiment of the present invention, an integrated circuit of a thermopile pixel array chip and a driving circuit chip is provided, such as... Figure 1 As shown, the circuit includes:

[0098] The thermopile pixel array chip 121 includes: a first thermocouple 102 and a second thermocouple 103; the first thermocouple 102 and the second thermocouple 103 are arranged opposite each other in a horizontal direction;

[0099] The driving circuit chip 122 is stacked vertically with the first thermocouple 102 and / or the second thermocouple 103, and the thermopile pixel array chip 121 is electrically connected to the driving circuit chip 122.

[0100] In one embodiment, the number of the first thermocouples is several; the number of the first thermocouples is not limited, and any implementation of the number of the first thermocouples that can achieve the purpose of the present invention is within the protection scope of the present invention, and the present invention is not limited thereto.

[0101] In one embodiment, the number of the second thermocouples is several; the number of the second thermocouples is not limited, and any implementation of the number of the second thermocouples that can achieve the purpose of the present invention is within the protection scope of the present invention, and the present invention is not limited thereto.

[0102] The accompanying drawings of this application only schematically show the basic units in the thermocouple array chip and the driving circuit chip. In fact, the thermocouple array chip or the driving circuit chip is composed of several basic units shown in the drawings.

[0103] Wherein, the horizontal direction refers to the horizontal direction of the paper surface, and the vertical direction is perpendicular to the horizontal direction on the paper surface; the driving circuit and the first thermocouple 102 and / or the second thermocouple 103 are stacked in the vertical direction in sequence, which means that the driving circuit is formed at the bottom of the first thermocouple 102 and / or the second thermocouple 103.

[0104] This invention provides an integrated circuit of a thermopile pixel array chip and a driving circuit chip. The driving circuit chip is cleverly electrically connected to the bottom of the thermopile pixel array chip, forming a vertically stacked integrated circuit structure. Compared to existing technologies, this eliminates the need for a suspended wafer at the bottom of the thermopile pixel array chip. It effectively utilizes the space occupied by the suspended silicon at the bottom of the thermopile pixel array chip, maximizing the effective area of ​​the thermopile pixel array chip and reducing its size. Furthermore, because the readout circuit chip is moved to the bottom of the thermopile pixel array chip, rather than being designed side-by-side with it, the chip size is further reduced. Therefore, the technical solution provided by this invention solves the problem of how to reduce the integrated circuit size of the thermopile pixel array chip and the driving circuit chip. In addition, the design proposed in this invention is fully compatible with CMOS processes and is suitable for mass production.

[0105] In one embodiment, the driving circuit chip 122 includes: a plurality of first interconnect structures formed on a first side of the driving circuit chip 122; the first side of the driving circuit chip 122 represents the side of the driving circuit chip 122 that is close to the first thermocouple 102 or the second thermocouple 103.

[0106] The thermopile pixel array chip 121 further includes a plurality of second interconnect structures, which are formed on a first side of the thermopile pixel array chip 121; the first side of the thermopile pixel array chip 121 represents the side of the thermopile pixel array chip 121 that is close to the driving circuit chip 122.

[0107] The plurality of second interconnect structures are formed on top of the plurality of first interconnect structures, so that the thermopile pixel array chip 121 is electrically connected to the driving circuit chip 122.

[0108] In one embodiment, the thermopile pixel array chip 121 further includes:

[0109] The first support post 106 is formed between the first thermocouple 102 and the corresponding second interconnection structure, and connects the first thermocouple 102 and the corresponding second interconnection structure, for transferring the heat of the first thermocouple 102 through the first support post 106 and the driving circuit chip 122.

[0110] The second support post 107 is formed between the second thermocouple 103 and the corresponding second interconnection structure, and connects the second thermocouple 103 and the corresponding second interconnection structure, for transferring the heat of the second thermocouple 103 to the driving circuit chip 122 through the second support post 107.

[0111] In the technical solution provided by the present invention, compared with the prior art, the heat transfer path of the first thermocouple 102 and the second thermocouple 103 is changed. Specifically, the heat of the first thermocouple 102 and the second thermocouple 103 arranged in the horizontal direction is transferred out through the first support column 106 or the second support column 107, the second interconnection structure and the first interconnection structure. Compared with the prior art, there is no need to design a silicon wafer with the bottom suspended, which maximizes the effective area of ​​the thermopile pixel chip and thus reduces the size of the thermopile pixel chip.

[0112] In one embodiment, the integrated circuit of the thermopile pixel array chip and the driving circuit chip further includes:

[0113] An insulating dielectric layer 112 is filled in the gap between the second interconnect structure and the first interconnect structure.

[0114] In one embodiment, the thermopile pixel array chip 121 further includes:

[0115] Release barrier layer 105 is formed at the top of the plurality of second interconnect structures and on the surface of the insulating dielectric layer 112.

[0116] In one embodiment, the second interconnect structure includes:

[0117] A plurality of first metal layers 108, a plurality of first metal plugs 111, and a plurality of first metal interconnect layers 110; wherein, the plurality of first metal layers 108 are formed on the surface of the release barrier layer 105 opposite to the first thermocouple 102 or the second thermocouple 103; the plurality of first metal interconnect layers 110 are connected to the corresponding first metal layers 108 through the corresponding first metal plugs 111.

[0118] In one embodiment, the integrated circuit of the thermopile pixel array chip and the driving circuit chip further includes:

[0119] The second metal layer 117 and the third metal layer 118 are respectively formed at both ends of the driving circuit chip 122 that are away from the plurality of first interconnect structures;

[0120] A number of PAD openings are formed on the top of the second metal layer 117 and the third metal layer 118, respectively, and penetrate the release barrier layer 105 and part of the insulating dielectric layer 112.

[0121] The following is a brief description of the other components of the driver circuit chip 122. It should be noted that this part of the structure belongs to the prior art, and this invention will not describe it in detail.

[0122] The driving circuit chip 122 further includes: a plurality of CMOS devices 114, a fourth metal layer 116, a second metal interconnect layer 120, a second metal plug 115, a third metal plug 119, and a second substrate 113; the plurality of CMOS devices 114 are formed on the second substrate 113 and arranged in a horizontal direction; the plurality of fourth metal layers 116 and the plurality of second metal interconnect layers 120 in the central portion of the driving circuit chip 122 are sequentially stacked on the corresponding CMOS devices 114 in a direction away from the second substrate 113; wherein, the fourth metal layer 116 is connected to the corresponding CMOS device 114 through the third metal plug 119, and the second metal interconnect layer 120 is connected to the fourth metal layer 116 through the fourth metal plug, and the second metal interconnect layer 120 is used to connect the driving circuit chip 122 and the second interconnect structure. The plurality of fourth metal layers 116 in the edge portion of the driving circuit chip 122 are stacked at intervals on the top of the corresponding CMOS devices 114 through an insulating dielectric layer 112. The second metal interconnect layer 120 and the third metal interconnect layer are respectively formed on one side of the fourth metal layer 116 in the remote edge portion and the fourth metal layer 116 in the center portion of the insulating dielectric layer 112.

[0123] In one embodiment, the integrated circuit of the thermopile pixel array chip 121 and the driving circuit chip 122 further includes: a package cover structure 128, such as... Figure 2 As shown, it specifically includes:

[0124] A capping wafer 126 is provided, wherein the center of the capping wafer 126 includes a trench that forms a capping window;

[0125] A plurality of getter structures 124 are sequentially distributed on the surfaces of the release barrier layer 105 on opposite sides of the first thermocouple 102 and the second thermocouple 103, as well as on the sidewalls, part of the surface, and part of the bottom of the capping window; wherein the plurality of getter structures 124 in the capping window and the plurality of getter structures 124 on the corresponding release barrier layer 105 are arranged opposite to each other along a first direction; the first direction characterizes the stacking direction of the second interconnection structure and the first interconnection structure.

[0126] A plurality of first closed-loop bonding rings 125 and a plurality of second closed-loop bonding rings; the plurality of first closed-loop bonding rings 125 are respectively formed on the surface of the release barrier layer 105 between the first thermocouple 102 and the second thermocouple 103 and the adjacent PAD opening; a plurality of second closed-loop bonding rings 127 are formed on the surface of the capping wafer 126 outside the capping window, and the second closed-loop bonding rings 127 are disposed opposite to the corresponding first closed-loop bonding rings 125.

[0127] Secondly, according to an embodiment of the present invention, a method for fabricating an integrated circuit of a thermopile pixel array chip 121 and a driving circuit chip 122 is also provided, for fabricating an integrated circuit of the thermopile pixel array chip 121 and the driving circuit chip 122 as described in any of the foregoing embodiments of the present invention. A schematic flowchart of the fabrication method is shown below. Figure 3 As shown, it includes:

[0128] S11: Form the driving circuit chip 122, such as Figure 8 As shown;

[0129] S12: Forming a thermopile pixel array chip 121 structure; the thermopile pixel array chip 121 structure includes: the thermopile pixel array chip 121, a sacrificial layer 104, and a first substrate 101; wherein, the thermopile pixel array chip 121 includes a first thermocouple 102 and a second thermocouple 103, the first thermocouple 102 and the second thermocouple 103 being formed on the first substrate 101; the sacrificial layer 104 fills the gap between the first substrate 101 and the thermopile pixel array chip 121, such as... Figure 7 As shown;

[0130] S13: Bond the driving circuit chip 122 to the first side of the thermopile pixel array chip 121, such as... Figure 9 As shown;

[0131] S14: Remove the first substrate 101, such as Figure 10 As shown;

[0132] S15: Release the sacrificial layer 104. Thermal insulation between the pixel array chip and the driving circuit chip 122 is achieved by introducing the sacrificial layer 104, as shown below. Figure 1 As shown.

[0133] In one embodiment, step S12, forming the thermopile pixel array chip 121 structure specifically includes: steps S121-S124:

[0134] S121: Provide a first substrate 101;

[0135] S122: The first thermocouple 102 and the second thermocouple 103 are formed on the first substrate 101, such as Figure 4 As shown;

[0136] S123: Form the first support pillar 106, the second support pillar 107, the sacrificial layer 104, and the release barrier layer 105; wherein, the sacrificial layer 104 is formed on the surfaces of the first substrate 101, the first thermocouple 102, and the second thermocouple 103, and fills the gap between the first support pillar 106 and the second support pillar 107; the release barrier layer 105 is formed on the surface of the sacrificial layer 104; the first support pillar 106 is formed on the surface of the first thermocouple 102 and penetrates the release barrier layer 105 and the sacrificial layer 104; the second support pillar 107 is formed on the surface of the second thermocouple 103 and penetrates the release barrier layer 105 and the sacrificial layer 104;

[0137] S124: Forming the plurality of second interconnect structures and the insulating dielectric layer 112: wherein the plurality of second interconnect structures are connected to the corresponding first thermocouple 102 and the corresponding second thermocouple 103 through the first support post 106 or the second support post 107; the insulating dielectric layer 112 is formed on the surface of the release barrier layer 105 and fills the gaps between the plurality of first interconnect structures.

[0138] In one embodiment, step S124, forming the plurality of second interconnect structures and the insulating dielectric layer 112, specifically includes: steps S1241-S1244:

[0139] S1241: Forming a plurality of first metal layers 108; the plurality of first metal layers 108 are formed on the surface of the release barrier layer 105, and the first metal layers 108 contact the corresponding first support post 106 or the corresponding second support post 107, such as Figure 5 As shown;

[0140] S1242: Forming a patterned insulating layer 109; the patterned insulating layer 109 covers a portion of the surface of the release barrier layer 105 and the first metal layer 108, thereby exposing a portion of the surface of the first metal layer 108, such as... Figure 6 As shown;

[0141] S1243: Forming a first metal plug 111 and a first metal interconnect layer 110; the first metal plug 111 is formed on a portion of the exposed surface of the first metal layer 108; the first interconnect layer is formed at the top of the first metal plug 111;

[0142] S1244: Deposit insulating layer material on the surface of the patterned insulating layer 109 and the surface of the first metal interconnect layer 110, such as... Figure 7 As shown.

[0143] The insulating dielectric layer 112 includes the patterned insulating layer 109 formed in the thermopile pixel array chip 121 and the subsequently deposited insulating layer material, and also includes the insulating layer in the drive circuit chip 122.

[0144] In one embodiment, step S14, after removing the first substrate 101, further includes: forming the plurality of PAD holes, such as... Figure 11 As shown. Forming the plurality of PAD holes is one optional implementation method;

[0145] In other embodiments, the TSV process is used to bring out the PAD, which eliminates the need to drill a PAD hole.

[0146] In one embodiment, the method further includes forming the plurality of PAD holes before:

[0147] A patterned sacrificial layer 123104 is formed; the patterned sacrificial layer 123104 is formed on the surface of the release barrier layer 105 and exposes the surface of the release barrier layer 105 on the side where the first thermocouple 102 and the second thermocouple 103 are opposite to each other, such as... Figure 12 As shown;

[0148] The plurality of getter structures 124, the first closed-loop bonding ring 125, the second closed-loop bonding ring 127, and the capped wafer 126 are formed, as follows: Figure 14 As shown;

[0149] Remove the graphical sacrifice layer 123104, such as Figure 13 As shown;

[0150] The first closed-loop bonding ring 125 is bonded to the corresponding second closed-loop bonding ring 127 to form the packaged integrated circuit of the thermopile pixel array chip and the driving circuit chip.

[0151] When the interconnect pads are formed in the form of TSV, the first closed-loop bonding ring 125 is bonded to the corresponding second closed-loop bonding ring 127 to form the packaged integrated circuit of the thermopile pixel array chip and the driving circuit chip. Then, the interconnect pads are formed by TSV. This part belongs to the prior art and will not be described in detail here.

[0152] In addition, according to one embodiment of the present invention, a sensor is also provided, comprising an integrated circuit of a thermopile pixel array chip 121 and a driving circuit chip 122 as described in any one embodiment of the present invention.

[0153] According to one embodiment of the present invention, a method for manufacturing a sensor is also provided, including a method for manufacturing an integrated circuit of a thermopile pixel array chip and a driving circuit chip as described in any of the foregoing embodiments of the present invention.

[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating an integrated circuit comprising a thermopile pixel array chip and a driving circuit chip, characterized in that, include: A driving circuit chip is formed, the driving circuit chip including a plurality of first interconnect structures; The formation of a thermopile pixel array chip structure specifically includes: providing a first substrate; forming a first thermocouple and a second thermocouple on the first substrate, forming a first support pillar on the surface of the first thermocouple, forming a second support pillar on the surface of the second thermocouple, forming a sacrificial layer on the first substrate, the first thermocouple, and the surface of the second thermocouple, with the first support pillar and the second support pillar penetrating the sacrificial layer; forming a plurality of second interconnect structures on the first support pillar and the second support pillar, with the first support pillar and the second support pillar connected to the second interconnect structures; The plurality of first interconnects of the driving circuit chip are bonded to the plurality of second interconnect structures of the thermopile pixel array chip structure; Remove the first substrate; Then release the sacrifice layer.

2. The method for fabricating the integrated circuit of the thermopile pixel array chip and the driving circuit chip according to claim 1, characterized in that, After removing the first substrate, the process further includes forming a plurality of PAD holes.

3. The method for fabricating the integrated circuit of the thermopile pixel array chip and the driving circuit chip according to claim 2, characterized in that, A release barrier layer is formed on the sacrificial layer, and the first support post and the second support post penetrate the release barrier layer; An insulating dielectric layer is formed on the surface of the release barrier layer and fills the gaps between a plurality of second interconnect structures.

4. The method for fabricating the integrated circuit of the thermopile pixel array chip and the driving circuit chip according to claim 3, characterized in that, The formation of the plurality of second interconnect structures and the insulating dielectric layer specifically includes: A plurality of first metal layers are formed; the plurality of first metal layers are formed on the surface of the release barrier layer, and the first metal layers contact the corresponding first support post or the corresponding second support post; a patterned insulating layer is formed; the patterned insulating layer covers a portion of the surface of the release barrier layer and the first metal layers to expose a portion of the surface of the first metal layers; a first metal plug and a first metal interconnect layer are formed; the first metal plug is formed on the exposed portion of the first metal layer; the first metal interconnect layer is formed at the top of the first metal plug; an insulating layer material is deposited on the surface of the patterned insulating layer and the surface of the first metal interconnect layer.

5. The method for fabricating the integrated circuit of the thermopile pixel array chip and the driving circuit chip according to claim 4, characterized in that, Before forming the plurality of PAD holes, the method further includes: The sacrificial layer is patterned; the patterned sacrificial layer is formed on the surface of the release barrier layer and exposes the surface of the release barrier layer on the side of the first thermocouple and the second thermocouple that are opposite to each other; A first closed-loop bonding ring is formed on the surface of the release barrier layer; Remove the graphical sacrifice layer; A second closed-loop bonding ring and several getter structures located within the second closed-loop bonding ring are formed on the capped wafer; The first closed-loop bonding ring is bonded to the corresponding second closed-loop bonding ring to form the packaged integrated circuit of the thermopile pixel array chip and the driving circuit chip.

6. An integrated circuit comprising a thermopile pixel array chip and a driving circuit chip fabricated using the fabrication method described in any one of claims 1-5, characterized in that, include: A thermopile pixel array chip includes: a first thermocouple and a second thermocouple; the first thermocouple and the second thermocouple are arranged opposite each other in a horizontal direction; A driving circuit chip, wherein the driving circuit and the first thermocouple and / or the second thermocouple are stacked sequentially in a vertical direction, and the thermopile pixel array chip is electrically connected to the driving circuit chip.

7. The integrated circuit of the thermopile pixel array chip and the driving circuit chip according to claim 6, characterized in that, The driving circuit chip includes: a plurality of first interconnect structures, the plurality of first interconnect structures being formed on a first side of the driving circuit chip; the first side of the driving circuit chip represents the side of the driving circuit chip that is close to the first thermocouple or the second thermocouple; The thermopile pixel array chip further includes a plurality of second interconnect structures, which are formed on a first side of the thermopile pixel array chip; the first side of the thermopile pixel array chip represents the side of the thermopile pixel array chip that is closer to the driving circuit chip. The plurality of second interconnect structures are formed on top of the plurality of first interconnect structures, so that the thermopile pixel array chip is electrically connected to the driving circuit chip.

8. The integrated circuit of the thermopile pixel array chip and the driving circuit chip according to claim 7, characterized in that, The thermopile pixel array chip also includes: A first support post is formed between the first thermocouple and the corresponding second interconnection structure, and connects the first thermocouple and the corresponding second interconnection structure, for transferring the heat of the first thermocouple through the first support post and the driving circuit chip. The second support post is formed between the second thermocouple and the corresponding second interconnection structure, and connects the second thermocouple and the corresponding second interconnection structure, for transferring the heat of the second thermocouple to the driving circuit chip through the second support post.

9. The integrated circuit of the thermopile pixel array chip and the driving circuit chip according to claim 8, characterized in that, The integrated circuit of the thermopile pixel array chip and the driving circuit chip also includes: An insulating dielectric layer is filled in the gap between the second interconnect structure and the first interconnect structure.

10. The integrated circuit of the thermopile pixel array chip and the driving circuit chip according to claim 9, characterized in that, The thermopile pixel array chip also includes: A release barrier layer is formed at the top of the plurality of second interconnect structures and on the surface of the insulating dielectric layer.

11. The integrated circuit of the thermopile pixel array chip and the driving circuit chip according to claim 10, characterized in that, The second interconnect structure includes: A plurality of first metal layers, a plurality of first metal plugs, and a plurality of first metal interconnect layers; wherein the plurality of first metal layers are formed on the surface of the release barrier layer opposite to the first thermocouple or the second thermocouple; the plurality of first metal interconnect layers are connected to corresponding first metal layers through corresponding first metal plugs.

12. The integrated circuit of the thermopile pixel array chip and the driving circuit chip according to claim 11, characterized in that, The integrated circuit of the thermopile pixel array chip and the driving circuit chip also includes: The second metal layer and the third metal layer are respectively formed at both ends of the driving circuit chip away from the plurality of first interconnect structures; Several PAD openings are formed on the top of the second metal layer and the third metal layer, respectively, and penetrate the release barrier layer and part of the insulating dielectric layer.

13. The integrated circuit of the thermopile pixel array chip and the driving circuit chip according to claim 12, characterized in that, The integrated circuits for the thermopile pixel array chip and the driving circuit chip also include: A capped wafer, wherein the center of the capped wafer includes a trench that forms a capping window; A plurality of getter structures are sequentially distributed on the surfaces of the release barrier layers on opposite sides of the first thermocouple and the second thermocouple, as well as on the sidewalls, part of the surface, and part of the bottom of the capping window; wherein the plurality of getter structures in the capping window and the plurality of getter structures on the corresponding release barrier layers are arranged opposite to each other along a first direction; the first direction characterizes the stacking direction of the second interconnect structure and the first interconnect structure; A plurality of first closed-loop bonding rings and a plurality of second closed-loop bonding rings; the plurality of first closed-loop bonding rings are respectively formed on the surface of the release barrier layer between the first thermocouple and the second thermocouple and the adjacent PAD opening; the plurality of second closed-loop bonding rings are formed on the surface of the capping wafer outside the capping window, and the second closed-loop bonding rings are disposed opposite to the corresponding first closed-loop bonding rings.

14. A sensor, characterized in that, The integrated circuit includes the thermopile pixel array chip and driving circuit chip as described in any one of claims 6-13.

15. A method for manufacturing a sensor, characterized in that, A method for fabricating an integrated circuit including the thermopile pixel array chip and the driving circuit chip as described in any one of claims 1-5.

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