Radio frequency switch circuit and method of formation

Abstract

The application provides a radio frequency switch circuit and a forming method, which comprise: M MOS tube gate structures, bias of the first stage to the Mth stage MOS tube gate structure from a signal input end decreases in turn, and all the MOS tube gate structures are divided into first type to Nth type MOS tube gate structures according to the different bias; a first oxide layer is located on all the MOS tube gate structures; a first metal layer is located on the first oxide layer, the first metal layer comprises a plurality of spaced metal wires, and a groove is formed in the first oxide layer between the two adjacent metal wires; a dielectric layer covers the first metal layer, the first oxide layer and fills the groove, and the dielectric layer forms an air gap between the adjacent metal wires; and the second to Nth metal layers, the first to Nth metal layers are arranged on the first type MOS tube gate structure, the first to N-1 metal layers are arranged on the second type MOS tube, and the first metal layer and the second metal layer are arranged on the N-1th type MOS tube.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a radio frequency switch circuit and its fabrication method. Background Technology

[0002] In radio frequency (RF) front-end circuits, RF switches are essential components. RF switches are used to electrically connect antennas to the transmit or receive paths of an RF system, allowing multiple components to be connected to the antenna. Typically, RF switches are configured using a stack of multiple transistors (such as field-effect transistors (FETs)). When an RF switch is in the OFF state, it can be considered as acting as a shunt "high" impedance about ground. Such an OFF stacked RF switch generally presents both capacitance and impedance. With the development of mobile communication technology, multiple communication standards coexist. Therefore, it is necessary to integrate RF power amplifiers of multiple modes and different frequency bands, and to select the required RF power amplifier through RF switch circuits to establish RF signal reception and transmission channels, enabling switching between different communication networks.

[0003] However, when the RF switch is off, it was found that the bias voltage (Vds) of some MOSFETs located at the front of the stack is higher. For example, the bias voltage (Vds) of the first two, three, or even more MOSFETs in the front row is significantly higher than that of the remaining MOSFETs in the back row. In some cases, the bias voltage decreases sequentially from the front row to the back row, resulting in uneven bias voltage across all MOSFETs. Consequently, when the voltage is increased in the RF switch circuit, it is possible for several MOSFETs in the front row to break down. Summary of the Invention

[0004] The purpose of this invention is to provide a radio frequency switch circuit and its formation method, which makes the bias voltage of all MOSFETs uniform and reduces the probability of MOSFET breakdown.

[0005] To achieve the above objectives, the present invention provides a radio frequency switching circuit, comprising:

[0006] There are M MOS gate structures, starting from the signal input terminal, which are sequentially classified as the first-stage MOS gate structure to the Mth-stage MOS gate structure. The bias voltage of the first-stage MOS gate structure to the Mth-stage MOS gate structure decreases sequentially. All the MOS gate structures are classified into the first type MOS gate structure to the Nth type MOS gate structure according to their different bias voltages. The bias voltage of the first type MOS gate structure to the Nth type MOS gate structure decreases sequentially.

[0007] The first oxide layer is located on all of the MOS gate structures;

[0008] A first metal layer is located on the first oxide layer. The first metal layer includes a plurality of spaced metal lines, with the first oxide layer exposed between the metal lines. Each MOS gate structure corresponds to two metal lines, and the source and drain are each connected to a metal line. In all the MOS gate structures, there is a groove in the first oxide layer between two adjacent metal lines.

[0009] A dielectric layer covering all the first metal layers, the first oxide layer, and the filling grooves, wherein air gaps are formed between adjacent metal lines in the dielectric layer;

[0010] The second to Nth metal layers are sequentially formed on the first metal layer, and the second to Nth metal layers are interconnected by contact holes and connected to the first metal layer. The second to Nth metal layers are separated by dielectric layers. The first type of MOS gate structure has the first to Nth metal layers, the second type of MOS gate structure has the first to N-1th metal layers, and the N-1th type of MOS gate structure has the first metal layer and the second metal layer. M and N are both integers greater than 1.

[0011] Optionally, the radio frequency switching circuit further includes a semiconductor substrate, wherein the plurality of MOS gate structures are partially formed on the surface of the semiconductor substrate and partially formed inside the semiconductor substrate.

[0012] Optionally, in the aforementioned radio frequency switching circuit, the semiconductor substrate includes:

[0013] Substrate;

[0014] A parasitic capacitance wiring layer is located on the surface of the substrate;

[0015] The second oxide layer is located on the surface of the parasitic capacitance wiring layer. The plurality of MOS gate structures are partially formed on the surface of the second oxide layer and partially formed inside the second oxide layer.

[0016] Optionally, in the radio frequency switch circuit, the second metal layer to the Nth metal layer are all formed by spaced metal lines, and the metal lines of the first metal layer and the metal lines of the second metal layer to the Nth metal layer are all connected through contact holes.

[0017] Optionally, in the aforementioned RF switching circuit, each type of MOS gate structure includes at least one MOS gate structure.

[0018] Optionally, in the aforementioned RF switch circuit, those with the same bias voltage or bias voltage within a certain range are of the same type of MOS gate structure.

[0019] This invention provides a method for forming a radio frequency switch circuit, comprising:

[0020] M MOS gate structures are formed, starting from the signal input terminal and sequentially from the first-stage MOS gate structure to the Mth-stage MOS gate structure. The bias voltage of the first-stage MOS gate structure to the Mth-stage MOS gate structure decreases sequentially. All the MOS gate structures are divided into first-type MOS gate structures to Nth-type MOS gate structures according to their different bias voltages. The bias voltage of the first-type MOS gate structure to the Nth-type MOS gate structure decreases sequentially.

[0021] A first oxide layer is formed on all of the MOS gate structures;

[0022] A first metal layer is formed on the first oxide layer. The first metal layer includes a plurality of spaced metal lines, with the first oxide layer exposed between the metal lines. Each MOS gate structure corresponds to two metal lines, and the source and drain are each connected to a metal line. In all MOS gate structures, the first oxide layer between two adjacent metal lines has a groove.

[0023] A dielectric layer is formed, which covers all the first metal layer, the first oxide layer and the filling groove, and air gaps are formed between adjacent metal lines in the dielectric layer;

[0024] A second to an Nth metal layer are sequentially formed on a first metal layer, and the second to Nth metal layers are interconnected by contact holes and connected to the first metal layer. The second to Nth metal layers are separated by dielectric layers. The first type of MOS gate structure has a first to an Nth metal layer, the second type of MOS gate structure has a first to an (N-1)th metal layer, and the (N-1)th type of MOS gate structure has a first metal layer and a second metal layer. M and N are both integers greater than 1.

[0025] Optionally, the method for forming the radio frequency switch circuit further includes providing a semiconductor substrate, the semiconductor substrate comprising:

[0026] Substrate;

[0027] A parasitic capacitance wiring layer is located on the surface of the substrate;

[0028] The second oxide layer is located on the surface of the parasitic capacitance wiring layer. All the MOS gate structures are partially formed on the surface of the second oxide layer and partially formed inside the second oxide layer.

[0029] Optionally, in the method of forming the radio frequency switch circuit, forming a first metal layer on the first oxide layer, wherein the first metal layer includes a plurality of spaced metal lines, includes: forming a metal layer on the first oxide layer and etching the metal layer to form a plurality of metal lines.

[0030] Optionally, in the method for forming the radio frequency switch circuit, the method for forming the second metal layer includes:

[0031] A contact hole is formed within the dielectric layer of the first type of MOS gate structure, and one contact hole is formed on each of the first metal layers;

[0032] A second metal layer is formed on the dielectric layer, and the second metal layer is in contact with the contact hole.

[0033] In the radio frequency switch circuit and forming method provided by the present invention, the formed second metal layer to the Nth metal layer can increase the parasitic capacitance of the first type MOS gate structure to the Nth type MOS gate structure. The more metal layers there are, the more parasitic capacitance is increased. As a result, the capacitance of the first type MOS gate structure to the Nth type MOS gate structure gradually decreases, thereby reducing the capacitance of the first type MOS gate structure to the Nth type MOS gate structure. This makes the voltage of all MOS transistors more even and reduces the risk of breakdown of the first few types of MOS transistors. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of the radio frequency switch circuit according to an embodiment of the present invention;

[0035] Figure 2 This is a circuit diagram of the radio frequency switch circuit according to an embodiment of the present invention;

[0036] Figure 3 This is a flowchart of a method for forming a radio frequency switch circuit according to an embodiment of the present invention;

[0037] Figures 4 to 8 This is a schematic diagram of forming a radio frequency switch circuit according to an embodiment of the present invention;

[0038] In the figure: 110-substrate, 120-parasitic capacitance wiring layer, 130-second oxide layer, 140-MOS gate structure, 141-source, 142-drain, 143-third oxide layer, 144-gate, 145-sidewall, 146-ONO layer, 150-first oxide layer, 160-contact hole, 171-metal layer, 170-metal line, 180-dielectric layer, 190-air gap, 200-second metal layer, 210-third metal layer. Detailed Implementation

[0039] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0040] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0041] Please refer to Figure 1This invention provides a radio frequency switching circuit, comprising: M MOS gate structures, arranged sequentially from the signal input terminal to the Mth stage MOS gate structure, wherein the bias voltage of the first stage MOS gate structure to the Mth stage MOS gate structure decreases sequentially; all the MOS gate structures are classified into first type MOS gate structure to Nth type MOS gate structure according to different bias voltages, wherein the bias voltage of the first type MOS gate structure to the Nth type MOS gate structure decreases sequentially; a first oxide layer located on all the MOS gate structures; a first metal layer located on the first oxide layer, the first metal layer comprising multiple spaced metal lines, the first oxide layer being exposed between the metal lines; each MOS gate structure corresponding to two metal lines, the source and drain being respectively connected to a... Each of the M MOS gate structures has interconnected metal lines, and each adjacent metal line has a groove in the first oxide layer. A dielectric layer covers all the first metal layers, the first oxide layer, and fills the grooves. Air gaps are formed between adjacent metal lines in the dielectric layer. Second to Nth metal layers are sequentially formed on the first metal layer, and each of these layers is interconnected and connected to the first metal layer via contact holes. Each of these layers is separated by a dielectric layer. The first type of MOS gate structure has first to Nth metal layers, the second type of MOS gate structure has first to N-1th metal layers, and the N-1th type of MOS gate structure has a first metal layer and a second metal layer. M and N are both integers greater than 1. The RF switching circuit also includes a semiconductor substrate, where each of the M MOS gate structures 140 is partially formed on the surface of the semiconductor substrate and partially formed inside the semiconductor substrate. The semiconductor substrate includes: a substrate 110; a parasitic capacitance wiring layer 120 located on the surface of the substrate 110; a second oxide layer 130 located on the surface of the parasitic capacitance wiring layer 120; and M MOS gate structures 140, each partially formed on the surface of the second oxide layer 130 and partially formed inside the second oxide layer 130. The source and drain are each connected to a metal line through a contact hole 160.

[0042] For example, Figure 1 If the MOSFET gate structures are divided into two types, the first type consists of a first-stage MOSFET gate structure and a second-stage MOSFET gate structure, where the bias voltages of the first-stage and second-stage MOSFET gate structures are the same or within a certain range (this range can be set, meaning the bias voltages of the first-stage and second-stage MOSFET gate structures are not significantly different), and the remaining structures are the second type of MOSFET gate structures, then a second metal layer 200 is formed on the dielectric layer 180 of the first type of MOSFET gate structure. The second metal layer 200 is connected to the first metal layer 170 of the first type of MOSFET gate structure through a contact hole 160.

[0043] Please refer to Figure 2 The present invention provides a method for forming a radio frequency switch circuit, comprising:

[0044] S11: Form M MOS gate structures, starting from the signal input terminal, sequentially from the first-stage MOS gate structure to the Mth-stage MOS gate structure. The bias voltage of the first-stage MOS gate structure to the Mth-stage MOS gate structure decreases sequentially. All the MOS gate structures are divided into first-type MOS gate structures to Nth-type MOS gate structures according to different bias voltages. The bias voltage of the first-type MOS gate structure to the Nth-type MOS gate structure decreases sequentially.

[0045] S12: Form a first oxide layer located on all the MOS gate structures;

[0046] S13: Form a first metal layer on the first oxide layer. The first metal layer includes a plurality of spaced metal lines. The first oxide layer is exposed between the metal lines. Each MOS gate structure corresponds to two metal lines. The source and drain are connected to a metal line respectively. In all MOS gate structures, the first oxide layer between two adjacent metal lines has a groove.

[0047] S14: Form a dielectric layer that covers all the first metal layers, the first oxide layers, and the filling grooves, wherein air gaps are formed between adjacent metal lines in the dielectric layer;

[0048] S15: The second to Nth metal layers are formed sequentially on the first metal layer, and the second to Nth metal layers are interconnected by contact holes and connected to the first metal layer. The second to Nth metal layers are separated by dielectric layers. The first type of MOS gate structure has the first to Nth metal layers, the second type of MOS gate structure has the first to N-1th metal layers, and the N-1th type of MOS gate structure has the first metal layer and the second metal layer. M and N are both integers greater than 1.

[0049] For details on how to construct an RF switch circuit, please refer to [link / reference]. Figure 3 First, a semiconductor substrate is provided, comprising: a substrate 110; a parasitic capacitance wiring layer 120 located on the surface of the substrate 110; and a second oxide layer 130 located on the surface of the parasitic capacitance wiring layer 120. The semiconductor substrate can be formed by: providing a substrate 110, which may be a wafer; forming the parasitic capacitance wiring layer 120 on the surface of the substrate 110; and forming a second oxide layer 130 on the surface of the parasitic capacitance wiring layer 120, which may be formed by depositing a layer of silicon dioxide.

[0050] Next, please continue to refer to Figure 3 and Figure 4 Within the second oxide layer 130, a well region is formed by implanting ions. Within the well region, source and drain regions are formed by implanting ions, thereby forming source 141 and drain 142. A third oxide layer 143 is formed on the surface of the second oxide layer, along with a gate 144 located on the third oxide layer 143, sidewalls 145 located on both sides of the gate 144, and an ONO layer 146 located on the gate 144 and sidewalls 145, completing the fabrication of the MOS gate structure. The specific formation method is prior art and will not be elaborated here.

[0051] Next, please continue to refer to Figure 3 A first oxide layer 150 is formed on the ONO layer, which can be formed by depositing silicon dioxide. Next, the first oxide layer 150 and the ONO layer are etched starting from the surface of the first oxide layer 150, forming vias on both the source and drain terminals. Each MOSFET has vias formed on both the source and drain terminals, with the radial direction of the vias perpendicular to the surface of the first oxide layer. Then, metal is filled into the vias to form contact holes 160.

[0052] Next, please continue to refer to Figure 3 and Figure 5 A metal layer 171 is formed on the first oxide layer 150, and the contact hole 160 contacts and communicates with the metal layer 171. The metal layer 171 is etched to form a plurality of metal lines 170, such that each contact hole 160 corresponds to a metal line 170, and different contact holes 160 correspond to different metal lines 170.

[0053] Next, please refer to Figure 6 The first oxide layer 150 between the two metal lines 170 corresponding to the second type MOS gate structure is etched to form a groove. Theoretically, in the second type MOS gate structure, the first oxide layer 150 between any two corresponding metal lines 170 will be etched to form a groove, and the depth of the groove is 180nm to 220nm.

[0054] Next, please continue to refer to Figure 6 A dielectric layer 180 is formed, covering all the first metal layers, the first oxide layer 150, and the filling grooves. In this embodiment of the invention, the dielectric layer 180 is formed by HDP deposition. Since the surface of the first oxide layer 150 between the metal lines 170 is lower than the surface of the metal layer, an air gap 190 is formed within the dielectric layer 180 between the metal lines 170 during the deposition process. Furthermore, in the second type of MOS gate structure, there are also grooves between the metal lines, so an air gap 190 is formed above the grooves after the dielectric layer 180 is deposited. The air gap 190 reduces the parasitic capacitance between the metal lines 170; a larger air gap 190 reduces the parasitic capacitance even more.

[0055] Next, please refer to Figure 7 A dielectric layer 180 is deposited on top of the first metal layer 170 and the dielectric layer 180. A portion of the dielectric layer 180 is etched to form vias within the dielectric layer 180, which are then filled with metal to form contact holes 160. A second metal layer 200 is then formed on the surface of the dielectric layer 180, and the second metal layer 200 is connected to the contact holes 160. The second metal layer 200 increases the parasitic capacitance between the metal lines of the first metal layer of the first type of MOS transistor gate structure, thereby reducing the voltage division of the first type of MOS transistor gate structure. Therefore, after the RF switch circuit is formed, when the RF switch is off, the overall capacitance of the first type of MOS transistor gate structure is greater than that of the second type of MOS transistor. This reduces the bias voltage (Vds) of the first type of MOS transistor gate structure, bringing it closer to the bias voltage of the second type of MOS transistor gate structure. In the entire RF switch, the bias voltage of all MOS transistor gate structures is averaged, so when the voltage is increased, the leading MOS transistors will not break down, thus improving the operating capability of the RF switch.

[0056] Please refer to Figure 8 If we categorize MOS transistor gate structures into three types, where the first type is a first-stage MOS gate structure, the second type is a second-stage MOS gate structure, and the rest are third-stage MOS gate structures, then we need to... Figure 7 A third metal layer 210 is formed on top of the first metal layer 170 of the first type of MOS gate structure, further reducing the parasitic capacitance between the metal lines of the first metal layer 170. Both the second metal layer 200 and the third metal layer 210 reduce the parasitic capacitance between the metal lines of the first metal layer 170 of the first type of MOS gate structure. The second metal layer 200 also reduces the parasitic capacitance between the metal lines of the first metal layer 170 of the second type of MOS. This results in an average bias voltage across all types of MOS transistors. In other embodiments of the invention, there may be more levels of MOS gate structures, i.e., N can be a value other than 2 or 3. The second metal layer 200 to the Nth metal layer are all formed by spaced metal lines, and the metal lines of the first metal layer and the metal lines of the second metal layer to the Nth metal layer are all connected through contact holes. The number of MOS gate structures for each type of MOS gate structure may also be other values, but all include at least one MOS gate structure.

[0057] In summary, in the RF switch circuit and forming method provided in the embodiments of the present invention, the formed second metal layer to the Nth metal layer can increase the parasitic capacitance of the first type of MOS gate structure to the Nth type of MOS gate structure. The more metal layers there are, the more parasitic capacitance is increased. As a result, the capacitance of the first type of MOS gate structure to the Nth type of MOS gate structure gradually decreases, thereby reducing the capacitance of the first type of MOS gate structure to the Nth type of MOS gate structure. This makes the voltage of all MOS transistors more even and reduces the risk of breakdown of the first few types of MOS transistors.

[0058] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A radio frequency switching circuit, characterized in that, include: There are M MOS gate structures, starting from the signal input terminal, which are sequentially classified as the first-stage MOS gate structure to the Mth-stage MOS gate structure. The bias voltage of the first-stage MOS gate structure to the Mth-stage MOS gate structure decreases sequentially. All the MOS gate structures are classified into the first type MOS gate structure to the Nth type MOS gate structure according to their different bias voltages. The bias voltage of the first type MOS gate structure to the Nth type MOS gate structure decreases sequentially. The first oxide layer is located on all of the MOS gate structures; A first metal layer is located on the first oxide layer. The first metal layer includes a plurality of spaced metal lines, with the first oxide layer exposed between the metal lines. Each MOS gate structure corresponds to two metal lines, and the source and drain are each connected to a metal line. In all the MOS gate structures, there is a groove in the first oxide layer between two adjacent metal lines. A dielectric layer covering all the first metal layers, the first oxide layer, and the filling grooves, wherein air gaps are formed between adjacent metal lines in the dielectric layer; The second to Nth metal layers are sequentially formed on the first metal layer, and the second to Nth metal layers are interconnected by contact holes and connected to the first metal layer. The second to Nth metal layers are separated by dielectric layers. The first type of MOS gate structure has the first to Nth metal layers, the second type of MOS gate structure has the first to N-1th metal layers, and the N-1th type of MOS gate structure has the first metal layer and the second metal layer. M and N are both integers greater than 1.

2. The radio frequency switching circuit as described in claim 1, characterized in that, Also includes: A semiconductor substrate, wherein multiple MOS gate structures are partially formed on the surface of the semiconductor substrate and partially formed inside the semiconductor substrate.

3. The radio frequency switching circuit as described in claim 2, characterized in that, The semiconductor substrate includes: Substrate; A parasitic capacitance wiring layer is located on the surface of the substrate; The second oxide layer is located on the surface of the parasitic capacitance wiring layer. The plurality of MOS gate structures are partially formed on the surface of the second oxide layer and partially formed inside the second oxide layer.

4. The radio frequency switching circuit as described in claim 1, characterized in that, The second to Nth metal layers are all formed by spaced metal lines, and the metal lines of the first metal layer and the metal lines of the second to Nth metal layers are all connected through contact holes.

5. The radio frequency switching circuit as described in claim 1, characterized in that, Each type of MOS gate structure includes at least one MOS gate structure.

6. The radio frequency switching circuit as described in claim 1, characterized in that, MOSFETs with the same bias voltage or bias voltage within a certain range are classified as the same type of MOS gate structure.

7. A method for forming a radio frequency switching circuit as described in any one of claims 1 to 6, characterized in that, include: M MOS gate structures are formed, starting from the signal input terminal and sequentially from the first-stage MOS gate structure to the Mth-stage MOS gate structure. The bias voltage of the first-stage MOS gate structure to the Mth-stage MOS gate structure decreases sequentially. All the MOS gate structures are divided into first-type MOS gate structures to Nth-type MOS gate structures according to their different bias voltages. The bias voltage of the first-type MOS gate structure to the Nth-type MOS gate structure decreases sequentially. A first oxide layer is formed on all of the MOS gate structures; A first metal layer is formed on the first oxide layer. The first metal layer includes a plurality of spaced metal lines, with the first oxide layer exposed between the metal lines. Each MOS gate structure corresponds to two metal lines, and the source and drain are each connected to a metal line. In all MOS gate structures, the first oxide layer between two adjacent metal lines has a groove. A dielectric layer is formed, which covers all the first metal layer, the first oxide layer and the filling groove, and air gaps are formed between adjacent metal lines in the dielectric layer; A second metal layer to an Nth metal layer are sequentially formed on a first metal layer, and the second metal layer to an Nth metal layer are interconnected by contact holes and connected to the first metal layer. The second metal layer to an Nth metal layer are separated by a dielectric layer. The first type of MOS gate structure has a first metal layer to an Nth metal layer, the second type of MOS gate structure has a first metal layer to an (N-1)th metal layer, and the (N-1)th type of MOS gate structure has a first metal layer and a second metal layer. M and N are both integers greater than 1.

8. The method for forming the radio frequency switch circuit as described in claim 7, characterized in that, It also includes providing a semiconductor substrate, the semiconductor substrate comprising: Substrate; A parasitic capacitance wiring layer is located on the surface of the substrate; The second oxide layer is located on the surface of the parasitic capacitance wiring layer. All the MOS gate structures are partially formed on the surface of the second oxide layer and partially formed inside the second oxide layer.

9. The method for forming the radio frequency switch circuit as described in claim 7, characterized in that, A method for forming a first metal layer on a first oxide layer, the first metal layer comprising a plurality of spaced metal lines, includes: forming a metal layer on the first oxide layer and etching the metal layer to form a plurality of metal lines.

10. The method for forming the radio frequency switch circuit as described in claim 7, characterized in that, Methods for forming a second metal layer include: A contact hole is formed within the dielectric layer of the first type of MOS gate structure, and one contact hole is formed on each of the first metal layers; A second metal layer is formed on the dielectric layer, and the second metal layer is in contact with the contact hole.

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