Display device

Abstract

A display device. A main active layer positioned on a substrate includes a channel region, a first conductorized region positioned on a first side of the channel region, and a second conductorized region positioned on a second side of the channel region opposite the first side. At least one sacrificial active layer is positioned on the main active layer. A gate insulating film is positioned on the channel region of the main active layer. A first electrode is positioned on the at least one sacrificial active layer. A portion of the first electrode overlaps the first conductorized region of the main active layer. A second electrode is positioned on the at least one sacrificial active layer. A portion of the second electrode overlaps the second conductorized region of the main active layer. A third electrode positioned on the gate insulating film overlaps the channel region of the main active layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0152621, filed on November 8, 2021, which is incorporated herein by reference for all purposes as fully set forth herein. Technical Field

[0003] The embodiment relates to a display device. Background Technology

[0004] In the field of electronic devices, transistors are widely used as switching or driving devices. Specifically, thin-film transistors, which can be fabricated on glass or plastic substrates, are widely used as switching devices in display devices such as liquid crystal displays (LCDs) or organic light-emitting displays.

[0005] Based on the material of its active layer, thin-film transistors can be classified into: amorphous silicon (a-Si) thin-film transistors, in which amorphous silicon is used as the active layer; polycrystalline silicon (poly-Si) thin-film transistors, in which polycrystalline silicon is used as the active layer; and oxide semiconductor thin-film transistors, in which oxide semiconductor is used as the active layer.

[0006] Because amorphous silicon can be deposited to form an active layer in a short time, a-Si thin-film transistors have advantages in terms of short manufacturing time and low manufacturing cost. In contrast, the use of a-Si thin-film transistors in organic light-emitting display devices is adversely limited by their low current drive capability and threshold voltage variation due to low mobility.

[0007] Poly-Si thin-film transistors are formed by depositing amorphous silicon and then crystallizing the deposited amorphous silicon. Because the manufacturing process of poly-Si thin-film transistors requires a-Si crystallization process, the number of process steps increases, thereby increasing manufacturing costs. Furthermore, since the crystallization process is carried out at high processing temperatures, it is difficult to use poly-Si thin-film transistors in large-area devices. Additionally, due to the properties of poly-Si, achieving uniformity in poly-Si thin-film transistors is difficult.

[0008] In the case of oxide semiconductor thin-film transistors (OSTs), the active layer can be formed at relatively low temperatures. Furthermore, OSTs exhibit high mobility and a significant variation in resistance depending on their oxygen content. The desired physical characteristics are advantageously readily obtainable with OSTs. Moreover, due to the properties of oxides, transparent OSTs are advantageous for realizing transparent displays. However, to use an oxide active layer in a thin-film transistor, a separate conductorization process may be required to form the connection between the source and drain electrodes.

[0009] In the transistor manufacturing process of related technologies, metal can be deposited on the active layer, and an etching process can be performed. However, there is a problem that the active layer may be damaged. Furthermore, in the transistor manufacturing process of related technologies, there is also a problem that the active layer may be damaged by the metal deposited on it. Summary of the Invention

[0010] In this regard, the inventors of this disclosure have invented a display device having a transistor structure capable of preventing damage to the active layer.

[0011] The embodiment may provide a display device having a transistor structure that can prevent damage to the active layer during panel manufacturing.

[0012] An embodiment may provide a display device having a capacitor structure corresponding to a transistor structure that can prevent damage to the active layer during panel manufacturing.

[0013] The embodiments may provide a display device having a transistor structure that prevents metal from damaging (or contaminating) the active layer even when metal is deposited on the active layer.

[0014] The embodiments may provide a display device including transistors with high performance, high stability and high reliability.

[0015] According to an embodiment, a display device is provided, comprising: a substrate; a main active layer positioned on the substrate and including a channel region, a first conductive region positioned on a first side of the channel region, and a second conductive region positioned on a second side of the channel region opposite to the first side; at least one sacrificial active layer positioned on the main active layer; a gate insulating film positioned on the channel region of the main active layer; a first electrode positioned on at least one sacrificial active layer, a portion of the first electrode overlapping the first conductive region of the main active layer; a second electrode positioned on at least one sacrificial active layer, a portion of the second electrode overlapping the second conductive region of the main active layer; and a third electrode positioned on the gate insulating film and overlapping the channel region of the main active layer.

[0016] The thickness of each of the at least one sacrificial active layer may be less than the thickness of the main active layer.

[0017] The at least one sacrificial active layer may include a sacrificial active layer, and a gate insulating film may be positioned on the sacrificial active layer.

[0018] The thickness of the sacrificial active layer may be non-uniform, and each of the thickness of the portion of the sacrificial active layer overlapping with the first electrode and the thickness of the portion of the sacrificial active layer overlapping with the second electrode may be greater than the thickness of the portion of the sacrificial active layer overlapping with the third electrode.

[0019] The thickness of the thickest part of the sacrificial active layer can be less than the thickness of the main active layer.

[0020] The sacrificial active layer may include: a first portion overlapping with a first electrode; a second portion overlapping with a second electrode; a third portion overlapping with a third electrode; and a fourth portion not overlapping with any of the first, second, and third electrodes, wherein the fourth portion may include a conductive portion, and a portion of the third portion may include a non-conductive portion.

[0021] The primary active layer may contain a first semiconductor material, and the sacrificial active layer may contain a second semiconductor material that is different from the first semiconductor material.

[0022] The at least one sacrificial active layer may include a first sacrificial active layer located on a first conductive region of the main active layer, and a second sacrificial active layer located on a second conductive region of the main active layer, wherein a first electrode may be located on the first sacrificial active layer, and a second electrode may be located on the second sacrificial active layer.

[0023] Each of the first and second sacrificial active layers can be conductord.

[0024] Each of the first sacrificial active layer and the second sacrificial active layer may include a first semiconductor material, and the main active layer may include a second semiconductor material different from the first semiconductor material.

[0025] The first semiconductor material may have a first etch rate, and the second semiconductor material may have a second etch rate that is less than the first etch rate.

[0026] Compared to the second semiconductor material, the first semiconductor material is more susceptible to damage by metals.

[0027] Compared to the second semiconductor material, the first semiconductor material is less susceptible to damage from wet etching.

[0028] The first semiconductor material can be based on In, and the second semiconductor material can be based on Sn.

[0029] The display device may further include: a first auxiliary electrode located between the at least one sacrificial active layer and the first electrode; and a second auxiliary electrode located between the at least one sacrificial active layer and the second electrode.

[0030] Each of the first auxiliary electrode and the second auxiliary electrode may include a metal.

[0031] Each of the first auxiliary electrode and the second auxiliary electrode may include a transparent conductive oxide.

[0032] The display device may also include a transistor disposed in the display area or non-display area of ​​the display device, wherein the transistor includes a main active layer, at least one sacrificial active layer, a first electrode, a second electrode, and a third electrode.

[0033] The display device may further include: a light shield positioned on a substrate and overlapping a channel region of a main active layer; a buffer layer positioned on the light shield and located below the main active layer; and a capacitor disposed in a display area or a non-display area of ​​the display device; wherein the capacitor may include a first plate, a second plate, and a third plate, and the buffer layer may be positioned between the first plate and the second plate, and the gate insulating film may be positioned between the second plate and the third plate.

[0034] The first plate may be a light-shielding element or include the metal contained in the light-shielding element. The third plate may include an electrode plate, which is a third electrode, electrically connected to the third electrode, or contains the same metal as the third electrode. The second plate may include a main plate and a sacrificial plate. The main plate includes a conductive material formed of the same semiconductor material contained in the main active layer. The sacrificial plate includes a conductive material formed of the same semiconductor material contained in at least one sacrificial active layer.

[0035] The third plate may include an additional plate located between the electrode plate and the gate insulating film; or the second plate may include an additional plate located between the sacrificial plate and the gate insulating film.

[0036] The auxiliary plate may contain a metallic material that is the same as the metallic material contained in each of the first auxiliary electrode located between at least one sacrificial active layer and the first electrode and the second auxiliary electrode located between at least one sacrificial active layer and the second electrode.

[0037] According to an embodiment, the display device has a transistor structure that prevents damage to the active layer during panel manufacturing.

[0038] According to an embodiment, the display device has a capacitor structure corresponding to a transistor structure that can prevent damage to the active layer during panel manufacturing.

[0039] According to an embodiment, the display device has a transistor structure that prevents metal from damaging (or contaminating) the active layer even when metal is deposited on the active layer.

[0040] According to an embodiment, the display device includes transistors with high performance, high stability, and high reliability. Attached Figure Description

[0041] The above and other objects, features and advantages of this disclosure will become more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0042] Figure 1 This is a diagram illustrating the configuration of a display device according to an embodiment;

[0043] Figure 2 The equivalent circuit of a sub-pixel of a display device according to an embodiment is shown;

[0044] Figure 3 Another equivalent circuit for a subpixel of a display device is shown;

[0045] Figure 4 This is a diagram illustrating a light-shielding element in a sub-pixel of a display device according to an embodiment;

[0046] Figure 5 This is a cross-sectional view showing the transistor structure of a display device according to an embodiment;

[0047] Figure 6A yes Figure 5 Cross-sectional view of region X1 in the diagram;

[0048] Figure 6B yes Figure 5 Cross-sectional view of region X2 in the diagram;

[0049] Figure 7 It is shown Figure 5 Cross-sectional view of the structure of the main active layer and the sacrificial active layer;

[0050] Figure 8A It is shown that... Figure 5 The cross-sectional view of the capacitor structure corresponding to the transistor structure shown;

[0051] Figure 8B It is shown that... Figure 5 A cross-sectional view of another capacitor structure corresponding to the transistor structure shown;

[0052] Figure 9 This is a cross-sectional view showing the transistor structure in a display device according to an embodiment;

[0053] Figure 10A yes Figure 9 Cross-sectional view of region Y1 in the diagram;

[0054] Figure 10B yes Figure 9 Cross-sectional view of the Y2 region in the diagram;

[0055] Figure 11A It is shown that... Figure 9 The cross-sectional view of the capacitor structure corresponding to the transistor structure shown; and

[0056] Figure 11B It is shown that... Figure 9 The diagram shows a cross-sectional view of another capacitor structure corresponding to the transistor structure shown. Detailed Implementation

[0057] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of example, and in the drawings, the same reference numerals and reference numerals are used to designate the same or similar parts, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and parts incorporated herein will be omitted where it is determined that the description may make the subject matter of some embodiments of the invention considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional parts, unless these terms are used in conjunction with the term “only.” As used herein, the singular forms are intended to include the plural forms unless the context otherwise clearly indicates otherwise.

[0058] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used herein to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but merely to distinguish the corresponding element from the others.

[0059] When it is mentioned that the first element is "connected or coupled to" the second element, or "contacts or overlaps" the second element, it should be interpreted as meaning that not only can the first element be "directly connected or coupled" to the second element or "directly contact or overlap" the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled," "contacts or overlaps" with each other through a fourth element. Here, the second element can be included within at least one of two or more elements that are "connected or coupled," "contacts or overlaps" with each other.

[0060] When time-relative terms, such as “after,” “following,” “next,” “before,” etc., are used to describe the process or operation of an element or configuration, or the flow or steps in an operation, processing, or manufacturing method, these terms may be used to describe non-continuous or non-sequential processes or operations, unless the terms “directly” or “immediately after” are used together.

[0061] Furthermore, when referring to any size, relative size, etc., the numerical value or corresponding information of the element or feature (e.g., level, range, etc.) should be taken into account, including tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no specific description is given. In addition, the term "may" fully encompasses all the meanings of the term "can".

[0062] Various embodiments will now be described with reference to the accompanying drawings.

[0063] Figure 1 This is a diagram illustrating the configuration of a display device 100 according to an embodiment.

[0064] refer to Figure 1 The display device 100 according to the embodiment may include a display panel 110 and a driver circuit for driving the display panel 110.

[0065] The driver circuit may include a data driver circuit 120, a gate driver circuit 130, etc. The driver circuit may also include a controller 140 for controlling the data driver circuit 120 and the gate driver circuit 130.

[0066] The display panel 110 may include a substrate SUB and signal lines, such as multiple data lines DL and multiple gate lines GL disposed on the substrate SUB. The display panel 110 may include multiple sub-pixels SP connected to the multiple data lines DL and the multiple gate lines GL.

[0067] The display panel 110 may include a display area DA on which an image is displayed and a non-display area NDA on which no image is displayed. In the display panel 110, a plurality of sub-pixels SP for displaying the image are disposed within the display area DA. In the non-display area NDA, a pad portion may be disposed, and driver circuitry (i.e., data driver circuitry 120, gate driver circuitry 130, and controller 140) is electrically connected to the pad portion. The driver circuitry may be mounted on the pad portion, or an integrated circuit or printed circuit may be connected to the pad portion.

[0068] Data driver circuit 120 drives multiple data lines DL and can provide data signals to the multiple data lines DL. Controller 140 can provide control signal DCS to data driver circuit 120 to control the operating timing of data driver circuit 120. Controller 140 can provide gate control signal GCS to gate driver circuit 130 to control the operating timing of gate driver circuit 130.

[0069] The controller 140 can start scanning at a time point defined for the corresponding frame, convert image data input from the external source 150 into image data Data with a data signal format that can be read by the data driver circuit 120, provide the image data Data to the data driver circuit 120, and control the data drive at the appropriate time point in response to the scan.

[0070] The controller 140 can output various gate control signals GCS, including gate start pulse (GSP) signal, gate shift clock (GSC) signal, gate output enable (GOE) signal, etc., in order to control the gate driver circuit 130.

[0071] The controller 140 can output various data control signals DCS, including source start pulse (SSP) signal, source sampling clock (SSC) signal, source output enable (SOE) signal, etc., in order to control the data driver circuit 120.

[0072] The controller 140 may be provided as a separate component from the data driver circuitry 120, or it may be combined with the data driver circuitry 120 to form an integrated circuit (IC).

[0073] The data driver circuit 120 drives multiple data lines DL by receiving image data Data from the controller 140 and providing data voltage to the multiple data lines DL. In this document, the data driver circuit 120 is also referred to as the source driver circuit.

[0074] The data driver circuit 120 may include one or more source driver integrated circuits (SDICs).

[0075] For example, each SDIC can be connected to the display panel 110 via tape-automated bonding (TAB), via chip-on-glass (COG) or chip-on-panel (COP) bonding pads of the display panel 110, or via a chip-on-film (COF) structure connected to the display panel 110.

[0076] The gate driver circuit 130 can output a gate signal with an on or off level under the control of the controller 140. The gate driver circuit 130 can sequentially drive multiple gate lines GL by sequentially providing gate signals with on or off levels to multiple gate lines GL.

[0077] The gate driver circuit 130 can be connected to the display panel 110 via the TAB method, to the bonding pads of the display panel 110 via the COG or COP method, or to the display panel 110 via the COF method. Alternatively, the gate driver circuit 130 can be formed in the non-display area NDA of the display panel 110 via the gate-in-panel (GIP) method. The gate driver circuit 130 can be disposed on or connected to the substrate SUB. That is, when the gate driver circuit 130 is of the GIP type, the gate driver circuit 130 can be disposed on the substrate SUB in the non-display area NDA of the display panel 110. When the gate driver circuit 130 is of the COG type, COF type, etc., the gate driver circuit 130 can be connected to the substrate SUB.

[0078] Furthermore, at least one driver circuit of the data driver circuit 120 and the gate driver circuit 130 may be disposed within the display area DA. For example, at least one driver circuit of the data driver circuit 120 and the gate driver circuit 130 may be configured not to overlap with the sub-pixel SP or to partially or completely overlap with the sub-pixel SP.

[0079] When a specific gate line GL among multiple gate lines GL is turned on by the gate driver circuit 130, the data driver circuit 120 can convert the image data Data received from the controller 140 into an analog voltage and provide the analog voltage to the multiple data lines DL.

[0080] The data driver circuit 120 may be connected to one side of the display panel 110 (e.g., the top or bottom side). The data driver circuit 120 may be connected to both sides of the display panel 110 (e.g., the top and bottom sides) or to two or more of the four sides of the display panel 110, depending on the driving method, the design of the display panel, etc.

[0081] The gate driver circuit 130 may be connected to one side of the display panel 110 (e.g., the left or right side). The gate driver circuit 130 may be connected to both sides of the display panel 110 (e.g., the left and right sides), or to two or more of the four sides of the display panel 110, depending on the driving method, the design of the display panel, etc.

[0082] The controller 140 can be a timing controller typically used in the display field, a control device that includes a timing controller and is capable of performing other control functions, a control device different from a timing controller, or a circuit in a control device. The controller 140 can be implemented as various circuits or electronic components, such as integrated circuits (ICs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), processors, etc.

[0083] The controller 140 can be mounted on a printed circuit board (PCB), flexible printed circuit (FPC), etc., and is electrically connected to the data driver circuit 120 and the gate driver circuit 130 via the PCB, FPC, etc.

[0084] The display device 100 according to an embodiment of the present invention may be, for example, a display of a liquid crystal display device, which includes a backlight unit, or may be a self-emissive display such as an organic light-emitting diode (OLED) display, a quantum dot display, or a micro light-emitting diode (LED) display.

[0085] When the display device 100 according to an embodiment of the present invention is an OLED display, each sub-pixel SP may include a self-emissive OLED as an emitting device. When the display device 100 is a quantum dot display, each sub-pixel SP may include an emitting device that is a quantum dot implemented as a self-emissive semiconductor crystal. When the display device 100 according to an embodiment of the present invention is a micro-LED display, each sub-pixel SP may include a self-emissive micro-LED based on inorganic materials as an emitting device.

[0086] Figure 2 The equivalent circuit of a sub-pixel SP of a display device 100 according to an embodiment is shown, and Figure 3 Another equivalent circuit for a subpixel SP of the display device 100 is shown.

[0087] refer to Figure 2 Each of the plurality of sub-pixels SP disposed in the display panel 110 of the display device 100 according to the embodiment may include an emitting device ED, a driving transistor DRT, a scanning transistor SCT, and a storage capacitor Cst.

[0088] refer to Figure 2 The emitting device ED may include a pixel electrode PE, a common electrode CE, and an emitting layer EL positioned between the pixel electrode PE and the common electrode CE.

[0089] The pixel electrode PE of the emitting device ED can be an electrode disposed on each sub-pixel SP, while the common electrode CE can be an electrode commonly disposed on all sub-pixels SP. Here, the pixel electrode PE can be an anode, and the common electrode CE can be a cathode. Conversely, the pixel electrode PE can be a cathode, and the common electrode CE can be an anode.

[0090] For example, the emitting device ED can be an organic light-emitting diode (OLED), an inorganic light-emitting diode (LED), or a quantum dot emitting device.

[0091] The driving transistor DRT may include a first node N1, a second node N2, a third node N3, etc., for driving the light-emitting device ED.

[0092] The first node N1 of the driving transistor DRT can be the gate node of the driving transistor DRT and is electrically connected to the source node or drain node of the scan transistor SCT. The second node N2 of the driving transistor DRT can be the source node or drain node of the driving transistor DRT and is electrically connected to the sensing transistor SENT (see...). Figure 3 The source or drain node of the transistor DRT is electrically connected to the pixel electrode PE of the emitter device ED. The third node N3 of the driving transistor DRT can be electrically connected to the driving voltage line DVL, through which the driving voltage EVDD is provided.

[0093] The scanning transistor SCT can be controlled by a scan signal SCAN, which is a type of gate signal, and is connected to the first node N1 of the driving transistor DRT and the data line DL. That is, the scanning transistor SCT can be turned on or off by the scan signal SCAN provided through the scan signal line SCL, which is a type of gate line GL, and controls the connection between the data line DL and the first node N1 of the driving transistor DRT.

[0094] The scanning transistor SCT can be turned on by the scanning signal SCAN, which has a turn-on voltage level, to transmit the data voltage Vdata provided through the data line DL to the first node N1 of the driving transistor DRT.

[0095] Here, when the scanning transistor SCT is an N-type transistor, the on-state voltage of the scanning signal SCAN can be a high-level voltage. When the scanning transistor SCT is a P-type transistor, the on-state voltage of the scanning signal SCAN can be a low-level voltage.

[0096] The storage capacitor Cst can be connected to the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst is charged with an amount of charge corresponding to the voltage difference between its two ends, and is used to maintain the voltage difference between its two ends for a predetermined frame time. Therefore, the corresponding sub-pixel SP can emit light during the predetermined frame time.

[0097] refer to Figure 3 Each of the plurality of sub-pixels SP disposed in the display panel 110 of the display device 100 according to an embodiment of the present invention may further include a sensing transistor SENT.

[0098] The sensing transistor SENT can be controlled by a sensing signal SENSE, which is a type of gate signal, and is connected to the second node N2 of the driving transistor DRT and the reference voltage line RVL. In other words, the sensing transistor SENT can be turned on or off by the sensing signal SENSE provided through the sensing signal line SENL, which is a type of gate line GL, to control the connection between the reference voltage line RVL and the second node N2 of the driving transistor DRT.

[0099] The sensing transistor SENT can be turned on by a sensing signal SENSE with a conduction level voltage to transmit the reference voltage Vref provided through the reference voltage line RVL to the second node N2 of the driving transistor DRT.

[0100] In addition, the sensing transistor SENT can be turned on by a sensing signal SENSE with a conduction level voltage to transfer the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL.

[0101] Here, when the sensing transistor SENT is an N-type transistor, the on-state voltage of the sensing signal SENSE can be a high-level voltage. When the sensing transistor SENT is a P-type transistor, the on-state voltage of the sensing signal SENSE can be a low-level voltage.

[0102] The function of the sensing transistor SENT in transmitting the voltage of the second node N2 of the driving transistor DRT to the reference voltage line RVL can be used in the driving process to sense the characteristics of the sub-pixel SP. In this case, the voltage transmitted to the reference voltage line RVL can be a voltage used to calculate the characteristics of the sub-pixel SP, or a voltage on which the characteristics of the sub-pixel SP are reflected.

[0103] Each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT can be an N-type transistor or a P-type transistor. In this disclosure, for the sake of brevity, each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT will be shown as an N-type transistor.

[0104] The storage capacitor Cst can be an external capacitor that is intentionally designed to be provided outside the driving transistor DRT, rather than a parasitic capacitor, such as an internal capacitor (i.e., Cgs or Cgd) existing between the gate node and the source node (or drain node) of the driving transistor DRT.

[0105] The scan signal line SCL and the sensing signal line SENL can have different gate lines GL. In this case, the scan signal SCAN and the sensing signal SENSE can have different gate signals, and the on / off timing of the scan transistor SCT in a single sub-pixel SP can be independent of the on / off timing of the sensing transistor SENT in the same sub-pixel SP. That is, the on / off timing of the scan transistor SCT and the sensing transistor SENT in a single sub-pixel SP can be the same or different from each other.

[0106] Alternatively, the scan signal line SCL and the sensing signal line SENL can be the same gate line GL. In a single sub-pixel SP, the gate node of the scan transistor SCT and the gate node of the sensing transistor SENT can be connected to a single gate line GL. In this case, the scan signal SCAN and the sensing signal SENSE can be the same gate signal, and the on / off timing of the scan transistor SCT and the sensing transistor SENT can be the same in a single sub-pixel SP.

[0107] Figure 2 and Figure 3 The structure of the sub-pixel SP shown is for illustrative purposes only and can be modified in various forms by further including one or more transistors or one or more capacitors.

[0108] In addition, Figure 2 and Figure 3 In this paper, the subpixel structure has been described by assuming that the display device 100 is a self-emissive display device. Alternatively, when the display device 100 is a liquid crystal display (LCD), each subpixel SP may include a transistor, a pixel electrode, etc.

[0109] Figure 4 This is a diagram showing a light-shielding member LS in a sub-pixel SP of a display device 100 according to an embodiment.

[0110] refer to Figure 4 In the sub-pixel SP of the display device 100 according to the embodiment, the driving transistor DRT may have unique characteristics, such as threshold voltage and mobility. When the unique characteristics of the driving transistor DRT change, the current driving performance (i.e., current supply performance) of the driving transistor DRT may also change, thereby changing the emission characteristics of the corresponding sub-pixel SP.

[0111] The device characteristics (e.g., threshold voltage and mobility) of the driving transistor DRT can change with the driving time of the driving transistor DRT. In addition, when the driving transistor DRT is illuminated, specifically when the channel region of the driving transistor DRT is illuminated, the device characteristics (e.g., threshold voltage and mobility) of the driving transistor DRT may change.

[0112] Therefore, as Figure 4 As shown, in order to reduce variations in the device characteristics of the driving transistor DRT (e.g., variations in threshold voltage or mobility), a light-shielding element LS can be placed adjacent to the driving transistor DRT. For example, the light-shielding element LS can be placed below the channel region of the driving transistor DRT.

[0113] The light-shielding element LS can be disposed below the channel region of the driving transistor DRT to serve as the main body of the driving transistor DRT.

[0114] Body effects may occur in the driving transistor DRT. To reduce the impact of body effects, the light-shielding element LS, which is the main body of the driving transistor DRT, can be electrically connected to the second node N2 of the driving transistor DRT. Here, the second node N2 of the driving transistor DRT can be the source node of the driving transistor DRT.

[0115] Meanwhile, the light-shielding element LS can be disposed not only below the channel region of the driving transistor DRT, but also below the channel region of another transistor (e.g., the scanning transistor SCT or the sensing transistor SENT).

[0116] Furthermore, during transistor formation, the channel region of the active layer may be etched (specifically, wet etching) and damaged. The channel region of the active layer may be damaged when metal is formed on it. In this document, the active layer may be referred to as the semiconductor layer or the channel layer. Damage may also be interpreted as contamination.

[0117] The embodiments disclose a transistor structure that can reduce the risk of damage to the active layer, which serves as the channel layer, during etching or metal formation processes. Therefore, the transistors of the display device 100 according to the embodiments can have high performance, high stability, and high reliability.

[0118] Here, the transistors having the transistor structure according to the embodiment may be all or some of the transistors disposed in the display panel 110. In one example, the transistors having the transistor structure according to the embodiment may include all or some of the transistors in each sub-pixel SP. In another example, the transistors having the transistor structure according to the embodiment may include all or some of the transistors in the GIP-type gate driver circuit 130.

[0119] The transistor structure according to the embodiment may include not only a main active layer but also a sacrificial active layer for preventing damage to the main active layer. In this document, the transistor will also be referred to as a thin-film transistor (TFT).

[0120] Figure 5 This is a cross-sectional view showing the transistor structure of the display device 100 according to an embodiment. Figure 6A yes Figure 5 Cross-sectional view of region X1 in the diagram. Figure 6B yes Figure 5 Cross-sectional view of region X2 in the image. Figure 7 It is shown Figure 5 A cross-sectional view of the structure of the main active layer MACT and the sacrificial active layer SACT. Figure 7 In order to describe the structure of each of the main active layer MCT and the sacrificial active layer SACT, electrodes E1, E2 and E3, the main active layer MCT and the sacrificial active layer SACT are shown in an exploded view.

[0121] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7 The display device 100 according to the embodiment may include a main active layer MCT, a sacrificial active layer SACT, a gate insulating film GI, a first electrode E1, a second electrode E2, a third electrode E3, etc.

[0122] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7 The main active layer MCT can be positioned on the substrate SUB and includes a channel region CHA, a first conductive region CA1 positioned on a first side of the channel region CHA, and a second conductive region CA2 positioned on a second side of the channel region CHA opposite to the first side.

[0123] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7 The sacrificial active layer SACT can be located on the primary active layer MACT.

[0124] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7 The gate insulating film GI can be positioned on the sacrificial active layer SACT and on the channel region CHA of the main active layer MCT.

[0125] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7 The first electrode E1 can be positioned on the sacrificial active layer SACT. A portion of the first electrode E1 can overlap with the first conductive region CA1 of the main active layer MCT.

[0126] The second electrode E2 can be positioned on the sacrificial active layer SACT. A portion of the second electrode E2 can overlap with the second conductor region CA2 of the main active layer MACT.

[0127] The third electrode E3 can be positioned on the gate insulating film GI. A portion of the third electrode E3 can overlap with the channel region CHA of the main active layer MCT.

[0128] The third electrode E3 can be the gate electrode, the first electrode E1 can be the source electrode or the drain electrode, and the second electrode E2 can be the drain electrode or the source electrode.

[0129] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7 In this embodiment, the channel region CHA of the primary active layer MCT can be used as the primary channel. The sacrificial active layer SACT can be used as a sacrificial layer. Although the sacrificial active layer SACT is used as a sacrificial layer according to this embodiment, the sacrificial active layer SACT is an active layer retained in the final product. Furthermore, in this embodiment, the sacrificial active layer SACT can be used as the interface of the channel region CHA of the primary active layer MCT.

[0130] In this regard, in the embodiments, each of the primary active layer MACT and the sacrificial active layer SACT may have unique characteristics. Here, unique characteristics may include structural features such as thickness, material characteristics, etc. These features will be described in more detail below.

[0131] refer to Figure 5 The thickness Hs of the sacrificial active layer (SACT) can be smaller than the thickness Hm of the main active layer (MACT). Therefore, carrier transport (e.g., electrons and holes) can proceed appropriately. The main active layer (MACT) functions as the main channel without hindrance.

[0132] For example, the thickness Hs of the sacrificial active layer SACT can be uniform, or in some cases, non-uniform.

[0133] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7When the thickness Hs of the sacrificial active layer SACT is non-uniform, each of the first thickness Hs1 of the portion of the sacrificial active layer SACT overlapping with the first electrode E1 and the second thickness Hs2 of the portion of the sacrificial active layer SACT overlapping with the second electrode E2 can be greater than the thickness Hs3 of the portion of the sacrificial active layer SACT overlapping with the third electrode E3.

[0134] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7 Each of the first thickness Hs1 and the second thickness Hs2 of the thickest part of the sacrificial active layer SACT can be less than the thickness Hm of the main active layer MACT.

[0135] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7 The sacrificial active layer SACT may include a first part PART1 that overlaps with the first electrode E1, a second part PART2 that overlaps with the second electrode E2, a third part PART3 that overlaps with the third electrode E3, and a fourth part PART4 that does not overlap with any of the first electrode E1, the second electrode E2, and the third electrode E3.

[0136] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7 In the Sacrificial Active Layer (SACT), Part 4 may include at least a portion formed by the conductor region CA, and a portion of Part 3 may include a non-conductor region.

[0137] For example, in a sacrificial active layer (SACT), the third part (PART3) may not be conductor-modified, and the first part (PART1), the second part (PART2), and the fourth part (PART4) include at least a portion formed by the conductor-modified region (CA). However, in a sacrificial active layer (SACT), the portions of the third part (PART3) adjacent to the fourth part (PART4) on both sides may be conductor-modified.

[0138] Therefore, the sacrificial active layer SACT can be used as the interface of the channel region CHA of the main active layer MCT, and at the same time as the sacrificial layer.

[0139] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7The display device 100 according to the embodiment may further include a first auxiliary electrode AUX1 located between the sacrificial active layer SACT and the first electrode E1, and a second auxiliary electrode AUX2 located between the sacrificial active layer SACT and the second electrode E2.

[0140] For example, each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 may contain metal.

[0141] Each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 can be formed by wet etching.

[0142] According to an embodiment, since the sacrificial active layer SACT is positioned on the main active layer MCT, the sacrificial active layer SACT can be sacrificed by the wet etching during the wet etching process for forming the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2, thereby preventing the main active layer MCT from being etched.

[0143] Furthermore, in the wet etching used to form the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2, the metals contained in the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 may be contaminants to the surrounding environment. However, according to the embodiment, since the sacrificial active layer SACT is positioned on the main active layer MACT, the phenomenon that the surface of the main active layer MACT, which serves as the main channel, is damaged (or contaminated) by metals generated as byproducts (e.g., metals contained in each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2) during wet etching can be avoided.

[0144] Regarding the aforementioned characteristics, the primary active layer (MACT) may comprise a first semiconductor material with a relatively high etch rate. In contrast, the sacrificial active layer (SACT) may comprise a second semiconductor material with a relatively low etch rate.

[0145] The primary active layer (MACT) may contain a first semiconductor material that is relatively more damaged by the metal. In contrast, the sacrificial active layer (SACT) may contain a second semiconductor material that is relatively less damaged by the metal.

[0146] Therefore, the sacrificial active layer SACT positioned on the main active layer MCT can prevent the surface of the main active layer MCT, which serves as the main channel, from being damaged by metal generated as a byproduct during the formation of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2.

[0147] The primary active layer (MACT) may contain a first semiconductor material that is less damaged by wet etching. In contrast, the sacrificial active layer (SACT) may contain a second semiconductor material that is more damaged by wet etching. In this context, damage caused by wet etching can refer to changes in the electrical properties of the semiconductor material. In this case, the channel region CHA of the primary active layer (MACT) may not function as a channel, the transport characteristics of charge carriers (e.g., electrons or holes) may degrade, or the switching characteristics of the corresponding transistors may degrade.

[0148] Therefore, since the sacrificial active layer (SACT) is located on the main active layer (MACT), the sacrificial active layer (SACT) can be etched first via wet etching, while the main active layer (MACT) can be avoided from being etched. Even if the main active layer (MACT) is etched, it is less damaged by wet etching, thus preventing it from being etched to the point where it cannot be used properly as the main channel.

[0149] Meanwhile, to reduce the likelihood of the main active layer (MACT) being etched during wet etching, wet processing is performed after a sacrificial active layer (SACT) with a predetermined thickness is formed. Therefore, the thickness Hs3 of the etched portion can be less than the thickness (Hs1 or Hs2) of the portion not etched by the wet etching process.

[0150] The portion of the sacrificial active layer SACT that is not etched by wet etching may include the portion overlapping with the first auxiliary electrode AUX1 and the portion overlapping with the second auxiliary electrode AUX2.

[0151] To reduce the possibility of the main active layer MCT being etched, even if a sacrificial active layer SACT with a predetermined thickness Hs is formed, the sacrificial active layer SACT should not be too thick to hinder the function of the main active layer MCT as the main channel.

[0152] Meanwhile, in order to prevent the surface of the main active layer MCT used as the main channel from being damaged by metal generated as a byproduct during the formation of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2, each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 may contain a transparent conductive oxide (TCO) instead of a metal.

[0153] As described above, the primary active layer (MACT) may contain a first semiconductor material. The sacrificial active layer (SACT) may contain a second semiconductor material that is different from the first semiconductor material.

[0154] For example, the primary active layer (MACT) may contain a first semiconductor material based on In. The sacrificial active layer (SACT) may contain a second semiconductor material based on Sn.

[0155] For example, the first semiconductor material based on In may include indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc. The second semiconductor material based on Sn may include indium tin zinc oxide (ITZO), indium tin gallium zinc oxide (ITGZO), tin(II) oxide (SnO), tin oxide (Sn2O), tin(IV) oxide (SnO2), etc.

[0156] For example, the etching rate of the first semiconductor material can be higher than that of the second semiconductor material.

[0157] For example, the first semiconductor material can be damaged by metals relatively more, while the second semiconductor material can be damaged by metals relatively less.

[0158] For example, the first semiconductor material can be damaged relatively less by wet etching, while the second semiconductor material can be damaged relatively more by wet etching.

[0159] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7 All first electrodes E1, second electrodes E2, and third electrodes E3 may contain the same metallic material. For example, each of the first electrodes E1 and second electrodes E2 may contain the same metallic material as the metallic material contained in the third electrode E3. For example, each of the first electrodes E1, second electrodes E2, and third electrodes E3 may contain a gate metal material. The gate metal material may refer to the metallic material of the third electrode E3 used as the gate electrode or the metallic material of the gate line GL.

[0160] refer to Figure 5 , Figure 6A , Figure 6B and Figure 7 The described structure is a transistor structure. The display device 100 according to an embodiment includes transistors disposed within a display area DA or a non-display area NDA. Each transistor may include a main active layer MACT, a sacrificial active layer SACT, a first electrode E1, a second electrode E2, and a third electrode E3.

[0161] The transistors having the transistor structure according to the embodiment described above may be all or some of the transistors disposed within the display panel 110. In one example, the transistors having the transistor structure according to the embodiment may include all or some of the transistors in the sub-pixel SP. In another example, the transistors having the transistor structure according to the embodiment may include all or some of the transistors in the GIP-type gate driver circuit 130.

[0162] Figure 8A It is shown that... Figure 5 The cross-sectional view of the capacitor structure corresponding to the transistor structure shown. Figure 8B It is shown that... Figure 5 The diagram shows a cross-sectional view of another capacitor structure corresponding to the transistor structure shown.

[0163] refer to Figure 5 The display device 100 according to the embodiment may further include a light-shielding member LS positioned on the substrate SUB and overlapping the channel region CHA of the main active layer MCT, and a buffer layer BUF positioned on the light-shielding member LS and located below the main active layer MCT.

[0164] refer to Figure 8A and Figure 8B According to an embodiment, the display device 100 may include a capacitor having a vertical structure corresponding to the transistor structure described above and disposed in at least one of the display area DA and the non-display area NDA.

[0165] refer to Figure 8A and Figure 8B In the display device 100 according to the embodiment, the capacitor may include a first plate 810, a second plate 820 and a third plate 830.

[0166] refer to Figure 8A and 8B The first plate 810 can be positioned on the substrate SUB. The buffer layer BUF can be positioned between the first plate 810 and the second plate 820. The gate insulating film GI can be positioned between the second plate 820 and the third plate 830.

[0167] refer to Figure 8A and 8B The first plate 810 may be a light-shielding element LS or include the metal contained in the light-shielding element LS.

[0168] refer to Figure 8A and 8B The third plate 830 may include an electrode plate 832, which includes the same metal as the third electrode E3.

[0169] refer to Figure 8A and 8B The second board 820 may include a main board 821 and a sacrificial board 822. The main board 821 includes a conductor material formed from the same semiconductor material contained in the main active layer MACT. The sacrificial board 822 is formed by conductor-forming the same semiconductor material contained in the sacrificial active layer SACT.

[0170] refer to Figure 8A and Figure 8BIn the display device 100 according to an embodiment, for example, the capacitor may include a first plate 810 of a metal material containing a light-shielding element LS, a second plate 820 of a semiconductor material containing an active layer, and a third plate 830 of a gate metal material. In this case, the capacitor may be referred to as having a light-shielding element-active layer-gate metal (LAG) structure.

[0171] In the manufacturing of the panel, the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 can be formed before or after the gate insulating film GI.

[0172] Figure 8A The capacitor structure shown illustrates the formation of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 after the gate insulating film GI during panel manufacturing.

[0173] refer to Figure 8A The third plate 830 of the capacitor may include not only the electrode plate 832 (which is the third electrode E3, electrically connected to the third electrode E3, or containing the same metal as the third electrode E3), but also an additional plate 831 located between the electrode plate 832 and the gate insulating film GI.

[0174] The auxiliary plate 831 may contain the same metal material as the metal material contained in each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2.

[0175] Figure 8B The capacitor structure shown illustrates the formation of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 before the gate insulating film GI during panel manufacturing.

[0176] refer to Figure 8B The second plate 820 of the capacitor may also include an additional plate 823 located between the sacrificial plate 822 and the gate insulating film GI. The sacrificial plate 822 contains a conductive material formed of the same semiconductor material contained in the sacrificial active layer SACT.

[0177] The auxiliary plate 823 may contain the same metal material as the metal material contained in each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2.

[0178] refer to Figure 8A and 8BThe third plate 830 can be any one of the first to third electrodes (E1, E2, and E3) or can be electrically connected to any one of the first to third electrodes (E1, E2, and E3). The second plate 820 can be another one of the first to third electrodes (E1, E2, and E3) or can be electrically connected to another one of the first to third electrodes (E1, E2, and E3). The first plate 810 can be another one of the first to third electrodes (E1, E2, and E3) or can be electrically connected to another one of the first to third electrodes (E1, E2, and E3).

[0179] For example, the third plate 830 can be either the first electrode E1 or the second electrode E2, or it can be electrically connected to either the first electrode E1 or the second electrode. The second plate 820 can be another form of the third electrode E3, or it can be electrically connected to another form of the third electrode E3. The first plate 810 can be either the first electrode E1 or the second electrode, or it can be electrically connected to either the first electrode E1 or the second electrode. Here, the first electrode E1 or the second electrode can be the source node or the drain node of the transistor (e.g., the second node N2 driving the transistor DRT). The third electrode E3 can be the gate node of the transistor (e.g., the first node N1 driving the transistor DRT).

[0180] Below, we will refer to Figure 9 , Figure 10A and Figure 10B The description also includes another example of a transistor structure for using a sacrificial active layer to prevent damage to the main active layer.

[0181] Figure 9 This is a cross-sectional view showing the transistor structure in the display device 100 according to an embodiment. Figure 10A yes Figure 9 Cross-sectional view of region Y1 in the diagram. Figure 10B yes Figure 9 A cross-sectional view of the Y2 region in the diagram.

[0182] refer to Figure 9 , Figure 10A and Figure 10B The display device 100 according to the embodiment may include a main active layer MCT for constituting transistors, a first sacrificial active layer SACT1 and a second sacrificial active layer SACT2, a first electrode E1, a second electrode E2, a third electrode E3, etc.

[0183] refer to Figure 9 , Figure 10A and Figure 10BThe main active layer MCT can be positioned on the substrate SUB and includes a channel region CHA, a first conductive region CA1 positioned on a first side of the channel region CHA, and a second conductive region CA2 positioned on a second side of the channel region CHA opposite to the first side.

[0184] refer to Figure 9 , Figure 10A and Figure 10B The first sacrificial active layer SACT1 can be located on the first conductor region CA1 of the main active layer MCT.

[0185] refer to Figure 9 , Figure 10A and Figure 10B The second sacrificial active layer SACT2 can be located on the second conductor region CA2 of the main active layer MCT.

[0186] refer to Figure 9 , Figure 10A and Figure 10B The gate insulating film GI can be positioned on the channel region CHA of the main active layer MCT.

[0187] refer to Figure 9 , Figure 10A and Figure 10B The first electrode E1 can be positioned on the first sacrificial active layer SACT1, and a portion of the first electrode E1 can overlap with the first conductive region CA1 of the main active layer MCT.

[0188] refer to Figure 9 , Figure 10A and Figure 10B The second electrode E2 can be positioned on the second sacrificial active layer SACT2, and a portion of the second electrode E2 can overlap with the second conductor region CA2 of the main active layer MCT.

[0189] refer to Figure 9 , Figure 10A and Figure 10B The third electrode E3 can be positioned on the gate insulating film GI, and a portion of the third electrode E3 can overlap with the channel region CHA of the main active layer MCT.

[0190] The third electrode E3 can be the gate electrode, the first electrode E1 can be the source electrode or the drain electrode, and the second electrode E2 can be the drain electrode or the source electrode.

[0191] refer to Figure 9 , Figure 10A and Figure 10B In this embodiment, the channel region CHA of the main active layer MCT can be used as the main channel, and can also be used as the interface of the channel region CHA of the main active layer MCT.

[0192] In this embodiment, the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 can be used as sacrificial layers to prevent damage to the main active layer MACT1 during panel manufacturing. Although the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 are used as sacrificial layers, they are active layers retained in the final product.

[0193] In this embodiment, each of the main active layer MACT, the first sacrificial active layer SACT1, and the second sacrificial active layer SACT2 may have unique characteristics. These unique characteristics may include structural features such as thickness, material characteristics, etc. These features will be described in more detail below.

[0194] refer to Figure 9 , Figure 10A and Figure 10B The thickness Hs of each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 can be less than the thickness Hm of the main active layer MCT. Therefore, the electrical connection between the first conductive region CA1 of the main active layer MCT and the first electrode E1 can be improved, and the electrical connection between the second conductive region CA2 of the main active layer MCT and the second electrode E2 can be improved.

[0195] Each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 can be in a conductive state. Therefore, the electrical connection between the first conductive region CA1 of the main active layer MCT and the first electrode E1 can be further improved, and the electrical connection between the second conductive region CA2 of the main active layer MCT and the second electrode E2 can be further improved.

[0196] refer to Figure 9 , Figure 10A and Figure 10B The display device 100 according to the embodiment may further include a first auxiliary electrode AUX1 located between the first sacrificial active layer SACT1 and the first electrode E1, and a second auxiliary electrode AUX2 located between the second sacrificial active layer SACT2 and the second electrode E2.

[0197] Each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 may contain metal.

[0198] Meanwhile, each of the first conductor region CA1 and the second conductor region CA2 in the main active layer MCT can be in a state of being fully conductord or in a state of being partially conductord.

[0199] In one example, each of the first conductive region CA1 and the second conductive region CA2 of the main active layer MCT can be actually conductive from the top surface to the bottom surface in the depth direction. In another example, each of the first conductive region CA1 and the second conductive region CA2 of the main active layer MCT can be actually conductive from the top surface to the middle portion, rather than being completely conductive from the top surface to the bottom surface in the depth direction.

[0200] According to an embodiment, since the first sacrificial active layer SACT1 is located on the first conductive region CA1 of the main active layer MCT, the first sacrificial active layer SACT1 can be sacrificed by wet etching during the wet etching process for forming the first auxiliary electrode AUX1, thereby preventing the main active layer MCT from being etched.

[0201] Furthermore, according to the embodiment, since the second sacrificial active layer SACT2 is located on the second conductor region CA2 of the main active layer MCT, the second sacrificial active layer SACT2 can be sacrificed by wet etching during the wet etching for forming the second auxiliary electrode AUX2, thereby preventing the main active layer MCT from being etched.

[0202] In wet etching or metal deposition used to form the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2, the metals contained in the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 may be contaminants to the surrounding environment. However, according to an embodiment, since the main active layer MCT contains a semiconductor material resistant to damage caused by metals, the phenomenon that the surface of the main active layer MCT used as the main channel is damaged (or contaminated) by metals generated as byproducts (such as the metals contained in each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2) during wet etching can be avoided.

[0203] Regarding the above description, the primary active layer MACT may contain a second semiconductor material with a relatively low etch rate. In contrast, each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 may contain a first semiconductor material with a relatively high etch rate.

[0204] The primary active layer MACT may contain a second semiconductor material that has greater resistance to damage caused by metals. In contrast, each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 may contain a first semiconductor material that has less resistance to damage caused by metals.

[0205] Each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 is conductord to serve as an auxiliary electrode, and only the main active layer MACTT, which is resistant to damage caused by metal, serves as the channel and interface. Therefore, the surface of the main active layer MACTT, which serves as the main channel, can avoid metal damage that occurs as a byproduct during the formation of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2.

[0206] The primary active layer MCT may contain a second semiconductor material that has less resistance to damage caused by wet etching. In contrast, each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 may contain a first semiconductor material that has greater resistance to damage caused by wet etching.

[0207] Therefore, the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 are etched first and sacrificed in wet etching, thereby preventing the main active layer MCT, which has less resistance to wet etching, from being damaged by wet etching.

[0208] In addition, in order to more effectively prevent the surface of the main active layer MCT used as the main channel from being damaged by metal generated as a byproduct during the formation of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2, each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 may contain TCO instead of metal.

[0209] refer to Figure 9 , Figure 10A and Figure 10B Each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 may contain a first semiconductor material. The main active layer MACT may contain a second semiconductor material that is different from the first semiconductor material.

[0210] For example, each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 may contain a first semiconductor material based on In. The main active layer MACT may contain a second semiconductor material based on Sn.

[0211] For example, the first semiconductor material based on In may include indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc. The second semiconductor material based on Sn may include indium tin zinc oxide (ITZO), indium tin gallium zinc oxide (ITGZO), tin(II) oxide (SnO), tin oxide (Sn2O), tin(IV) oxide (SnO2), etc.

[0212] For example, the etching rate of the first semiconductor material can be higher than that of the second semiconductor material.

[0213] For example, the first semiconductor material can be damaged by metals relatively more, while the second semiconductor material can be damaged by metals relatively less.

[0214] For example, the first semiconductor material can be damaged relatively less by wet etching, while the second semiconductor material can be damaged relatively more by wet etching.

[0215] refer to Figure 9 , Figure 10A and Figure 10B All first electrodes E1, second electrodes E2, and third electrodes E3 may contain the same metallic material. For example, each of the first electrodes E1 and second electrodes E2 may contain the same metallic material as the metallic material contained in the third electrode E3. For example, each of the first electrodes E1, second electrodes E2, and third electrodes E3 may contain a gate metal material. The gate metal material may refer to the metallic material of the third electrode E3 used as the gate electrode or the metallic material of the gate line GL.

[0216] refer to Figure 9 , Figure 10A and Figure 10B The described structure is a transistor structure. The display device 100 according to an embodiment includes transistors disposed within a display area DA or a non-display area NDA. Each transistor may include a main active layer MACT, a first sacrificial active layer SACT1 and a second sacrificial active layer SACT2, a first electrode E1, a second electrode E2, and a third electrode E3.

[0217] The transistors having the transistor structure according to the embodiment described above may be all or some of the transistors disposed within the display panel 110. In one example, the transistors having the transistor structure according to the embodiment may include all or some of the transistors in the sub-pixel SP. In another example, the transistors having the transistor structure according to the embodiment may include all or some of the transistors in the GIP-type gate driver circuit 130.

[0218] Figure 11A It is shown that... Figure 9 The cross-sectional view of the capacitor structure corresponding to the transistor structure shown. Figure 11B It is shown that... Figure 9 The diagram shows a cross-sectional view of another capacitor structure corresponding to the transistor structure shown.

[0219] refer to Figure 9 The display device 100 according to the embodiment may further include: a light shield LS positioned on the substrate SUB and overlapping the channel region CHA of the main active layer MCT; and a buffer layer BUF positioned on the light shield LS and located below the main active layer MCT.

[0220] refer to Figure 11Aand 11B According to an embodiment, the display device 100 may include a capacitor having a vertical structure corresponding to the transistor structure described above and being disposed in at least one of the display area DA and the non-display area NDA.

[0221] refer to Figure 11A and Figure 11B In the display device 100 according to the embodiment, the capacitor may include a first plate 1110, a second plate 1120 and a third plate 1130.

[0222] refer to Figure 11A and Figure 11B The first plate 1110 can be positioned on the substrate SUB. The buffer layer BUF can be positioned between the first plate 1110 and the second plate 1120. The gate insulating film GI can be positioned between the second plate 1120 and the third plate 1130.

[0223] refer to Figure 11A and Figure 11B The first plate 1110 may be a light-shielding element LS or include the metal contained in the light-shielding element LS.

[0224] refer to Figure 11A and Figure 11B The third plate 1130 may include an electrode plate 1132, which includes the same metal as the third electrode E3.

[0225] refer to Figure 11A and Figure 11B The second board 1120 may include a main board 1121 and a sacrificial board 1122. The main board 1121 includes a conductor material formed of the same semiconductor material as the semiconductor material contained in the main active layer MCT. The sacrificial board 1122 includes a conductor material formed of the same semiconductor material as the semiconductor material contained in each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2.

[0226] In the manufacturing of the panel, the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 can be formed before or after the gate insulating film GI.

[0227] Figure 11A The capacitor structure shown illustrates the formation of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 after the gate insulating film GI during panel manufacturing.

[0228] refer to Figure 11AThe third plate 1130 of the capacitor may include not only the electrode plate 1132 (which is the third electrode E3, electrically connected to the third electrode E3, or containing the same metal as the third electrode E3), but also an additional plate 1131 located between the electrode plate 1132 and the gate insulating film GI.

[0229] The auxiliary plate 1131 may contain the same metal material as the metal material contained in each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2.

[0230] refer to Figure 11B , Figure 11B The capacitor structure shown illustrates the formation of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 before the gate insulating film GI during panel manufacturing.

[0231] refer to Figure 11B The second plate 1120 of the capacitor may also include an additional plate 1123 located between the sacrificial plate 1122 and the gate insulating film GI. The sacrificial plate 1122 contains a conductive material formed of the same semiconductor material contained in the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2.

[0232] The auxiliary plate 1123 may contain the same metal material as the metal material contained in each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2.

[0233] refer to Figure 11A and 11B The third plate 1130 can be any one of the first to third electrodes (E1, E2, and E3) or can be electrically connected to any one of the first to third electrodes (E1, E2, and E3). The second plate 1120 can be another one of the first to third electrodes (E1, E2, and E3) or can be electrically connected to another one of the first to third electrodes (E1, E2, and E3). The first plate 1110 can be another one of the first to third electrodes (E1, E2, and E3) or can be electrically connected to another one of the first to third electrodes (E1, E2, and E3).

[0234] For example, the third plate 1130 can be either the first electrode E1 or the second electrode E2, or it can be electrically connected to either the first electrode E1 or the second electrode. The second plate 1120 can be another form of the third electrode E3, or it can be electrically connected to another form of the third electrode E3. The first plate 1110 can be either the first electrode E1 or the second electrode, or it can be electrically connected to either the first electrode E1 or the second electrode. Here, the first electrode E1 or the second electrode can be the source node or the drain node of the transistor (e.g., the second node N2 driving the transistor DRT). The third electrode E3 can be the gate node of the transistor (e.g., the first node N1 driving the transistor DRT).

[0235] The first plate (810, 1110) may be an extension of the light-shielding member LS, or may include the metal (light-shielding member metal) included in the light-shielding member LS. The first plate (810, 1110) may be electrically connected to the light-shielding member LS or electrically connected to the first electrode E1 or the second electrode E2 of the second node N2 of the driving transistor DRT.

[0236] The second plate (820, 1120) may include the semiconductor material of the main active layer MCT. The second plate (820, 1120) may be electrically connected to the third electrode E3, which serves as the first node N1 of the driving transistor DRT.

[0237] The third plate (830, 1130) may include the metal (also referred to as gate metal) included in the first to third electrodes E1, E2 and E3. The third plate (830, 1130) may be electrically connected to the first electrode E1 or the second electrode E2 of the second node N2 of the driving transistor DRT.

[0238] A first capacitor may be formed between the first plates 810 and 1110 and the second plates 820 and 1120. A second capacitor may be formed between the second plates 820 and 1120 and the third plates 830 and 1130. According to the above electrical connection structure, the first capacitor and the second capacitor may be connected in parallel to form a storage capacitor Cst.

[0239] The embodiments of this disclosure described above will be briefly described below:

[0240] The display device 100 according to an embodiment may include: a substrate SUB; a main active layer MACT positioned on the substrate SUB and including a channel region CHA, a first conductive region CA1 positioned on a first side of the channel region CHA, and a second conductive region CA2 positioned on a second side of the channel region CHA opposite to the first side; a sacrificial active layer SACT positioned on the main active layer MACT; a gate insulating film GI positioned on the sacrificial active layer SACT; a first electrode E1 positioned on the sacrificial active layer SACT, a portion of the first electrode E1 overlapping the first conductive region CA1 of the main active layer MACT; a second electrode E2 positioned on the sacrificial active layer SACT, a portion of the second electrode E2 overlapping the second conductive region CA2 of the main active layer MACT; and a third electrode E3 positioned on the gate insulating film GI and overlapping the channel region CHA of the main active layer MACT.

[0241] In the display device 100 according to an embodiment, the thickness Hs of the sacrificial active layer SACT may be less than the thickness Hm of the main active layer MACT.

[0242] In the display device 100 according to an embodiment, the thickness Hs of the sacrificial active layer SACT may be non-uniform. Each of the thickness Hs1 of the portion of the sacrificial active layer SACT overlapping with the first electrode E1 and the thickness Hs2 of the portion of the sacrificial active layer SACT overlapping with the second electrode E2 may be greater than the thickness Hs3 of the portion of the sacrificial active layer SACT overlapping with the third electrode E3.

[0243] In the display device 100 according to the embodiment, the thickness (Hs1 or Hs2) of the thickest part of the sacrificial active layer SACT may be less than the thickness Hm of the main active layer MCT.

[0244] In the display device 100 according to an embodiment, the sacrificial active layer SACT may include: a first portion PART1 overlapping with the first electrode E1; a second portion PART2 overlapping with the second electrode E2; a third portion PART3 overlapping with the third electrode E3; and a fourth portion PART4 not overlapping with any of the first electrode E1, the second electrode E2, and the third electrode E3.

[0245] In the display device 100 according to an embodiment, in the sacrificial active layer SACT, the fourth part PART4 may include at least a portion formed by the conductive region CA, and a portion of the third part PART3 may include a non-conductive region.

[0246] In the display device 100 according to an embodiment, in the sacrificial active layer SACT, a portion of the first part PART1 adjacent to the fourth part PART4 may be conductive. A portion of the second part PART2 adjacent to the fourth part PART4 may be conductive. The two portions of the third part PART3 adjacent to the fourth part PART4 may be conductive.

[0247] The display device 100 according to an embodiment may further include: a first auxiliary electrode AUX1 located between the sacrificial active layer SACT and the first electrode E1; and a second auxiliary electrode AUX2 located between the sacrificial active layer SACT and the second electrode E2.

[0248] In the display device 100 according to an embodiment, each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 may contain metal.

[0249] In the display device 100 according to an embodiment, each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 may contain transparent conductive oxide (TCO).

[0250] In the display device 100 according to an embodiment, the main active layer MACT may include a first oxide semiconductor material. The sacrificial active layer SACT may include a second oxide semiconductor material different from the first oxide semiconductor material.

[0251] In the display device 100 according to an embodiment, the main active layer MCT may include a first oxide semiconductor material based on In. The sacrificial active layer SACT may include a second oxide semiconductor material based on Sn.

[0252] In the display device 100 according to an embodiment, the etch rate (i.e., the first etch rate) of the first oxide semiconductor material may be greater than the etch rate (i.e., the second etch rate) of the second oxide semiconductor material (first etch rate > second etch rate). That is, in the display device 100 according to an embodiment, the main active layer MACT may include a first oxide semiconductor material having a first etch rate. The sacrificial active layer SACT may include a second oxide semiconductor material having a second etch rate lower than the first etch rate.

[0253] The display device 100 according to an embodiment may further include a light-shielding member LS positioned on a substrate SUB and overlapping with the channel region CHA of the main active layer MCT, and a buffer layer BUF positioned on the light-shielding member LS and located below the main active layer MCT.

[0254] The display device 100 according to an embodiment may include transistors and capacitors disposed within a display area DA or a non-display area NDA.

[0255] In the display device 100 according to an embodiment, the transistor may include a main active layer MCT, a sacrificial active layer SACT, a first electrode E1, a second electrode E2, and a third electrode E3.

[0256] In the display device 100 according to an embodiment, the capacitor may include a first plate 810, a second plate 820, and a third plate 830. The first plate 810 may be positioned on a substrate SUB. A buffer layer BUF may be positioned between the first plate 810 and the second plate 820. A gate insulating film GI may be positioned between the second plate 820 and the third plate 830.

[0257] In the display device 100 according to an embodiment, the first plate 810 may be a light-shielding member LS or include the metal contained in the light-shielding member LS. The third plate 830 may include an electrode plate, which may be a third electrode E3, electrically connected to the third electrode E3, or contain the same metal as the third electrode E3. The second plate 820 may include a main plate 821 and a sacrificial plate 822. The main plate 821 includes a conductive material formed of the same semiconductor material contained in the main active layer MACT, and the sacrificial plate 822 includes a conductive material formed of the same semiconductor material contained in the sacrificial active layer SACT.

[0258] A display device 100 according to an embodiment may include: a substrate SUB; a main active layer MCT positioned on the substrate SUB and including a channel region CHA, a first conductive region CA1 positioned on a first side of the channel region CHA, and a second conductive region CA2 positioned on a second side of the channel region CHA opposite to the first side; a first sacrificial active layer SACT1 positioned on the first conductive region CA1 of the main active layer MCT; and a second sacrificial active layer SAC positioned on the second conductive region CA2 of the main active layer MCT. T2; a gate insulating film GI positioned on the channel region CHA of the main active layer MCT; a first electrode E1 positioned on the first sacrificial active layer SACT1, a portion of which overlaps with the first conductive region CA1 of the main active layer MCT; a second electrode E2 positioned on the second sacrificial active layer SACT2, a portion of which overlaps with the second conductive region CA2 of the main active layer MCT; and a third electrode E3 positioned on the gate insulating film GI and overlapping with the channel region CHA of the main active layer MCT.

[0259] In the display device 100 according to an embodiment, the thickness Hs of each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 may be less than the thickness Hm of the main active layer MCT.

[0260] In the display device 100 according to an embodiment, each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 may be conductive.

[0261] The display device 100 according to an embodiment may further include: a first auxiliary electrode AUX1 located between the first sacrificial active layer SACT1 and the first electrode E1; and a second auxiliary electrode AUX2 located between the second sacrificial active layer SACT2 and the second electrode E2.

[0262] In the display device 100 according to an embodiment, each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 may contain metal.

[0263] In the display device 100 according to an embodiment, each of the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 may comprise a transparent conductive oxide (TCO).

[0264] In the display device 100 according to an embodiment, each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 may comprise a first oxide semiconductor material. The main active layer MACT may comprise a second oxide semiconductor material different from the first oxide semiconductor material.

[0265] In the display device 100 according to an embodiment, each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 may include a first oxide semiconductor material based on In. The main active layer MACT may include a second oxide semiconductor material based on Sn.

[0266] In the display device 100 according to an embodiment, the etch rate (i.e., the first etch rate) of the first oxide semiconductor material may be greater than the etch rate (i.e., the second etch rate) of the second oxide semiconductor material (first etch rate > second etch rate). That is, in the display device 100 according to an embodiment, each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2 may include a first oxide semiconductor material having a first etch rate. The main active layer MACT may include a second oxide semiconductor material having a second etch rate lower than the first etch rate.

[0267] The display device 100 according to an embodiment may further include: a light-shielding member LS positioned on a substrate SUB and overlapping with the channel region CHA of the main active layer MCT; and a buffer layer BUF positioned on the light-shielding member LS and located below the main active layer MCT.

[0268] The display device 100 according to an embodiment may further include transistors and capacitors disposed in the display area DA or the non-display area NDA.

[0269] In the display device 100 according to the embodiment, the transistor may include a main active layer MACT, a first sacrificial active layer SACT1, a second sacrificial active layer SACT2, a first electrode E1, a second electrode E2, and a third electrode E3.

[0270] In the display device 100 according to an embodiment, the capacitor may include a first plate 1110, a second plate 1120, and a third plate 1130. The first plate 1110 may be positioned on a substrate SUB. A buffer layer BUF may be positioned between the first plate 1110 and the second plate 1120. A gate insulating film GI may be positioned between the second plate 1120 and the third plate 1130.

[0271] In the display device 100 according to an embodiment, the first plate 1110 may be a light-shielding member LS or include the metal contained in the light-shielding member LS. The third plate 1130 may include an electrode plate, which may be a third electrode E3, electrically connected to the third electrode E3, or contain the same metal as the third electrode E3. The second plate 1120 may include a main plate 1121 and a sacrificial plate 1122. The main plate 1121 includes a conductive material formed of the same semiconductor material contained in the main active layer MCT, and the sacrificial plate 1122 includes a conductive material formed of the same semiconductor material contained in each of the first sacrificial active layer SACT1 and the second sacrificial active layer SACT2.

[0272] According to the embodiment described above, the display device has a transistor structure capable of preventing damage to the active layer during panel manufacturing.

[0273] According to an embodiment, the display device has a capacitor structure corresponding to a transistor structure that can prevent damage to the active layer during panel manufacturing.

[0274] According to an embodiment, the display device has a transistor structure that prevents metal from damaging (or contaminating) the active layer even when metal is deposited on the active layer.

[0275] According to an embodiment, the display device includes transistors with high performance, high stability, and high reliability.

[0276] The foregoing description is provided to enable any person skilled in the art to make and use the technical concept of the invention, and is given in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The foregoing description and drawings provide examples of the technical concept of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of the invention. Therefore, the scope of the invention is not limited to the illustrated embodiments, but should be given the broadest scope consistent with the claims. The scope of protection of the invention should be interpreted based on the following claims, and all technical concepts within the scope of their equivalents should be interpreted as being included within the scope of the invention.

Claims

1. A display device, comprising: substrate; A main active layer is positioned on the substrate and includes a channel region, a first conductive region positioned on a first side of the channel region, and a second conductive region positioned on a second side of the channel region opposite to the first side. At least one sacrificial active layer is positioned on the primary active layer; A gate insulating film positioned on the channel region of the main active layer; A first electrode is positioned on the at least one sacrificial active layer, a portion of which overlaps with the first conductive region of the main active layer; A second electrode is positioned on the at least one sacrificial active layer, a portion of which overlaps with the second conductive region of the main active layer; A third electrode positioned on the gate insulating film and overlapping the channel region of the main active layer; as well as The thickness of each of the at least one sacrificial active layer is less than the thickness of the main active layer.

2. The display device according to claim 1, wherein, The at least one sacrificial active layer includes a sacrificial active layer, and the gate insulating film is disposed on the sacrificial active layer.

3. The display device according to claim 2, wherein, The thickness of the sacrificial active layer is non-uniform, and The thickness of the portion of the sacrificial active layer overlapping the first electrode and the thickness of the portion of the sacrificial active layer overlapping the second electrode are both greater than the thickness of the portion of the sacrificial active layer overlapping the third electrode.

4. The display device according to claim 3, wherein, The thickness of the thickest portion of the sacrificial active layer is less than the thickness of the main active layer.

5. The display device according to claim 2, wherein, The aforementioned sacrificial active layer includes: The first portion overlapping the first electrode; The second portion overlapping the second electrode; The third portion overlapping with the third electrode; and A fourth portion that does not overlap with any of the first electrode, the second electrode, and the third electrode; The fourth part includes a conductor portion, and a portion of the third part includes a non-conductor portion.

6. The display device according to claim 2, wherein, The primary active layer comprises a first semiconductor material, and the sacrificial active layer comprises a second semiconductor material that is different from the first semiconductor material.

7. The display device according to claim 1, wherein, The at least one sacrificial active layer includes a first sacrificial active layer positioned on the first conductive region of the main active layer, and a second sacrificial active layer positioned on the second conductive region of the main active layer, wherein the first electrode is positioned on the first sacrificial active layer, and the second electrode is positioned on the second sacrificial active layer.

8. The display device according to claim 7, wherein, Each of the first sacrificial active layer and the second sacrificial active layer is conductord.

9. The display device according to claim 7, wherein, Each of the first sacrificial active layer and the second sacrificial active layer includes a first semiconductor material, and the main active layer includes a second semiconductor material that is different from the first semiconductor material.

10. The display device according to claim 6 or 9, wherein, The first semiconductor material has a first etch rate, and the second semiconductor material has a second etch rate that is less than the first etch rate.

11. The display device according to claim 6 or 9, wherein, Compared to the second semiconductor material, the first semiconductor material is damaged by metals relatively more.

12. The display device according to claim 6 or 9, wherein, Compared to the second semiconductor material, the first semiconductor material is less damaged by wet etching.

13. The display device according to claim 6 or 9, wherein, The first semiconductor material is based on In, and the second semiconductor material is based on Sn.

14. The display device according to claim 1, wherein, The display device further includes: A first auxiliary electrode located between the at least one sacrificial active layer and the first electrode; and A second auxiliary electrode located between the at least one sacrificial active layer and the second electrode.

15. The display device according to claim 14, wherein, Each of the first auxiliary electrode and the second auxiliary electrode comprises a metal.

16. The display device according to claim 14, wherein, Each of the first auxiliary electrode and the second auxiliary electrode comprises a transparent conductive oxide.

17. The display device according to claim 1, wherein, The display device further includes: Transistors disposed within the display area or non-display area of ​​the display device. The transistor includes the main active layer, the at least one sacrificial active layer, the first electrode, the second electrode, and the third electrode.

18. The display device according to claim 17, wherein, The display device further includes: A light-shielding element positioned on the substrate and overlapping the channel region of the main active layer; A buffer layer positioned on the light-shielding member and located below the main active layer; A capacitor disposed in the display area or non-display area of ​​the display device; The capacitor includes a first plate, a second plate, and a third plate, and The buffer layer is positioned between the first plate and the second plate, and the gate insulating film is positioned between the second plate and the third plate.

19. The display device according to claim 18, wherein, The first plate is the light-shielding element or includes the metal contained in the light-shielding element. The third plate includes an electrode plate, which is the third electrode or contains the same metal as the third electrode. The second board includes a main board and a sacrificial board. The main board includes a conductor material formed of the same semiconductor material as the semiconductor material contained in the main active layer, and the sacrificial board includes a conductor material formed of the same semiconductor material as the semiconductor material contained in the at least one sacrificial active layer.

20. The display device according to claim 19, wherein, The third plate includes an additional plate located between the electrode plate and the gate insulating film; or the second plate includes an additional plate located between the sacrificial plate and the gate insulating film.

21. The display device according to claim 20, wherein, The additional plate contains a metallic material that is the same as the metallic material contained in each of the first auxiliary electrode located between the at least one sacrificial active layer and the first electrode and the second auxiliary electrode located between the at least one sacrificial active layer and the second electrode.

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