TN type display panel, manufacturing process thereof and display device

Abstract

The application discloses a TN type display panel, a manufacturing process thereof and a display device. The TN type display panel comprises a glass substrate, a first metal layer, a first insulating layer, a silicon island layer, a first transparent electrode layer, a second metal layer and a second transparent electrode layer. The source electrode layer is also overlapped on the first transparent electrode layer, and the second wire is overlapped on the first wire to be replaced through a via. The second transparent electrode layer is deposited on the source electrode layer, the drain electrode layer and the second wire. The first transparent electrode layer is directly overlapped with the source electrode layer, so that the resistance at the overlapping position is reduced, the current is increased, the charging capacity of the pixel is improved, the metal expansion area at the via position is saved, and the aperture ratio of the pixel is increased. In the peripheral circuit, the first wire to be replaced is directly overlapped with the second wire to realize the cross-wire layer replacement, and the problems of large resistance, uneven resistance, instability, corrosion, static electricity and the like of the ITO layer via are solved, and the reliability of the display panel is improved.

Description

Technical Field

[0001] This invention relates to the field of display panel technology, and in particular to a TN type display panel, its manufacturing process, and a display device thereof. Background Technology

[0002] In a traditional TN-type display panel product array glass substrate, the film layers formed on the glass substrate 101 are in the following order: a first metal layer (including but not limited to gate 102, common electrode 103, and bottom layer wiring 104 around the display area), a gate insulating layer 105, a silicon island layer 106, a second metal layer (including but not limited to source 107, drain 108, and upper layer wiring 109 around the display area), a pixel insulating layer 110, and a transparent electrode layer (including but not limited to pixel electrode layer 111 located within the pixel area and bridging electrode located around the display area). Figure 1-5 A total of 5 photomasks are needed for 5 pattern exposures, namely the first metal layer, silicon island layer 106, second metal layer, via, and pixel electrode layer 111. Figure 1 The diagram shows the film structure. The pixel electrode layer 111 is connected to the source electrode 107 of the second metal layer through the via 112 in the pixel area. After the TFT switch is turned on, the pixel electrode layer 111 is charged and discharged.

[0003] Among them, such as Figure 2 The overlapping portion of the pixel electrode layer 111 and the common electrode 103 of the first metal layer constitutes the storage capacitor of the pixel. According to the capacitance formula... ε is the dielectric constant of the medium between the common electrode 103 and the pixel electrode layer 111, S is the overlapping area of ​​the common electrode 103 and the pixel electrode layer 111, and d is the distance between the common electrode 103 and the pixel electrode layer 111, which is the film thickness of the gate insulating layer 105 plus the pixel insulating layer 110.

[0004] like Figure 3 The bottom layer trace 104 on the periphery of the display area is connected to the bridging electrode 115 located on the periphery through the first peripheral via 113, and the upper layer trace 109 on the periphery of the display area is also connected to the bridging electrode 115 through the second peripheral via 114, thereby realizing the conduction between the bottom layer trace 104 and the upper layer trace 109 of different layers. Figure 4 In the first peripheral via 113, the gate insulating layer 105 and the pixel insulating layer 110 were dry-etched away. In the second peripheral via 114, the pixel insulating layer 110 was also dry-etched away. After the pixel insulating layer 110 was etched, during the etching of the gate insulating layer 105 at the first peripheral via 113, although the reaction rate between the dry etching gas and the metal was slow, a portion of the top Mo layer of the second metal layer at the location of the second peripheral via 114 was still etched away. In some cases, the top Mo layer was even etched away, leading to oxidation and corrosion of the Al layer. Figure 5 A cross-sectional view of the overlap between the bridging electrode 115 and the bottom trace 104 in the actual product shows that the gate insulating layer 105 is etched away, the ITO film of the pixel electrode layer 111 is not uniform, and the sheet resistance of the pixel electrode layer 111 is several hundred times that of the first metal layer / second metal layer. Therefore, the design of the transparent electrode layer overlapping with the first metal layer / second metal layer through vias (i.e., via 112 in the pixel area, the first peripheral via 113, and the second peripheral via 114) will cause the via to become a large resistor. For the design of the periphery of the display area, the use of ITO combined with vias for some trace layer changes will cause differences in resistance between traces; if vias are used for uniformity, the resistance of each trace will increase.

[0005] In addition, due to the thinness of the transparent electrode layer and the uneven film thickness at the via locations, the peripheral vias near the edge of the display panel are prone to corrosion due to moisture intrusion and other reasons; moreover, the overlapping positions of the peripheral vias are also prone to electrostatic discharge damage. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention proposes a TN-type display panel, its manufacturing process, and a display device thereof.

[0007] The technical solution to achieve the above-mentioned objective is as follows:

[0008] In a first aspect, a TN-type display panel includes: a glass substrate, a first metal layer, a first insulating layer, a silicon island layer, a first transparent electrode layer, a second metal layer, and a second transparent electrode layer.

[0009] The first metal layer is deposited on the glass substrate, and the first metal layer includes a gate, a common electrode located in the pixel area, and a first trace located on the periphery of the display area;

[0010] The first insulating layer is deposited on the glass substrate and the first metal layer;

[0011] The silicon island layer is deposited on the first insulating layer corresponding to the gate;

[0012] The first transparent electrode layer is deposited on the first insulating layer located in the pixel area, and overlaps with the common electrode.

[0013] The second metal layer is deposited on the first insulating layer, the silicon island layer, and the first transparent electrode layer. The second metal layer includes a source layer, a drain layer, and a second trace located on the periphery of the display area. The source layer and the drain layer are respectively connected to both sides of the silicon island layer. The source layer is also connected to the first transparent electrode layer. The second trace is connected to the first trace of the layer to be replaced through a via.

[0014] The second transparent electrode layer is deposited on the source layer, the drain layer, and the second trace.

[0015] In conjunction with the TN-type display panel described in the first aspect of the present invention, in a first possible embodiment, the TN-type display panel further includes: a second insulating layer;

[0016] The second insulating layer is located above the second transparent electrode and is disposed corresponding to the silicon island layer.

[0017] In conjunction with the TN-type display panel described in the first aspect of the present invention, in a second possible embodiment, the TN-type display panel further includes: a second insulating layer;

[0018] The second insulating layer is located below the second transparent electrode and is disposed corresponding to the silicon island layer.

[0019] In conjunction with the second possible implementation of the first aspect of the present invention, in the third possible implementation, the second transparent electrode layer and the second metal layer are etched using the same mask; the second insulating layer and the silicon island layer are etched using the same mask.

[0020] Secondly, a TN-type display panel manufacturing process is provided for manufacturing the TN-type display panel described in the first aspect. Specifically, the TN-type display panel manufacturing process includes the following steps:

[0021] A first metal layer is deposited on a glass substrate, and the first metal layer is divided into a gate, a common electrode located in the pixel area, and a first trace located outside the display area by a first patterning process.

[0022] A first insulating layer is deposited on the first metal layer and the glass substrate;

[0023] A silicon island layer is deposited on the first insulating layer, and a silicon island layer located above the gate is obtained by a second patterning process;

[0024] A via is obtained by drilling holes in the first insulating layer through a third patterning process, and the via is located on the first trace of the layer to be replaced.

[0025] A transparent electrode layer is deposited over the first insulating layer and the silicon island layer, and a first transparent electrode layer located in the pixel area is obtained by a fourth patterning process. The first transparent electrode layer has an overlapping area with the common electrode.

[0026] A second metal layer is deposited on the first insulating layer, the silicon island layer, and the first transparent electrode layer. The second metal layer is divided into a source layer, a drain layer, and a second trace located on the periphery of the display area through a fifth patterning process. The source layer and the drain layer are respectively connected to both sides of the silicon island layer. The source layer is also connected to the first transparent electrode layer. The second trace is connected to the first trace of the layer to be replaced through the via.

[0027] A transparent electrode layer is deposited on the first insulating layer, silicon island layer, first transparent electrode layer, and second metal layer, and a second transparent electrode layer is obtained above the source layer, drain layer, and second trace through a sixth patterning process.

[0028] In conjunction with the TN-type display panel manufacturing process described in the second aspect of the present invention, in a first possible embodiment, the manufacturing process further includes:

[0029] An insulating layer is deposited on the first insulating layer, the silicon island layer, the first transparent electrode layer, and the second transparent electrode layer, and a second insulating layer located above the silicon island layer is obtained through a seventh patterning process.

[0030] In conjunction with the TN-type display panel manufacturing process described in the second aspect of the present invention, in a second possible embodiment, the following steps are further included before obtaining the second transparent electrode layer: depositing an insulating layer on the first insulating layer, the silicon island layer, the first transparent electrode layer, and the second metal layer, and obtaining the second insulating layer located above the silicon island layer through a seventh patterning process.

[0031] In conjunction with the TN-type display panel manufacturing process described in the second aspect of the present invention, in a third possible embodiment, the fifth patterning process and the sixth patterning process use the same mask, and the exposure amount of the sixth patterning process is less than that of the fifth patterning process.

[0032] In conjunction with the TN-type display panel manufacturing process described in the second aspect of the present invention, in a fourth possible embodiment, the second patterning process and the seventh patterning process use the same mask, and the exposure amount of the seventh patterning process is less than that of the second patterning process.

[0033] Thirdly, a display device comprising the display panel described in the first aspect or a display panel manufactured using the process described in the second aspect.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] By directly connecting the first transparent electrode layer, which serves as the pixel electrode, to the source electrode, the existing method of connecting the pixel electrode layer with vias within the pixel region is eliminated. This not only reduces the resistance at the connection point between the first transparent electrode layer and the source electrode, thus increasing the current and improving the pixel's charging capability, but also eliminates the need for metal expansion at the vias, increasing the pixel's aperture ratio and improving pixel transmittance. Furthermore, since there is only one insulating layer between the first transparent electrode layer and the common electrode, compared to the two insulating layers (gate insulating layer and pixel insulating layer) in traditional TN pixel designs, the storage capacitance of the pixel in this invention is approximately twice that of the conventional solution. Therefore, there is still room to reduce the width of the common electrode to reduce the storage capacitance, thereby also increasing the pixel aperture ratio.

[0036] In the peripheral circuit, the first trace to be replaced is directly connected to the second trace to achieve cross-line replacement without the need for additional transparent electrode bridging. In this way, there are no ITO layer vias in the traces and circuit design around the display area, which solves the problems of high resistance, uneven resistance, instability, corrosion and easy static electricity generation of ITO layer vias, and improves the reliability of the display panel.

[0037] The manufacturing process of this invention uses 5 photomasks and performs 6 or 7 exposures without increasing the cost of photomask molds. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of pixel planar design in the prior art;

[0040] Figure 2 for Figure 1 A cross-sectional view at line A in the middle;

[0041] Figure 3 This is a schematic diagram of the structure for changing the outer layer of the display area in the prior art;

[0042] Figure 4 for Figure 3 A cross-sectional view at line B in the middle section;

[0043] Figure 5 This is a schematic diagram showing the overlap position of the bridging electrode and the underlying trace in an actual product in the prior art.

[0044] Figure 6 This is a schematic diagram of the pixel structure of Embodiment 1 of the TN-type display panel in this invention;

[0045] Figure 7 for Figure 6 A cross-sectional view at line C in the middle;

[0046] Figure 8 This is a cross-sectional view at line C of Embodiment 2 of the TN-type display panel in this invention;

[0047] Figure 9 This is a schematic diagram of the peripheral wiring vias in Embodiment 1 of the TN-type display panel of the present invention;

[0048] Figure 10 for Figure 9 A cross-sectional view at line D. Detailed Implementation

[0049] The technical solutions of this invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are all within the scope of protection of this invention.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0051] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0052] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0053] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0054] Example 1

[0055] like Figure 6 , 7 As shown in Figures 9 and 10, a schematic diagram of Embodiment 1 of the TN-type display panel of the present invention is illustrated.

[0056] A TN-type display panel includes a glass substrate 201 and a first metal layer, a first insulating layer 205, a silicon island layer 206, a first transparent electrode layer 207, a second metal layer, a second transparent electrode layer 211, and a second insulating layer 212 disposed on the glass substrate 201.

[0057] A first metal layer is deposited on a glass substrate 201. The first metal layer includes a gate 202, a common electrode 203, and a first trace 204. The common electrode 203 is located in the pixel area and partially overlaps with the subsequently formed first transparent electrode layer 207. The first trace 204 is located outside the display area and serves as a lead to lead the gate 202 or the drain layer 209 to a driver IC or GIP circuit to realize the on / off control of the TFT switch.

[0058] The first insulating layer 205 is deposited on the glass substrate 201 and the first metal layer to protect the first metal layer and provide mutual insulation between the upper and lower conductive layers.

[0059] The silicon island layer 206 is deposited on the first insulating layer 205 corresponding to the gate 202, and the silicon island layer 206 serves as the semiconductor layer of the TFT switch.

[0060] The first transparent electrode layer 207 is deposited on the first insulating layer 205 located in the pixel area and has an overlapping area with the common electrode 203. The first transparent electrode layer 207 serves as the pixel electrode.

[0061] The second metal layer is deposited on the first insulating layer 205, the silicon island layer 206, and the first transparent electrode layer 207. The second metal layer includes a source layer 208, a drain layer 209, and a second trace 210.

[0062] The source layer 208 and drain layer 209 are respectively bonded to both sides of the silicon island layer 206 to form a TFT switch. The source layer 208 is also bonded to the first transparent electrode layer 207 so that a voltage can be applied to the first transparent electrode layer 207, which serves as the pixel electrode, to deflect the liquid crystal. By directly bonding the first transparent electrode layer 207, which serves as the pixel electrode, to the source, the existing method of bonding the pixel electrode layer with vias in the pixel area is eliminated. This not only reduces the resistance at the bonding point between the first transparent electrode layer 207 and the source, thus increasing the current and improving the pixel's charging capability, but also eliminates the need for metal expansion at the vias, increasing the pixel's aperture ratio and improving pixel transmittance. Moreover, there is only one insulating layer between the first transparent electrode layer 207 and the common electrode 203. Compared with the two insulating layers (gate insulating layer and pixel insulating layer) of the traditional TN pixel design, the storage capacitance of the pixel of the present invention is about twice that of the traditional solution. Therefore, there is still room to reduce the width of the common electrode 203 to reduce the storage capacitance, thereby increasing the pixel aperture ratio.

[0063] The second trace 210 is located on the periphery of the display area and also serves as a lead to bring the gate 202 or drain layer 209 to the driver IC or GIP circuit to realize the on / off control of the TFT switch. Furthermore, when the trace needs to be replaced, the second trace 210 is connected to the first trace 204 to be replaced through the via 213.

[0064] The trace to be replaced is a layer change for the peripheral trace. The location where a crossover is needed also requires a layer change, which necessitates the use of vias 213 for bridging. For example, if two first traces 204 of the same driver IC signal need to be crossed, the second trace 210 can be directly connected to the two first traces 204 via via 213 to achieve the layer change. Alternatively, the trace to be replaced could refer to replacing the first trace 204 connected to the gate 202 with the second trace 210 via via 213 and then connecting it to the IC signal, or it could refer to replacing the second trace 210 connected to the drain layer 209 with the first trace 204 via via 213 and then connecting it to the IC signal. In practice, the location of the vias 213 and the layer-change connection relationship can be specifically designed according to the needs of the peripheral circuit. In the peripheral circuit, the first trace 204 to be replaced is directly connected to the second trace 210 to achieve cross-line replacement without the need for additional transparent electrode bridging. In this way, there are no ITO layer vias in the traces and circuit design around the display area, which solves the problems of high resistance, uneven resistance, instability, corrosion and easy static electricity generation of ITO layer vias, and improves the reliability of the display panel.

[0065] The second transparent electrode layer 211 is deposited on the source layer 208, drain layer 209, and second trace 210. The second transparent electrode layer 211 and the second metal layer are etched using the same mask, eliminating the need for additional mask molds and reducing costs. When etching the second transparent electrode layer 211, a smaller exposure is used compared to patterned etching of the second metal layer, ensuring that the second transparent electrode layer 211 completely covers the source layer 208, drain layer 209, and second trace 210 of the second metal layer, preventing oxidation and corrosion of the Al layer of the second metal layer. Besides protecting the second metal layer, locations on the display panel that need external conductivity (such as driver IC bonding locations) are in direct contact with the second transparent electrode layer 211, thus connecting to the second trace 210. There is no contact between external conductors and vias, preventing damage to vias during bonding. Furthermore, this mitigates via reliability risks.

[0066] The second insulating layer 212 is located above the second transparent electrode and is disposed corresponding to the silicon island layer 206. The second insulating layer 212 and the silicon island layer 206 are etched using the same mask. In this embodiment, when etching the second insulating layer 212, a smaller exposure is used compared to etching the silicon island layer 206, so that the second insulating layer 212 completely covers the silicon island layer 206, preventing the silicon island layer 206 from being affected by dust, moisture, ions, etc., which could cause instability in the TFT characteristics.

[0067] Example 2

[0068] like Figure 7 , Figure 7 This is a schematic diagram of Embodiment 2 of the TN-type display panel of the present invention. Unlike Embodiment 1, in this embodiment, the second transparent electrode layer 211 is deposited on the outside of the second insulating layer 212, that is, the second insulating layer 212 is formed first and then the second transparent electrode is formed.

[0069] Example 3

[0070] A manufacturing process for a TN-type display panel is provided for manufacturing the TN-type display panel of Example 1. Specifically, the manufacturing process includes the following steps:

[0071] A first metal layer is deposited on a glass substrate 201, and the first metal layer is divided into a gate 202, a common electrode 203 located in the pixel area, and a first trace 204 located on the periphery of the display area through a first patterning process.

[0072] A first insulating layer 205 is deposited on the first metal layer and the glass substrate 201;

[0073] A silicon island layer is deposited on the first insulating layer 205, and a silicon island layer 206 located above the gate 202 is obtained through a second patterning process.

[0074] A via 213 is obtained by drilling holes in the first insulating layer 205 through a third patterning process. The via 213 is located on the first trace 204 of the layer to be replaced.

[0075] A transparent electrode layer is deposited over the first insulating layer 205 and the silicon island layer 206. A first transparent electrode layer 207 located in the pixel area is obtained by a fourth patterning process. The first transparent electrode layer 207 has an overlapping area with the common electrode 203.

[0076] A second metal layer is deposited on the first insulating layer 205, the silicon island layer 206, and the first transparent electrode layer 207. The second metal layer is divided into a source layer 208, a drain layer 209, and a second trace 210 located on the periphery of the display area through a fifth patterning process. The source layer 208 and the drain layer 209 are respectively connected to both sides of the silicon island layer 206. The source layer 208 is also connected to the first transparent electrode layer 207. The second trace 210 is connected to the first trace 204 of the layer to be replaced through a via 213.

[0077] A transparent electrode layer is deposited on the first insulating layer 205, the silicon island layer 206, the first transparent electrode layer 207, and the second metal layer. A second transparent electrode layer 211 is obtained by a sixth patterning process, located above the source layer 208, the drain layer 209, and the second trace 210. The second transparent electrode layer 211 and the second metal layer are etched using the same mask, that is, the fifth and sixth patterning processes use the same mask. Moreover, the exposure amount of the sixth patterning process is less than that of the fifth patterning process. Due to the use of a smaller exposure amount, the second transparent electrode layer 211 completely covers the source layer 208, the drain layer 209, and the second trace 210 of the second metal layer, preventing the Al layer of the second metal layer from being oxidized and corroded.

[0078] Preferably, the manufacturing process of this embodiment further includes the following steps:

[0079] An insulating layer is deposited on the first insulating layer 205, the silicon island layer 206, the first transparent electrode layer 207, and the second transparent electrode layer 211. A second insulating layer 212 is then obtained above the silicon island layer 206 through a seventh patterning process. The second insulating layer 212 and the silicon island layer 206 are etched using the same mask.

[0080] In this embodiment, the second patterning process and the seventh patterning process use the same mask, and the exposure amount of the seventh patterning process is less than that of the second patterning process. In the seventh patterning process of this embodiment, when etching the second insulating layer 212, a smaller exposure amount is used compared to the second patterning process, so that the second insulating layer 212 completely covers the silicon island layer 206, preventing the silicon island layer 206 from being affected by dust, moisture, ions, etc., which could cause instability in the TFT characteristics.

[0081] The manufacturing process of this invention uses five photomasks and performs six or seven exposures, eliminating the need for additional photomask mold costs. Furthermore, by directly connecting the first transparent electrode layer 207, which serves as the pixel electrode, to the source electrode, the existing method of connecting the pixel electrode layer with vias within the pixel region is eliminated. This not only reduces the resistance at the connection point between the first transparent electrode layer 207 and the source electrode, thus increasing the current and improving the pixel's charging capability, but also eliminates the need for metal expansion at the vias, increasing the pixel's aperture ratio and improving pixel transmittance. Moreover, there is only one insulating layer between the first transparent electrode layer 207 and the common electrode 203. Compared to the two insulating layers (first insulating layer 205 and second insulating layer 212) in traditional TN pixel designs, the storage capacitance of the pixel in this invention is approximately twice that of the conventional solution. Therefore, there is still room to reduce the width of the common electrode 203 to reduce the storage capacitance, thereby also increasing the pixel aperture ratio. In the peripheral circuit, the first trace 204 to be replaced is directly connected to the second trace 210 to achieve cross-line replacement without the need for additional transparent electrode bridging. In this way, there are no ITO layer vias in the traces and circuit design around the display area, which solves the problems of high resistance, uneven resistance, instability, corrosion and easy static electricity generation of ITO layer vias, and improves the reliability of the display panel.

[0082] Example 4

[0083] Unlike Embodiment 3, in this embodiment, before obtaining the second transparent electrode layer 211, the following steps are included: depositing an insulating layer on the first insulating layer 205, silicon island layer 206, first transparent electrode layer 207, and second metal layer, and obtaining the second insulating layer 212 located above the silicon island layer 206 through a seventh patterning process.

[0084] Example 5

[0085] A display device comprising a display panel of embodiment 1 or 2 or a display panel manufactured using a process as described in embodiment 3 or 4.

[0086] Therefore, the display device possesses all the features and beneficial effects of the front display panel, which will not be elaborated further here.

[0087] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A TN-type display panel, characterized in that, include: A glass substrate, a first metal layer, a first insulating layer, a silicon island layer, a first transparent electrode layer, a second metal layer, and a second transparent electrode layer; The first metal layer is deposited on the glass substrate, and the first metal layer includes a gate, a common electrode located in the pixel area, and a first trace located on the periphery of the display area; The first insulating layer is deposited on the glass substrate and the first metal layer; The silicon island layer is deposited on the first insulating layer corresponding to the gate; The first transparent electrode layer is deposited on the first insulating layer located in the pixel area, and overlaps with the common electrode. The second metal layer is deposited on the first insulating layer, the silicon island layer, and the first transparent electrode layer. The second metal layer includes a source layer, a drain layer, and a second trace located on the periphery of the display area. The source layer and the drain layer are respectively connected to both sides of the silicon island layer. The source layer is also connected to the first transparent electrode layer. The second trace is directly connected to the first trace of the layer to be replaced through a via, and the connection does not pass through the transparent electrode layer for bridging. The second transparent electrode layer is deposited on the source layer, the drain layer, and the second trace.

2. The TN type display panel according to claim 1, characterized in that, The TN-type display panel further includes: a second insulating layer; The second insulating layer is located above the second transparent electrode and is disposed corresponding to the silicon island layer.

3. The TN type display panel according to claim 1, characterized in that, The TN-type display panel further includes: a second insulating layer; The second insulating layer is located below the second transparent electrode and is disposed corresponding to the silicon island layer.

4. A manufacturing process for a TN-type display panel, characterized in that, The manufacturing process is used to manufacture a TN-type display panel as described in any one of claims 1-3; the manufacturing process includes the following steps: A first metal layer is deposited on a glass substrate, and the first metal layer is divided into a gate, a common electrode located in the pixel area, and a first trace located outside the display area by a first patterning process. A first insulating layer is deposited on the first metal layer and the glass substrate; A silicon island layer is deposited on the first insulating layer, and a silicon island layer located above the gate is obtained by a second patterning process; A via is obtained by drilling holes in the first insulating layer through a third patterning process, and the via is located on the first trace of the layer to be replaced. A transparent electrode layer is deposited over the first insulating layer and the silicon island layer, and a first transparent electrode layer located in the pixel area is obtained by a fourth patterning process. The first transparent electrode layer has an overlapping area with the common electrode. A second metal layer is deposited on the first insulating layer, the silicon island layer, and the first transparent electrode layer. The second metal layer is divided into a source layer, a drain layer, and a second trace located on the periphery of the display area through a fifth patterning process. The source layer and the drain layer are respectively connected to both sides of the silicon island layer. The source layer is also connected to the first transparent electrode layer. The second trace is directly connected to the first trace of the layer to be replaced through the via, and the connection does not pass through the transparent electrode layer for bridging. A transparent electrode layer is deposited on the first insulating layer, silicon island layer, first transparent electrode layer, and second metal layer, and a second transparent electrode layer located above the source layer, drain layer, and second trace is obtained through a sixth patterning process. The fifth and sixth patterning processes use the same mask, and the exposure amount of the sixth patterning process is less than that of the fifth patterning process.

5. The TN-type display panel manufacturing process according to claim 4, characterized in that, The manufacturing process also includes: An insulating layer is deposited on the first insulating layer, the silicon island layer, the first transparent electrode layer, and the second transparent electrode layer, and a second insulating layer located above the silicon island layer is obtained through a seventh patterning process; The second patterning process and the seventh patterning process use the same mask, and the exposure amount of the seventh patterning process is less than that of the second patterning process.

6. The TN-type display panel manufacturing process according to claim 4, characterized in that, Before obtaining the second transparent electrode layer, the following steps are also included: depositing an insulating layer on the first insulating layer, the silicon island layer, the first transparent electrode layer, and the second metal layer, and obtaining the second insulating layer located above the silicon island layer through a seventh patterning process; The second patterning process and the seventh patterning process use the same mask, and the exposure amount of the seventh patterning process is less than that of the second patterning process.

7. The TN-type display panel manufacturing process according to claim 5 or 6, characterized in that, The fifth and sixth patterning processes use the same mask, and the exposure of the sixth patterning process is less than that of the fifth patterning process.

8. The TN-type display panel manufacturing process according to claim 5 or 6, characterized in that, The second patterning process and the seventh patterning process use the same mask, and the exposure amount of the seventh patterning process is less than that of the second patterning process.

9. A display device, characterized in that, This includes the display panel as described in any one of claims 1-3 or the display panel manufactured using the manufacturing process described in any one of claims 4-8.

Images