A high-voltage LDMOS device structure resistant to single event radiation

Abstract

The application belongs to the technical field of semiconductor power devices, and particularly relates to a high-voltage LDMOS device structure resistant to single-particle irradiation. The device comprises a P-type substrate, a P-type buried layer, an N-type drift region, a P-type well region, a local buried oxide layer, a source region P+ implantation, a source region N+ implantation, a gate oxide layer, a source region Ptop implantation, a local field oxide layer, a drain N+ implantation, an N-type buffer layer and polycrystalline silicon. The structure provided by the application introduces the N-type buffer layer and the local buried oxide layer without changing the inherent size. The N-type buffer layer changes the internal electric field distribution of the device, reestablishes the position of the peak electric field, the local buried oxide layer reestablishes the paths of the electron current and the hole current, reduces the risk of the parasitic bipolar transistor (BJT), and improves the ability to resist single-particle transient effects.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a high-voltage LDMOS device structure resistant to single-event irradiation. Background Technology

[0002] With the widespread use of spacecraft in both military and civilian aerospace industries, an increasing number of electronic components are being applied to the space environment, such as spaceborne BeiDou systems, satellite communication systems, and remote sensing systems. When spacecraft operate in outer space, radiation particles in the radiation environment have adverse radiation effects on the electronic components on the spacecraft, thus placing higher demands on the reliability of the spacecraft.

[0003] When LDMOS devices are used in switching power supplies, LDOs, and charging circuits in spacecraft, they are inevitably affected by disturbance radiation. Space contains a large number of charged particles and cosmic rays. When high-energy particle beams bombard devices, high-density non-equilibrium electron-hole pairs are generated along heavy ion orbits and drift under the influence of strong electric fields. Once a parasitic bipolar transistor is turned on, its positive feedback will lead to large current and low voltage. If transient currents propagate through the combinational logic of digital circuits and are latched into memory elements, single-event currents may cause single-event disturbances.

[0004] Single-event effects can be categorized into recoverable and unrecoverable. Recoverable effects include single-event upsets, single-event transients, and single-event interrupts, which typically occur in CMOS devices. These soft errors are insufficient to damage the device and can be corrected using current-limiting resistors, power-end resets, etc. Unrecoverable effects refer to physical damage or permanent functional damage caused by a single event. Examples include single-event latch-up, single-event burn-out, and single-event gate breakdown, which are two unrecoverable effects occurring in power MOSFETs.

[0005] like Figure 1 The diagram shows a cross-sectional view of a conventional LDMOS device. It includes: a P-type substrate 1 at the bottom; an N-type buffer layer 2 to the upper right of the P-type substrate 1; a P-type buried layer 3 to the upper left of the P-type substrate 1; an N-type drift region 4 to the right of the P-type buried layer 3; a P-type well region 5 to the upper left of the P-type buried layer 3; a local buried oxide layer 6 to the upper right of the P-type buried layer 3; a source region P+ implantation 7 to the upper left of the P-type well region 5; a source region N+ implantation 8 to the right of the source region P+ implantation 7; a gate oxide layer 9 to the upper right of the P-type well region 5; a source region Ptop implantation 10 above the local buried oxide layer 6; a local field oxide layer 11 above the Ptop implantation 10; a drain N+ implantation 12 to the upper right of the local buried oxide layer 6; and polysilicon 13 above the gate oxide layer 9.

[0006] like Figure 2The diagram illustrates a single-particle collision (SPCC) inside a device. When a particle enters the device, due to the presence of the drain and substrate voltages, the electron-hole pairs on the particle's incident trajectory undergo diffusion and drift motion under the influence of the electric field generated by these voltages, eventually converging at the drain to form a large transient current. It is noteworthy that single-particle transient pulses can propagate from the output of the previous stage to the input of the next stage in the driving circuit, generating so-called "glitches." When the pulse width of this "glitch" is sufficiently wide, it can cause abnormal circuit function.

[0007] like Figure 3 The diagram illustrates single-event burnout. When the device is off, a particle enters the device from the drain, generating numerous electron-hole pairs within its trajectory. According to the "funnel effect" theory, initially, electrons move towards higher potential electrodes, while holes move towards lower potential electrodes, forming a funnel. Over time, the electron-hole pairs diffuse to both sides of the particle trajectory under the influence of the drain voltage. Current flows towards the P-well region, creating a potential between the P-well and the N+ source. When this potential is sufficiently high, the P-well / N+ source PN junction is forward biased. Simultaneously, due to the high drain potential, the NPN parasitic transistor formed by the N-drift region, P-well, and N+ source is in an amplified state. Ultimately, as the drain current increases, the LDMOS device burns out. Another possible explanation is that electron-hole pairs on the particle trajectory collide and ionize in the depletion region, causing avalanche breakdown. Ultimately, excessive current flows through the device, leading to thermal burnout.

[0008] like Figure 4 The diagram shows a cross-sectional view of a full SOI (FSOI) LDMOS device. It includes: a P-type substrate 1 at the bottom; a deep N-type well region 2 located to the upper right of the P-type substrate 1; a P-type buried layer 3 located to the upper left of the P-type substrate 1; an N-type drift region 4 located to the right of the P-type buried layer 3; a P-type well region 5 located to the upper left of the P-type buried layer 3; the entire buried oxide layer 6 located to the upper right of the P-type buried layer 3; a source region P+ implantation 7 located to the upper left of the P-type well region 5; a source region N+ implantation 8 located to the right of the source region P+ implantation 7; a gate oxide layer 9 located to the upper right of the P-type well region 5; a source region Ptop implantation 10 located above the partially buried oxide layer 6; a local field oxide layer 11 located above the Ptop implantation 10; a drain N+ implantation 12 located to the upper right of the locally buried oxide layer 6; and polysilicon 13 located above the gate oxide layer 9. Compared to traditional devices, SOI devices offer advantages such as stronger radiation resistance, faster operating speed, better insulation, higher integration density, and no SCR parasitic effects. However, SOI LDMOS transistors used for radiation protection are typically based on all-SOI technology, and their breakdown voltage is limited by the thickness of the buried oxide layer and the silicon film. Therefore, reducing the impact of transient response time on LDMOS transistors and circuits is extremely critical.

[0009] like Figure 5 The diagram shows a comparison of drain-source currents in a conventional LDMOS device at VDS of 196V and 197V. When the drain bias voltage (VDS) is 196V or lower, conventional LDMOS devices do not trigger single-event burn-out (SEB), which can be considered a safe operating area (SOA). When VDS reaches 197V, SEB occurs for the first time on the D orbital of heavy ions, while the other three orbitals remain safe. Therefore, the minimum VDS to trigger burn-out is 197V, which corresponds to the SEB trigger voltage (VSEB) of conventional LDMOS at a LET of 0.2pC / μm and a range of 30μm for heavy ion events. During SEB, although the hole current at the source is greater than the electron current for a few nanoseconds after the heavy ion event, the electron current quickly exceeds the hole current due to the opening of the parasitic NPN. Burn-out eventually occurs when the electron current is several orders of magnitude larger than the hole current. Summary of the Invention

[0010] The purpose of this invention is to address the problem that after single-event irradiation, high-density non-equilibrium electron-hole pairs are generated in the heavy ion orbitals, resulting in violent collisional ionization, avalanche breakdown at the drain, and activation of parasitic NPN bipolar transistors (BJTs) at the source. This invention proposes a feasible high-voltage LDMOS structure with variable current distribution that is resistant to single-event irradiation. This new structure has a high resistance to single-event transient effects under a higher single-event burn-out trigger voltage.

[0011] The technical solution of this invention is:

[0012] A high-voltage LDMOS device structure resistant to single-particle irradiation is characterized by comprising a P-type substrate 1, an N-type buffer layer 2, an N-type drift region 4, and a P-type buried layer 3 located on the upper surface of the P-type substrate 1, wherein the N-type drift region 4 is located between the N-type buffer layer 2 and the P-type buried layer 3; the upper surface of the P-type buried layer 3 has a P-type well region 5, the side of the P-type well region 5 is in contact with the N-type drift region 4, and at the end of the upper layer of the P-type well region 5 away from the N-type buffer layer 2, there are a source region P+ implantation 7 and a source region N+ implantation 8 arranged in parallel, wherein the source region P+ implantation 7 is located at the end away from the N-type buffer layer 2; the upper layer of the N-type buffer layer 2 has a drain N+ implantation 12 at the end away from the P-type well region 5; the N-type drift region 4 has a local buried oxide layer 6, and one end of the local buried oxide layer 6 has a gap with the N-type buffer layer 2. The other end extends into the P-type well region 5 and the end face is located below the source region N+ implantation 8; a gate oxide layer 9 is provided on the upper surface of the P-type well region 5 between the source region N+ implantation 8 and the N-type drift region 4, and the two ends of the gate oxide layer 9 extend to the upper surface of part of the source region N+ implantation 8 and the upper surface of the N-type drift region 4, respectively; a local field oxide layer 11 is provided on the upper surface of the N-type drift region 4 and the upper surface of the N-type buffer layer 2 between the gate oxide layer 9 and the drain N+ implantation 12, and the upper surface of the gate oxide layer 9 is provided with polysilicon 13, and the polysilicon 13 extends to the upper surface of part of the local field oxide layer 11; at the bottom of the local field oxide layer 11, there is a source region Ptop implantation 10, the source region Ptop implantation 10 is discontinuously distributed, and there is a gap between the bottom of the source region Ptop implantation 10 and the top of the local buried oxide layer 6.

[0013] Furthermore, the material of the local field oxide layer 11 is silicon dioxide or a low-K material with K≤2.8.

[0014] The beneficial effects of this invention are as follows: Figure 6 As shown, the structure proposed in this invention introduces an N-type buffer layer and a locally buried oxide layer without changing the inherent dimensions. SEB It can reach 396V, which is about 200V higher than conventional LDMOS and about 90V higher than LDMOS with only a buffer layer. Meanwhile, V th Unaffected, both remain at 1.75V, improving resistance to single-event transient effects. Attached Figure Description

[0015] Figure 1 This is a cross-sectional view of a conventional LDMOS device;

[0016] Figure 2 A schematic diagram of a single particle implantation device.

[0017] Figure 3 This is a schematic diagram of single-particle burn-off.

[0018] Figure 4This is a cross-sectional view of an all-SOI LDMOS device;

[0019] Figure 5 A comparison of drain-source currents of traditional LDMOS devices at VDS of 196V and 197V;

[0020] Figure 6 Comparison of optimal single-particle-hardened LDMOS drain-source currents;

[0021] Figure 7 This is a cross-sectional view of the high-voltage LDMOS device resistant to single-particle irradiation that can change the current distribution according to the present invention.

[0022] Wherein, 1 is a P-type substrate, 2 is an N-type buffer layer, 3 is a P-type buried layer, 4 is an N-type drift region, 5 is a P-type well region, 6 is a local buried oxide layer, 7 is a source region P+ implantation, 8 is a source region N+ implantation, 9 is a gate oxide layer, 10 is a source region Ptop implantation, 11 is a local field oxide layer, 12 is a drain N+ implantation, and 13 is polysilicon. Detailed Implementation

[0023] The technical solution of the present invention will be described below with reference to the accompanying drawings:

[0024] like Figure 7 As shown, a high-voltage LDMOS device structure with variable current distribution and resistance to single-particle irradiation includes a P-type substrate 1 at the bottom; an N-type buffer layer 2 located to the upper right of the P-type substrate 1; a P-type buried layer 3 located to the upper left of the P-type substrate 1; an N-type drift region 4 located to the right of the P-type buried layer 3; a P-type well region 5 located to the upper left of the P-type buried layer 3; a local buried oxide layer 6 located to the upper right of the P-type buried layer 3; a source region P+ implantation 7 located to the upper left of the P-type well region 5; a source region N+ implantation 8 located to the right of the source region P+ implantation 7; a gate oxide layer 9 located to the upper right of the P-type well region 5; a source region Ptop implantation 10 located above the local buried oxide layer 6; a local field oxide layer 11 located above the Ptop implantation 10; a drain N+ implantation 12 located to the upper right of the local buried oxide layer 6; and a polysilicon layer 13 located above the gate oxide layer 9.

[0025] This invention and Figure 1 Compared to the conventional LDMOS structure shown, an N-type buffer layer and a local buried oxide layer are introduced without changing the inherent size. The N-type buffer layer changes the electric field distribution inside the device and reconstructs the location of the peak electric field. The local buried oxide layer reconstructs the paths of electron current and hole current, reduces the risk of parasitic bipolar transistors (BJTs), and improves the ability to resist single-event transient effects.

[0026] The material of the local field oxide layer 11 is silicon dioxide or a low-K material with K≤2.8.

Claims

1. A high-voltage LDMOS device structure resistant to single-event irradiation, characterized in that, The system includes a P-type substrate (1), an N-type buffer layer (2), an N-type drift region (4), and a P-type buried layer (3) located on the upper surface of the P-type substrate (1), wherein the N-type drift region (4) is located between the N-type buffer layer (2) and the P-type buried layer (3); the upper surface of the P-type buried layer (3) has a P-type well region (5), the side of the P-type well region (5) is in contact with the N-type drift region (4), and at one end of the P-type well region (5) away from the N-type buffer layer (2) there is a There are parallel source region P+ injection (7) and source region N+ injection (8), wherein the source region P+ injection (7) is located at the end away from the N-type buffer layer (2); the upper layer of the N-type buffer layer (2) has a drain N+ injection (12) at the end away from the P-type well region (5); the N-type drift region (4) has a local buried oxide layer (6), one end of the local buried oxide layer (6) has a gap with the N-type buffer layer (2), and the other end extends into the P-type well region. (5) and the end face is located below the source region N+ implantation (8); a gate oxide layer (9) is provided on the upper surface of the P-type well region (5) between the source region N+ implantation (8) and the N-type drift region (4), and the two ends of the gate oxide layer (9) extend to the upper surface of part of the source region N+ implantation (8) and the upper surface of the N-type drift region (4), respectively; a local field oxide layer (11) is provided on the upper surface of the N-type drift region (4) between the gate oxide layer (9) and the drain N+ implantation (12) and the upper surface of the N-type buffer layer (2), and a polysilicon layer (13) is provided on the upper surface of the gate oxide layer (9), and the polysilicon layer (13) extends to the upper surface of part of the local field oxide layer (11); at the bottom of the local field oxide layer (11), there is a source region Ptop implantation (10), the source region Ptop implantation (10) is discontinuously distributed, and there is a gap between the bottom of the source region Ptop implantation (10) and the top of the local buried oxide layer (6).

2. The high-voltage LDMOS device structure resistant to single-event irradiation according to claim 1, characterized in that, The material of the local field oxide layer (11) is silicon dioxide or a low-K material with K ≤ 2.8.

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