Semiconductor device
By incorporating barrier layers and multilayer passivation layers into semiconductor devices, the risks of reduced drain efficiency and HAST failure caused by moisture intrusion are resolved, resulting in higher device reliability and extended lifespan.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENZHEN SHIDAI SUXIN TECH CO LTD
- Filing Date
- 2023-03-16
- Publication Date
- 2026-06-05
AI Technical Summary
While improving the resistance to moisture intrusion, existing semiconductor devices suffer from reduced drain efficiency and increased risk of HAST failure, especially due to increased parasitic capacitance and stress caused by the organic protective film.
In semiconductor devices, a barrier layer and a multilayer passivation layer structure are formed. By forming a barrier groove and depositing a barrier layer in the edge region of the metal electrode, and combining low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition methods, first and second passivation layers are formed to cover the barrier layer, thereby extending the moisture intrusion path and improving the isolation effect.
It effectively improves the device's resistance to moisture intrusion, reduces the risk of HAST failure, improves drain efficiency, and extends device lifespan.
Smart Images
Figure CN116093138B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor device. Background Technology
[0002] To improve the resistance of devices to moisture intrusion and enhance the reliability of HAST tests, current semiconductor devices typically have an additional organic protective film (PBO) on top of the SiN protective film. PBO reduces stress at the corners where the SiN protective film connects to the metal electrodes on the semiconductor stack. However, because PBO has a higher dielectric constant than SiN, it increases the parasitic capacitance (Cds) between the source and drain, reducing the drain efficiency of GaN devices. While removing the PBO layer can improve drain efficiency by approximately 3%, it significantly increases the risk of HAST test failure and impacts device lifetime. Summary of the Invention
[0003] The objectives of this invention include, for example, providing a semiconductor device that can improve the device's resistance to moisture intrusion while increasing the device's drain efficiency, reducing the risk of HAST failure, and improving the device's lifespan.
[0004] The embodiments of the present invention can be implemented as follows:
[0005] In a first aspect, the present invention provides a semiconductor device, comprising:
[0006] Substrate;
[0007] Semiconductor stacks disposed on the substrate;
[0008] Metal electrodes disposed on the semiconductor stack;
[0009] A barrier layer is disposed in the edge region of the metal electrode;
[0010] A first passivation layer is disposed on the semiconductor stack and extends to the edge region of the metal electrode;
[0011] And a second passivation layer disposed on the first passivation layer and covering the barrier layer;
[0012] The first passivation layer extends toward one edge of the barrier layer, and the second passivation layer extends to cover the other edge of the barrier layer and contacts the surface of the metal electrode.
[0013] In an optional embodiment, the edge region of the metal electrode is provided with a blocking groove, the blocking layer is at least partially disposed in the blocking groove, and the first passivation layer is bonded to the blocking layer.
[0014] In an optional embodiment, the material of the first passivation layer is the same as the material of the barrier layer, and the first passivation layer and the barrier layer are integrally disposed.
[0015] In an optional embodiment, the opening depth of the blocking groove is less than or equal to the thickness of the first passivation layer.
[0016] In an optional embodiment, the opening width of the blocking groove is greater than or equal to the opening depth of the blocking groove.
[0017] In an optional embodiment, the blocking groove is disposed around the periphery of the metal electrode, and the cross-sectional shape of the blocking groove is rectangular, stepped, trapezoidal, or arc-shaped.
[0018] In an optional embodiment, the barrier layer includes an insulating layer, the lower portion of which is accommodated in the barrier groove, and the insulating layer protrudes from the surface of the metal electrode.
[0019] In an optional implementation, the first passivation layer partially covers the insulating layer.
[0020] In an optional embodiment, the barrier layer includes a metal boss that protrudes from the surface of the metal electrode.
[0021] In an optional embodiment, the metal boss is made of the same material as the metal electrode.
[0022] In an optional embodiment, the thickness of the first passivation layer is the same as the thickness of the metal boss, and the first passivation layer is flush with the metal boss.
[0023] In an alternative embodiment, the first passivation layer partially covers the metal boss.
[0024] In an optional embodiment, the barrier layer further includes an insulating layer, the first passivation layer being bonded to one side of the metal boss, the insulating layer covering the metal boss, extending towards the side closer to the first passivation layer, partially covering the first passivation layer, and extending from the side of the metal boss away from the first passivation layer to the surface of the metal electrode.
[0025] In an optional embodiment, the barrier layer includes an insulating layer that partially covers the edge of the first passivation layer and extends to the surface of the metal electrode.
[0026] In a second aspect, the present invention provides a method for fabricating a semiconductor device, used to fabricate a semiconductor device as described in any of the foregoing embodiments, the method comprising:
[0027] Metal electrodes are formed on the semiconductor stack;
[0028] A barrier layer is formed in the edge region of the metal electrode;
[0029] A first passivation layer is formed on the semiconductor stack;
[0030] A second passivation layer is formed on the first passivation layer;
[0031] The first passivation layer extends to the edge region of the metal electrode and toward the barrier layer, while the second passivation layer covers the barrier layer and extends to cover the surface of the metal electrode.
[0032] In an optional embodiment, the step of forming a barrier layer in the edge region of the metal electrode includes:
[0033] A blocking groove is etched to form a blocking groove in the edge region of the metal electrode;
[0034] A barrier layer is deposited within the barrier groove to form a barrier layer.
[0035] In an optional embodiment, the step of forming a barrier layer in the edge region of the metal electrode includes:
[0036] Metal bosses are sputtered to form at the edge region of the metal electrode.
[0037] In an optional embodiment, the step of forming a first passivation layer on the semiconductor stack includes:
[0038] A first passivation layer is formed on the semiconductor stack by low-pressure chemical vapor deposition.
[0039] In an optional implementation, the step of forming a second passivation layer on the first passivation layer includes:
[0040] A second passivation layer is formed on the semiconductor stack by plasma-enhanced chemical vapor deposition.
[0041] The beneficial effects of the embodiments of the present invention include, for example:
[0042] The semiconductor device provided in this invention comprises a metal electrode disposed on a semiconductor stack, a barrier layer disposed at the edge region of the metal electrode, and a first passivation layer disposed on the semiconductor stack, extending to the edge region of the metal electrode and towards the barrier layer. Finally, a second passivation layer is disposed on the first passivation layer, covering the barrier layer and covering its edge, and contacting the surface of the metal electrode. Compared to the prior art, this invention, by providing a second passivation layer that completely covers the first passivation layer and the barrier layer, improves the moisture isolation effect. Furthermore, by providing the barrier layer, the moisture intrusion path is extended, making it less likely for moisture to contact the first passivation layer and the semiconductor stack, thus improving device reliability. Additionally, the PBO protective layer on the device surface can be removed, avoiding the influence of the dielectric material, improving drain efficiency, and enhancing device performance. Attached Figure Description
[0043] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0044] Figure 1 This is a schematic diagram of the structure of a semiconductor device in the prior art;
[0045] Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in the first embodiment of the present invention;
[0046] Figures 3 to 7 A process flow diagram of the method for fabricating a semiconductor device provided in the first embodiment of the present invention;
[0047] Figure 8 This is a schematic diagram of the structure of a semiconductor device provided in the second embodiment of the present invention;
[0048] Figure 9 This is a schematic diagram of the structure of a semiconductor device provided in the third embodiment of the present invention;
[0049] Figure 10 This is a schematic diagram of the structure of a semiconductor device provided in the fourth embodiment of the present invention;
[0050] Figure 11 This is a schematic diagram of the structure of a semiconductor device provided in the fifth embodiment of the present invention.
[0051] Icons: 100 - Semiconductor device; 110 - Substrate; 120 - Semiconductor stack; 130 - Metal electrode; 131 - Barrier groove; 140 - Barrier layer; 141 - Insulating layer; 143 - Metal boss; 150 - First passivation layer; 160 - Second passivation layer. Detailed Implementation
[0052] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0053] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0054] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0055] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.
[0056] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.
[0057] As disclosed in the background section, the common solution to the moisture intrusion problem faced by semiconductor devices in the prior art is to cover the surface of the top passivation layer with an organic protective layer. This organic protective layer has a high dielectric constant, which increases the parasitic capacitance between the source and drain, thus reducing the drain efficiency of GaN devices. Removing the PBO layer and simply thickening the single passivation layer to resist moisture intrusion has some effect in non-edge areas. However, thickening the passivation layer also leads to increased stress at corners, even causing cracking at the corners. However, the edge of the passivation layer usually needs to extend to the metal electrode, and moisture easily intrudes into the gap between it and the metal electrode. The moisture intrusion path is short and straight, allowing moisture to quickly penetrate into the passivation layer. Even thickening the passivation layer is insufficient to solve the moisture intrusion problem at this location, significantly increasing the risk of HAST test failure and affecting device lifespan.
[0058] To address the aforementioned problems, this invention provides a novel semiconductor device and a method for fabricating the semiconductor device, which can improve the device's resistance to moisture intrusion, enhance drain efficiency, reduce the risk of HAST failure, and extend device lifespan. It should be noted that, unless otherwise specified, features in the embodiments of this invention can be combined with each other.
[0059] First Embodiment
[0060] Please refer to Figure 1 This embodiment provides a semiconductor device 100. By optimizing the electrode and passivation layer structure, the moisture intrusion path can be extended, the device's resistance to moisture intrusion can be improved, the drain efficiency of the device can be improved, the risk of HAST failure can be reduced, and the device lifespan can be increased.
[0061] The semiconductor device 100 provided in this embodiment includes a substrate 110, a semiconductor stack 120, a metal electrode 130, a barrier layer 140, a first passivation layer 150, and a second passivation layer 160. The semiconductor stack 120 is disposed on the substrate 110, and the metal electrode 130 is disposed on the semiconductor stack 120. The barrier layer 140 is disposed on the edge region of the metal electrode 130. The first passivation layer 150 is disposed on the semiconductor stack 120 and extends to the edge region of the metal electrode 130. The second passivation layer 160 is disposed on the first passivation layer 150 and covers the barrier layer 140. The first passivation layer 150 extends toward one edge of the barrier layer 140, and the second passivation layer 160 extends to cover the other edge of the barrier layer 140 and contacts the surface of the metal electrode 130.
[0062] It should be noted that the metal electrode 130 in this embodiment can be a source metal, a drain metal, or a gate metal. The edge region of the metal electrode 130 refers to the four edges of the metal electrode 130. After the metal electrode 130 is fabricated, a first passivation layer 150 and a second passivation layer 160 can be deposited. Both the first passivation layer 150 and the second passivation layer 160 extend to the four edges of the metal electrode 130 and expose the middle region of the metal electrode 130 to facilitate its functionality.
[0063] In this embodiment, a metal electrode 130 is disposed on the semiconductor stack 120, a barrier layer 140 is disposed at the edge region of the metal electrode 130, and a first passivation layer 150 is disposed on the semiconductor stack 120. The first passivation layer 150 extends to the edge region of the metal electrode 130 and extends toward the barrier layer 140. Finally, a second passivation layer 160 is disposed on the first passivation layer 150, covering the barrier layer 140, and the second passivation layer 160 covers the edge of the barrier layer 140 and contacts the surface of the metal electrode 130. This embodiment improves the moisture isolation effect by providing the second passivation layer 160, which completely covers the first passivation layer 150 and the barrier layer 140. Furthermore, by providing the barrier layer 140, the moisture intrusion path is extended, making it less likely for moisture to contact the first passivation layer 150 and the semiconductor stack 120, thus improving device reliability. Additionally, the PBO protective layer on the device surface can be removed, avoiding the influence of the dielectric material, improving drain efficiency, and enhancing device performance.
[0064] In this embodiment, a blocking groove 131 is provided at the edge region of the metal electrode 130, and a blocking layer 140 is at least partially disposed in the blocking groove 131. The first passivation layer 150 is bonded to the blocking layer 140. Specifically, the blocking groove 131 can be arranged in a ring around the periphery of the metal electrode 130. In actual fabrication, the blocking groove 131 can be formed by etching in the edge region of the metal electrode 130. By providing the blocking groove 131, the position of the blocking layer 140 can be defined, and its ability to block moisture can be ensured. Furthermore, the edge of the first passivation layer 150 is bonded to the edge of the blocking layer 140 away from the center region of the metal electrode 130, which is beneficial for the formation of the blocking layer 140 and the first passivation layer 150.
[0065] It should be noted that in this embodiment, the number of blocking grooves 131 can be one or more. Multiple blocking grooves 131 can be arranged in layers around each other, and the blocking layer 140 can be arranged in multiple blocking grooves 131 at the same time. The number of blocking grooves 131 is not specifically limited here.
[0066] In this embodiment, the material of the first passivation layer 150 is the same as that of the barrier layer 140, and the first passivation layer 150 and the barrier layer 140 are integrally formed. Specifically, the first passivation layer 150 and the barrier layer 140 can be common passivation materials such as SiN and SiO2. In actual forming, the first passivation layer 150 and the barrier layer 140 can be formed together by low-pressure chemical vapor deposition (LPCVD). Using LPCVD can make the first passivation layer 150 and the barrier layer 140 have better step coverage and lower structural stress, reducing the deposition difficulty of the barrier layer 140 and the first passivation layer 150. Of course, in other preferred embodiments of the present invention, the barrier layer 140 and the first passivation layer 150 can also be made of different materials, or the barrier layer 140 can be deposited in the barrier groove 131 and then the first passivation layer 150 can be deposited again.
[0067] In this embodiment, the opening depth of the blocking groove 131 is less than or equal to the thickness of the first passivation layer 150. Preferably, the opening depth of the blocking groove 131 is equal to the thickness of the first passivation layer 150, that is, the opening depth of the blocking groove 131 is the same as the thickness of the blocking layer 140. When the blocking layer 140 is deposited and formed, the surfaces of the blocking layer 140 and the metal electrode 130 can be made flat, which is beneficial for the subsequent deposition and formation of the second passivation layer 160.
[0068] In this embodiment, the opening width of the blocking groove 131 is greater than or equal to the opening depth of the blocking groove 131. Specifically, the ratio of the opening width to the opening depth of the blocking groove 131 is not less than 1, which can reduce the difficulty of depositing the blocking layer 140.
[0069] In this embodiment, the blocking groove 131 is arranged around the periphery of the metal electrode 130, and the cross-sectional shape of the blocking groove 131 is rectangular, stepped, trapezoidal, or arc-shaped. Preferably, the cross-sectional shape of the blocking groove 131 is rectangular, which is beneficial for etching. Of course, by controlling the etching process parameters, the cross-section of the blocking groove 131 can also be made into other shapes such as arc or wave-shaped. Here, the cross-sectional shape of the blocking groove 131 is not specifically limited.
[0070] In this embodiment, the second passivation layer 160 completely covers the first passivation layer 150 and the barrier layer 140, effectively blocking external moisture and reducing and releasing stress. This reduces the risk of delamination and cracking at the interface between the first passivation layer 150 and the metal electrode 130, and also reduces the risk of cracking in corner areas. The barrier layer 140 significantly enhances the path for external moisture to penetrate the first passivation layer 150. Furthermore, the barrier layer 140 is positioned within the barrier groove 131, ensuring that the moisture penetration path is not limited to the straight seam direction, further improving resistance to moisture intrusion.
[0071] It should be noted that in this embodiment, the second passivation layer 160 can be formed on the first passivation layer 150 using plasma-enhanced chemical vapor deposition (PECVD). PECVD can increase the adhesion of the second passivation layer 160 and allow for the fabrication of a thicker thin film. Simultaneously, the second passivation layer 160 exhibits low stress and good density, and its thickness can be greater than or equal to the thickness of the first passivation layer 150, thereby improving the coverage at the corners of the first passivation layer 150. Furthermore, the second passivation layer 160 can be made of the same material as the first passivation layer 150 or a different material. Common passivation materials such as SiN and SiO2 can be used for the second passivation layer 160.
[0072] This embodiment also provides a method for fabricating a semiconductor device 100, which includes the following steps:
[0073] S1: A metal electrode 130 is formed on the semiconductor stack 120.
[0074] Specifically, firstly, a semiconductor stack 120 is formed on the substrate 110, and then photoresist is used on the semiconductor stack 120 to define the area where the metal electrode 130 will be grown. See [link to documentation]. Figure 2 Then, a metal electrode 130 is grown using electroplating or evaporation processes. The metal electrode 130 is typically Au, but can also be other common metals such as Al. See [link to relevant documentation]. Figure 3 .
[0075] S2: A barrier layer 140 is formed in the edge region of the metal electrode 130.
[0076] S3: A first passivation layer 150 is formed on the semiconductor stack 120.
[0077] Specifically, steps S2 and S3 can be formed together. In actual forming, a blocking groove 131 can be first etched in the edge area of the metal electrode 130, and then a blocking layer 140 can be deposited in the blocking groove 131.
[0078] In this embodiment, after forming the metal electrode 130, photoresist can be used to define the area to be etched at the edge of the metal electrode 130, see [link to documentation]. Figure 4Then, the metal electrode 130 is etched using methods such as dry etching to form a closed-loop barrier groove 131 at the edge region of the metal electrode 130. After forming the barrier groove 131, a passivation material can be deposited on the semiconductor stack 120 using low-pressure chemical vapor deposition (LPCVD) to form a first passivation layer 150 and a barrier layer 140. Then, the excess first passivation layer 150 is etched away, exposing the metal electrode 130. The first passivation layer 150 extends to the edge region of the metal electrode 130 and towards the barrier layer 140 to a bonding state. Here, the first passivation layer 150 and the barrier layer 140 can be integrally formed. See [reference needed]. Figure 5 and Figure 6 LPCVD can enable the first passivation layer 150 and the barrier layer 140 to have better step coverage and lower structural stress, thereby reducing the deposition difficulty of the barrier layer 140 and the first passivation layer 150.
[0079] S4: A second passivation layer 160 is formed on the first passivation layer 150.
[0080] Specifically, after forming the first passivation layer 150, a thicker second passivation layer 160 can be formed on the first passivation layer 150 using plasma-enhanced chemical vapor deposition (PECVD). See [link to relevant documentation]. Figure 7 Then, the excess second passivation layer 160 is etched away again. The structure can be found in [reference]. Figure 1 PECVD can increase the adhesion of the second passivation layer 160 and enable the fabrication of a thicker thin film. Simultaneously, the second passivation layer 160 exhibits low stress and good density, and its thickness can be greater than or equal to that of the first passivation layer 150, thereby improving the coverage at the corners of the first passivation layer 150. The second passivation layer 160 covers the barrier layer 140 and extends to cover the surface of the metal electrode 130.
[0081] It is worth noting that in this embodiment, both the first passivation layer 150 and the second passivation layer 160 can be formed through multiple growth processes to gradually release stress. Specifically, the first passivation layer 150 can be formed through multiple growth processes, and each growth can use the same material for passivation, or different materials can be used in a stacked design, such as combinations of SiN+SiO2, SiN1+SiN2+SiO2, etc. The growth process and materials of the second passivation layer 160 are the same as those of the first passivation layer 150.
[0082] In summary, this embodiment provides a semiconductor device 100 and its fabrication method. A metal electrode 130 is disposed on a semiconductor stack 120, a barrier layer 140 is disposed at the edge region of the metal electrode 130, and a first passivation layer 150 is disposed on the semiconductor stack 120. The first passivation layer 150 extends to the edge region of the metal electrode 130 and extends toward the barrier layer 140. Finally, a second passivation layer 160 is disposed on the first passivation layer 150, covering the barrier layer 140. The second passivation layer 160 covers the edge of the barrier layer 140 and is in contact with the surface of the metal electrode 130. Compared to existing technologies, this embodiment improves the moisture isolation effect by setting a second passivation layer 160 that completely covers the first passivation layer 150 and the barrier layer 140. Furthermore, by setting the barrier layer 140 in the barrier groove 131, the moisture intrusion path is extended, making it less likely for moisture to contact the first passivation layer 150 and the semiconductor stack 120, thus improving the reliability of the device. In addition, the PBO protective layer on the device surface can be removed, avoiding the influence of the dielectric material, improving the drain efficiency, and enhancing the device performance.
[0083] Second Embodiment
[0084] This embodiment provides a semiconductor device 100, whose basic structure, principle, and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.
[0085] See Figure 8 In this embodiment, the semiconductor device 100 includes a substrate 110, a semiconductor stack 120, a metal electrode 130, a barrier layer 140, a first passivation layer 150, and a second passivation layer 160. The semiconductor stack 120 is disposed on the substrate 110, and the metal electrode 130 is disposed on the semiconductor stack 120. The barrier layer 140 is disposed on the edge region of the metal electrode 130. The first passivation layer 150 is disposed on the semiconductor stack 120 and extends to the edge region of the metal electrode 130. The second passivation layer 160 is disposed on the first passivation layer 150 and covers the barrier layer 140. The first passivation layer 150 extends toward one edge of the barrier layer 140, and the second passivation layer 160 extends to cover the other edge of the barrier layer 140 and contacts the surface of the metal electrode 130.
[0086] In this embodiment, a blocking groove 131 is provided at the edge region of the metal electrode 130, and a blocking layer 140 is at least partially disposed in the blocking groove 131. The first passivation layer 150 is bonded to the blocking layer 140. Specifically, the blocking layer 140 includes an insulating layer 141, the lower part of which is accommodated in the blocking groove 131, and the insulating layer 141 protrudes from the surface of the metal electrode 130. The insulating layer 141 can be made of a non-metallic insulating material, and the thickness of the insulating layer 141 is the same as the thickness of the first passivation layer 150, so that the first passivation layer 150 and the sidewall of the insulating layer 141 can be fully bonded.
[0087] In this embodiment, the first passivation layer 150 partially covers the insulating layer 141. Specifically, the first passivation layer 150 extends above the insulating layer 141 and partially covers the insulating layer 141, further forming a stepped first passivation layer 150 to achieve better resistance to moisture intrusion. Of course, the first passivation layer 150 may not cover the insulating layer 141, that is, the first passivation layer 150 is flush with the insulating layer 141, so that the second passivation layer 160 can be better planarized, which is beneficial to the deposition of the second passivation layer 160.
[0088] The semiconductor device 100 provided in this embodiment uses dry etching at the edge of the metal electrode 130 to etch a blocking groove 131 on the surface of the metal electrode 130. The blocking groove 131 is filled with a non-metallic insulating material to form an insulating layer 141, which partially covers the surface of the metal electrode 130. The first passivation layer 150 may partially cover or not cover the insulating material, while the second passivation layer 160 must completely cover and encapsulate both the first passivation layer 150 and the insulating layer 141. By providing the insulating layer 141, a good blocking effect is achieved, extending the moisture intrusion path and improving moisture resistance. Simultaneously, the insulating material prevents electrochemical corrosion, thus avoiding damage to the device.
[0089] Third Embodiment
[0090] See Figure 9 This embodiment provides a semiconductor device 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.
[0091] In this embodiment, the semiconductor device 100 includes a substrate 110, a semiconductor stack 120, a metal electrode 130, a barrier layer 140, a first passivation layer 150, and a second passivation layer 160. The semiconductor stack 120 is disposed on the substrate 110, and the metal electrode 130 is disposed on the semiconductor stack 120. The barrier layer 140 is disposed on the edge region of the metal electrode 130. The first passivation layer 150 is disposed on the semiconductor stack 120 and extends to the edge region of the metal electrode 130. The second passivation layer 160 is disposed on the first passivation layer 150 and covers the barrier layer 140. The first passivation layer 150 extends toward one edge of the barrier layer 140, and the second passivation layer 160 extends to cover the other edge of the barrier layer 140 and contacts the surface of the metal electrode 130.
[0092] In this embodiment, the barrier layer 140 includes a metal boss 143, which protrudes from the surface of the metal electrode 130. Specifically, the metal boss 143 can be formed on the surface of the metal electrode 130 by sputtering, and the cross-sectional shape of the metal boss 143 can be rectangular, arc-shaped, or trapezoidal, etc., without specific limitation. The second passivation layer 160 needs to completely cover and enclose the first passivation layer 150 and the metal boss 143.
[0093] In this embodiment, the metal boss 143 is made of the same material as the metal electrode 130. Specifically, the metal boss 143 can be directly sputtered onto the surface of the metal electrode 130 and is made of the same material as the metal electrode 130, which can prevent electrochemical corrosion and ensure device reliability.
[0094] In this embodiment, the thickness of the first passivation layer 150 is the same as the thickness of the metal boss 143, and the first passivation layer 150 is flush with the metal boss 143. Specifically, the edge of the first passivation layer 150 is joined to the edge of the metal boss 143 on the side away from the center of the metal electrode, and the first passivation layer 150 is flush with the metal boss 143, which makes the surface of the second passivation layer 160 as flat as possible and reduces the risk of cracking of the second passivation layer 160. Of course, in other preferred embodiments of the present invention, the first passivation layer 150 may also partially cover the metal boss 143 to achieve a better moisture release effect.
[0095] This embodiment also provides a method for fabricating a semiconductor device 100, which is used to fabricate the aforementioned semiconductor device 100. The basic steps and principles are the same as in the first embodiment, except for the formation step of the barrier layer 140. In this embodiment, the step of forming the barrier layer 140 in the edge region of the metal electrode 130 includes: sputtering to form a metal protrusion 143 in the edge region of the metal electrode 130. Specifically, based on the first embodiment, etching is changed to sputtering to form the metal protrusion 143.
[0096] The semiconductor device 100 provided in this embodiment, based on the first embodiment, changes the etching of the metal electrode 130 to a sputtering method to form a metal protrusion 143, and the material of the metal protrusion 143 is the same as that of the metal electrode 130 to prevent electrochemical corrosion. The first passivation layer 150 may partially cover or not cover the metal protrusion 143, while the second passivation layer 160 needs to completely cover and encapsulate the first passivation layer 150 and the metal protrusion 143. By setting the metal protrusion 143, the intrusion path of water vapor can also be increased, the resistance to water vapor can be improved, and the device performance can be guaranteed.
[0097] Fourth embodiment
[0098] See Figure 10 This embodiment provides a semiconductor device 100, whose basic structure, principle and technical effects are the same as those of the first embodiment or the third embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment or the third embodiment.
[0099] In this embodiment, the semiconductor device 100 includes a substrate 110, a semiconductor stack 120, a metal electrode 130, a barrier layer 140, a first passivation layer 150, and a second passivation layer 160. The semiconductor stack 120 is disposed on the substrate 110, and the metal electrode 130 is disposed on the semiconductor stack 120. The barrier layer 140 is disposed on the edge region of the metal electrode 130. The first passivation layer 150 is disposed on the semiconductor stack 120 and extends to the edge region of the metal electrode 130. The second passivation layer 160 is disposed on the first passivation layer 150 and covers the barrier layer 140.
[0100] In this embodiment, the barrier layer 140 includes a metal boss 143 and an insulating layer 141. The metal boss 143 protrudes from the surface of the metal electrode 130. The first passivation layer 150 is bonded to one side of the metal boss 143. The insulating layer 141 covers the metal boss 143 and extends from the side of the metal boss 143 away from the first passivation layer 150 to the surface of the metal electrode 130. Specifically, the metal boss 143 can be formed on the surface of the metal electrode 130 by sputtering, and the cross-sectional shape of the metal boss 143 can be rectangular, arc-shaped, or trapezoidal, etc., without specific limitation. The insulating layer 141 covers the edges of both the metal boss 143 and the first passivation layer 150.
[0101] In this embodiment, the thickness of the first passivation layer 150 is the same as the protrusion height of the metal boss 143, and the edge of the first passivation layer 150 is joined with the edge of the metal boss 143 away from the center of the metal electrode 130, so that the insulating layer 141 can flatly cover the first passivation layer 150 and the metal boss 143. At the same time, the insulating layer 141 needs to completely cover the metal boss 143 and partially cover the surface of the metal electrode 130, while the second passivation layer 160 needs to completely cover and wrap the first passivation layer 150 and the insulating layer 141.
[0102] It should be noted that in this embodiment, the insulating layer 141 may partially cover the edge of the first passivation layer 150 and completely cover the metal boss 143, or it may only cover the top of the metal boss 143 without covering the first passivation layer 150.
[0103] Fifth embodiment
[0104] See Figure 11 This embodiment provides a semiconductor device 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the first embodiment.
[0105] In this embodiment, the semiconductor device 100 includes a substrate 110, a semiconductor stack 120, a metal electrode 130, a barrier layer 140, a first passivation layer 150, and a second passivation layer 160. The semiconductor stack 120 is disposed on the substrate 110, and the metal electrode 130 is disposed on the semiconductor stack 120. The barrier layer 140 is disposed on the edge region of the metal electrode 130. The first passivation layer 150 is disposed on the semiconductor stack 120 and extends to the edge region of the metal electrode 130. The second passivation layer 160 is disposed on the first passivation layer 150 and covers the barrier layer 140. The first passivation layer 150 extends toward one edge of the barrier layer 140, and the second passivation layer 160 extends to cover the other edge of the barrier layer 140 and contacts the surface of the metal electrode 130. The barrier layer 140 is laid flat on the semiconductor stack 120 and partially covers the first passivation layer 150.
[0106] In this embodiment, the barrier layer 140 includes an insulating layer 141, which partially covers the edge of the first passivation layer 150 and extends to the surface of the metal electrode 130. Specifically, the first passivation layer 150 can be formed first, and then the insulating layer 141 can be covered between the first passivation layer 150 and the surface of the metal electrode 130, so that the insulating layer 141 can partially cover the first passivation layer 150 and extend to cover the surface of the metal electrode 130. That is, the insulating layer 141 can overlap between the first passivation layer 150 and the metal electrode 130, thereby completely covering the junction between the two and preventing external moisture from entering between the first passivation layer 150 and the metal electrode 130, thus improving the moisture resistance effect.
[0107] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A semiconductor device, characterized in that, include: Substrate (110); Semiconductor stack (120) disposed on the substrate (110); Metal electrodes (130) disposed on the semiconductor stack (120); A barrier layer (140) is provided in the edge region of the metal electrode (130). A first passivation layer (150) is disposed on the semiconductor stack (120) and extends to the edge region of the metal electrode (130); and, A second passivation layer (160) is disposed on the first passivation layer (150) and covers the barrier layer (140). The first passivation layer (150) extends toward one side edge of the barrier layer (140), and the second passivation layer (160) extends to cover the other side edge of the barrier layer (140) and contacts the surface of the metal electrode (130). The metal electrode (130) has a blocking groove (131) on its edge region, and the blocking layer (140) is at least partially disposed in the blocking groove (131). The first passivation layer (150) is bonded to the blocking layer (140). The blocking groove (131) is arranged around the periphery of the metal electrode (130).
2. The semiconductor device according to claim 1, characterized in that, The first passivation layer (150) is made of the same material as the barrier layer (140), and the first passivation layer (150) and the barrier layer (140) are integrally formed.
3. The semiconductor device according to claim 1, characterized in that, The cross-sectional shape of the blocking groove (131) is rectangular, stepped, trapezoidal or arc-shaped.
4. The semiconductor device according to claim 1, characterized in that, The barrier layer (140) includes an insulating layer (141), the lower part of which is accommodated in the barrier groove (131), and the insulating layer (141) protrudes from the surface of the metal electrode (130).
5. The semiconductor device according to claim 4, characterized in that, The first passivation layer (150) partially covers the insulating layer (141).
6. The semiconductor device according to claim 1, characterized in that, The barrier layer (140) includes a metal boss (143) which protrudes from the surface of the metal electrode (130) and the material of the metal boss (143) is the same as that of the metal electrode (130).
7. The semiconductor device according to claim 6, characterized in that, The thickness of the first passivation layer (150) is the same as the thickness of the metal boss (143), and the first passivation layer (150) is flush with the metal boss (143).
8. The semiconductor device according to claim 6 or 7, characterized in that, The barrier layer (140) further includes an insulating layer (141), the first passivation layer (150) is bonded to one side of the metal boss (143), the insulating layer (141) covers the metal boss (143), extends towards the side close to the first passivation layer (150), partially covers the first passivation layer (150), and extends from the side of the metal boss (143) away from the first passivation layer (150) to the surface of the metal electrode (130).
9. The semiconductor device according to claim 1, characterized in that, The barrier layer (140) includes an insulating layer (141) that partially covers the edge of the first passivation layer (150) and extends to the surface of the metal electrode (130).