Vertical structure deep ultraviolet LED chip and manufacturing method thereof

Abstract

The application discloses a vertical structure deep ultraviolet LED structure and a manufacturing method thereof. The vertical structure deep ultraviolet LED structure comprises an epitaxial layer, which comprises a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer and the like; the epitaxial layer has a first surface and a second surface opposite to each other, the second surface is arranged away from the first conductive semiconductor layer, at least one second groove is arranged on the second surface, groove bottom surfaces of the second groove are distributed on the first surface of the epitaxial layer, a protective layer is covered on the groove bottom surfaces of the second groove, and meanwhile, stress matching materials are filled in the second groove. The application can effectively prevent or eliminate problems such as the falling off of the epitaxial layer caused by excessive stress of the epitaxial layer when the epitaxial substrate is removed, can significantly improve the horizontal light emission of the deep ultraviolet LED device, improve the light extraction efficiency, and help effectively reduce the risk of sidewall leakage of the device, greatly improve the production yield of the device and improve the reliability of the device.

Description

Technical Field

[0001] This invention relates to a method for manufacturing an LED chip, specifically to a vertical structure deep ultraviolet LED chip and its manufacturing method, belonging to the field of semiconductor optoelectronic devices. Background Technology

[0002] III-V nitride semiconductors, known as third-generation semiconductor materials, possess advantages such as a wide bandgap, good chemical stability, and strong radiation resistance. Their bandgap covers the entire visible light spectrum, from deep ultraviolet and the near-infrared, making them suitable for fabricating semiconductor light-emitting devices such as LEDs, lasers, and superluminescent LEDs. Deep ultraviolet LEDs based on III-V nitrides offer advantages such as energy efficiency, environmental friendliness, simple fabrication, small size, light weight, and long lifespan, showing broad market application prospects in sterilization and disinfection, water purification, ultraviolet curing, plant illumination, and jewelry identification.

[0003] Deep ultraviolet (DUV) LEDs have long suffered from low light extraction efficiency. A significant reason for this is that the epitaxial structure of DUV LEDs typically uses sapphire or silicon as the substrate and AlN as the buffer layer. The internal materials, especially the silicon substrate and AlN buffer layer, exhibit severe absorption of light in the deep ultraviolet band. Vertically structured DUV LEDs can eliminate the substrate and buffer layer, significantly reducing light absorption and improving extraction efficiency. However, due to substantial lattice and thermal mismatches between the substrate, buffer layer, and the DUV LED epitaxial structure, significant stress accumulates after epitaxial growth. During substrate removal, this accumulated stress is released, causing the epitaxial film to detach. Furthermore, for AlGaN-based DUV LEDs, as the Al content increases, the emission wavelength becomes shorter, and the proportion of horizontal emission increases significantly, making it difficult to extract horizontally emitted light. Summary of the Invention

[0004] The main objective of this invention is to provide a vertical structure deep ultraviolet LED chip and its manufacturing method to overcome the shortcomings of the prior art.

[0005] To achieve the aforementioned objectives, the technical solution adopted by this invention includes:

[0006] One aspect of the present invention provides a vertical structure deep ultraviolet LED chip, which includes an epitaxial layer, the epitaxial layer including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer stacked sequentially, the first conductive semiconductor layer being electrically connected to a first electrode and the second conductive semiconductor layer being electrically connected to a second electrode;

[0007] Furthermore, the epitaxial layer has a first side and a second side facing away from each other. The second side is disposed away from the first conductive semiconductor layer. At least one second trench is also formed on the second side. The bottom surface of the second trench is distributed in the epitaxial layer or on the first side. At least the bottom surface of the second trench is covered with a protective layer. At the same time, the second trench is also filled with stress matching material.

[0008] Furthermore, a second insulating layer and a second reflective layer are formed on the inner wall of the second trench. The second insulating layer continuously covers the inner wall of the second trench, the protective layer, and the second conductive semiconductor layer. The second reflective layer continuously covers the second insulating layer, and the second reflective layer is connected to the bonding substrate via a bonding barrier layer, a bonding layer, etc.

[0009] Another aspect of the present invention provides a method for fabricating a vertical structure deep ultraviolet LED chip, comprising: a step of growing an epitaxial layer on an epitaxial substrate and a step of fabricating a first electrode and a second electrode that cooperate with the epitaxial layer, wherein the epitaxial layer comprises a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer stacked sequentially, the first conductive semiconductor layer being electrically connected to the first electrode and the second conductive semiconductor layer being electrically connected to the second electrode;

[0010] Furthermore, the manufacturing method also includes:

[0011] At least one second trench is formed on the second surface of the epitaxial layer, and the bottom surface of the second trench is distributed inside the epitaxial layer or on the first surface of the epitaxial layer. The second surface is disposed away from the first conductive semiconductor layer, and the first surface is opposite to the second surface.

[0012] A protective layer is at least covered on the bottom surface of the second trench, and the second trench is filled with stress-matching material.

[0013] Furthermore, the manufacturing method further includes: after covering the bottom surface of the second trench with a protective layer, forming a second insulating layer, a second reflective layer, etc. on the inner wall of the second trench, filling the second trench with stress matching material, then bonding the second reflective layer to the bonding substrate, then removing the epitaxial substrate, and at least partially removing the buffer layer distributed between the epitaxial substrate and the first conductive semiconductor layer.

[0014] Compared with existing technologies, this invention first creates trenches on the epitaxial layer of the deep ultraviolet LED, and then sets a protective layer and fills the trenches with stress-matching material. Finally, the epitaxial layer is bonded to the bonding layer. This allows the entire epitaxial layer to achieve stress balance under the combined action of the bonding layer and the stress-matching material, thereby preventing the epitaxial layer from falling off due to excessive stress during substrate removal. At the same time, it can significantly improve the horizontal light output of the deep ultraviolet LED device, enhance light extraction efficiency, and effectively reduce the risk of sidewall leakage, thereby greatly improving device production yield and device reliability. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a cross-sectional view of a deep ultraviolet LED epitaxial structure bonded to a bonding substrate in one embodiment of the present invention before the epitaxial substrate is removed.

[0017] Figure 2 yes Figure 1 An enlarged view of the area selected by the dashed box;

[0018] Figure 3 This is a cross-sectional view of a deep ultraviolet LED epitaxial structure bonded to a bonding substrate in one embodiment of the present invention after the epitaxial substrate has been removed.

[0019] Figure 4 yes Figure 3 The cross-sectional view of the deep ultraviolet LED epitaxial structure shown is after further processing.

[0020] Figure 5 yes Figure 4 An enlarged view of the area selected by the dashed box;

[0021] Figure 6 This is a top view of a deep ultraviolet LED device according to an embodiment of the present invention;

[0022] Explanation of reference numerals in the attached figures: 110 Epitaxial substrate, 111 Buffer layer, 112 First conductive semiconductor layer (n-type layer), 113 Active layer, 114 Second conductive semiconductor layer (p-type layer), 115 First insulating layer, 116 First electrode (n-electrode), 117 First trench, 118 Second trench, 120 Second electrode, First reflective layer (p-electrode), 121 Second electrode connection layer (p-first pad connection layer), 130 Protective layer, 131 Second insulating layer, 132 Second reflective layer, 133 Stress matching filling layer, 140 Bonding barrier layer and bonding layer, 150 Bonding substrate, 160 First pad. Detailed Implementation

[0023] As mentioned above, existing vertical structure deep ultraviolet LEDs often encounter problems such as epitaxial layer detachment due to excessive residual stress inside the material during the process of removing the epitaxial substrate. In view of this, the inventors of this application have proposed the technical solution after long-term research and extensive practice, which is described below.

[0024] Some embodiments of the present invention provide a vertical deep ultraviolet LED structure, including an epitaxial layer. The epitaxial layer includes a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer stacked sequentially. The first conductive semiconductor layer is electrically connected to a first electrode, and the second conductive semiconductor layer is electrically connected to a second electrode. The epitaxial layer has a first surface and a second surface facing away from each other. The second surface is disposed away from the first conductive semiconductor layer. At least one second trench is formed on the second surface. The bottom surface of the second trench is distributed within the epitaxial layer or on the first surface. At least the bottom surface of the second trench is covered with a protective layer, and the second trench is filled with a stress-matching material.

[0025] One approach is to create a second trench on the epitaxial layer before bonding it to the bonding substrate. This can help release stress in the epitaxial layer to some extent. However, the stress-relieving effect of the second trench alone is limited. In this application, after creating the second trench, a protective layer is placed at the bottom of the second trench, and a stress-matching material is filled inside the second trench. This prevents the second trench from being damaged during the removal of the epitaxial substrate. Furthermore, the second trench, the protective layer, and the stress-matching material work together with the bonding layer to achieve stress balance, reducing or even eliminating the problem of epitaxial layer detachment caused by excessive stress during substrate removal.

[0026] In some embodiments, a second insulating layer is further formed on the inner wall of the second trench. The second insulating layer continuously covers the inner wall of the second trench, the protective layer, and the second conductive semiconductor layer, and the second insulating layer is connected to the bonding substrate via a bonding layer. By providing the second insulating layer, problems such as sidewall leakage of the device can be reduced or even eliminated.

[0027] Preferably, the wall of the second trench is inclined and forms an angle of 30-60° with the first or second surface of the epitaxial layer. This can more effectively reflect the light emitted by the device, especially the light emitted in the horizontal direction, back into the device or its light-emitting surface, thereby improving the light-harvesting efficiency of the device.

[0028] In some embodiments, there are multiple second trenches, which are spaced apart on the epitaxial layer.

[0029] In some embodiments, the bottom surface of the second trench is distributed on the first surface.

[0030] In some embodiments, the epitaxial layer further includes a buffer layer, wherein the first conductive semiconductor layer is formed on one side surface of the buffer layer, and the other side surface of the buffer layer is the first surface.

[0031] In some embodiments, the surface of the first conductive semiconductor layer away from the active layer is the first surface.

[0032] In some embodiments, a second reflective layer is continuously coated on the second insulating layer, and the stress-matching material is distributed between the second reflective layer and the bonding layer. This second reflective layer can further reflect light from the device sidewalls back to the surface, increasing light extraction efficiency. This second reflective layer can be formed of a highly reflective material such as Al.

[0033] In some embodiments, a bonding barrier layer is further distributed between the bonding layer and the second reflective layer to prevent metal elements in the bonding layer from diffusing into the epitaxial layer.

[0034] In some embodiments, the second electrode is distributed between the second insulating layer and the second conductive semiconductor layer, and the second electrode is electrically bonded to the second conductive semiconductor layer. Preferably, the second electrode forms an ohmic contact with the second conductive semiconductor layer.

[0035] In some embodiments, the second electrode is also used to form a first reflective layer.

[0036] In some embodiments, the second conductive semiconductor layer is further covered with a first insulating layer.

[0037] In some embodiments, at least one first trench is further formed on the second surface of the epitaxial layer, the bottom surface of the first trench is distributed inside the first conductive semiconductor layer or on the surface of the first conductive semiconductor layer, and the first electrode is at least partially disposed in the first trench and electrically contacted with the first conductive semiconductor layer, for example, forming an ohmic contact.

[0038] In some embodiments, the first trench is a plurality of trenches and is spaced apart on the epitaxial layer.

[0039] In some embodiments, the first electrode is disposed entirely within the first trench and directly bonded to the second reflective layer.

[0040] In some embodiments, the inner wall of the first trench is further covered with a first insulating layer, which extends continuously to the surface of the second conductive semiconductor layer.

[0041] In some embodiments, the first electrode is disposed within the first trench and in contact with the second reflective layer.

[0042] In some embodiments, the second electrode is also in electrical contact with a second electrode connection layer, which is disposed between the second electrode and the second insulating layer.

[0043] In some embodiments, the first surface of the epitaxial layer has a surface roughening structure to further improve the light extraction efficiency of the device.

[0044] In some embodiments, a third trench is further formed on the first surface of the epitaxial layer, the bottom surface of the third trench reaches the surface of the second electrode connection layer, and a first pad is provided in the third trench, the first pad being in electrical contact with the second electrode connection layer.

[0045] In some embodiments, there are multiple third trenches, which are spaced apart on the epitaxial layer.

[0046] In some embodiments, the first conductive semiconductor layer is formed on an epitaxial substrate, and a buffer layer is further distributed between the first conductive semiconductor layer and the epitaxial substrate.

[0047] Some embodiments of the present invention also provide a method for fabricating a vertical deep ultraviolet LED structure, including the steps of growing an epitaxial layer on an epitaxial substrate and fabricating a first electrode and a second electrode that cooperate with the epitaxial layer. The epitaxial layer includes a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer stacked sequentially. The first conductive semiconductor layer is electrically connected to the first electrode and the second conductive semiconductor layer is electrically connected to the second electrode.

[0048] The manufacturing method further includes:

[0049] At least one second trench is formed on the second surface of the epitaxial layer, and the bottom surface of the second trench is distributed inside the epitaxial layer or on the first surface of the epitaxial layer. The second surface is disposed away from the first conductive semiconductor layer, and the first surface is opposite to the second surface.

[0050] A protective layer is at least covered on the bottom surface of the second trench, and the second trench is filled with stress-matching material.

[0051] In some embodiments, the manufacturing method further includes: tilting the wall of the second trench to form an angle of 30-60° with the first or second surface of the epitaxial layer.

[0052] In some embodiments, the manufacturing method specifically includes:

[0053] A protective layer is placed over the bottom surface of the second trench;

[0054] A second insulating layer is formed on the inner wall of the second trench, and the second insulating layer continuously covers the inner wall of the second trench, the protective layer, and the second conductive semiconductor layer.

[0055] A second reflective layer is formed on the second insulating layer;

[0056] The second trench is filled with a stress-matching material;

[0057] The second reflective layer is bonded to the bonding substrate via a bonding layer;

[0058] Remove the epitaxial substrate and at least partially remove the buffer layer distributed between the epitaxial substrate and the first conductive semiconductor layer.

[0059] In some embodiments, the buffer layer may be partially removed, and the side of the buffer layer away from the first conductive semiconductor layer may be used as the first surface of the epitaxial layer.

[0060] In some embodiments, the buffer layer can be completely removed, and the surface of the first conductive semiconductor layer away from the active layer can be used as the first surface of the epitaxial layer.

[0061] In some embodiments, the epitaxial substrate and buffer layer can also be completely removed.

[0062] In some embodiments, a buffer layer, a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer may be sequentially grown on an epitaxial substrate.

[0063] In some embodiments, the manufacturing method specifically includes:

[0064] At least one first trench is formed on the second surface of the epitaxial layer, and the bottom surface of the first trench is distributed inside the first conductive semiconductor layer or on the surface of the first conductive semiconductor layer.

[0065] A first electrode is disposed on the first conductive semiconductor layer, and the first electrode is at least partially disposed in the first trench and in electrical contact with the first conductive semiconductor layer;

[0066] A continuous first insulating layer is formed on the inner wall of the first trench, and the first insulating layer extends to the surface of the second conductive semiconductor layer.

[0067] A window is opened on the first insulating layer to expose the area on the surface of the second conductive semiconductor layer corresponding to the second electrode, and then the second electrode is formed within the window.

[0068] The second trench is formed on the second surface of the epitaxial layer.

[0069] In some embodiments, the manufacturing method further includes: depositing a second electrode connection layer on the second electrode and making the second electrode connection layer electrically contact the second electrode, and then covering the second electrode connection layer with a second insulating layer and a second reflective layer.

[0070] In some embodiments, the fabrication method further includes roughening the first surface of the epitaxial layer.

[0071] In some embodiments, the fabrication method further includes: disposing a bonding barrier layer between the bonding layer and the second reflective layer.

[0072] In some embodiments, the fabrication method further includes: forming a third trench on a first surface of the epitaxial layer, and bringing the bottom surface of the third trench to the surface of the second electrode connection layer, then forming a first pad in the third trench, and making the first pad electrically contact the second electrode connection layer.

[0073] In the above embodiments of the present invention, the first conductive semiconductor layer may be an n-type layer, the second conductive semiconductor layer may be a p-type layer, the active layer may be a multiple quantum well, etc., and correspondingly, the first electrode may be an n-electrode and the second electrode may be a p-electrode.

[0074] In the above embodiments of the present invention, the epitaxial layer may be formed of III-V group compounds, such as GaN, AlGaN, InGaN, AlInGaN, etc., and is not limited thereto.

[0075] In the above embodiments of the present invention, the first electrode and the second electrode may be formed by any one or more combinations of metallic materials such as Cu, Ag, Au, Ni, Cr, Al, Rh, V, Ti, Pt, Mo, In, Sn, or their alloys and metal oxides such as ITO, and are not limited thereto.

[0076] In the above embodiments of the present invention, the first insulating layer and the second insulating layer may be formed of insulating materials such as aluminum nitride, silicon nitride, and silicon oxide, and are not limited thereto.

[0077] In the above embodiments of the present invention, the protective layer is made of a corrosion-resistant material, such as Cr, Pt, Au, or their alloys, and its thickness is preferably 100nm-500nm.

[0078] In the above embodiments of the present invention, the material of the epitaxial substrate includes silicon, sapphire, silicon carbide, gallium nitride, aluminum nitride, or combinations thereof, and the material of the buffer layer may be selected from aluminum nitride, etc., but is not limited thereto.

[0079] In the above embodiments of the present invention, the material of the bonding layer may be selected from AuSn, NiSn, CuSn, AgSn, Au1n, AuAu, etc., and is not limited thereto.

[0080] In the above embodiments of the present invention, the material of the bonding substrate may be selected from conductive materials such as silicon, copper, and molybdenum-copper alloy, but is not limited thereto.

[0081] The technical solution of the present invention will be further described in detail below with reference to several preferred embodiments and accompanying drawings. This embodiment is implemented on the premise of the technical solution of the invention, and provides detailed implementation methods and specific operation processes. However, the protection scope of the present invention is not limited to the following embodiments.

[0082] Example 1: The fabrication method of a vertical structure deep ultraviolet LED device provided in this example mainly includes the following steps:

[0083] S1. Growing a deep ultraviolet LED epitaxial structure, including sequentially epitaxially growing a buffer layer 111, a first conductive semiconductor layer 112 (n-type layer), an active layer 113 (multiple quantum wells), and a second conductive semiconductor layer 114 (p-type layer) on an epitaxial substrate 110 to obtain an epitaxial wafer. The material of the epitaxial substrate can be sapphire (Al2O3), SiC, GaN, AlN, ZnO, Si, GaP, InP, and Ge, etc., and the deposition method can be metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), etc., and is not limited to these. Optionally, an electron blocking layer (EBL) can also be grown between the active layer 113 and the second conductive semiconductor layer 114. Figures 1-5(Not shown in the image) to reduce electron injection from the first conductive semiconductor layer 112 into the second conductive semiconductor layer 114. The buffer layer is preferably made of AlN and has a thickness of 1-4 μm, but is not limited thereto. The first conductive semiconductor layer 112 is preferably made of Si-doped n-type Al. x1 Ga 1-x1 N (0≤X1≤1), with a thickness preferably 1-4μm. The active layer can emit deep ultraviolet light of 200-340nm, and may include a well layer and a barrier layer, or may have any of the following structures: single-well structure, multi-well structure, single quantum well structure, multiple quantum well (MQW) structure, quantum dot structure, or quantum wire structure. The second conductive semiconductor layer 114 is preferably made of Mg-doped p-type Al. x2 Ga 1-x2 N (0≤X2≤1), the thickness is preferably 0.05-0.2μm, but is not limited thereto.

[0084] S2. Cleaning the epitaxial wafer, generally using organic or inorganic cleaning methods. Organic cleaning can use propanol and ethanol, while inorganic cleaning can use a mixture of sulfuric acid and hydrogen peroxide, as well as hydrochloric acid, to remove impurities and contaminants from the surface of the epitaxial wafer.

[0085] S3. Anneal the epitaxial wafer to effectively activate the Mg in the p-type layer.

[0086] S4. Photolithography is performed on the surface of the epitaxial wafer (this surface can be defined as the second surface). After photolithography, a first trench is formed by etching using a dry or wet etching process. The preferred etching process is ICP, etc. The etching location penetrates the second conductive semiconductor layer 114, the active layer 113, and part of the first conductive semiconductor layer 112 to form the first trench 117. The location and structure of the first trench can be referred to Figure 1 and Figure 2 As shown.

[0087] S5. Photolithography is performed again on the second surface of the epitaxial wafer, followed by metal deposition. Preferred deposition processes include electron beam evaporation and magnetron sputtering. Preferred metals are one or more combinations of metals selected from Cr, Al, Ti, Ni, Au, Pt, and V. The resist is then removed to form the first electrode 116 (n electrode), followed by annealing to form a good ohmic contact. The position and structure of the first electrode 116 can also be referenced. Figure 1 and Figure 2 As shown.

[0088] S6. A first insulating layer 115 is deposited on the second surface of the epitaxial wafer. Preferred deposition processes include PECVD, ICPCVD, LPCVD, and ALD. Preferred deposition materials include one or a combination of SiO2, SiN, and Al2O3. This first insulating layer 115 continuously covers the walls of the first trench and other areas of the second surface of the epitaxial wafer. The location and structure of the first insulating layer 115 can also be referenced. Figure 1 and Figure 2 As shown.

[0089] S7. Perform photolithography again to open a window on the first insulating layer 115. The preferred window opening process is wet etching, and the preferred etching solution is BOE, so that the area on the second surface of the epitaxial wafer corresponding to the second electrode 120 (p electrode) is exposed.

[0090] S8. Deposition of the second electrode 120 (i.e., the first reflective layer): Preferred deposition processes include electron beam evaporation and magnetron sputtering. Preferred metals include one or more combinations of Cr, Al, Ti, Ni, Au, Pt, V, Rh, and ITO. The adhesive is removed by stripping to form the second electrode 120, followed by annealing to form good ohmic contact. The position and structure of the second electrode 120 can also be referenced. Figure 1 and Figure 2 As shown.

[0091] S9. Perform photolithography again to deposit the second electrode connection layer 121. Preferred deposition processes include electron beam evaporation and magnetron sputtering. Preferred metals include one or more combinations of Cr, Al, Ti, Ni, Au, Pt, and V. Remove the resist and form the second electrode connection layer 121. The position and structure of the second electrode connection layer 121 can also be referenced. Figure 1 and Figure 2 As shown.

[0092] S10. Photolithography is performed again, followed by dry or wet etching to form a second trench 118 on the second surface of the epitaxial wafer. The preferred etching process is ICP (Inductively Coupled Processing). The etching penetrates the second conductive semiconductor layer 114, the active layer 113, the first conductive semiconductor layer 112, and the buffer layer 111, ending at the epitaxial substrate 110. The location and structure of the second trench can also be referenced. Figure 1 and Figure 2 As shown.

[0093] S11. After etching, a corrosion-resistant material, preferably Cr, Pt, Au, etc., is filled into the exposed substrate layer (i.e., the bottom surface of the second trench) to form a protective layer 130. The filling height should not exceed the buffer layer position, and the thickness is preferably 100nm-500nm, which is used to prevent damage to the second trench during the removal of the epitaxial substrate. The position and structure of the protective layer can also be referenced. Figure 1 and Figure 2 As shown.

[0094] S12. An insulating material is deposited on the second surface of the epitaxial wafer to form a second insulating layer 131. Preferred deposition processes include PECVD, ICPCVD, LPCVD, and ALD. Preferred deposition materials include one or more combinations of SiO2, SiN, and Al2O3. The preferred thickness is 600-1000 nm. This second insulating layer 131 continuously covers the second trench wall and the remaining area of ​​the second surface of the epitaxial wafer. The position and structure of the second insulating layer can also be referenced. Figure 1 and Figure 2 As shown.

[0095] S13. Perform photolithography again to create a window on the second insulating layer 131. Preferred windowing processes include RIE etching and BOE etching. The windowed area corresponds to the first electrode, etc. After windowing, deposit the second reflective layer. Preferred deposition processes include electron beam evaporation and magnetron sputtering. The preferred material for the second reflective layer is Al. The position and structure of the second reflective layer can also be referenced. Figure 1 and Figure 2 As shown.

[0096] S14. The second trench is filled with stress matching material 133, preferably SOG, PSG, various resin materials, etc., to further match the stress of the epitaxial layer and reduce problems such as epitaxial warpage.

[0097] S15. A bonding barrier layer and a bonding layer 140 are deposited on the second surface of the epitaxial wafer. The epitaxial wafer is then bonded to the bonding substrate 150 using a bonding process. The preferred bonding substrate is silicon, metal, or other conductive materials. The resulting device structure can also be found in [reference needed]. Figures 1-2 As shown.

[0098] S16. After bonding, remove the epitaxial substrate. The removal process can be thinning, laser lift-off, dry etching, or wet etching, as known in the art. Preferably, most (e.g., 90%) of the epitaxial substrate can be removed by mechanical grinding, and the remaining portion can be removed by dry etching (e.g., RIE) or wet etching to expose the buffer layer.

[0099] S17. Define the surface of the buffer layer furthest from the first conductive semiconductor layer as the first surface of the epitaxial wafer. Alternatively, more preferably, a dry etching process can be used to partially remove the buffer layer, and the surface of the remaining buffer layer can be defined as the first surface of the epitaxial wafer. The corresponding device structure is as follows: Figure 3 As shown.

[0100] S18. The surface of the first conductive semiconductor layer is roughened. Preferred processes include KOH etching and ICP etching to further improve light extraction and increase the light extraction efficiency of the device.

[0101] S19. Perform photolithography again to form a window corresponding to the first pad on the first surface of the epitaxial wafer. Preferred windowing processes include phosphoric acid etching and ICP etching, which expose the first insulating layer after processing.

[0102] S20. Deposit a passivation layer on the first surface of the epitaxial wafer. The preferred deposition process is PECVD, ICPCVD, LPCVD, ALD, etc., and the preferred deposition material is one or a combination of SiO2, SiN, Al2O3, etc.

[0103] S21. Perform photolithography again to form a window (which can also be defined as a third trench) on the passivation layer. Preferred windowing processes include RIE etching, BOE etching, etc., to expose the second electrode connection layer.

[0104] S22. Deposit a first pad 160 within the window on the passivation layer. Preferred deposition processes include electron beam evaporation and magnetron sputtering. Preferred materials include one or more metals such as Ti, Pt, Au, Cr, and Ni. Remove the adhesive to form the first pad 160, which bonds to the second electrode connection layer, for wire bonding. The resulting device structure is as follows: Figures 4-5 As shown.

[0105] The top view of the vertical structure deep ultraviolet LED device finally obtained in this embodiment is as follows: Figure 6 As shown.

[0106] Example 2: The fabrication method and device structure of the vertical structure deep ultraviolet LED device provided in this example are basically the same as those in Example 1, except that:

[0107] In step S10, the depth of the second trench formed by etching penetrates the second conductive semiconductor layer, the active layer, and the first conductive semiconductor layer, until it terminates at the buffer layer.

[0108] In step S11, a corrosion-resistant material is filled at the exposed buffer layer location (i.e., the bottom surface of the second trench) to form a protective layer. The filling height does not exceed the location of the first conductive semiconductor layer, which is used to prevent damage to the second trench during the removal of the epitaxial substrate.

[0109] In step S17, the buffer layer is completely removed, and one side surface of the exposed first conductive semiconductor layer is defined as the first surface of the epitaxial wafer.

[0110] Comparative Example 1: The fabrication method and device structure of the vertical structure deep ultraviolet LED device provided in this comparative example are basically the same as those in Example 1, except that the operation of opening a second trench on the second surface of the epitaxial wafer is omitted.

[0111] Comparative Example 2: The fabrication method and device structure of the vertical structure deep ultraviolet LED device provided in this comparative example are basically the same as those in Example 1, except that the operation of forming a protective layer at the bottom of the second trench in step S11 is omitted.

[0112] Comparative Example 3: The fabrication method and device structure of the vertical structure deep ultraviolet LED device provided in this comparative example are basically the same as those in Example 1, except that the operation of filling the second trench with stress matching material in step S14 is omitted.

[0113] Comparing Example 1 with Comparative Examples 1, 2, and 3, it is evident that the vertical structure deep ultraviolet LED device fabricated using the process in Example 1 exhibits a significantly improved yield, along with enhanced light extraction efficiency and reliability. In contrast, Comparative Example 1 shows a very low yield (less than 30%) and low light extraction efficiency. Furthermore, it should be noted that Comparative Examples 2 and 3 exhibit a certain probability of epitaxial wafer detachment or cracking during substrate removal, and the final devices also show a certain probability of sidewall leakage. Example 1 completely overcomes these defects of Comparative Examples 1-3.

[0114] It should be understood that the technical solutions of the present invention are not limited to the specific embodiments described above. Any technical modifications made to the technical solutions of the present invention without departing from the spirit and scope of the claims are within the scope of protection of the present invention.

Claims

1. A vertical deep ultraviolet LED structure, comprising an epitaxial layer, wherein the epitaxial layer comprises a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer stacked sequentially, wherein the first conductive semiconductor layer is electrically connected to a first electrode, and the second conductive semiconductor layer is electrically connected to a second electrode; Its features are: The epitaxial layer has a first side and a second side facing away from each other. The second side is disposed away from the first conductive semiconductor layer. At least one second trench is formed on the second side. The trench wall is inclined and forms an angle of 30-60° with the first side or the second side of the epitaxial layer. The bottom surface of the second trench is distributed in the epitaxial layer or on the first side. At least the bottom surface of the second trench is covered with a protective layer, and the second trench is also filled with a stress-matching material. A second insulating layer is formed on the inner wall of the second trench. The second insulating layer continuously covers the inner wall of the second trench, the protective layer, and the second conductive semiconductor layer. The second insulating layer is connected to the bonding substrate via a bonding layer. A second reflective layer is continuously covered on the second insulating layer, and the stress matching material is distributed between the second reflective layer and the bonding layer; The protective layer is made of Cr, Pt, Au or their alloys; the stress matching material is at least one of SOG, PSG or resin.

2. The vertical deep ultraviolet LED structure according to claim 1, characterized in that: The second electrode is distributed between the second insulating layer and the second conductive semiconductor layer, and the second electrode is electrically bonded to the second conductive semiconductor layer.

3. The vertical deep ultraviolet LED structure according to claim 1, characterized in that: The second electrode is also used to form the first reflective layer.

4. The vertical deep ultraviolet LED structure according to claim 1, characterized in that: The second conductive semiconductor layer is also covered with a first insulating layer.

5. The vertical deep ultraviolet LED structure according to claim 1, characterized in that: The epitaxial layer further includes a buffer layer, wherein the first conductive semiconductor layer is formed on one side surface of the buffer layer, and the other side surface of the buffer layer is the first surface.

6. The vertical deep ultraviolet LED structure according to claim 1, characterized in that: At least one first trench is also formed on the second surface of the epitaxial layer. The bottom surface of the first trench is distributed inside the first conductive semiconductor layer or on the surface of the first conductive semiconductor layer. The first electrode is at least partially disposed in the first trench and is in electrical contact with the first conductive semiconductor layer.

7. The vertical deep ultraviolet LED structure according to claim 6, characterized in that: The inner wall of the first trench is also covered with a first insulating layer, which extends continuously to the surface of the second conductive semiconductor layer.

8. The vertical deep ultraviolet LED structure according to claim 6, characterized in that: The first electrode is disposed within the first trench and is in contact with the second reflective layer.

9. The vertical deep ultraviolet LED structure according to claim 1, characterized in that: The second electrode is also in electrical contact with the second electrode connection layer, which is disposed between the second electrode and the second insulating layer.

10. The vertical deep ultraviolet LED structure according to claim 1, characterized in that: The first surface of the epitaxial layer has a surface roughening structure.

11. The vertical deep ultraviolet LED structure according to claim 9, characterized in that: A third trench is also formed on the first surface of the epitaxial layer. The bottom surface of the third trench reaches the surface of the second electrode connection layer. A first pad is provided in the third trench, and the first pad is in electrical contact with the second electrode connection layer.

12. The vertical deep ultraviolet LED structure according to claim 1, characterized in that: A bonding barrier layer is also distributed between the bonding layer and the second insulating layer.

13. The vertical deep ultraviolet LED structure according to claim 1, characterized in that: The first conductive semiconductor layer is formed on an epitaxial substrate, and a buffer layer is distributed between the first conductive semiconductor layer and the epitaxial substrate.

14. A method for fabricating a vertical deep ultraviolet LED structure according to any one of claims 1-13, comprising the steps of growing an epitaxial layer on an epitaxial substrate and fabricating a first electrode and a second electrode that cooperate with the epitaxial layer, wherein the epitaxial layer comprises a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer stacked sequentially, the first conductive semiconductor layer being electrically connected to the first electrode and the second conductive semiconductor layer being electrically connected to the second electrode; Its features are, The manufacturing method also includes: At least one second trench is formed on the second surface of the epitaxial layer, and the trench wall is inclined, forming an angle of 30-60° with the first or second surface of the epitaxial layer. The bottom surface of the second trench is distributed within the epitaxial layer or on the first surface of the epitaxial layer, the second surface is disposed away from the first conductive semiconductor layer, and the first and second surfaces are opposite to each other. At least a protective layer shall be applied to the bottom surface of the second trench; A second insulating layer is formed on the inner wall of the second trench, and the second insulating layer continuously covers the inner wall of the second trench, the protective layer, and the second conductive semiconductor layer. A second reflective layer is formed on the second insulating layer; The second trench is filled with a stress-matching material; The second reflective layer is bonded to the bonding substrate via a bonding layer; Remove the epitaxial substrate and at least partially remove the buffer layer distributed between the epitaxial substrate and the first conductive semiconductor layer.

15. The manufacturing method according to claim 14, characterized in that, Specifically, it includes: At least one first trench is formed on the second surface of the epitaxial layer, and the bottom surface of the first trench is distributed inside the first conductive semiconductor layer or on the surface of the first conductive semiconductor layer. A first electrode is disposed on the first conductive semiconductor layer, and the first electrode is at least partially disposed in the first trench and in electrical contact with the first conductive semiconductor layer; A continuous first insulating layer is formed on the inner wall of the first trench, and the first insulating layer extends to the surface of the second conductive semiconductor layer. A window is opened on the first insulating layer to expose the area on the surface of the second conductive semiconductor layer corresponding to the second electrode, and then the second electrode is formed within the window. The second trench is formed on the second surface of the epitaxial layer.

16. The manufacturing method according to claim 14, characterized in that, Also includes: A second electrode connection layer is disposed on the second electrode and electrically connected to the second electrode. Then, a second insulating layer and a second reflective layer are covered on the second electrode connection layer.

17. The manufacturing method according to claim 14, characterized in that, Also includes: The first surface of the epitaxial layer is roughened.

18. The manufacturing method according to claim 14, characterized in that, Also includes: A bonding barrier layer is disposed between the bonding layer and the second reflective layer.

19. The manufacturing method according to claim 16, characterized in that, Also includes: A third trench is formed on the first surface of the epitaxial layer, and the bottom surface of the third trench reaches the surface of the second electrode connection layer. Then, a first pad is formed in the third trench, and the first pad is electrically contacted with the second electrode connection layer.

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