Vcsel chip and method of manufacturing the same

Abstract

Disclosed are a VCSEL chip and a preparation method thereof, wherein the VCSEL chip comprises a plurality of VCSEL light-emitting units and a plurality of light modulation elements which are arranged integrally at the VCSEL light-emitting units at a wafer level and are electrically isolated from each other. Each of the VCSEL light-emitting units comprises a light-emitting body, a positive electrode and a negative electrode which are electrically connected to the light-emitting body, wherein the light-emitting body comprises, from bottom to top, a substrate layer, a P-type electrical contact layer, a P-DBR layer, an active region, a confinement layer, an N-DBR layer and an N-type electrical contact layer, and the confinement layer has a confinement hole corresponding to the active region. The plurality of light modulation elements have a preset structural configuration and cooperate with each other so that the overall divergence angle of the VCSEL chip is greater than or equal to 120°. In this way, the overall divergence angle of the VCSEL chip can be regulated through the structural design of the VCSEL chip itself, so as to expand the scanning domain of the VCSEL chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor lasers, and more specifically to VCSEL chips and their fabrication methods. Background Technology

[0002] A VCSEL (Vertical-Cavity Surface-Emitting Laser) is a semiconductor laser that emits laser light in a vertical direction by forming a resonant cavity in the vertical direction of the substrate. VCSEL chips have characteristics such as low temperature drift, low threshold voltage, high fiber coupling efficiency, and ease of integration and packaging, and are widely used in fields such as intelligent transportation, healthcare, biological detection, and military security.

[0003] In practical industries, VCSEL chips are often used as projection light sources to measure the depth of targets for 3D modeling and depth mapping. In some applications, wide-angle scanning of the target is also required for large-view modeling. For example, when a VCSEL chip is used as the projection light source for automotive LiDAR, this application requires a large scanning area to comprehensively collect road condition information to assist vehicles in route planning, obstacle avoidance, and other functionalities. However, existing VCSEL chips typically have a scanning area within 90°, meaning they can only scan a relatively narrow area of ​​the target.

[0004] To overcome this technical challenge, automotive LiDAR typically equips the VCSEL chip with a rotary motor to rotate it, thereby expanding the scanning range. However, this solution has several drawbacks.

[0005] First, the rotational accuracy of the VCSEL chip depends on the structural stability between it and the rotary motor, as well as the control accuracy of the rotary motor. In other words, if the control accuracy of the rotary motor is poor, or if the coordination between the VCSEL chip and the rotary motor changes, the scanning performance of the VCSEL chip will be affected.

[0006] Secondly, under the action of the rotary motor, the relative positional relationship between the VCSEL chip and the target under test is adjusted. Although this method can expand the scanning domain of the VCSEL chip, the adjustment of the relative positional relationship between the VCSEL chip and the target under test will increase the difficulty of information processing for subsequent 3D modeling.

[0007] Therefore, an optimized solution is needed to extend the scanning domain of the VCSEL chip. Summary of the Invention

[0008] One advantage of this application is that it provides a VCSEL chip and a method for fabricating the same. The VCSEL chip can adjust its overall divergence angle through its own structural design to expand the scanning domain of the VCSEL chip. In other words, the VCSEL chip according to the embodiments of this application can expand its own scanning domain without the need for an external driver.

[0009] Another advantage of this application is that it provides a VCSEL chip and a method for fabricating the same, wherein the VCSEL chip is adapted to high-speed circuits by heterogeneously modifying its own structure.

[0010] To achieve at least one of the above advantages or other advantages and objectives, according to one aspect of this application, a VCSEL chip is provided, comprising:

[0011] A plurality of electrically isolated VCSEL light-emitting units, each VCSEL light-emitting unit including a light-emitting body, a positive electrode and a negative electrode electrically connected to the light-emitting body, wherein the light-emitting body comprises, from bottom to top: a substrate layer, a P-type electrical contact layer, a P-DBR layer, an active region, a confinement layer, an N-DBR layer and an N-type electrical contact layer, the confinement layer having a confinement hole corresponding to the active region; and

[0012] Multiple light modulation elements are integrated at the wafer level on the multiple VCSEL light-emitting units, wherein the multiple light modulation elements have a preset structural configuration and cooperate with each other so that the overall divergence angle of the VCSEL chip is greater than or equal to 120°.

[0013] In the VCSEL chip of this application, the plurality of optical modulation elements have a preset structural configuration and cooperate with each other so that the overall divergence angle of the VCSEL chip is equal to 180°.

[0014] In the VCSEL chip of this application, the plurality of optical modulation elements include at least one concave lens and at least one convex lens.

[0015] In the VCSEL chip of this application, at least a portion of the concave lens is disposed in the VCSEL light-emitting unit located in the edge region of the VCSEL chip.

[0016] In the VCSEL chip of this application, at least a portion of the convex lens is disposed in the VCSEL light-emitting unit located in the central region of the VCSEL chip.

[0017] In the VCSEL chip of this application, at least a portion of the optical modulation elements are located on the optical axis set by the corresponding light-emitting body.

[0018] In the VCSEL chip of this application, at least a portion of the optical modulation elements have their optical centers deviated from the optical axis set by the corresponding light-emitting body.

[0019] In the VCSEL chip of this application, at least some of the convex lenses have different curvatures.

[0020] In the VCSEL chip of this application, the substrate layer is made of P-type semiconductor material.

[0021] According to another aspect of this application, a method for fabricating a VCSEL chip is provided, comprising:

[0022] A structure to be processed is formed, which, from bottom to top, includes a substrate structure, a P-type electrical contact structure, a P-DBR structure, an active region structure, an N-DBR structure, an N-type electrical contact structure, and a layer to be processed.

[0023] The layer to be processed is processed by etching to form multiple optical modulation elements above the N-type electrical contact structure to obtain a chip semi-finished product;

[0024] Multiple negative electrodes are formed that are electrically connected to the N-type electrical contact structure;

[0025] At least a portion of the chip semi-finished product is removed to form a plurality of electrically isolated sub-structural units, each of the sub-structural units comprising, from bottom to top, a P-type electrical contact layer, a P-DBR layer, an active region, an N-DBR layer and an N-type electrical contact layer;

[0026] The plurality of sub-structural units are processed to form a confinement layer with confinement holes above the active region to form a plurality of light-emitting bodies; and

[0027] Multiple positive electrodes are formed and electrically connected to the multiple light-emitting bodies respectively.

[0028] In the VCSEL chip fabrication method of this application, the layer to be processed is processed by an etching process to form a plurality of optical modulation elements above the N-type electrical contact structure to obtain a chip semi-finished product, including: applying an etchable layer on the layer to be processed; shaping the etchable material into a template with a preset shape and size using a mask, wherein the preset shape and size of the template is consistent with the shape and size of the optical modulation elements; and removing at least a portion of the template and the layer to be processed by an etching process, wherein the retained layer to be processed has a shape and size consistent with the template to form the plurality of optical modulation elements.

[0029] In the method for fabricating a VCSEL chip according to this application, processing the plurality of sub-structural units to form a confinement layer with confinement holes above the active region includes: forming a protective layer covering the negative electrode; oxidizing the plurality of sub-structural units; and exposing the negative electrode.

[0030] The further objectives and advantages of this application will become fully apparent from the following description and accompanying drawings.

[0031] These and other objects, features and advantages of this application are fully apparent from the following detailed description, the accompanying drawings and the claims. Attached Figure Description

[0032] These and / or other aspects and advantages of this application will become clearer and more readily understood from the following detailed description of embodiments of the invention taken in conjunction with the accompanying drawings, wherein:

[0033] Figure 1 The illustration shows a schematic diagram of a VCSEL chip according to an embodiment of this application.

[0034] Figure 2 The illustration shows a schematic diagram of a single VCSEL light-emitting unit of a VCSEL chip according to an embodiment of this application.

[0035] Figure 3 The illustration shows a flowchart of a method for fabricating a VCSEL chip according to an embodiment of this application.

[0036] Figure 4A One of the schematic diagrams illustrates the fabrication process of a VCSEL chip according to an embodiment of this application.

[0037] Figure 4B The illustration is a second schematic diagram of the fabrication process of a VCSEL chip according to an embodiment of this application.

[0038] Figure 4C The third illustration shows a schematic diagram of the fabrication process of a VCSEL chip according to an embodiment of this application. Detailed Implementation

[0039] The terms and words used in the following specification and claims are not limited to their literal meaning, but are used solely by the inventors to enable a clear and consistent understanding of this application. Therefore, it will be apparent to those skilled in the art that the following description of various embodiments of this application is provided for illustrative purposes only and not for the purpose of limiting the application as defined in the appended claims and their equivalents.

[0040] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0041] While ordinal numbers such as "first," "second," etc., will be used to describe various components, there is no limitation on which components are used herein. The term is used only to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the teachings of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0042] The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “having” as used in this specification specify the presence of the described features, numbers, steps, operations, components, elements or combinations thereof, without excluding the presence or addition of one or more other features, numbers, steps, operations, components, elements or groups thereof.

[0043] Application Overview

[0044] As mentioned above, VCSEL (Vertical-Cavity Surface-Emitting Laser) is a semiconductor laser that forms a resonant cavity in the vertical direction of a substrate and emits laser light in the vertical direction. With the development of VCSEL technology, VCSEL chips are widely used in fields such as intelligent transportation, healthcare, biological detection, and military security.

[0045] In practical industries, VCSEL chips are often used as projection light sources to measure the depth of targets for 3D modeling and depth mapping. In some applications, wide-angle scanning of the target is also required for large-view modeling. For example, when a VCSEL chip is used as the projection light source for automotive LiDAR, this application requires a large scanning area to comprehensively collect road condition information to assist vehicles in route planning, obstacle avoidance, and other functionalities. However, existing VCSEL chips typically have a scanning area within 90°, meaning they can only scan a relatively narrow area of ​​the target.

[0046] To overcome this technical challenge, automotive LiDAR typically equips the VCSEL chip with a rotary motor to rotate it, thereby expanding the scanning range. However, this solution has several drawbacks.

[0047] First, the rotational accuracy of the VCSEL chip depends on the structural stability between it and the rotary motor, as well as the control accuracy of the rotary motor. In other words, if the control accuracy of the rotary motor is poor, or if the coordination between the VCSEL chip and the rotary motor changes, the scanning performance of the VCSEL chip will be affected.

[0048] Secondly, under the action of the rotary motor, the relative positional relationship between the VCSEL chip and the target under test is adjusted. Although this method can expand the scanning domain of the VCSEL chip, the adjustment of the relative positional relationship between the VCSEL chip and the target under test will increase the difficulty of information processing for subsequent 3D modeling.

[0049] Furthermore, to achieve real-time monitoring of the surrounding environment, the rotating mechanism needs to maintain high-frequency rotation, which is prone to wear. This places high demands on the performance of the rotating mechanism and also indicates that its working performance is difficult to maintain stably.

[0050] In addition, expanding the laser projection range (i.e., scanning domain) of the VCSEL light source by coordinating the VCSEL light source with the driving device is not conducive to the miniaturization of the overall equipment. For example, the main reason why existing lidar equipment is large is that the rotating mechanism occupies a relatively large volume.

[0051] To address the aforementioned technical problems, the technical concept of this application is as follows: The overall divergence angle of the VCSEL chip is controlled through its own structural design to expand the scanning domain of the VCSEL chip. In other words, the VCSEL chip according to the embodiments of this application can expand its own scanning domain (i.e., the laser projection range) without the need for an external driver. Specifically, by arranging an array of light modulation elements with different light modulation performance along the emission paths of multiple VCSEL light-emitting units in the VCSEL chip, the overall divergence angle of the VCSEL chip can be controlled through the light modulation element array, thereby expanding its scanning domain or laser projection range.

[0052] Based on this, according to one aspect of this application, a VCSEL chip is proposed, comprising: a plurality of electrically isolated VCSEL light-emitting units and a plurality of optical modulation elements integrated at the wafer level on the plurality of VCSEL light-emitting units. Each VCSEL light-emitting unit includes a light-emitting body, a positive electrode and a negative electrode electrically connected to the light-emitting body, wherein the light-emitting body comprises, from bottom to top: a substrate layer, a P-type electrical contact layer, a P-DBR layer, an active region, a confinement layer, an N-DBR layer and an N-type electrical contact layer, and the confinement layer has a confinement hole corresponding to the active region. The plurality of optical modulation elements have a preset structural configuration and cooperate with each other such that the overall divergence angle of the VCSEL chip is greater than or equal to 120°.

[0053] According to another aspect of this application, a method for fabricating a VCSEL chip is proposed, comprising: forming a structure to be processed, the structure to be processed comprising, from bottom to top, a substrate structure, a P-type electrical contact structure, a P-DBR structure, an active region structure, an N-DBR structure, an N-type electrical contact structure, and a layer to be processed; processing the layer to be processed by an etching process to form a plurality of optical modulation elements above the N-type electrical contact structure to obtain a chip semi-finished product; forming a plurality of negative electrodes electrically connected to the N-type electrical contact structure; removing at least a portion of the chip semi-finished product to form a plurality of electrically isolated sub-structural units, each of the sub-structural units comprising, from bottom to top, a P-type electrical contact layer, a P-DBR layer, an active region, an N-DBR layer, and an N-type electrical contact layer; processing the plurality of sub-structural units to form a confinement layer with confinement holes above the active region to form a plurality of light-emitting bodies; and forming a plurality of positive electrodes respectively electrically connected to the plurality of light-emitting bodies.

[0054] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0055] Indicative VCSEL chip

[0056] like Figures 1 to 2As shown, a VCSEL chip according to an embodiment of this application is illustrated, wherein the VCSEL chip includes a plurality of electrically isolated VCSEL light-emitting units 10, and a plurality of optical modulation elements 20 integrated at the wafer level on the plurality of VCSEL light-emitting units 10. The plurality of optical modulation elements 20 are disposed on the laser emission path of at least a portion of the plurality of VCSEL light-emitting units 10, so that the optical modulation elements 20 can modulate the laser emitted by the VCSEL light-emitting units 10 to adjust the light emission characteristics of the VCSEL light-emitting units 10 (e.g., laser emission direction, laser wavelength). The overall divergence angle of the VCSEL chip can be increased and the scanning domain of the VCSEL chip can be expanded through the mutual cooperation between the plurality of optical modulation elements 20.

[0057] For example, when the laser emitted by the VCSEL light-emitting unit 10 exits from its top side, the optical modulation element 20 is disposed at the top of the VCSEL light-emitting unit 10, so that the laser emitted from the top of the VCSEL light-emitting unit 10 is modulated by the optical modulation element 20. When the laser emitted by the VCSEL light-emitting unit 10 exits from its bottom side, the optical modulation element 20 is disposed at the bottom of the VCSEL light-emitting unit 10, so that the laser emitted from the bottom of the VCSEL light-emitting unit 10 is modulated by the optical modulation element 20.

[0058] Specifically, in this embodiment, each VCSEL light-emitting unit 10 includes a light-emitting body 11, a positive electrode 13 and a negative electrode 12 electrically connected to the light-emitting body 11. The light-emitting body 11 corresponding to the positive electrode 13 and the negative electrode 12 can be switched on by connecting the positive electrode 13 and the negative electrode 12. In practical applications, all or part of the light-emitting bodies 11 can be selectively illuminated according to actual needs; that is, all or part of the VCSEL chip can be illuminated, allowing the VCSEL chip to adapt to different application scenarios. For example, when a wide-angle scan or all-around illumination of the target is required, the entire VCSEL chip can be lit by turning on all the light-emitting elements 11. When only a specific area of ​​the target needs to be scanned or concentratedly illuminated, a local area of ​​the VCSEL chip can be lit by turning on some of the light-emitting elements 11. In this way, not only can the scanning domain requirements of the VCSEL chip in different scenarios be met, but also the method of lighting up a part of the VCSEL chip can reduce energy consumption and reduce the impact of temperature rise caused by high power on the performance of the VCSEL chip.

[0059] It is worth mentioning that the VCSEL chip can be adapted to high-speed circuits by heterogeneously configuring its light-emitting body 11. Specifically, in this embodiment, the light-emitting body 11 includes, from bottom to top: a substrate layer 111, a P-type electrical contact layer 112, a P-DBR layer 113, an active region 114, a confinement layer 115, an N-DBR layer 116, and an N-type electrical contact layer 117. The light-emitting body 11 can be externally connected to other components, allowing the VCSEL chip to form a circuit system together with other components. In a specific example of this application, the substrate layer 111 is adapted to be connected to an N-type field-effect transistor structure to improve the operating efficiency of the circuit system.

[0060] Those skilled in the art will understand that, compared to P-type field-effect transistor switches, N-type field-effect transistor switches have relatively lower on-resistance, smaller size, and faster switching speed, making them suitable for high-speed circuits. However, in conventional VCSEL chips, the substrate layer 111 is directly connected to the N-type electrical contact layer 117 and the N-DBR layer 116. When the substrate layer 111 and the field-effect transistor structure are conducting, parasitic devices (e.g., parasitic resistance) can easily affect the operating performance (e.g., operating efficiency) of the N-type field-effect transistor switch circuit. In this specific example, the substrate layer 111 is made of P-type semiconductor material (i.e., the substrate layer 111 is a P-type substrate layer 111) to form an N-type field-effect transistor switch with the N-type field-effect transistor structure. The P-type substrate layer 111 is directly connected to the P-type electrical contact layer 112 and the P-DBR layer 113. In this way, the adverse effects of parasitic devices on the N-type field-effect transistor switch circuit can be reduced.

[0061] It is worth mentioning that, in order to achieve electrical isolation between the plurality of VCSEL light-emitting units 10, in a specific example of this application, an isolation trench 102 may be provided between every two VCSEL light-emitting units 10. That is, the VCSEL chip has a plurality of isolation trenches 102 formed between every two VCSEL light-emitting units 10. Specifically, each isolation trench 102 extends through the N-type electrical contact layer 117 to the P-type electrical contact layer 112, so that the plurality of VCSEL light-emitting units 10 are electrically isolated from each other through the plurality of isolation trenches 102.

[0062] In other examples of this application, electrical isolation between the plurality of VCSEL light-emitting units 10 can also be achieved in other ways, and this is not limited to this application. In another specific example of this application, the VCSEL chip further includes a plurality of isolation medium channels located between every two VCSEL light-emitting units 10 and formed doped in the light-emitting body 11 of each VCSEL light-emitting unit 10, so as to electrically isolate the plurality of VCSEL light-emitting units 10 from each other through the plurality of isolation medium channels.

[0063] In this embodiment, the N-DBR layer 116 is composed of N-type doped Al with high aluminum content. x Ga 1-x As (x = 1 to 0) and N-type doped low-aluminum Al x Ga 1-x Alternating layers of As (x = 1 to 0) are formed. The P-DBR layer 113 is composed of p-type doped Al with high aluminum content. x Ga 1-x As (x = 1 to 0) and P-type doped low-aluminum Al x Ga 1-x Alternating layers of As (x = 1 to 0) are formed. In some examples of this application, the materials used to make the N-DBR layer 116 and the P-DBR layer 113 may even contain no aluminum, that is, no aluminum is included. It is worth mentioning that the material selection of the alternating layers depends on the operating wavelength of the laser emitted by the VCSEL light-emitting unit 10, and the optical thickness of the alternating layers is equal to or approximately equal to 1 / 4 of the operating wavelength of the laser.

[0064] The active region 114 is sandwiched between the N-DBR layer 116 and the P-DBR layer 113 to form a resonant cavity. Photons, after being excited, are repeatedly amplified by reflection within the resonant cavity to form laser oscillations, thereby generating laser light. Those skilled in the art will understand that the laser emission direction can be selectively controlled by configuring and designing the N-DBR layer 116 and the P-DBR layer 113. For example, in a specific example of this application, the N-DBR layer 116 and the P-DBR layer 113 are configured such that after the VCSEL light-emitting unit 10 is turned on, the laser light generated by the active region 114 is reflected multiple times within the resonant cavity formed between the N-DBR layer 116 and the P-DBR layer 113 and then emitted from the P-DBR layer 113, i.e., from the bottom side of the VCSEL light-emitting unit 10. In another specific example of this application, the N-DBR layer 116 and the P-DBR layer 113 are configured such that after the VCSEL light-emitting unit 10 is turned on, the laser generated by the active region 114 is reflected multiple times in the resonant cavity formed between the N-DBR layer 116 and the P-DBR layer 113 and then emitted from the N-DBR layer 116, that is, emitted from the top side of the VCSEL light-emitting unit 10.

[0065] The confinement layer 115 has a confinement hole 101 corresponding to the active region 114. The laser generated by the active region 114 is reflected multiple times in the resonant cavity and then passes through the confinement hole 101 before being emitted from the P-DBR layer 113 or the N-DBR layer 116 of the VCSEL light-emitting unit 10.

[0066] In some examples of this application, the confinement layer 115 may be implemented as an oxide confinement layer, which is formed above the active region 114 by an oxidation process. In specific implementations, the oxide confinement layer may be formed as a separate layer above the active region 114. Of course, in other specific embodiments, the oxide confinement layer may also be formed above the active region 114 by oxidizing at least a portion of the region below the P-DBR layer 113, which is not limited to this application. In other examples of this application, the confinement may also be implemented in other forms, for example, as an ion confinement layer (not shown in the figure), which is formed above the active region 114 by an ion planting process, which is not limited to this application.

[0067] In this embodiment, the positive electrode 13 and the negative electrode 12 are electrically connected to the light-emitting body 11. Specifically, the positive electrode 13 and the negative electrode 12 are electrically connected to the P-type electrical contact layer 112 and the N-type electrical contact layer 117, respectively. The specific locations of the positive electrode 13 and the negative electrode 12 are not limited to this application. In one specific example, the positive electrode 13 is located on the side surface of the P-type electrical contact layer 112. In another specific example, the positive electrode 13 is located on the lower surface of the substrate layer 111. In yet another specific example, the positive electrode 13 is located between the substrate layer 111 and the P-type electrical contact layer 112. In other specific examples, the positive electrode 13 may be located at other locations. In one specific example, the negative electrode 12 is located on the upper surface of the N-type electrical contact layer 117. In other specific examples, the negative electrode 12 may be located at other locations.

[0068] The shapes of the positive electrode 13 and the negative electrode 12 are not limited to those specified in this application. In one specific example, the laser generated by the VCSEL light-emitting unit 10 is emitted from the N-DBR layer 116. The negative electrode 12 has an annular cross-section and an emission aperture 103 corresponding to the limiting aperture 101, to prevent the negative electrode 12 from affecting the light emission performance of the VCSEL light-emitting unit 10. In another specific example, the negative electrode 12 has a parallelogram cross-section and is made of a light-transmitting material.

[0069] In this embodiment, not only can different areas of the VCSEL chip be illuminated to adapt to different application scenarios, but the overall divergence angle of the VCSEL chip can also be adjusted with the cooperation of the optical modulation elements 20 to adapt to different application scenarios. Specifically, the plurality of optical modulation elements 20 have a preset structural configuration and cooperate with each other to control the overall divergence angle of the VCSEL chip. Quantitatively, in this embodiment, the overall divergence angle of the VCSEL chip is greater than or equal to 120°. Here, the overall divergence angle of the VCSEL chip refers to the angle formed by the outermost laser beam emitted by the VCSEL chip. In a specific example of this application, the overall divergence angle of the VCSEL chip can reach 180°.

[0070] In one specific example of this application, the plurality of optical modulation elements 20 includes at least one modulation element for converging light (e.g., a convex lens 21) and at least one modulation element for diverging light (e.g., a concave lens). The convex lens 21 can reduce the beam divergence angle of the laser emitted from the VCSEL light-emitting unit 10, and the concave lens can increase the beam divergence angle of the laser emitted from the VCSEL light-emitting unit 10. It should be understood that in other examples of this application, the plurality of optical modulation elements 20 may include only the modulation element for converging light (e.g., a convex lens 21), or only the modulation element for diverging light (e.g., a concave lens), and this is not limited to this application.

[0071] The overall divergence angle or scanning domain of the VCSEL chip can be adjusted by utilizing the structure of the optical modulation element 20 and the illuminated area of ​​the VCSEL chip.

[0072] When the entire area of ​​the VCSEL chip is illuminated, the divergence angle of the light beam emitted from the VCSEL light-emitting unit 10 can be relatively increased by providing the concave lens on at least a portion of the outermost VCSEL light-emitting unit 10 of the VCSEL chip, thereby increasing the overall divergence angle of the VCSEL chip. Conversely, the divergence angle of the light beam emitted from the VCSEL light-emitting unit 10 can be relatively reduced by providing the convex lens 21 on at least a portion of the outermost VCSEL light-emitting unit 10 of the VCSEL chip, thereby decreasing the overall divergence angle of the VCSEL chip.

[0073] When a localized area of ​​the VCSEL chip is illuminated, the divergence angle of the light beam emitted from the VCSEL light-emitting unit 10 can be relatively increased by providing the concave lens on at least a portion of the VCSEL light-emitting unit 10 in that localized area of ​​the VCSEL chip, thereby increasing the overall divergence angle of the VCSEL chip. Conversely, the divergence angle of the light beam emitted from the VCSEL light-emitting unit 10 can be relatively reduced by providing the convex lens 21 on at least a portion of the VCSEL light-emitting unit 10 in that localized area of ​​the VCSEL chip, thereby reducing the overall divergence angle of the VCSEL chip, thus enabling concentrated illumination of a specific area of ​​the target being measured.

[0074] Accordingly, in a specific example of this application, at least a portion of the concave lens is disposed on the VCSEL light-emitting unit 10 located in the edge region of the VCSEL chip, and at least a portion of the convex lens 21 is disposed on the VCSEL light-emitting unit 10 located in the middle region of the VCSEL chip.

[0075] Furthermore, the divergence angle or scanning range of the laser emitted by a single VCSEL light-emitting unit 10 can be controlled by adjusting the curvature of the convex lens 21 and / or the concave lens, thereby controlling the overall divergence angle or scanning range of the VCSEL chip.

[0076] In this embodiment, at least some of the convex lenses 21 (or concave lenses) have different radii of curvature. The greater the curvature and the smaller the radius of curvature of the convex lens 21, the stronger its ability to converge light. The greater the curvature and the smaller the radius of curvature of the concave lens, the stronger its ability to diverge light. The smaller the radius of curvature of the convex lens 21 corresponding to the outermost VCSEL light-emitting unit 10 of the VCSEL chip, the smaller the overall divergence angle of the VCSEL chip. The smaller the radius of curvature of the concave lens corresponding to the outermost VCSEL light-emitting unit 10 of the VCSEL chip, the larger the overall divergence angle of the VCSEL chip. Of course, the radii of curvature of all the convex lenses 21 or concave lenses disposed in the plurality of VCSEL light-emitting units 10 can be the same, which is not limited to this application.

[0077] In a specific example of this application, the curvature of the concave lenses disposed on the plurality of VCSEL light-emitting units 10 increases sequentially in the direction extending outward from the center of the VCSEL chip. Correspondingly, the divergence angle of the plurality of VCSEL light-emitting units 10 increases sequentially in the direction extending outward from the center of the VCSEL chip, which not only makes the overall divergence angle of the VCSEL chip relatively large, but also makes the laser emitted by the plurality of VCSEL light-emitting units 10 form a continuous scanning field.

[0078] Furthermore, the divergence angle of the laser emitted from a single VCSEL light-emitting unit 10 can be controlled by the relative positional relationship between the light modulation element 20 and the corresponding light-emitting body 11, thereby controlling the overall divergence angle of the VCSEL chip.

[0079] When the light modulation element 20 is the convex lens 21 or the concave lens, the light modulation element 20 has an optical center, and the propagation path of light rays passing through the optical center remains unchanged. The light-emitting body 11 has an optical axis, which can be defined as the straight line containing the longitudinal central axis of the active region 114 of the light-emitting body 11. The light modulation element 20 can be disposed in the VCSEL light-emitting unit 10 with its optical center located on the optical axis set by the light-emitting body 11, or it can be disposed in the VCSEL light-emitting unit 10 with its optical center deviating from the optical axis set by the light-emitting body 11.

[0080] In one specific example of this application, at least a portion of the convex lenses 21 of the plurality of light modulation elements 20 have their optical centers located on the optical axis set by the corresponding light-emitting body 11, while the optical centers of another portion of the convex lenses 21 are offset from the optical axis set by the corresponding light-emitting body 11. Similarly, at least a portion of the concave lenses of the plurality of light modulation elements 20 have their optical centers located on the optical axis set by the corresponding light-emitting body 11, while the optical centers of another portion of the concave lenses are offset from the optical axis set by the corresponding light-emitting body 11.

[0081] When the optical center of the convex lens 21 (or the concave lens) deviates from the optical axis set by the corresponding light-emitting body 11, the laser emitted from the light-emitting body 11, after being modulated by the convex lens 21 (or the concave lens), has its projection direction deviate from the direction in which the optical center of the convex lens 21 (or the concave lens) deviates from the optical axis of the light-emitting body 11.

[0082] Specifically, when the optical center of the convex lens 21 (or concave lens) corresponding to the outermost VCSEL light-emitting unit 10 of the VCSEL chip shifts outward, compared to when the optical center of the convex lens 21 (or concave lens) is located on the optical axis set by the light-emitting body 11, the laser projection direction deviates outward, and the overall divergence angle of the VCSEL chip increases relatively.

[0083] It should be understood that in other examples of this application, the optical centers of all the convex lenses 21 of the plurality of light modulation elements 20 may be offset from the optical axis set by the corresponding light-emitting body 11. The optical centers of all the concave lenses of the plurality of light modulation elements 20 may also be offset from the optical axis set by the corresponding light-emitting body 11, which is not limited to this application.

[0084] When the optical center of the convex lens 21 corresponding to the outermost VCSEL light-emitting unit 10 of the VCSEL chip shifts outward, the smaller the curvature of the convex lens 21, the more outward the direction of laser projection, and the larger the overall divergence angle of the VCSEL chip. The overall divergence angle of the VCSEL chip can be adjusted according to the structure of the dimming element and the relative positional relationship between the light modulation element 20 and its corresponding light-emitting body 11 to regulate the modulation law of laser generation.

[0085] It should be understood that, compared to controlling the laser projection range of the VCSEL light source by using a driving device (e.g., a rotary motor) to achieve relative rotation of the VCSEL chip, the laser projection range of the VCSEL chip can be controlled more stably by providing light modulation elements 20 on at least a portion of the VCSEL light-emitting units 10 of the VCSEL chip. Simultaneously, the increased overall divergence angle of the VCSEL chip through its own structure simplifies the method of expanding the laser projection range of the VCSEL light source, reducing its application cost.

[0086] In summary, the VCSEL chip based on the embodiments of this application is explained. The VCSEL chip increases its overall divergence angle through its own structural design, thereby expanding the scanning domain of the VCSEL chip.

[0087] Schematic fabrication method of VCSEL chip

[0088] According to another aspect of this application, a method for fabricating a VCSEL chip is also provided, which is used to fabricate the VCSEL chip described above. (Refer to the accompanying drawings.) Figures 3 to 4C The fabrication method of the VCSEL chip according to the embodiments of this application is explained. As shown in Figure 4, the method for fabricating a VCSEL chip according to an embodiment of this application includes: S110, forming a structure to be processed, the structure to be processed including, from bottom to top, a substrate structure, a P-type electrical contact structure, a P-DBR structure, an active region structure, an N-DBR structure, an N-type electrical contact structure, and a layer to be processed; S120, processing the layer to be processed by an etching process to form a plurality of optical modulation elements above the N-type electrical contact structure to obtain a chip semi-finished product; S130, forming a plurality of negative electrodes electrically connected to the N-type electrical contact structure; S140, removing at least a portion of the chip semi-finished product to form a plurality of electrically isolated sub-structural units, each of the sub-structural units including, from bottom to top, a P-type electrical contact layer, a P-DBR layer, an active region, an N-DBR layer, and an N-type electrical contact layer; S150, processing the plurality of sub-structural units to form a confinement layer with confinement holes above the active region to form a plurality of light-emitting bodies; and S160, forming a plurality of positive electrodes respectively electrically connected to the plurality of light-emitting bodies.

[0089] Figures 4A to 4C The illustration shows a schematic diagram of the fabrication process of the VCSEL chip according to an embodiment of this application. Figure 4AAs shown, in step S110, a structure to be processed 100 is formed. Specifically, the substrate structure 110, the P-type electrical contact structure 120, the P-DBR structure 130, the active region structure 140, the N-DBR structure 160, the N-type electrical contact structure 170, and the layer to be processed 180 are formed by semiconductor growth process.

[0090] In one specific example of this application, the substrate structure 110 is made of a P-type semiconductor material, suitable for connection with an N-type field-effect transistor structure, so that the resulting VCSEL chip is adapted to high-speed circuits. The material for the layer to be processed 180 is selected from one of the following: GaN, AlN, Al... X Ga 1-X As (x = 0~1), lnP, Al X Ga 1-X AsSb (x=0~1), AlInAs, InGaAsP.

[0091] In step S120, the layer 180 to be processed is treated by an etching process to form a plurality of optical modulation elements 20 above the N-type electrical contact structure 170 to obtain a chip semi-finished product 200. Specifically, firstly, an etchable layer is applied to the layer 180 to be processed, wherein the material of the etchable layer may be a photoresist layer. Next, the etchable layer is exposed through a mask with a preset pattern to remove corresponding portions of the etchable layer based on the preset pattern, wherein the retained etchable layer forms a template 800 with a preset shape and size, wherein the preset shape and size of the template 800 are consistent with the shape and size of the optical modulation elements 20. Then, at least a portion of the template 800 and the layer 180 to be processed is removed by an etching process, wherein the retained layer 180 to be processed has a shape and size consistent with the template 800 to form the plurality of optical modulation elements 20, wherein the plurality of optical modulation elements 20 include a convex lens 21 and a concave lens.

[0092] That is, step S120 includes: applying an etchable layer to the layer to be processed 180; shaping the etchable material into a template 800 with a preset shape and size using a mask, wherein the preset shape and size of the template 800 is consistent with the shape and size of the optical modulation element 20; and removing at least a portion of the template 800 and the layer to be processed 180 by an etching process, wherein the remaining layer to be processed 180 has a shape and size consistent with the template 800, to form the plurality of optical modulation elements 20.

[0093] Specifically, a portion of the template 800 and the layer 180 to be processed can be removed using either a dry etching process or a wet etching process. Accordingly, the retained layer 180 to be processed has a shape and size consistent with the template 800 to form the optical modulation element 20. During the etching process, to ensure that the ultimately retained layer 180 to be processed has a shape and size consistent with the template 800, the etching speed and the etched area should be precisely controlled.

[0094] It is worth mentioning that during the etching process of removing a portion of the layer 180 to be processed, at least a portion of the P-type electrical contact structure 120 is exposed, forming an electrical connection region capable of electrical connection. Accordingly, the structure 100 to be processed after etching forms the chip semi-finished product 200, wherein the chip semi-finished product 200 includes, from bottom to top, the substrate structure 110, the P-type electrical contact structure 120, the P-DBR structure 130, the active region structure 140, the N-DBR structure 160, the N-type electrical contact structure 170, and the optical modulation element 20.

[0095] It is worth mentioning that the overall divergence angle of the final VCSEL chip can be controlled by designing the structure and position of the optical modulation element 20. For example, in a specific example of this application, at least one concave lens is arranged in the region near the outer edge of the chip semi-finished product 200 to expand the overall divergence angle of the final VCSEL chip, and at least one convex lens 21 is arranged in a local region of the chip semi-finished product 200 to reduce the overall divergence angle of the VCSEL chip when the local region is lit.

[0096] In step S130, a plurality of negative electrodes 12 electrically connected to the N-type electrical contact structure 170 are formed. Specifically, the plurality of negative electrodes 12 electrically connected to the N-type electrical contact structure 170 are formed by an electroplating process, wherein the plurality of negative electrodes 12 are formed in the electrical connection region of the N-type electrical contact structure 170 of the chip semi-finished product 200. It should be understood that the plurality of negative electrodes 12 may also be formed on the chip semi-finished product 200 by other processes, and this is not limited to this application.

[0097] Preferably, to ensure the light emission performance of the VCSEL chip, the negative electrode 12 of the N-type electrical contact structure 170 is annular in shape, and the negative electrode 12 has a light emission aperture 103 corresponding to the active region structure 140. The negative electrode 12 is formed around the optical modulation element 20, and correspondingly, the optical modulation element 20 corresponds to the light emission aperture 103 of the negative electrode 12 to adjust the overall divergence angle of the VCSEL chip and expand the scanning domain (i.e., the laser projection range) of the VCSEL chip.

[0098] In step S140, at least a portion of the chip semi-finished product 200 is removed to form a plurality of electrically isolated sub-structural units 300. Each sub-structural unit 300 includes, from bottom to top, a P-type electrical contact layer 112, a P-DBR layer 113, an active region 114, an N-DBR layer 116, and an N-type electrical contact layer 117. Specifically, at least a portion of the chip semi-finished product 200 is removed by an etching process to form a plurality of mutually spaced sub-structural units 300. An isolation trench 102 is formed in the spacer region between every two sub-structural units 300, thereby achieving electrical isolation between the plurality of sub-structural units 300.

[0099] In step S150, the plurality of sub-structural units 300 are processed to form a confinement layer 115 with a confinement hole 101 above the active region 114. Specifically, the confinement layer 115 can be formed by an oxidation process. First, in order to protect the negative electrode 12, a protective layer 900 covering the negative electrode 12 needs to be formed before oxidizing the sub-structural units 300. Next, the plurality of sub-structural units 300 are oxidized. After the sub-structural units 300 are oxidized, a portion of the N-DBR layer 116 is oxidized to form the confinement layer 115 above the active region 114. The plurality of sub-structural units 300 after forming the confinement layer 115 form a plurality of light-emitting bodies 11 with the substrate structure. The confinement hole 101 corresponds to the light-emitting hole 103. Then, the negative electrode 12 is exposed. Specifically, the negative electrode 12 can be exposed by removing at least a portion of the protective layer 900 covering the negative electrode 12. That is, step S160 includes: forming a protective layer 900 covering the negative electrode 12; oxidizing the plurality of sub-structural units 300; and exposing the negative electrode 12.

[0100] It is worth mentioning that the confinement layer 115 can be formed by other processes, for example, the ion confinement layer above the active region 114 can be formed by an ion planting process, and this is not limited to the present application.

[0101] Accordingly, the multiple sub-structural units 300 formed after the confinement layer 115 are formed together with the substrate structure to form multiple light-emitting bodies 11. Each light-emitting body 11 includes, from bottom to top, a substrate layer 111, a P-type electrical contact layer 112, a P-DBR layer 113, an active region 114, a confinement layer 115, an N-DBR layer 116, and an N-type electrical contact layer 117.

[0102] In step S160, a plurality of positive electrodes 13 are formed, each electrically connected to one of the plurality of light-emitting bodies 11. Specifically, the plurality of positive electrodes 13 are formed by an electroplating process, and the positive electrodes 13 are electrically connected to the P-type electrical contact layer 112. Other processes may also be used to form the plurality of positive electrodes 13, and this is not limited to the present application.

[0103] In summary, the fabrication method of the VCSEL chip based on the embodiments of this application has been clarified. The fabrication method of the VCSEL chip controls its overall divergence angle by designing the junction of the VCSEL chip, thereby expanding the scanning domain of the VCSEL chip.

[0104] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

Claims

1. A VCSEL chip, characterized in that, include: A plurality of electrically isolated VCSEL light-emitting units, each VCSEL light-emitting unit including a light-emitting body, a positive electrode and a negative electrode electrically connected to the light-emitting body, wherein the light-emitting body comprises, from bottom to top: a substrate layer, a P-type electrical contact layer, a P-DBR layer, an active region, a confinement layer, an N-DBR layer and an N-type electrical contact layer, the confinement layer having a confinement hole corresponding to the active region; the substrate layer is made of a P-type semiconductor material; and Multiple light modulation elements are integrated at the wafer level on the multiple VCSEL light-emitting units, wherein the multiple light modulation elements have a preset structural configuration and cooperate with each other so that the overall divergence angle of the VCSEL chip is greater than or equal to 120°. The plurality of optical modulation elements include at least one concave lens and at least one convex lens; at least a portion of the concave lens is disposed on the VCSEL light-emitting unit located in the edge region of the VCSEL chip; at least a portion of the convex lens is disposed on the VCSEL light-emitting unit located in the central region of the VCSEL chip; the curvature of the concave lenses disposed on the plurality of VCSEL light-emitting units increases sequentially in the direction extending outward from the center of the VCSEL chip.

2. The VCSEL chip according to claim 1, wherein, The plurality of optical modulation elements have a preset structural configuration and cooperate with each other so that the overall divergence angle of the VCSEL chip is equal to 180°.

3. The VCSEL chip according to claim 1, wherein, At least a portion of the optical modulation element has its optical center located on the optical axis set by the corresponding light-emitting body.

4. The VCSEL chip according to claim 1, wherein, At least a portion of the optical modulation element has its optical center deviated from the optical axis set by the corresponding light-emitting body.

5. The VCSEL chip according to claim 1, wherein, At least some of the convex lenses have different curvatures.

6. A method for fabricating a VCSEL chip, characterized in that, include: A structure to be processed is formed, which, from bottom to top, includes a substrate structure, a P-type electrical contact structure, a P-DBR structure, an active region structure, an N-DBR structure, an N-type electrical contact structure, and a layer to be processed; the substrate structure is made of a P-type semiconductor material. The layer to be processed is processed by etching to form multiple optical modulation elements above the N-type electrical contact structure to obtain a chip semi-finished product; Multiple negative electrodes are formed that are electrically connected to the N-type electrical contact structure; At least a portion of the chip semi-finished product is removed to form a plurality of electrically isolated sub-structural units, each of the sub-structural units comprising, from bottom to top, a P-type electrical contact layer, a P-DBR layer, an active region, an N-DBR layer and an N-type electrical contact layer; The plurality of sub-structural units are processed to form a confinement layer with confinement holes above the active region to form a plurality of light-emitting bodies; as well as Multiple positive electrodes are formed, each electrically connected to one of the multiple light-emitting bodies; The plurality of optical modulation elements include at least one concave lens and at least one convex lens; at least a portion of the concave lens is disposed in the VCSEL light-emitting unit located in the edge region of the VCSEL chip; at least a portion of the convex lens is disposed in the VCSEL light-emitting unit located in the middle region of the VCSEL chip; the curvature of the concave lenses disposed on the plurality of VCSEL light-emitting units increases sequentially in the direction extending outward from the center of the VCSEL chip.

7. The method for fabricating a VCSEL chip according to claim 6, wherein, The layer to be processed is treated by an etching process to form multiple optical modulation elements above the N-type electrical contact structure, thereby obtaining a chip semi-finished product, including: An etchable layer is applied to the layer to be processed; The etchable material is shaped into a template with a preset shape and size using a mask, wherein the preset shape and size of the template are consistent with the shape and size of the optical modulation element; and At least a portion of the template and the layer to be processed are removed by an etching process, wherein the remaining layer to be processed has the same shape and size as the template to form the plurality of optical modulation elements.

8. The method for fabricating a VCSEL chip according to claim 6, wherein, Processing the plurality of sub-structural units to form a confinement layer with confinement holes above the active region includes: A protective layer is formed covering the negative electrode; Oxidize the plurality of substructural units; and Expose the negative electrode.

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