A low power consumption gate voltage bootstrap charge pump circuit
Patent Information
- Application Number
- CN202211590070.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-12
- Publication Date
- 2026-10-27
- Estimated Expiration
- 2042-12-12
AI Technical Summary
[0002]随着便携式电池驱动消费类电子产品的快速发展，为了延长电池寿命或者充电时间间隔，需要尽可能减小电荷泵的静态电流；同时基于半导体制造工艺和集成电路设计能力不断提高，片上系统(SOC)技术成为当前大规模集成电路的发展趋势，所使用电源电压通常较低(5V以下)，为高压电荷泵电路设计带来了困难
[0016]在本发明提供的一种低功耗栅压自举电荷泵电路中，电荷泵电路与栅压自举电路、微电流源偏置电路构成负反馈控制环路，使得保证电荷泵电路工作偏置在较低的静态电流模式下；所述栅压自举电路将电荷泵电路的时钟控制信号逻辑电平倍增，使得在较低电源输入下控制开关管能够完全关闭与开启，使得每一级电荷转移效率提高，抑制电荷共享的发生，实现将低电压升压至高电压输出。本发明的电路结构简单，具有低功耗、电荷转移效率高的特点，可实现将低电压升压至高电压稳定输出。
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Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a low-power gate voltage bootstrap charge pump circuit. Background Technology
[0002] With the rapid development of portable battery-powered consumer electronics, it is necessary to minimize the quiescent current of charge pumps in order to extend battery life or reduce charging intervals. Meanwhile, due to continuous improvements in semiconductor manufacturing processes and integrated circuit design capabilities, System-on-Chip (SoC) technology has become the current trend in large-scale integrated circuit development, typically using lower power supply voltages (below 5V), which poses challenges to the design of high-voltage charge pump circuits. Therefore, designing a high-voltage output charge pump circuit with low power consumption and high-efficiency charge transfer capabilities is of paramount importance. Summary of the Invention
[0003] The purpose of this invention is to provide a low-power gate voltage bootstrap charge pump circuit to solve the problems in the prior art.
[0004] To solve the above-mentioned technical problems, the present invention provides a circuit including a charge pump circuit, a gate voltage bootstrap circuit, and a micro-current source bias circuit.
[0005] The microcurrent source bias circuit defines the bias current through the bias voltage, and then mirrors it to the gate voltage bootstrap circuit through the current mirror structure to provide an initialization state for its startup.
[0006] The gate voltage bootstrap circuit enables the PMOS switch to be turned on and off by multiplying the clock level and controlling the Y-series clock signal of the charge pump circuit. The Y-series clock signal is generated by the logic control circuit.
[0007] The charge pump circuit uses a four-stage PMOS transistor series configuration to boost the low power supply voltage to the required high voltage output.
[0008] In one embodiment, the micro current source bias circuit includes a current source I1, NMOS transistors MN1 to MN5, and PMOS transistors MP1 to MP2;
[0009] The positive terminal of current source I1 is connected to power supply VDD, and the negative terminal is connected to the drain terminal of NMOS transistor MN1. The gate terminal of NMOS transistor MN1 is connected to its own drain terminal, and the source terminal is connected to common ground GND. The gate terminal of NMOS transistor MN2 is connected to the gate terminal of NMOS transistor MN1, and the drain terminal is simultaneously connected to the gate terminal and drain terminal of PMOS transistor MP1. The source terminal of NMOS transistor MN2 is connected to common ground GND. The source terminal of PMOS transistor MP1 is connected to power supply VDD. The source terminal of PMOS transistor MP2 is connected to power supply VDD, and the gate terminal is connected to the gate terminal of PMOS transistor MP1. The drain terminal is simultaneously connected to the gate terminal and drain terminal of NMOS transistor MN3. The source terminal of NMOS transistor MN3 is connected to common ground GND. The gate terminal of NMOS transistor MN4 is connected to the gate terminal of NMOS transistor MN3, and the drain terminal is connected to the gate voltage bootstrap circuit. The source terminal is connected to common ground GND. The gate terminal of NMOS transistor MN5 is connected to the gate terminal of NMOS transistor MN3, and the drain terminal is connected to the gate voltage bootstrap circuit. The source terminal is connected to common ground GND.
[0010] In one embodiment, the gate bootstrap circuit includes PMOS transistors MP3 to MP9, capacitors C1 to C6, inverters INV1 to INV2, and an NPN BJT transistor Q1.
[0011] The source terminal of PMOS transistor MP3 is connected to the output voltage Vout of the charge pump circuit, and its gate terminal is connected to its own drain terminal, and is also connected to the source terminals of PMOS transistors MP4 and MP5. The gate terminal of PMOS transistor MP4 is connected to its own drain terminal, and is connected to the drain terminal of NMOS transistor MN4 in the micro-current source bias circuit. The upper plate of capacitor C1 is connected to the drain terminal of PMOS transistor MP4, and the lower plate is connected to the first output Y0 of the logic control circuit. The input terminal of inverter INV1 is connected to the first output Y0 of the logic control circuit, and the output terminal is connected to the lower plate of capacitor C2. The upper plate of capacitor C2 is connected to the drain terminal of PMOS transistor MP5, the gate terminal of PMOS transistor MP5 is connected to the gate terminal of PMOS transistor MP4, and the source terminal is connected to the source terminal of PMOS transistor MP4.
[0012] The base and collector of the NPN type BJT transistor Q1 are connected together and connected to the output voltage Vout of the charge pump circuit. The emitter is connected to the source terminals of both PMOS transistor MP6 and PMOS transistor MP7. The drain terminal of PMOS transistor MP6 is connected to its own gate terminal and connected to the drain terminal of NMOS transistor MN5 in the micro-current source bias circuit.
[0013] The upper plate of capacitor C3 is connected to the drain of PMOS transistor MN6, and the lower plate is connected to the second output Y1N of the logic control circuit. The input of inverter INV2 is connected to the second output Y1N of the logic control circuit, and its output is connected to the lower plate of capacitor C4. The upper plate of capacitor C4 is connected to the drain of PMOS transistor MP7. The gate of PMOS transistor MP7 is connected to the gate of PMOS transistor MP6, and its source is connected to the source of PMOS transistor MP6. The gate of PMOS transistor MP8 is connected to the third output Y1 of the logic control circuit, its drain is connected to the power supply VDD, and its source is connected to the upper plate of capacitor C5. The lower plate of capacitor C5 is connected to the fourth output Y2 of the logic control circuit. The gate of PMOS transistor MP9 is connected to the fifth output Y0N of the logic control circuit, its drain is connected to the source of PMOS transistor MP8, and its source is connected to the upper plate of capacitor C6. The lower plate of capacitor C6 is connected to the common ground GND, and its upper plate is connected to the power input VDD of both inverters INV1 and INV2. DD_INV Connected.
[0014] In one embodiment, the charge pump circuit includes capacitors C7 to C11 and PMOS transistors MP10 to MP13;
[0015] The upper plate of capacitor C7 is connected to power supply VDD, and the lower plate is connected to common ground GND; the gate of PMOS transistor MP10 is connected to the output of inverter INV1, the drain is connected to power supply VDD, and the source is connected to the upper plate of capacitor C8; the lower plate of capacitor C8 is connected to the sixth output Y2N of the logic control circuit, and the upper plate is connected to the drain of PMOS transistor MP11; the gate of PMOS transistor MP11 is connected to the output of inverter INV2, the drain is connected to the source of PMOS transistor MP10, and the source is connected to the upper plate of capacitor C9; the upper plate of capacitor C9 is connected to the drain of PMOS transistor MP12, and the lower plate is connected to the lower plate of PMOS transistor MP12. The fourth output Y2 of the logic control circuit is connected to the board; the gate of PMOS transistor MP12 is connected to the drain of PMOS transistor MP5, the drain is connected to the source of PMOS transistor MP11, and the source is connected to the upper plate of capacitor C10; the upper plate of capacitor C10 is connected to the drain of PMOS transistor MP13, and the lower plate is connected to the sixth output Y2N of the logic control circuit; the gate of PMOS transistor MP13 is connected to the drain of PMOS transistor MP7, the drain is connected to the source of PMOS transistor MP12, and the source is connected to the upper plate of capacitor C11; the upper plate of capacitor C11 is connected to the output voltage Vout, and the lower plate is connected to the common ground GND.
[0016] In the low-power gate-voltage bootstrap charge pump circuit provided by this invention, the charge pump circuit, the gate-voltage bootstrap circuit, and the micro-current source bias circuit form a negative feedback control loop, ensuring that the charge pump circuit operates under a low quiescent current mode. The gate-voltage bootstrap circuit multiplies the logic level of the clock control signal of the charge pump circuit, enabling the control switch to be completely turned off and on under low power input conditions. This improves the charge transfer efficiency of each stage, suppresses charge sharing, and achieves a low-voltage boost to a high-voltage output. The circuit structure of this invention is simple, featuring low power consumption and high charge transfer efficiency, and can achieve a stable high-voltage boost from low voltage. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of a low-power gate voltage bootstrap charge pump circuit provided by the present invention.
[0018] Figure 2 This is a timing diagram of the normal operation logic control for a low-power gate voltage bootstrap charge pump circuit provided by the present invention. Detailed Implementation
[0019] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the low-power gate voltage bootstrap charge pump circuit proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.
[0020] This invention provides a low-power gate voltage bootstrap charge pump circuit, the principle and structure of which are as follows: Figure 1 As shown, the circuit includes a micro-current source bias circuit, a gate voltage bootstrap circuit, and a charge pump circuit. The micro-current source bias circuit defines the bias current through a bias voltage, and then mirrors it to the gate voltage bootstrap circuit through a current mirror structure, providing an initialization state for the gate voltage bootstrap circuit to start. The gate voltage bootstrap circuit controls the PMOS switching transistors by multiplying the clock level and controlling the Y-series clock signal of the charge pump circuit. The Y-series clock signal is generated by a logic control circuit. The charge pump circuit uses a four-stage PMOS transistor series configuration, which can boost the low supply voltage to the required high voltage output.
[0021] Please continue reading. Figure 1The micro-current source bias circuit includes a current source I1, NMOS transistors MN1-MN5, and PMOS transistors MP1-MP2. The positive terminal of current source I1 is connected to the power supply VDD, and the negative terminal is connected to the drain of NMOS transistor MN1. The gate of NMOS transistor MN1 is connected to its own drain, and the source terminal is connected to the common ground GND. The gate of NMOS transistor MN2 is connected to the gate of NMOS transistor MN1, and its drain is connected to both the gate and drain of PMOS transistor MP1. The source terminal of NMOS transistor MN2 is connected to the common ground GND. The source terminal of PMOS transistor MP1 is connected to the power supply VDD. The source of transistor MP2 is connected to power supply VDD, its gate is connected to the gate of PMOS transistor MP1, and its drain is connected to both the gate and drain of NMOS transistor MN3. The source of NMOS transistor MN3 is connected to common ground GND. The gate of NMOS transistor MN4 is connected to the gate of NMOS transistor MN3, its drain is connected to the drain of PMOS transistor MP4 in the gate voltage bootstrap circuit, and its source is connected to common ground GND. The gate of NMOS transistor MN5 is connected to the gate of NMOS transistor MN3, its drain is connected to the drain of PMOS transistor MP6 in the gate voltage bootstrap circuit, and its source is connected to common ground GND.
[0022] The gate voltage bootstrap circuit includes PMOS transistors MP3-MP9, capacitors C1-C6, inverters INV1-INV2, and an NPN BJT transistor Q1. The source terminal of PMOS transistor MP3 is connected to the output voltage Vout of the charge pump circuit, and its gate terminal is connected to its own drain terminal, and simultaneously connected to the source terminals of PMOS transistors MP4 and MP5. The gate terminal of PMOS transistor MP4 is connected to its own drain terminal, and also connected to the drain terminal of NMOS transistor MN4 in the micro-current source bias circuit. The upper plate of capacitor C1 is connected to the drain terminal of PMOS transistor MP4, and the lower plate is connected to the first output Y0 of the logic control circuit. Inverter INV1... The input terminal of V1 is connected to the first output Y0 of the logic control circuit, and the output terminal is connected to the lower plate of capacitor C2; the upper plate of capacitor C2 is connected to the drain terminal of PMOS transistor MP5, the gate terminal of PMOS transistor MP5 is connected to the gate terminal of PMOS transistor MP4, and the source terminal is connected to the source terminal of PMOS transistor MP4; the base and collector of NPN type BJT transistor Q1 are connected and connected to the output voltage Vout of the charge pump circuit, and the emitter is connected to the source terminal of PMOS transistor MP6 and the source terminal of PMOS transistor MP7; the drain terminal of PMOS transistor MP6 is connected to its own gate terminal and connected to the drain terminal of NMOS transistor MN5 in the micro-current source bias circuit. The upper plate of capacitor C3 is connected to the drain of PMOS transistor MN6, and the lower plate is connected to the second output Y1N of the logic control circuit. The input of inverter INV2 is connected to the second output Y1N of the logic control circuit, and its output is connected to the lower plate of capacitor C4. The upper plate of capacitor C4 is connected to the drain of PMOS transistor MP7. The gate of PMOS transistor MP7 is connected to the gate of PMOS transistor MP6, and its source is connected to the source of PMOS transistor MP6. The gate of PMOS transistor MP8 is connected to the third output Y1 of the logic control circuit, its drain is connected to the power supply VDD, and its source is connected to the upper plate of capacitor C5. The lower plate of capacitor C5 is connected to the fourth output Y2 of the logic control circuit. The gate of PMOS transistor MP9 is connected to the fifth output Y0N of the logic control circuit, its drain is connected to the source of PMOS transistor MP8, and its source is connected to the upper plate of capacitor C6. The lower plate of capacitor C6 is connected to the common ground GND, and its upper plate is connected to the power input VDD of both inverters INV1 and INV2. DD_INV Connected.
[0023] The charge pump circuit includes capacitors C7-C11 and PMOS transistors MP10-MP13. The upper plate of capacitor C7 is connected to power supply VDD, and the lower plate is connected to common ground GND. The gate of PMOS transistor MP10 is connected to the output of inverter INV1, its drain is connected to power supply VDD, and its source is connected to the upper plate of capacitor C8. The lower plate of capacitor C8 is connected to the sixth output Y2N of the logic control circuit, and its upper plate is connected to the drain of PMOS transistor MP11. The gate of PMOS transistor MP11 is connected to the output of inverter INV2, its drain is connected to the source of PMOS transistor MP10, and its source is connected to the upper plate of capacitor C9. The upper plate of capacitor C9... The upper plate is connected to the drain of PMOS transistor MP12, and the lower plate is connected to the fourth output Y2 of the logic control circuit; the gate of PMOS transistor MP12 is connected to the drain of PMOS transistor MP5, the drain is connected to the source of PMOS transistor MP11, and the source is connected to the upper plate of capacitor C10; the upper plate of capacitor C10 is connected to the drain of PMOS transistor MP13, and the lower plate is connected to the sixth output Y2N of the logic control circuit; the gate of PMOS transistor MP13 is connected to the drain of PMOS transistor MP7, the drain is connected to the source of PMOS transistor MP12, and the source is connected to the upper plate of capacitor C11; the upper plate of capacitor C11 is connected to the output voltage Vout, and the lower plate is connected to the common ground GND.
[0024] The detailed working process of this invention is as follows:
[0025] The micro-current source bias circuit generates a bias current I1 under the action of power supply VDD. The bias current I1 is replicated to the drain of NMOS transistor MN2 via a current mirror circuit composed of NMOS transistors MN1 and MN2. Then, it is mirrored to the drain of PMOS transistor MP2 via a current mirror structure composed of PMOS transistors MP1 and MP2. Finally, the bias current I1 is replicated to the drains of NMOS transistors MN4 and MN5 via a current mirror circuit composed of NMOS transistors MN3, MN4, and MN5. At this time, the output voltage Vout of the charge pump circuit has not yet been established. The NMOS transistors MN4 and MN5, capacitor C1, and capacitor C2 provide the initialization state for the startup of the gate voltage bootstrap circuit. Figure 2 The combined action of the third output Y1N, fifth output Y0N, and fourth output Y2 of the logic control circuit shown causes the inverter power supply circuit composed of PMOS transistors MP8 and MP9, capacitor C5, and capacitor C6 to operate, generating V. DD_INV Size:
[0026]
[0027] Where C S1 This is the total equivalent capacitance from the drain terminals of PMOS transistors MP8 and MP9 to the common ground.
[0028] When the first output Y0 of the logic control circuit is high, capacitor C1 begins to discharge, the output of inverter INV1 is low, and capacitor C2 begins to charge. Ultimately, the maximum charging voltage of capacitor C2 is limited to Vout - |V GSP3 |-V SD5 Between ranges; where V GSP3 V is the gate-source voltage of the PMOS transistor MP3. SD5 This is the source-drain voltage of PMOS transistor MP5. When the first output Y0 of the logic control circuit is low, a current path is formed through PMOS transistors MP3 and MP4 to start charging capacitor C1. The final voltage of capacitor C1 is limited to approximately VDD-2|V. GSP4 The output voltage of inverter INV1 is V. DD_INV V GSP4 This is the gate-source voltage of the PMOS transistor MP4; due to the characteristic that the charge on capacitor C2 cannot change instantaneously, the voltage across capacitor C2 becomes Vout - |V GSP3 |-V SD5 +V DD_INV ;
[0029] Similarly, when the second output Y1N of the logic control circuit is high, capacitor C3 and NMOS transistor MN5 form a discharge path. When the output voltage of inverter INV2 is low, capacitor C4 begins to charge through NPN transistor Q1 and PMOS transistor MP7. Ultimately, the maximum charging voltage of capacitor C4 is limited to Vout-V. BE1 -V SD7 Within the range, where V BE1 V is the voltage between the base and emitter of the NPN transistor Q1. SD7 The source-drain voltage of PMOS transistor MP7; when the second output Y1N of the logic control circuit is low, capacitor C3 is charged through NPN transistor Q1 and PMOS transistor MP6, ultimately limiting the maximum charging voltage of capacitor C3 to Vout-V. BE1 -|V GS6 | Within the range, where V GS6 This is the gate-source voltage of the PMOS transistor MP6; at this time, the output voltage of the inverter INV2 is at a high level V. DD_INV Because the charge on capacitor C4 cannot change instantaneously, the voltage across capacitor C4 becomes Vout - V. BE1 -V SD7 +V DD_INV ;
[0030] After the control signal of the gate voltage bootstrap circuit is established, the charge pump circuit starts to work. When the sixth output Y2N of the logic control circuit is low, the output voltage of inverter INV1 is low, and the output voltage of inverter INV2 is high, PMOS transistor MP10 is turned on and PMOS transistor MP11 is turned off, starting to charge capacitor C7 at VDD. When the sixth output Y2N of the logic control circuit is high, the fourth output Y2 is low, the output voltage of inverter INV1 is high, and the output voltage of inverter INV2 is low, PMOS transistor MP10 is turned off and PMOS transistor MP11 is turned on. At this time, due to the characteristic that the charge of capacitor C8 cannot change instantaneously, as... Figure 1 As shown, the voltage V at node A A Increase to:
[0031]
[0032] Where C S2 To see all the equivalent capacitances between common grounds from node A; charge begins to transfer from capacitor C8 to capacitor C9, eventually causing the voltage at node B to rise to V. B =V A When the fourth output Y2 of the logic control circuit goes high and the sixth output Y2N goes low, the gate voltage bootstrap circuit simultaneously generates a control signal to turn on the PMOS transistor MP12. The charge on capacitor C9 begins to transfer to capacitor C10, ultimately resulting in a voltage at node C of V. C =V DD +V B Similarly, when the sixth output Y2N of the logic control circuit goes high again, the gate voltage bootstrap circuit generates a control signal that turns on PMOS transistor MP13 and turns off PMOS transistor MP12. The charge on capacitor C10 begins to transfer to capacitor C11, ultimately resulting in the output node Vout voltage being:
[0033]
[0034] The output voltage Vout of the charge pump circuit is fed back to the source of the PMOS transistor MP3 and the collector of the NPN BJT transistor Q1 in the gate voltage bootstrap circuit. When the bias current I1 in the micro-current source bias circuit is too large, the current drawn from the charge pump circuit is too large, causing the charge pump circuit to be unable to output a high voltage. Therefore, the micro-current source bias circuit is suitable for biasing to work under micro-current conditions so that the charge pump circuit outputs a high voltage, thereby achieving the purpose of a low-power gate voltage bootstrap charge pump.
[0035] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A low-power gate voltage bootstrap charge pump circuit, characterized in that, This includes a charge pump circuit, a gate voltage bootstrap circuit, and a microcurrent source bias circuit; The microcurrent source bias circuit defines the bias current through the bias voltage, and then mirrors it to the gate voltage bootstrap circuit through the current mirror structure to provide an initialization state for its startup. The gate voltage bootstrap circuit enables the PMOS switch to be turned on and off by multiplying the clock level and controlling the Y-series clock signal of the charge pump circuit. The Y-series clock signal is generated by the logic control circuit. The charge pump circuit uses a four-stage PMOS transistor series configuration to boost the low power supply voltage to the required high voltage output. The micro-current source bias circuit includes a current source I1, NMOS transistors MN1~MN5 and PMOS transistors MP1~MP2; The positive terminal of current source I1 is connected to power supply VDD, and the negative terminal is connected to the drain terminal of NMOS transistor MN1. The gate terminal of NMOS transistor MN1 is connected to its own drain terminal, and the source terminal is connected to common ground GND. The gate terminal of NMOS transistor MN2 is connected to the gate terminal of NMOS transistor MN1, and the drain terminal is simultaneously connected to the gate terminal and drain terminal of PMOS transistor MP1. The source terminal of NMOS transistor MN2 is connected to common ground GND. The source terminal of PMOS transistor MP1 is connected to power supply VDD. The source terminal of PMOS transistor MP2 is connected to power supply VDD, and the gate terminal is connected to the gate terminal of PMOS transistor MP1. The drain terminal is simultaneously connected to the gate terminal and drain terminal of NMOS transistor MN3. The source terminal of NMOS transistor MN3 is connected to common ground GND. The gate terminal of NMOS transistor MN4 is connected to the gate terminal of NMOS transistor MN3, and the drain terminal is connected to the gate voltage bootstrap circuit. The source terminal is connected to common ground GND. The gate terminal of NMOS transistor MN5 is connected to the gate terminal of NMOS transistor MN3, and the drain terminal is connected to the gate voltage bootstrap circuit. The source terminal is connected to common ground GND.
2. The low-power gate voltage bootstrap charge pump circuit as described in claim 1, characterized in that, The gate voltage bootstrap circuit includes PMOS transistors MP3~MP9, capacitors C1~C6, inverters INV1~INV2, and NPN type BJT transistor Q1; The source terminal of PMOS transistor MP3 is connected to the output voltage Vout of the charge pump circuit, and its gate terminal is connected to its own drain terminal, and is also connected to the source terminals of PMOS transistors MP4 and MP5. The gate terminal of PMOS transistor MP4 is connected to its own drain terminal, and is connected to the drain terminal of NMOS transistor MN4 in the micro-current source bias circuit. The upper plate of capacitor C1 is connected to the drain terminal of PMOS transistor MP4, and the lower plate is connected to the first output Y0 of the logic control circuit. The input terminal of inverter INV1 is connected to the first output Y0 of the logic control circuit, and the output terminal is connected to the lower plate of capacitor C2. The upper plate of capacitor C2 is connected to the drain terminal of PMOS transistor MP5, the gate terminal of PMOS transistor MP5 is connected to the gate terminal of PMOS transistor MP4, and the source terminal is connected to the source terminal of PMOS transistor MP4. The base and collector of the NPN type BJT transistor Q1 are connected together and connected to the output voltage Vout of the charge pump circuit. The emitter is connected to the source terminals of both PMOS transistor MP6 and PMOS transistor MP7. The drain terminal of PMOS transistor MP6 is connected to its own gate terminal and connected to the drain terminal of NMOS transistor MN5 in the micro-current source bias circuit. The upper plate of capacitor C3 is connected to the drain of PMOS transistor MN6, and the lower plate is connected to the second output Y1N of the logic control circuit. The input of inverter INV2 is connected to the second output Y1N of the logic control circuit, and its output is connected to the lower plate of capacitor C4. The upper plate of capacitor C4 is connected to the drain of PMOS transistor MP7. The gate of PMOS transistor MP7 is connected to the gate of PMOS transistor MP6, and its source is connected to the source of PMOS transistor MP6. The gate of PMOS transistor MP8 is connected to the third output Y1 of the logic control circuit, its drain is connected to the power supply VDD, and its source is connected to the upper plate of capacitor C5. The lower plate of capacitor C5 is connected to the fourth output Y2 of the logic control circuit. The gate of PMOS transistor MP9 is connected to the fifth output Y0N of the logic control circuit, its drain is connected to the source of PMOS transistor MP8, and its source is connected to the upper plate of capacitor C6. The lower plate of capacitor C6 is connected to the common ground GND, and its upper plate is connected to the power input VDD of both inverters INV1 and INV2. DD_INV Connected.
3. The low-power gate voltage bootstrap charge pump circuit as described in claim 2, characterized in that, The charge pump circuit includes capacitors C7~C11 and PMOS transistors MP10~MP13; The upper plate of capacitor C7 is connected to power supply VDD, and the lower plate is connected to common ground GND; the gate of PMOS transistor MP10 is connected to the output of inverter INV1, the drain is connected to power supply VDD, and the source is connected to the upper plate of capacitor C8; the lower plate of capacitor C8 is connected to the sixth output Y2N of the logic control circuit, and the upper plate is connected to the drain of PMOS transistor MP11; the gate of PMOS transistor MP11 is connected to the output of inverter INV2, the drain is connected to the source of PMOS transistor MP10, and the source is connected to the upper plate of capacitor C9; the upper plate of capacitor C9 is connected to the drain of PMOS transistor MP12, and the lower plate is connected to the lower plate of PMOS transistor MP12. The fourth output Y2 of the logic control circuit is connected to the board; the gate of PMOS transistor MP12 is connected to the drain of PMOS transistor MP5, the drain is connected to the source of PMOS transistor MP11, and the source is connected to the upper plate of capacitor C10; the upper plate of capacitor C10 is connected to the drain of PMOS transistor MP13, and the lower plate is connected to the sixth output Y2N of the logic control circuit; the gate of PMOS transistor MP13 is connected to the drain of PMOS transistor MP7, the drain is connected to the source of PMOS transistor MP12, and the source is connected to the upper plate of capacitor C11; the upper plate of capacitor C11 is connected to the output voltage Vout, and the lower plate is connected to the common ground GND.
Citation Information
Patent Citations
Self-adaptive and self-biased charge pump with adjustable current
CN112787503A