Network controller of spaceborne high-reliability time-triggered network

Abstract

This invention provides a network controller for a spaceborne high-reliability time-triggered network, comprising a configuration management register module, a scheduling execution module, a processing and storage module, a Layer 3 forwarding query module, and an interface module. The configuration management register module stores the network controller's configuration parameters and processes access requests. The scheduling execution module performs routing, buffering, and forwarding of data frames in the network. The Layer 3 forwarding query module executes query requests against the Layer 3 forwarding table. The interface module receives / sends configuration management packets, routing packets, and security authentication packets from the switch and sends them to the processing and storage module. The processing and storage module parses the configuration management packets and updates the IP lookup table according to the protocols in the routing and security authentication packets. This enables monitoring and management of network exchange data, improves the speed of data packet processing, and provides highly reliable configuration management capabilities for spaceborne high-reliability time-triggered network switches.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and more specifically, to a network controller for a spaceborne high-reliability time-triggered network. Background Technology

[0002] With the rapid development of my country's aerospace industry, the demand for data interaction between satellite-borne units is constantly increasing, placing higher requirements on onboard information exchange capabilities. Multi-connectivity data interaction has become a development trend.

[0003] Against this backdrop, building a distributed Ethernet network based on multiple onboard platforms is an effective way to solve these problems. However, traditional Ethernet networks suffer from data transmission conflicts, which seriously affect the reliability and real-time performance of onboard data transmission.

[0004] Time-triggered Ethernet (TTE) is a new type of real-time industrial control Ethernet with high real-time performance, high resource utilization, and high fault tolerance, and it has been widely used in industrial fields. As a distributed network, TTE boasts communication rates exceeding 1Gbps and incorporates time attributes and various fault-tolerant designs to ensure reliable transmission of time-critical messages, exhibiting numerous superior characteristics such as high determinism and high real-time performance. However, existing TTE networks suffer from complex network controller architectures, poor scalability, and are inconvenient for debugging and use. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this invention is to provide a network controller for a spaceborne high-reliability time-triggered network.

[0006] This application provides a network controller for a spaceborne high-reliability time-triggered network, comprising: a configuration management register module, a scheduling execution module, a processing and storage module, a layer 3 forwarding and query module, and an interface module; wherein:

[0007] The configuration management register module is used to store the configuration parameters of the network controller and to receive access requests from the processing and storage module.

[0008] The scheduling execution module is used to perform routing, buffering, and forwarding of data frames in the network;

[0009] The Layer 3 forwarding query module is used to execute query requests against the Layer 3 forwarding table, which is used to record the index and data of memory addresses.

[0010] The interface module is used to receive / send configuration management packets, routing packets, and security authentication packets from the switch, and to send the received configuration management packets, routing packets, and security authentication packets to the processing and storage module.

[0011] The processing and storage module is used to parse the configuration management packet and update the IP (Internet Protocol) lookup table according to the protocols in the routing packet and security authentication packet.

[0012] Optionally, the scheduling execution module uses RISC-V instructions and special instructions to control the execution flow of the time-triggered network. During operation, it performs data scheduling on the registers according to the scheduling instructions stored in the DDR (Double Data Rate) memory on the FPGA (Field-Programmable Gate Array) side.

[0013] Optionally, when the scheduling execution module starts, it configures the Layer 2 forwarding table and registers according to the scheduling table.

[0014] Optionally, during the operation of the scheduling execution module, the number of memory accesses to scheduling instructions in the DDR memory is reduced by using the cache at the front end of the DDR controller and the instruction cache of the scheduling table executor.

[0015] Optionally, the three-layer forwarding query module is used to perform IP forwarding based on an IP lookup table, wherein the IP lookup table is represented in the form of a multi-bit trie.

[0016] Optionally, when the three-layer forwarding table needs to be updated, the three-layer forwarding table is updated by changing the entry address register of the multi-bit trie.

[0017] Optionally, the processing and storage module is stored in a 3-backup manner, loaded in a 3-out-of-2 manner, and protected by a (72,64) correction-one-check-two encoding.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] This invention routes, caches, and forwards data frames in the network according to preset configuration parameters, and can receive external instructions to modify the configuration table by changing the parameters. It also supports data loading, which can effectively ensure the configuration management of the spaceborne high-reliability time-triggered network. It can route, cache, and forward data frames in the network according to preset configuration parameters, making the interaction of spaceborne time-triggered network data highly reliable. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort. Other features, objects, and advantages of the present invention will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0021] Figure 1 A schematic diagram of the architecture of the network controller for the spaceborne high-reliability time-triggered network provided in the embodiments of this application;

[0022] Figure 2 A schematic diagram of the logic structure of the network controller for the spaceborne high-reliability time-triggered network provided in this embodiment;

[0023] Figure 3 This is a schematic diagram of the overall structure of the CPU processor within the network controller of the spaceborne high-reliability time-triggered network provided in this embodiment;

[0024] Figure 4 This is a schematic diagram of an instruction format for the scheduling instruction set of the spaceborne high-reliability time-triggered network provided in this embodiment. Detailed Implementation

[0025] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0026] It should be noted that when a component is referred to as "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as "connected to" another component, it can be directly connected to or indirectly connected to that other component. Furthermore, a connection can be for both fixing and circuit connection purposes.

[0027] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", and "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0028] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of the present invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0029] This application provides a network controller for a spaceborne high-reliability time-triggered network, designed to enable configuration management capabilities. It allows for routing, caching, and forwarding of data frames in the network according to preset configuration parameters, resulting in good engineering performance, convenient debugging, and improved system reliability. The network controller in this application may include: a configuration management register module, a scheduling execution module, a processing and storage module, a Layer 3 forwarding query module, and an interface module. Specifically: the configuration management register module stores the network controller's configuration parameters and receives access requests from the processing and storage module; the scheduling execution module executes routing, caching, and forwarding of data frames in the network; the Layer 3 forwarding query module executes query requests for the Layer 3 forwarding table, which records memory address indexes and data; the interface module receives / sends configuration management packets, routing packets, and security authentication packets from the switch, and sends the received packets to the processing and storage module; the processing and storage module parses the configuration management packets and updates the IP lookup table according to the protocols in the routing and security authentication packets.

[0030] In this embodiment, the network controller is mainly used for the configuration management of the spaceborne high-reliability time-triggered network. The network controller routes, caches, and forwards data frames in the network according to preset configuration parameters, and can receive external instructions to modify the configuration table by changing parameters. It also supports data loading. This enables monitoring and management of network-exchanged data, improves the speed of data packet processing, and provides highly reliable configuration management capabilities for the spaceborne high-reliability time-triggered network switch.

[0031] Optionally, the scheduling execution module uses RISC-V instructions and special instructions to control the execution flow of the time-triggered network. During operation, it performs data scheduling on the registers according to the scheduling instructions stored in the DDR memory on the FPGA side.

[0032] In this embodiment, a soft core with RISC-V+ dedicated instructions is used to implement the routing, caching, and forwarding of data frames in the network.

[0033] Optionally, when the scheduling execution module starts, it configures the Layer 2 forwarding table and registers according to the scheduling table.

[0034] Optionally, during the operation of the scheduling execution module, the number of memory accesses to scheduling instructions in the DDR memory is reduced by using the cache at the front end of the DDR controller and the instruction cache of the scheduling table executor.

[0035] Optionally, the three-layer forwarding query module is used to perform IP forwarding based on an IP lookup table, wherein the IP lookup table is represented in the form of a multi-bit trie.

[0036] Optionally, when the three-layer forwarding table needs to be updated, the three-layer forwarding table is updated by changing the entry address register of the multi-bit trie.

[0037] In this embodiment, the implementation of a three-layer forwarding table can be supported. The query function of the three-layer forwarding table requires access to the IP lookup table (multi-bit trie) to implement IP forwarding. Updating the lookup table is accomplished by modifying the configuration register. During the update, the network controller software is responsible for regenerating the index and data portions in memory. Each time the forwarding table is updated, a new index table and data table are always generated. Finally, the update of the forwarding table is completed by modifying the entry address register of the trie.

[0038] Optionally, the processing and storage module is stored in a 3-backup manner, loaded in a 3-out-of-2 manner, and protected by a (72,64) correction-one-check-two encoding.

[0039] Figure 1 This is a schematic diagram of the network controller architecture for the spaceborne high-reliability time-triggered network provided in the embodiments of this application, as shown below. Figure 1 As shown, the network controller in this embodiment may include: a high-capacity FPGA, a high-reliability processor, DDR memory, NOR Flash memory, NAND FlashFT6672 file system, VPX backplane interface, deterministic Ethernet interface, debug interface, programming interface, and RS422 bus, used to implement the functions of configuration management register module, scheduling execution module, processing and storage module, three-layer forwarding query module and interface module.

[0040] Figure 2 This is a schematic diagram of the logic structure of the network controller for the spaceborne high-reliability time-triggered network provided in this embodiment, as shown below. Figure 2 As shown, it may include: FPGA, CPU (Central Processing Unit) processor, DDR memory, NOR Flash memory, scheduler executor, exchange configuration register, PMGMT interface, EMIF interface and RapidIO interface, etc., to implement the functions of configuration management register module, scheduling execution module, processing and storage module, three-layer forwarding query module and interface module.

[0041] For example, in this embodiment, the CPU processor accesses the configuration registers of the switching structure and processes configuration management and routing protocol data packets sent from the PMGMT port through the EMIF interface and the RapidIO interface. In addition to providing access initiated by the CPU processor, the RapidIO interface also provides the function of mapping the DDR memory on the CPU side to the FPGA for direct access, which can speed up the processing of data packets.

[0042] In this embodiment, the CPU processor is the FT-6672 hybrid heterogeneous processor, which adopts a heterogeneous SoC architecture. It integrates one CPU processor core for system control tasks, two DSP processor cores for parallel digital signal processing, and a wealth of peripheral devices to form a powerful and self-consistent SoC (System-on-a-Chip) system.

[0043] Figure 3 This is a schematic diagram of the overall structure of the CPU processor within the network controller of the spaceborne high-reliability time-triggered network provided in this embodiment, as shown below. Figure 3 As shown, it is mainly divided into 12 parts in terms of function: CPU core, DSP (Digital Signal Processing) core, external memory system, interconnection network, high-speed interface, low-speed interface, integrated peripherals, global control register, bootstrap, reset, and debugging.

[0044] In this embodiment, the performance of the FT-6672 hybrid heterogeneous processor is as follows:

[0045] 1) Processor composition: (PowerPC460 + DSP C66X*2), PowerPC processor clock speed 200MHz, DSP clock speed 400MHz.

[0046] 2) Computing power: Fixed-point computing power, 300 MIPS; Floating-point computing power, 10 GFLOPS;

[0047] 3) Processor radiation resistance specifications: Total dose ≥ 100 Krad (Si); Single-event lockout threshold (LET) ≥ 75 Mev·cm2 / mg; Soft error rate (SER) ≤ 1E-10 errors / bit·day;

[0048] 4) 2Gbits DDRII with EDAC;

[0049] 5) 64MB with EDAC;

[0050] 6) Time management capability: Time resolution better than 10ns;

[0051] 7) Instruction response time: no more than 1ms;

[0052] 8) Provide at least 128Gb of cache space for application refactoring.

[0053] In one optional implementation, the network controller scheduler instruction executor is implemented using a soft core with RISC-V+ dedicated instructions. During runtime, its scheduling instructions are stored in DDR memory on the FPGA side, and the memory access frequency for fetching scheduling instructions is reduced by the high-speed cache at the front end of the DDR controller and the instruction cache of the scheduler executor. At startup, the scheduler executor also configures the Layer 2 forwarding table and registers according to the scheduler.

[0054] In this embodiment, the RISC-V instructions consist of a general RISC-V instruction set and a custom extended instruction set, used to control the execution flow of time-triggered Ethernet. By combining the custom extended instruction set with the general instruction set, highly reliable network switching can be achieved, improving the real-time performance of network device scheduling. This highly reliable real-time network scheduling instruction set can be used for data transmission and reception management of network switching devices, enabling the execution of time-triggered traffic scheduling tables. Table 1 lists some of the instructions in this embodiment.

[0055] Table 1 IP Switching Command Set

[0056]

[0057]

[0058] The aforementioned IP instruction set includes 10 categories of instructions: Idle, Best Effort (BE), Frame Synchronization (FRAME), Doorbell, Time Triggered Transmission (XMITTT), Rate Control Transmission (XMITRC), Time Triggered Reception (RECVTT), Rate Control Reception (RECVRC), Composite Window Start (WBEGIN), and Composite Window End (WEND). Figure 4 This is a schematic diagram of an instruction format for the scheduling instruction set of the spaceborne high-reliability time-triggered network provided in this embodiment.

[0059] In this embodiment, the Layer 3 forwarding table lookup function requires access to the IP lookup table (multi-bit dictionary) to achieve IP forwarding. The multi-bit dictionary is stored in the DDR memory on the FPGA side. When performing Layer 3 forwarding, the FPGA only reads the IP lookup table to complete the lookup. When the lookup table needs to be updated, the FT-6672V is responsible for generating a new IP lookup table, and finally, the update is completed by changing the configuration register. In this way, read / write conflicts between the FPGA and CPU processor software can be avoided.

[0060] In another embodiment of the present invention, the configuration management packet, routing packet and security authentication packet sent to the switch are sent to the DDR memory through the PMGMT port (FPGA or CPU through RapidIO), and the CPU processor is responsible for parsing the configuration management packet and responding to the security authentication and routing protocol.

[0061] In another embodiment of the invention, to improve system reliability, the CPU processor's program is stored in three SPI interface NOR Flash chips, and the FPGA is responsible for providing two out of three chips to the FT-6672V for loading and execution. Both the CPU processor and the FPGA's DDR memory use (72,64) error correction and detection coding protection to reduce the impact of single-event upsets on the system.

[0062] The above is the core idea of ​​this invention. To make the above-mentioned objectives, features, and advantages of this invention more apparent and understandable, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0063] The various embodiments described in this specification are presented in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0064] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A network controller of a spaceborne high-reliability time-triggered network, characterized in that include: The system comprises a configuration management register module, a scheduling execution module, a processing and storage module, a layer 3 forwarding query module, and an interface module; among which: The configuration management register module is used to store the configuration parameters of the network controller and to receive access requests from the processing and storage module. The scheduling execution module is used to perform routing, buffering, and forwarding of data frames in the network. The scheduling execution module uses RISC-V instructions and custom extended instructions to control the execution flow of the time-triggered network. During runtime, it performs data scheduling on registers according to scheduling instructions stored in the DDR memory on the FPGA side. The scheduling execution module uses RISC-V instructions and a custom extended instruction set, which includes: idle instruction, best-effort transmission instruction, frame synchronization instruction, doorbell instruction, time-triggered packet transmission instruction, rate control packet transmission instruction, time-triggered packet reception instruction, rate control packet reception instruction, composite window start instruction, and composite window end instruction. The Layer 3 forwarding query module is used to execute query requests against the Layer 3 forwarding table, which is used to record the index and data of memory addresses. When the IP lookup table queried by the Layer 3 forwarding table needs to be updated, the FT-6672V is responsible for generating a new IP lookup table and completing the update by changing the configuration register. When the FPGA performs Layer 3 forwarding, it only reads the IP lookup table to complete the lookup. The interface module is used to receive / send configuration management packets, routing packets, and security authentication packets from the switch, and to send the received configuration management packets, routing packets, and security authentication packets to the processing and storage module. The processing and storage module is used to parse the configuration management package and update the IP lookup table according to the protocols in the routing package and security authentication package. The processing and storage module uses a 3-backup storage method, loads the data in a 3-out-of-2 manner, and uses (72,64) correction-one-check-two encoding to protect the memory.

2. The network controller of a spaceborne high-reliability time-triggered network according to claim 1, characterized in that, When the scheduling execution module starts, it configures the Layer 2 forwarding table and registers according to the scheduling table.

3. The network controller of claim 1, wherein, When the scheduling execution module is running, the number of memory accesses to scheduling instructions in the DDR memory is reduced by the high-speed cache of the DDR controller front end and the instruction cache of the scheduling table executor.

4. The network controller of a spaceborne high-reliability time-triggered network according to claim 1, c h a r a c t e r i z e d b y The three-layer forwarding query module is used to forward IPs according to the IP lookup table, wherein the IP lookup table is represented in the form of a multi-bit trie.

5. The network controller of claim 4, wherein, When the three-layer forwarding table needs to be updated, it is updated by changing the entry address register of the multi-bit trie.

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