Transistor connection structure and method of manufacturing the same

Abstract

The application provides a transistor connection structure and a preparation method thereof. The preparation method comprises the following steps: providing a substrate, wherein the substrate comprises a plurality of vertical gate transistors arranged in an array; forming an isolation layer on a first surface of the substrate; partially etching the isolation layer to expose the vertical gate transistors to form a capacitor hole, wherein the capacitor hole comprises a plurality of first capacitor holes for exposing a single vertical gate transistor and at least one second capacitor hole for exposing a plurality of adjacent vertical gate transistors; and forming a first capacitor and a second capacitor in the first capacitor hole and the second capacitor hole, respectively, wherein each first capacitor is connected with one vertical gate transistor in series, and each second capacitor hole is connected with a plurality of adjacent vertical gate transistors. The application can realize the series connection or parallel connection of a plurality of transistors by making a large capacitor with a large size and connecting a plurality of adjacent transistor sources.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a transistor interconnect structure and its fabrication method. Background Technology

[0002] In existing technologies, the source of a memory transistor is typically connected to a capacitor cell, ferroelectric memory cell, or phase-change memory cell. Because capacitors cannot be brought out, bringing out the transistor source is difficult, especially for small-size memories. For three-terminal devices, if any one of the source, gate, or drain terminals cannot be brought out, transistor performance testing is impossible.

[0003] Therefore, how to perform performance testing on memory transistors has become a pressing technical problem that needs to be solved. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a transistor connection structure and its fabrication method, which connects multiple adjacent transistor sources by making a large-size capacitor.

[0005] To address the aforementioned problems, the present invention provides a method for fabricating a transistor interconnect structure, comprising: providing a substrate, the substrate including a plurality of vertical gate transistors arranged in an array; forming an isolation layer on a first surface of the substrate, and partially etching the isolation layer to expose the vertical gate transistors to form capacitor vias, the capacitor vias including a plurality of first capacitor vias exposing the sources of individual vertical gate transistors, and at least one second capacitor via exposing the sources of a plurality of adjacent vertical gate transistors; forming a first capacitor and a second capacitor in the first capacitor vias and the second capacitor vias respectively, each of the first capacitors being connected in series with the source of a vertical gate transistor, and each of the second capacitor vias being connected to the sources of a plurality of adjacent vertical gate transistors.

[0006] To address the aforementioned problems, the present invention also provides a transistor connection structure, comprising: a substrate including a plurality of vertical gate transistors arranged in an array; a first capacitor and a second capacitor disposed on a first surface of the substrate, wherein each first capacitor is connected to the source of a vertical gate transistor, and each second capacitor is connected to the source of a plurality of adjacent vertical gate transistors.

[0007] This invention enables multiple adjacent transistors to be connected in series or in parallel by creating a large capacitor and connecting the sources of multiple adjacent vertical gate transistors using the lower plate of the large capacitor. This facilitates the extraction of transistor sources and enables performance testing of memory transistors. It can be used to monitor test items such as current, voltage, leakage current, and resistance. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the specific embodiments of the invention, the drawings used in the specific embodiments of the invention will be briefly introduced below. Obviously, the drawings described below are only some specific embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 The diagram shown is a schematic representation of a method for fabricating a transistor interconnect structure according to an embodiment of the present invention.

[0010] Figures 2A to 2D The diagram shown is a schematic representation of the device structure formed by the main steps of the method for fabricating the transistor connection structure according to an embodiment of the present invention.

[0011] Figure 3 The diagram shown is a schematic representation of a substrate preparation method according to an embodiment of the present invention;

[0012] Figures 4A to 4L The diagram shown is a schematic representation of the device structure formed by the main steps of the substrate fabrication method according to an embodiment of the present invention.

[0013] Figures 5A-5B The diagram shown is a schematic representation of the device structure formed by the main steps of forming bit lines according to an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Please refer to the following: Figures 1-2D ,in, Figure 1 This is a schematic diagram of a method for fabricating a transistor connection structure according to an embodiment of the present invention. Figures 2A to 2D The diagram shown illustrates the device structure formed by the main steps of the transistor connection structure fabrication method according to an embodiment of the present invention. Hereinafter, the description will be based on the example where the first direction is the Y-axis in a Cartesian coordinate system, the second direction is the X-axis in a Cartesian coordinate system, and the third direction is the Z-axis in a Cartesian coordinate system.

[0016] like Figure 1As shown, the method for fabricating the transistor connection structure in this embodiment includes: step S10, providing a substrate, the substrate including a plurality of vertical gate transistors arranged in an array; step S11, forming an isolation layer on a first surface of the substrate, partially etching the isolation layer to expose the vertical gate transistors to form capacitor holes, the capacitor holes including a plurality of first capacitor holes exposing the sources of a single vertical gate transistor, and at least one second capacitor hole exposing the sources of a plurality of adjacent vertical gate transistors; step S12, forming a first capacitor and a second capacitor in the first capacitor hole and the second capacitor hole respectively, each first capacitor being connected to the source of a vertical gate transistor, and each second capacitor being connected to the sources of a plurality of adjacent vertical gate transistors.

[0017] Please refer to step S10 and Figure 2A A substrate 20 is provided, the substrate 20 including a plurality of vertical gate transistors 411 arranged in an array. Specifically, the vertical gate transistors 411 are spaced apart in a first direction by a plurality of fifth isolation structures 410, such as... Figure 2A As shown in section (a); the vertical gate transistor 411 is spaced apart by a plurality of first isolation structures 403 in the second direction, as... Figure 2A As shown in section (b); the source 411S of the vertical gate transistor 411 is located at one end close to the first surface of the substrate 20, and the drain 411D of the vertical gate transistor is located at one end away from the first surface of the substrate 20.

[0018] Please continue to refer to step S11 and... Figures 2B-2C An isolation layer 201 is formed on the first surface of the substrate 20, and the isolation layer 201 is partially etched to expose the vertical gate transistor 411 to form a capacitor via 202. The capacitor via 202 includes a plurality of first capacitor vias 202A exposing the source of a single vertical gate transistor 411, and at least one second capacitor via 202B exposing the source of a plurality of adjacent vertical gate transistors 411. Specifically, each second capacitor via 202B may expose the source of two or more adjacent vertical gate transistors 411.

[0019] To further illustrate the positional relationship between the first capacitor hole 202A and the second capacitor hole 202B, please refer to... Figure 2B The diagram shown is a schematic diagram of a capacitor hole according to an embodiment of the present invention. Figure 2B The figure shown is a top view of the base 20 along the Z direction; Figure 2C Part (a) is along Figure 2B A partial sectional view along the YZ direction of the section cut by line AA'. Figure 2C Part (b) is along Figure 2BPartial sectional view in the XZ direction with the BB' line as the cross section. Parts (a) and (b) are not drawn to the same scale for ease of illustration.

[0020] In this embodiment, the second capacitor aperture 202B is elliptical, with its major axis extending along the second direction shown, to expose a plurality of adjacent vertical gate transistors 411. Specifically, the second capacitor aperture 202B, spanning the plurality of vertical gate transistors 411 along the second direction, can be etched by thickening at least one photoresist pattern, thereby subsequently forming a second capacitor 204 connecting the sources of the plurality of adjacent vertical gate transistors 411. In this embodiment, the first capacitor aperture 202A and the second capacitor aperture 202B are formed using a double-pattern process.

[0021] Please continue to refer to step S12 and... Figure 2D A first capacitor 203 and a second capacitor 204 are formed in the first capacitor hole 202A and the second capacitor hole 202B, respectively. Each first capacitor 203 is connected to the source of a vertical gate transistor 411, and each second capacitor 204 is connected to the source of multiple adjacent vertical gate transistors 411.

[0022] Specifically, both the first capacitor 203 and the second capacitor 204 include a lower plate, an upper plate, and a capacitor dielectric. The lower plate 2031 of the first capacitor 203 is connected to the source of a vertical gate transistor 411. The lower plate 2041 of the second capacitor 204 is connected to the sources of multiple adjacent vertical gate transistors 411. Optionally, the upper plates 2032 of the first capacitor 203 and the upper plates 2042 of the second capacitor 204 also form a connection structure to realize the series or parallel connection of multiple adjacent transistors.

[0023] In this embodiment, a set of second capacitors 204 is provided along the Y direction. In other embodiments of the present invention, multiple sets of second capacitors 204 may also be provided. In other specific embodiments of the present invention, the first capacitor and the second capacitor may be general capacitor units, ferroelectric memory units, phase change memory units, etc.

[0024] Furthermore, the preparation steps of the substrate 20 are also described in section 3. Figure 4L ,in, Figure 3 The diagram shown is a schematic representation of a substrate preparation method according to an embodiment of the present invention; Figures 4A to 4L The diagram shown is a schematic representation of the device structure formed by the main steps of the substrate fabrication method according to an embodiment of the present invention.

[0025] like Figure 3As shown, the method for preparing the substrate further includes: step S300, providing a substrate; step S301, etching the substrate to form a plurality of first trenches extending along a first direction, all the first trenches being arranged along a second direction, wherein the first direction is perpendicular to the second direction; step S302, filling the first trenches with an isolation material and planarizing them to form a first isolation structure; step S303, continuing to etch the substrate to form a plurality of second trenches extending along the second direction, all the second trenches being arranged along the first direction; step S304, forming a second isolation structure at the bottom of each second trench; step S305, forming a first oxide layer on the first surface of the substrate and the sidewalls of the second trenches, the first oxide layer being in contact with the second isolation structure; step S306, forming two word lines that are insulated from each other by a third isolation structure on the surface of the first oxide layer on the sidewalls of the second trenches, wherein... The two word lines are connected at one end away from the first surface of the substrate to the second isolation structure, and at one end near the first surface of the substrate to the fourth isolation structure; in step S307, the substrate is etched further and the etched area is filled with isolation material to form a fifth isolation structure extending along the second direction between two adjacent second trenches; in step S308, the first oxide layer on the first surface of the substrate is removed and a vertical gate transistor is formed on both sides of the fifth isolation structure. The vertical gate transistor is separated by a plurality of the fifth isolation structures in the first direction and by a plurality of the first isolation structures in the second direction. The source of the vertical gate transistor is located at one end near the first surface of the substrate, the drain of the vertical gate transistor is located at one end away from the first surface of the substrate, and the first oxide layer retained on the sidewall of the second trench serves as the gate oxide layer of the vertical gate transistor.

[0026] Please refer to step S300 and Figure 4A A substrate 401 is provided. In this embodiment, the substrate 401 is made of monocrystalline silicon.

[0027] Please refer to step S301 and Figure 4B The substrate 401 is etched to form a plurality of first trenches 402 extending along a first direction, and all the first trenches 402 are arranged therein along a second direction, the second direction being perpendicular to the first direction.

[0028] Please refer to step S302 and Figure 4C The first trench 402 is filled with an insulating material and planarized to form a first insulating structure 403. In this embodiment, the material of the first insulating structure 403 is silicon oxide, and the first insulating structure 403 extends along a first direction and is arranged along a second direction.

[0029] Please refer to step S303 and Figure 4D The substrate 401 is then etched to form a plurality of second trenches 404 extending along a second direction, and all the second trenches 404 are arranged along the first direction. In this embodiment, the second trenches 404 are orthogonal to the first isolation structure 403, and the depth of the second trenches 404 is less than that of the first trenches 402, so as to ensure good isolation between the transistors subsequently formed.

[0030] Please refer to step S304 and Figure 4E A second isolation structure 405 is formed at the bottom of each of the second trenches 404. In this embodiment, the material of the second isolation structure 405 is silicon oxide.

[0031] Please refer to step S305 and Figure 4F A first oxide layer 406 is formed on the first surface of the substrate 401 and the sidewalls of the second trench 404, and the first oxide layer 406 is in contact with the second isolation structure 405. In this embodiment, the first oxide layer 406 is made of silicon oxide and is used as an etching mask and to form a gate oxide layer in subsequent steps.

[0032] Please refer to step S306 and Figure 4I Two word lines 420, insulated from each other by a third isolation structure 408, are formed on the surface of the first oxide layer 406 on the sidewall of the second trench 404. One end of each word line 420 away from the first surface of the substrate 401 is connected to the second isolation structure 405, and the other end closer to the first surface of the substrate 401 is connected to a fourth isolation structure 409. In this embodiment, the word lines 420 are made of tungsten metal.

[0033] The step of forming two mutually insulated word lines 420 may further include Figures 4G to 4I The steps are shown.

[0034] Please see Figure 4G A metal layer 407 and a third isolation structure 408 are formed in the second trench 404; wherein, the metal layer 407 covers the first oxide layer 406 on the sidewall of the second trench 404 and breaks off at the bottom of the second trench 404, and the third isolation structure 408 fills the second trench 404. In this embodiment, the material of the third isolation structure 408 is silicon oxide; the metal layer 407 is used to form word lines in subsequent steps. In this embodiment, the metal layer 407 is made of tungsten.

[0035] Please see Figures 4H to 4I Remove part of the metal layer 407 and the third isolation structure 408 (e.g.) Figure 4HAs shown), and fill with insulating material to form a fourth insulating structure 409 (as shown) near the first surface of the substrate in the second trench. Figure 4I As shown), the remaining metal layer within the second trench 404 forms two word lines 420 that are mutually insulated by the third isolation structure 408, with one end of each word line 420 connected to the second isolation structure 405 and the other end connected to the fourth isolation structure 409. In this embodiment, the fourth isolation structure 409 is made of silicon oxide.

[0036] Please refer to step S307 and Figures 4J to 4K Continue etching the substrate 401 (e.g.) Figure 4J (as shown), and fill the etched area with isolation material to form a fifth isolation structure 410 extending along the second direction between two adjacent second trenches 404 (as shown). Figure 4K (As shown). In this embodiment, the fifth isolation structure 410 is made of silicon oxide; the fifth isolation structure 410 protrudes from the word line 420 at both its upper and lower ends in the third direction to provide good isolation for the transistors formed subsequently.

[0037] Please refer to step S308 and Figure 4L The first oxide layer 406 on the first surface of the substrate 401 is removed, and a vertical gate transistor 411 is formed on both sides of the fifth isolation structure 410. The vertical gate transistor 411 is spaced apart by a plurality of the fifth isolation structures 410 in a first direction and by a plurality of the first isolation structures 403 in a second direction. The source 411S of the vertical gate transistor 411 is located at one end near the first surface of the substrate 401, the drain 411D of the vertical gate transistor is located at one end away from the first surface of the substrate 401, and the first oxide layer 406 retained on the sidewall of the second trench serves as the gate oxide layer 412 of the vertical gate transistor. A portion of the word line 420 near the vertical gate transistor 411 also serves as the gate of the vertical gate transistor. In this embodiment, the vertical gate transistor 411 is an MSG vertical channel transistor, but the present invention is not limited to this type; any other vertical gate transistor can be used to complete the present invention.

[0038] In this embodiment, a plurality of vertical gate transistors 411 are formed. For ease of explanation, one vertical gate transistor 411 is shown within the dashed box in the figure, while the other vertical gate transistors 411 are not shown.

[0039] In the above embodiments, the materials of the first isolation structure 403, the second isolation structure 405, the third isolation structure 408, the fourth isolation structure 409, and the fifth isolation structure 410 are selected from silicon nitride, silicon oxide, or polycrystalline silicon.

[0040] After completing the above steps, you will get Figure 2A The substrate 20 is shown.

[0041] The method described in this embodiment further includes a step of forming bit lines after the steps of forming the first capacitor and the second capacitor. For further details, please refer to... Figures 5A-5B This is a schematic diagram of a device structure formed by the main steps of forming a bit line according to an embodiment of the present invention, including: thinning the substrate on the second surface side of the substrate to expose the drain of the vertical gate transistor, wherein the second surface is the surface opposite to the first surface; forming a bit line on the thinned second surface of the substrate, the bit line being connected to the drain of the vertical gate transistor.

[0042] Please see Figure 5A The substrate 20 is thinned on its second surface side to expose the drain 411D of the vertical gate transistor 411. Specifically, a carrier sheet 601 can be bonded to the surfaces of the first capacitor 203 and the second capacitor 204 away from the substrate 20, and then the substrate 20 is flipped to facilitate thinning of the second surface of the substrate 20. In this embodiment, a portion of the second isolation structure 405 is thinned.

[0043] Please see Figure 5B A bit line 602 is formed on the second surface of the thinned substrate 20, and the bit line 602 is connected to the drain 411D of the vertical gate transistor 411.

[0044] Furthermore, the method described in this embodiment also includes covering the surface of the bit line 602 with a second dielectric layer and etching out bit line lead-out holes corresponding to each bit line 602. The bit line lead-out holes are filled with metal for connecting the bit lines 602. The etching location of the bit line lead-out holes should avoid capacitor holes to prevent leakage.

[0045] Based on the same inventive concept, the present invention also provides a transistor connection structure.

[0046] Please refer to Figure 2D The transistor connection structure includes: a substrate 20, the substrate 20 including a plurality of vertical gate transistors 411 arranged in an array; a first capacitor 203 and a second capacitor 204 disposed on a first surface of the substrate 20, each of the first capacitors 203 being connected to the source of a vertical gate transistor 411, and each of the second capacitors 204 being connected to the source of a plurality of adjacent vertical gate transistors 411.

[0047] In this embodiment, a set of second capacitors 204 is provided along the Y direction. In other embodiments of the present invention, multiple sets of second capacitors 204 may also be provided. The first capacitor and the second capacitor may be general capacitor units, ferroelectric memory units, phase change memory units, etc.

[0048] Specifically, both the first capacitor 203 and the second capacitor 204 include a lower plate, an upper plate, and a capacitor dielectric. The lower plate 2031 of the first capacitor 203 is connected to the source of a vertical gate transistor 411. The lower plate 2041 of the second capacitor 204 is connected to the sources of multiple adjacent vertical gate transistors 411. Optionally, the upper plates 2032 of the first capacitor 203 and the upper plates 2042 of the second capacitor 204 also form a connection structure to realize the series or parallel connection of multiple adjacent transistors.

[0049] Since the source terminal of the transistor located at the lower plate of the capacitor cannot be brought out through contact holes or wires, only the gate terminal at the word line and the drain terminal at the bit line of the transistor can be brought out. Therefore, it is necessary to connect multiple adjacent transistors through the lower plate of the capacitor to achieve the source terminal bringing out for transistor performance testing.

[0050] Furthermore, the array of vertical gate transistors 411 is spaced apart by multiple fifth isolation structures 410 in a first direction and by multiple first isolation structures 403 in a second direction, the second direction being perpendicular to the first direction. Two word lines 420, insulated from each other by a third isolation structure 408, are also provided on the sidewall of the gate oxide layer 412 of the vertical gate transistors 411. One end of each word line 420 away from the first surface of the substrate 20 is connected to a second isolation structure 405, and the other end near the first surface of the substrate 20 is connected to a fourth isolation structure 409. The third isolation structure 408 extends along the second direction. In this embodiment, the word lines 420 are made of tungsten metal.

[0051] In this embodiment, the source 411S of the vertical gate transistor 411 is located at one end close to the first surface of the substrate 20, and the drain 411D of the vertical gate transistor is located at one end away from the first surface of the substrate 20.

[0052] Please refer to Figure 5B Following the above embodiment, the transistor connection structure further includes: a bit line 602, disposed on the second surface of the substrate 20 and connected to the drain 411D of the vertical gate transistor 411; wherein the second surface is the surface opposite to the first surface.

[0053] The above technical solution achieves series or parallel connection of multiple adjacent transistors by making a large capacitor and connecting the sources of multiple adjacent vertical gate transistors through the lower plate of the large capacitor. This facilitates the extraction of transistor sources and enables performance testing of memory transistors. It can be used to monitor test items such as current, voltage, leakage current, and resistance.

[0054] It should be noted that all specific embodiments in this specification are described in a related manner, and the same or similar parts between the various specific embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the structural embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments.

[0055] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a transistor interconnect structure, characterized in that, include: A substrate is provided, the substrate comprising a plurality of vertical gate transistors arranged in an array; An isolation layer is formed on a first surface of the substrate, and the isolation layer is partially etched to expose the vertical gate transistor to form a capacitor hole. The capacitor hole includes a plurality of first capacitor holes exposing the source of a single vertical gate transistor and at least one second capacitor hole exposing the source of a plurality of adjacent vertical gate transistors. A first capacitor and a second capacitor are formed in the first capacitor hole and the second capacitor hole, respectively. Each first capacitor is connected to the source of a vertical gate transistor, and each second capacitor is connected to the source of multiple adjacent vertical gate transistors.

2. The method according to claim 1, characterized in that, The step of providing a substrate further includes: Provide a substrate; The substrate is etched to form a plurality of first trenches extending along a first direction, all of which are arranged along a second direction, wherein the first direction is perpendicular to the second direction. The first trench is filled with insulating material and flattened to form a first insulating structure; The substrate is etched further to form a plurality of second trenches extending along the second direction, and all the second trenches are arranged along the first direction; A second isolation structure is formed at the bottom of each of the second trenches; A first oxide layer is formed on the first surface of the substrate and the sidewall of the second trench, and the first oxide layer is in contact with the second isolation structure; Two word lines are formed on the surface of the first oxide layer on the sidewall of the second trench, which are insulated from each other by a third isolation structure. The two word lines are connected to the second isolation structure at one end away from the first surface of the substrate, and connected to the fourth isolation structure at one end closer to the first surface of the substrate. Continue etching the substrate and fill the etched area with isolation material to form a fifth isolation structure extending along the second direction between two adjacent second trenches; The first oxide layer on the first surface of the substrate is removed and a vertical gate transistor is formed on both sides of the fifth isolation structure. The vertical gate transistor is spaced apart by a plurality of the fifth isolation structures in the first direction and by a plurality of the first isolation structures in the second direction. The source of the vertical gate transistor is located at one end close to the first surface of the substrate, the drain of the vertical gate transistor is located at one end away from the first surface of the substrate, and the first oxide layer of the sidewall of the retained second trench serves as the gate oxide layer of the vertical gate transistor.

3. The method according to claim 1, characterized in that, After the steps of forming the first capacitor and the second capacitor respectively, the method further includes: thinning the substrate on the second surface side of the substrate to expose the drain of the vertical gate transistor, wherein the second surface is the surface opposite to the first surface; forming a bit line on the thinned second surface of the substrate, the bit line being connected to the drain of the vertical gate transistor.

4. The method according to claim 3, characterized in that, After the step of forming bit lines on the second surface of the thinned substrate, the method further includes: covering the surface of the bit lines with a second dielectric layer and etching bit line lead-out holes corresponding to each bit line, wherein the bit line lead-out holes are filled with metal for connecting the bit lines.

5. The method according to claim 1, characterized in that, Both the first capacitor and the second capacitor include a lower plate, an upper plate, and a capacitor dielectric. The lower plate of the first capacitor is connected to the source of a vertical gate transistor, and the lower plate of the second capacitor is connected to the sources of multiple adjacent vertical gate transistors.

6. The method according to claim 2, characterized in that, The second capacitor aperture is elliptical, with its major axis extending along the second direction to expose the sources of multiple adjacent vertical gate transistors.

7. A transistor connection structure, characterized in that, include: A substrate, the substrate comprising an array of vertically arranged gate transistors; A first capacitor and a second capacitor are disposed on a first surface of the substrate. Each first capacitor is connected to the source of a vertical gate transistor, and each second capacitor is connected to the source of multiple adjacent vertical gate transistors.

8. The transistor connection structure according to claim 7, characterized in that, Both the first capacitor and the second capacitor include a lower plate, an upper plate, and a capacitor dielectric. The lower plate of the first capacitor is connected to the source of a vertical gate transistor, and the lower plate of the second capacitor is connected to multiple adjacent vertical gate transistors.

9. The transistor connection structure according to claim 7, characterized in that, The array of vertical gate transistors is spaced apart by a plurality of fifth isolation structures in a first direction and by a plurality of first isolation structures in a second direction, wherein the second direction is perpendicular to the first direction; two word lines insulated from each other by a third isolation structure are also provided on the sidewall of the gate oxide layer of the vertical gate transistors, one end of the two word lines away from the first surface of the substrate is connected to a second isolation structure, and the other end close to the first surface of the substrate is connected to a fourth isolation structure.

10. The transistor connection structure according to claim 7, characterized in that, The source of the vertical gate transistor is located at one end close to the first surface of the substrate, and the drain of the vertical gate transistor is located at one end away from the first surface of the substrate. The transistor connection structure further includes a bit line disposed on the second surface of the substrate and connected to the drain of the vertical gate transistor, wherein the second surface is the surface opposite to the first surface.

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