Semiconductor memory device and method for manufacturing the semiconductor memory device

Abstract

This disclosure relates to a semiconductor memory device and a method of manufacturing the semiconductor memory device. A semiconductor memory device includes a plurality of conductive patterns and a plurality of second interlayer insulating layers arranged alternately beneath a first interlayer insulating layer. The semiconductor memory device further includes a doped semiconductor layer comprising an amorphous region overlapping the first interlayer insulating layer and a crystalline region overlapping the first interlayer insulating layer, with the amorphous region interposed between the first interlayer insulating layer and the crystalline region. The semiconductor memory device also includes a channel layer that contacts the doped semiconductor layer and extends through the first interlayer insulating layer, the plurality of second interlayer insulating layers, and the plurality of conductive patterns. The semiconductor memory device further includes a memory layer located between the respective conductive patterns and the channel layer.

Description

Technical Field

[0001] Various embodiments generally relate to semiconductor memory devices and methods of manufacturing such semiconductor memory devices, and more specifically, to a three-dimensional semiconductor memory device and a method of manufacturing such a three-dimensional semiconductor memory device. Background Technology

[0002] Semiconductor memory devices may include multiple memory cells for storing data. Three-dimensional semiconductor memory devices may include multiple memory cells arranged in a three-dimensional manner. The three-dimensional arrangement of memory cells reduces the two-dimensional space occupied by multiple memory cells on a substrate, and improves the integration density of the semiconductor memory device. As the number of memory cells stacked on the substrate increases, the integration density of the semiconductor memory device can be further improved. However, increasing the number of memory cells stacked on the substrate may lead to a deterioration in the operational reliability of the three-dimensional semiconductor memory device. Summary of the Invention

[0003] According to one embodiment, a semiconductor memory device may include a plurality of conductive patterns and a plurality of second interlayer insulating layers arranged alternately beneath a first interlayer insulating layer. The semiconductor memory device may further include a doped semiconductor layer comprising an amorphous region overlapping the first interlayer insulating layer and a crystalline region overlapping the first interlayer insulating layer, wherein the amorphous region is interposed between the first interlayer insulating layer and the crystalline region. The semiconductor memory device may further include a channel layer that contacts the doped semiconductor layer and extends through the first interlayer insulating layer, the plurality of second interlayer insulating layers, and the plurality of conductive patterns. The semiconductor memory device may additionally include a memory layer between the respective conductive patterns and the channel layer.

[0004] According to an embodiment, a method of manufacturing a semiconductor memory device may include forming a preliminary memory cell array structure, the preliminary memory cell array structure including: a first interlayer insulating layer including a first surface and a second surface facing opposite directions; a plurality of conductive patterns and a plurality of second interlayer insulating layers alternately stacked on the second surface of the first interlayer insulating layer; a channel layer passing through the first interlayer insulating layer, the plurality of conductive patterns, and the plurality of second interlayer insulating layers; and a memory layer between each of the plurality of conductive patterns and the channel layer. The method may further include forming an amorphous doped semiconductor layer above the first surface of the first interlayer insulating layer. The method may further include forming the doped semiconductor layer including crystalline regions and amorphous regions between the crystalline regions and the first interlayer insulating layer by crystallizing the surface of the amorphous doped semiconductor layer. The method may further include diffusing impurities in the doped semiconductor layer into the channel layer. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of a memory cell array of a semiconductor memory device according to an embodiment of the present disclosure;

[0006] Figure 2 It is shown as follows Figure 1 The circuit diagram of the memory cell array shown is shown.

[0007] Figure 3A and Figure 3B It is shown Figure 1 A cross-sectional view of an implementation of a memory cell array;

[0008] Figure 4 This is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure;

[0009] Figure 5 This is a flowchart illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure;

[0010] Figure 6 It is shown Figure 5 The flowchart for step ST33 is shown below;

[0011] Figure 7A , Figure 7B , Figure 7C and Figure 7D It is shown as follows Figure 5 A cross-sectional view of a portion of an embodiment of a method for manufacturing a semiconductor memory device;

[0012] Figure 8A , Figure 8B and Figure 8C It is shown as follows Figure 7D A cross-sectional view of an implementation of the subsequent process for region AR2 shown;

[0013] Figure 9A , Figure 9B and Figure 9C It is shown as follows Figure 5 A cross-sectional view of the embodiment of step ST33 shown;

[0014] Figure 10 This is a block diagram illustrating the configuration of a memory system according to an embodiment of the present disclosure; and

[0015] Figure 11 This is a block diagram illustrating the configuration of a computing system according to an embodiment of the present disclosure. Detailed Implementation

[0016] The descriptions in this disclosure are merely embodiments illustrating the structure or function, and therefore the scope of this teaching should not be construed as limited to the embodiments described in these embodiments. Consequently, various changes and modifications falling within the scope of the claims or their equivalents are therefore intended to be covered by the appended claims.

[0017] While terms such as "first" and "second" can be used to describe various components, these components should not be construed as limited to the terms mentioned above. The terms are used only to distinguish one component from another.

[0018] Various embodiments relate to a semiconductor memory device capable of improving operational reliability and a method of manufacturing the semiconductor memory device.

[0019] Figure 1 This is a schematic diagram of a memory cell array (MCA) of a semiconductor memory device according to an embodiment of the present disclosure.

[0020] Reference Figure 1 The memory cell array (MCA) may include multiple bit lines (BL), source layer (SL), and memory block (10).

[0021] Multiple bit lines BL can be separated from each other and extend parallel to each other. According to one embodiment, the multiple bit lines BL can be separated from each other in the X-axis direction and extend in the Y-axis direction. However, embodiments of this disclosure are not limited to this. For example, the multiple bit lines BL can extend diagonally between the X-axis and the Y-axis.

[0022] The source layer SL can overlap with multiple bit lines BL, and the memory block 10 is interposed between them. The source layer SL can be a horizontal pattern extending in the XY plane.

[0023] The memory block 10 can be disposed between multiple bit lines BL and the source layer SL. The memory block 10 may include multiple memory cell strings. Each of the multiple memory cell strings can be connected to the corresponding bit line BL and the source layer SL through a channel layer.

[0024] Figure 2 It is shown as follows Figure 1 The circuit diagram of the memory cell array (MCA) shown is shown.

[0025] Reference Figure 2 The memory cell array (MCA) may include multiple memory cell strings (CS) connected to multiple bit lines (BL). These memory cell strings (CS) may be connected in parallel with the source layer (SL).

[0026] Each memory cell string CS may include a drain-select transistor DST, multiple memory cells MC, and at least one source-select transistor SST.

[0027] Multiple memory cells MC can be connected in series between a drain-select transistor (DST) and a source-select transistor (SST). Multiple memory cells MC can be connected to the source layer SL via the source-select transistor SST. Multiple memory cells MC can be connected to the corresponding bit line BL via the drain-select transistor DST.

[0028] Multiple memory cells (MCs) can be connected to multiple word lines (WLs). The operation of the multiple memory cells (MCs) can be controlled by strobe signals applied to the multiple word lines (WLs). A drain-select transistor (DST) can be connected to a drain-select line (DSL). The operation of the drain-select transistor (DST) can be controlled by strobe signals applied to the drain-select line (DSL). A source-select transistor (SST) can be connected to a source-select line (SSL). The operation of the source-select transistor (SST) can be controlled by strobe signals applied to the source-select line (SSL). The source-select line (SSL), the multiple word lines (WLs), and the drain-select line (DSL) can be formed from separate and stacked conductive patterns.

[0029] Figure 3A and Figure 3B It is shown as follows Figure 1 A cross-sectional view of an embodiment of the memory cell array (MCA) shown. More specifically, Figure 3A This is a cross-sectional view of the memory cell array MCA taken along the direction intersecting multiple bit lines BL. Figure 3B Is it like this? Figure 3A The enlarged cross-sectional view of region AR1 is shown.

[0030] Reference Figure 3A and Figure 3B The memory cell array (MCA) may include a doped semiconductor layer 185, a first interlayer insulating layer 105, multiple conductive patterns 107, multiple second interlayer insulating layers 109, cell plugs (CPL), a memory layer 121, and bit lines (BL).

[0031] Multiple conductive patterns 107 and multiple second interlayer insulating layers 109 may be arranged alternately below the first interlayer insulating layer 105. Multiple conductive patterns 107 and multiple second interlayer insulating layers 109 may be arranged between the first interlayer insulating layer 105 and the bit line BL, and may be arranged alternately in the Z-axis direction.

[0032] The first interlayer insulating layer 105 and each of the second interlayer insulating layers 109 may comprise the same insulating material. According to an embodiment, the first interlayer insulating layer 105 and the second interlayer insulating layer 109 may comprise silicon oxide.

[0033] Multiple conductive patterns 107 can be insulated from the doped semiconductor layer 185 via a first interlayer insulating layer 105. Multiple conductive patterns 107 can be insulated from each other via multiple second interlayer insulating layers 109. At least one conductive pattern among the multiple conductive patterns 107 adjacent to the doped semiconductor layer 185 can be used as a reference above. Figure 2 The source selection line SSL is described. At least one conductive pattern among the plurality of conductive patterns 107 adjacent to the bit line BL can be used as described above. Figure 2 The drain select line DSL is described. The conductive pattern arranged among multiple conductive patterns 107, serving as the source select line SSL and the conductive pattern serving as the drain select line DSL, can be used as described above. Figure 2 The word line described is WL.

[0034] like Figure 1 and Figure 2 As shown, the doped semiconductor layer 185 may form a source layer SL. The doped semiconductor layer 185 may include a crystalline region 185A1 and an amorphous region 185A2. The amorphous region 185A2 may be disposed between the crystalline region 185A1 and the first interlayer insulating layer 105. The crystalline region 185A1 may overlap with the first interlayer insulating layer 105, and the amorphous region 185A2 may be interposed between them. The doped semiconductor layer 185 may include a semiconductor material such as silicon or germanium. The doped semiconductor layer 185 may include at least one of n-type impurities and p-type impurities. According to an embodiment, each of the crystalline region 185A1 and the amorphous region 185A2 of the doped semiconductor layer 185 may include an n-type impurity as the majority carrier. However, this disclosure is not limited thereto. For example, the doped semiconductor layer 185 may include n-type impurity regions and p-type impurity regions. According to the embodiments, the amorphous region 185A2 of the doped semiconductor layer 185 may include n-type impurities as majority carriers, and the crystalline region 185A1 of the doped semiconductor layer 185 may include p-type impurities as majority carriers.

[0035] The memory cell array (MCA) may include a first insulating layer 131 disposed between a stacked structure including a plurality of conductive patterns 107 and a plurality of second interlayer insulating layers 109 and a bit line BL.

[0036] The cell plug CPL may include a channel layer 123. The channel layer 123 may extend through a first interlayer insulating layer 105, a plurality of conductive patterns 107, and a plurality of second interlayer insulating layers 109. The channel layer 123 may contact a doped semiconductor layer 185. According to an embodiment, the channel layer 123 may extend into an amorphous region 185A2 of the doped semiconductor layer 185. The channel layer 123 may extend into a first insulating layer 131. The channel layer 123 may include a semiconductor material such as silicon. The channel layer 123 may include a first portion P1, a second portion P2, and a third portion P3. The first portion P1 may be defined as the portion adjacent to the doped semiconductor layer 185, the third portion P3 may be defined as the portion adjacent to the bit line BL, and the second portion P2 may be defined as the portion disposed between the first portion P1 and the third portion P3.

[0037] The third portion P3 of the channel layer 123 may include a first conductivity type impurity. According to an embodiment, the first conductivity type impurity may be an n-type impurity. The first portion P1 of the channel layer 123 may include a second conductivity type impurity. The second conductivity type impurity may be the same as the impurity in the doped semiconductor layer 185. The second conductivity type impurity may be the same as the first conductivity type impurity. According to an embodiment, the second conductivity type impurity may be an n-type impurity. The second portion P2 of the channel layer 123 may be a channel region and may differ from the doping state of each of the first portion P1 and the second portion P2. According to an embodiment, the second portion P2 of the channel layer 123 may be substantially an intrinsic region.

[0038] According to an embodiment, the first portion P1 of the doped region of the channel layer 123 may be distributed up to the height (level) of the first interlayer insulating layer 105. The third portion P3 of the doped region of the channel layer 123 may be distributed up to the height of the second interlayer insulating layer 109' adjacent to the first insulating layer 131. However, this disclosure is not limited thereto. The distribution range of the first portion P1 and the second portion P2 of the channel layer 123 in the Z-axis direction can be designed in various ways according to the design rules of semiconductor memory devices.

[0039] The channel layer 123 may have various shapes. According to one embodiment, the channel layer 123 may be formed in a tubular shape. The cell plug CPL may also include a core insulating layer 125 and a capping pattern 127 disposed in the central region of the tubular channel layer 123. The capping pattern 127 may include a semiconductor material such as silicon. The capping pattern 127 may be surrounded by a third portion P3 of the channel layer 123 and includes the same impurities as the third portion P3 of the channel layer 123. The core insulating layer 125 may be disposed between the capping pattern 127 and the doped semiconductor layer 185. The core insulating layer 125 may include a region surrounded by a first portion P1 and a second portion P2 of the channel layer 123. The first portion P1 of the channel layer 123 may extend along the surface of the core insulating layer 125 facing the doped semiconductor layer 185. Therefore, the core insulating layer 125 can be separated from the doped semiconductor layer 185 through the first portion P1 of the channel layer 123.

[0040] The boundary between the crystalline region 185A1 and the amorphous region 185A2 can be arranged at a height at the Z-axis-oriented end of the first portion P1 of the channel layer 123. However, this disclosure is not limited thereto. The height at which the boundary between the crystalline region 185A1 and the amorphous region 185A2 of the doped semiconductor layer 185 is arranged can vary. For example, the boundary between the crystalline region 185A1 and the amorphous region 185A2 of the doped semiconductor layer 185 can be located at a height lower or higher than the end of the first portion P1.

[0041] A memory layer 121 may be disposed between each conductive pattern 107 and the channel layer 123. According to an embodiment, the memory layer 121 may extend between each of the first interlayer insulating layer 105 and the second interlayer insulating layer 109 and the channel layer 123. However, this disclosure is not limited thereto. According to an embodiment, the memory layer 121 may extend between each of the first interlayer insulating layer 105 and the second interlayer insulating layer 109 and the adjacent conductive pattern 107.

[0042] Memory layer 121 may include a barrier insulating layer BI, a data storage layer DS, and a tunnel insulating layer TI. The barrier insulating layer BI may include a metal oxide layer, a silicon oxide layer, etc. The data storage layer DS may include a material layer capable of storing changing data using Fowler-Nordheim tunneling. The material layer may include a nitride layer that allows charge trapping. However, embodiments of this disclosure are not limited thereto. For example, the data storage layer DS may include nanodots. The tunnel insulating layer TI may include an insulating material that allows charge tunneling. According to an embodiment, the tunnel insulating layer TI may include a silicon oxide layer. The barrier insulating layer BI may extend along the sidewall of the channel layer 123. The data storage layer DS may be disposed between the barrier insulating layer BI and the channel layer 123. The tunnel insulating layer TI may be disposed between the data storage layer DS and the channel layer 123.

[0043] The memory cell array (MCA) may further include at least one insulating layer disposed between the first insulating layer 131 and the bit line BL. According to an embodiment, the MCA may include a second insulating layer 135 between the first insulating layer 131 and the bit line BL, and a third insulating layer 139 between the second insulating layer 135 and the bit line BL. The bit line BL may pass through a fourth insulating layer 143 overlapping the third insulating layer 139. The bit line BL may be connected to a capping pattern 127 of the cell plug CPL via a bit line-channel connection structure BCC. The bit line-channel connection structure BCC may include conductive patterns having various structures. According to an embodiment, the bit line-channel connection structure BCC may include a first conductive plug 133 extending from the capping pattern 127 through the first insulating layer 131, a conductive pad 137 extending from the first conductive plug 133 through the second insulating layer 135, and a second conductive plug 141 extending from the conductive pad 137 through the third insulating layer 139.

[0044] Figure 4 This is a cross-sectional view showing a semiconductor memory device according to an embodiment of the present disclosure.

[0045] Reference Figure 4 The semiconductor memory device may include a memory cell array (MCA), a peripheral circuit structure 200, a first interconnect 153, a second interconnect 230, a first conductive bonding pad 155, and a second conductive bonding pad 231. The peripheral circuit structure 200, the first interconnect 153, the second interconnect 230, the first conductive bonding pad 155, and the second conductive bonding pad 231 may be arranged below the memory cell array (MCA). The memory cell array (MCA) may be related to the above-mentioned... Figure 3A and Figure 3B The descriptions are the same.

[0046] The first interconnect 153 and the second interconnect 230 can be connected to each other via a connection structure of the first conductive bonding pad 155 and the second conductive bonding pad 231. According to an embodiment, the first conductive bonding pad 155 and the second conductive bonding pad 231 can be connected to each other via a bonding process.

[0047] The peripheral circuit structure 200 may include a substrate 201 and a plurality of transistors TR. The substrate 201 may be a semiconductor substrate including silicon or germanium. The substrate 201 may include active regions defined by an isolation layer 203.

[0048] Multiple transistors TR can form peripheral circuitry for controlling the operation of a memory cell array (MCA). According to one embodiment, the multiple transistors TR may include transistors for controlling page buffer circuitry for bit lines BL. Each of the multiple transistors TR may include a gate insulating layer 205, a gate electrode 207, and a junction 201J. The gate insulating layer 205 and the gate electrode 207 may be stacked on an active region of the substrate 201. The junction 201J may be configured as a source region and a drain region. The junction 201J can be provided by doping the active regions exposed on both sides of the gate electrode 207 with at least one of n-type and p-type impurities.

[0049] A first interconnect 153 and a first conductive bonding pad 155 may be formed in a cell array-side insulating structure 151. The cell array-side insulating structure 151 may include a double-layer or multi-layer insulating layer. The first interconnect 153 may include conductive patterns with various structures. The first conductive bonding pad 155 may be connected to the bit line BL of the memory cell array MCA via the first interconnect 153.

[0050] The second interconnect 230 and the second conductive bonding pad 231 may be formed in the peripheral circuit-side insulation structure 210. The peripheral circuit-side insulation structure 210 may include a double-layer or multi-layer insulating layer. The second interconnect 230 may include a plurality of conductive patterns 211, 213, 215, 217, 219, 221, 223, and 225 connected to the transistor TR. The plurality of conductive patterns 211, 213, 215, 217, 219, 221, 223, and 225 may have various structures. The second conductive bonding pad 231 may be connected to the transistor TR via the second interconnect 230.

[0051] According to the above structure, the bit line BL can be connected to the transistor TR through the first interconnect 153, the first conductive bonding pad 155, the second conductive bonding pad 231, and the second interconnect 230.

[0052] Figure 5 This is a flowchart illustrating a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0053] Reference Figure 5 A method for manufacturing a semiconductor memory device may include: forming a preliminary memory cell array structure in step ST11; forming a first interconnect in step ST13; forming a first conductive bonding pad in step ST15; forming a peripheral circuit in step ST21; forming a second interconnect in step ST23; forming a second conductive bonding pad in step ST25; bonding the first conductive bonding pad to the second conductive bonding pad in step ST31; and forming a connection structure between a doped semiconductor layer and a channel layer in step ST33.

[0054] Steps ST11 and ST21 can be performed independently of each other. Therefore, the degradation of the electrical characteristics of the peripheral circuit structure caused by the high temperature required by step ST11 can be fundamentally prevented.

[0055] To maintain the electrical characteristics of the peripheral circuit structure, step ST33 can be performed at a low temperature for a short time. According to the embodiment, step ST33 can be performed using an excimer laser annealing method. Surface roughness changes and impurity diffusion can be taken into account when performing the excimer laser annealing process.

[0056] Figure 6 It is shown Figure 5 The flowchart for step ST33 is shown.

[0057] Reference Figure 6 Step ST33 may include: exposing the channel layer in step ST33A; forming an amorphous doped semiconductor layer in step ST33B; forming a crystalline region in step ST33C; and diffusing impurities in step ST33D. Step ST33A may include at least one of selective etching and chemical mechanical polishing (CMP). Step ST33B may be performed such that the amorphous doped semiconductor layer can contact the channel layer exposed in step ST33A. Steps ST33C and ST33D may be performed using the excimer laser annealing method described above. Steps ST33C and ST33D may be performed using laser beams with different energy densities.

[0058] Hereinafter, a method for manufacturing a semiconductor memory device according to an embodiment of the present disclosure will be described with reference to a cross-sectional view showing the manufacturing process.

[0059] Figure 7A , Figure 7B , Figure 7C and Figure 7D It is shown as follows Figure 5 A cross-sectional view of an embodiment of a method for manufacturing a semiconductor memory device.

[0060] Figure 7A It is shown Figure 5 A cross-sectional view of an embodiment of step ST11 shown.

[0061] Reference Figure 7A In step ST11, a preliminary memory cell array structure PMCA can be formed over the substrate 101. However, embodiments of this disclosure are not limited thereto. For example, after forming an etch stop layer (not shown) over the substrate 101, the preliminary memory cell array structure PMCA can be formed on the etch stop layer. The substrate 101 may include silicon. The etch stop layer may include a material that has etch selectivity relative to silicon (e.g., nitride).

[0062] The preliminary memory cell array structure PMCA may include a first interlayer insulating layer 105, multiple conductive patterns 107, multiple second interlayer insulating layers 109, cell plugs CPL, memory layers 121, and bit lines BL.

[0063] A first interlayer insulating layer 105 may be formed over the substrate 101. The first interlayer insulating layer 105 may include a first surface SU1 facing the substrate 101 and a second surface SU2 facing the opposite direction toward the substrate 101. A plurality of conductive patterns 107 and a plurality of second interlayer insulating layers 109 may be alternately stacked on the second surface SU2 of the first interlayer insulating layer 105.

[0064] The unit plug CPL may include a channel layer 123 passing through a first interlayer insulating layer 105, a plurality of conductive patterns 107, and a plurality of second interlayer insulating layers 109. (Refer to the above...) Figure 3A and Figure 3B As described, the channel layer 123 may have a tubular shape, and the cell plug CPL may also include a core insulating layer 125 and a capping pattern 127 that fill the central region of the tubular channel layer 123. The channel layer 123 and the core insulating layer 125 of the cell plug CPL may pass through the first surface SU1 of the first interlayer insulating layer 105 and may extend into the substrate 101.

[0065] The memory layer 121 can pass through the first interlayer insulating layer 105, multiple conductive patterns 107, and multiple second interlayer insulating layers 109. The memory layer 121 can pass through the first surface SU1 of the first interlayer insulating layer 105 and extend into the substrate 101. The memory layer 121 can extend along the sidewalls and bottom surface of the channel layer 123 and includes a barrier insulating layer BI, a data storage layer DS, and a tunnel insulating layer TI, as shown below. Figure 3B As shown.

[0066] The first interlayer insulating layer 105, multiple conductive patterns 107, multiple second interlayer insulating layers 109, memory layer 121, and cell plug CPL can be formed through multiple processes. Hereinafter, the structure including the first interlayer insulating layer 105, multiple conductive patterns 107, multiple second interlayer insulating layers 109, memory layer 121, and cell plug CPL can be defined as a preliminary memory cell string structure.

[0067] According to an embodiment, forming a preliminary memory cell string structure may include: stacking a plurality of first material layers and a plurality of second material layers alternately stacked on a first interlayer insulating layer 105; forming a hole 120; forming a memory layer 121; and forming a cell plug CPL.

[0068] The first material layer and the second material layer may be different from each other. According to one embodiment, the first material layer may include a conductive material for the conductive pattern 107, and the second material layer may include an insulating material for the second interlayer insulating layer 109. According to another embodiment, the first material layer may include a sacrificial material, and the second material layer may include an insulating material for the second interlayer insulating layer 109. For example, the sacrificial material may include a nitride, and the second interlayer insulating layer 109 may include an oxide.

[0069] Forming the via 120 may include etching multiple first material layers and multiple second material layers using an etching process with a mask pattern (not shown) as an etching barrier, and etching the substrate 101. As a result, the via 120 may extend into the substrate 101. A memory layer 121 may be formed along the surface of the via 120. Forming the cell plug CPL may include forming a channel layer 123 on the memory layer 121 and filling the central region of the via 120 with a core insulating layer 125 and a capping pattern 127. The channel layer 123 may include a semiconductor material such as silicon. The channel layer 123 may include a first portion P1, a second portion P2, and a third portion P3. The first portion P1 may correspond to the portion of the channel layer 123 adjacent to the first interlayer insulating layer 105. The third portion P3 may be the end of the channel layer 123 facing in a direction opposite to that toward the semiconductor substrate 101. The second portion P2 may be defined as another portion of the channel layer 123 between the first portion P1 and the third portion P3.

[0070] In the preliminary memory cell array structure PMCA, each of the first portion P1 and the second portion P2 of the channel layer 123 can be substantially an intrinsic region. For example, in the preliminary memory cell array structure PMCA, each of the first portion P1 and the second portion P2 of the channel layer 123 can be an undoped region. The core insulating layer 125 can have a height smaller than that of the channel layer 123. (Refer to the above...) Figure 3A and Figure 3B As described, the capping pattern 127 may include a semiconductor material containing impurities. Impurities in the capping pattern 127 may diffuse from the sidewalls of the contact capping pattern 127 of the channel layer 123 into a third portion P3 of the channel layer 123. Consequently, the third portion P3 of the channel layer 123 may be defined as a doped region.

[0071] After forming the cell plug CPL, the aforementioned mask pattern (not shown) can be removed, and the first insulating layer 131 can fill the area where the mask pattern was removed. The cell plug CPL can be covered by the first insulating layer 131. When the first material layer and the second material layer include a conductive material for the conductive pattern 107 and an insulating material for the second interlayer insulating layer 109, the first material layer and the second material layer can be retained as the conductive pattern 107 and the second interlayer insulating layer 109 surrounding the cell plug CPL, respectively. When the first material and the second material include an insulating material for the second interlayer insulating layer 109 and a sacrificial material, forming the preliminary memory cell string structure may also include replacing the first material layer including the sacrificial material with the conductive pattern 107.

[0072] After the initial memory cell string is formed, a bit line BL can be formed that is electrically connected to the cell plug CPL. The bit line BL can be connected to the cap pattern 127 of the cell plug CPL through the bit line-channel connection structure BCC.

[0073] According to an embodiment, forming a bit-line-channel connection structure (BCC) may include: forming a first conductive plug 133 through a first insulating layer 131; forming a second insulating layer 135 covering the first conductive plug 133 and the first insulating layer 131; forming a conductive pad 137 through the second insulating layer 135; forming a third insulating layer 139 covering the conductive pad 137 and the second insulating layer 135; and forming a second conductive plug 141 through the third insulating layer 139.

[0074] According to an embodiment, forming a bit line BL may include: forming a fourth insulating layer 143 covering the second conductive plug 141 and the third insulating layer 139; forming a trench through the fourth insulating layer 143 and exposing the bit line-channel connection structure BCC; and filling the trench with a conductive material.

[0075] Figure 7B It is shown as follows Figure 5 Cross-sectional view of the implementation of steps ST13 and ST15 shown.

[0076] Reference Figure 7B The cell array-side insulating structure 151, the first interconnect 153, and the first conductive bonding pad 155 can be formed through steps ST13 and ST15. The cell array-side insulating structure 151 can be formed on the preliminary memory cell array structure PMCA. The first interconnect 153 and the first conductive bonding pad 155 can be embedded in the cell array-side insulating structure 151.

[0077] According to one embodiment, step ST13 may include forming a lower insulating layer of the cell array-side insulating structure 151 and a first interconnect 153 passing through the lower insulating layer. According to another embodiment, step ST15 may include forming an upper insulating layer of the cell array-side insulating structure 151 on the lower insulating layer and forming a first conductive bonding pad 155 passing through the upper insulating layer.

[0078] Figure 7C It is shown as follows Figure 5 Cross-sectional views of examples of steps ST21, ST23, ST25, and ST31 shown.

[0079] Reference Figure 7C In step ST21, the above reference can be used to form the structure. Figure 4 The peripheral circuit structure 200 is described. Additionally, a peripheral circuit-side insulating structure 210, a second interconnect 230, and a second conductive bonding pad 231 may be formed in steps ST23 and ST25. The peripheral circuit-side insulating structure 210 may cover the peripheral circuit structure 200. The second interconnect 230 and the second conductive bonding pad 231 may be embedded in the peripheral circuit-side insulating structure 210.

[0080] Subsequently, in step ST31, by referring to Figure 7A and Figure 7B The described process provides a first conductive bonding pad 155 that can be bonded to a second conductive bonding pad 231. Additionally, the peripheral circuit-side insulation structure 210 can be bonded to the cell array-side insulation structure 151.

[0081] Figure 7D It is shown as follows Figure 6 A cross-sectional view of an embodiment of step ST33A shown.

[0082] Reference Figure 7D Step ST33A may include selectively removing, such as Figure 7C The substrate 101 is shown, and a portion of the memory layer 121 is selectively removed. As a result, a first portion P1 of the channel layer 123 is exposed. By selectively removing the substrate 101 and the memory layer 121, the first portion P1 of the channel layer 123 can be retained and protrude above the first surface SU1 of the first interlayer insulating layer 105.

[0083] Figure 8A , Figure 8B and Figure 8C It is shown as follows Figure 7D The diagram shows a cross-sectional view of the subsequent processes in region AR2.

[0084] Figure 8A It is shown Figure 6 A cross-sectional view of an embodiment of step ST33B shown.

[0085] Reference Figure 8A In step ST33B, an amorphous doped semiconductor layer 185AL may be formed on the first surface SU1 of the first interlayer insulating layer 105. The amorphous doped semiconductor layer 185AL may include at least one of n-type impurities and p-type impurities. According to an embodiment, the amorphous doped semiconductor layer 185AL may include n-type impurities.

[0086] The amorphous doped semiconductor layer 185AL can contact the first portion P1 of the channel layer 123.

[0087] Figure 8B It is shown Figure 6 A cross-sectional view of an embodiment of step ST33C shown.

[0088] Reference Figure 8B It can be achieved by making such Figure 8A The crystallization region 185A1 is defined by surface crystallization of the amorphous doped semiconductor layer 185AL shown. Crystallization of the surface of the amorphous doped semiconductor layer 185AL can be achieved by irradiating it with a laser beam having a first energy density E1. Figure 8A This is performed on the surface of the amorphous doped semiconductor layer 185AL shown. The first energy density E1 can be controlled to be lower than that made as Figure 8A The energy density at which the amorphous doped semiconductor layer 185AL melts is shown. Unlike embodiments of this disclosure, when a laser beam with a sufficiently high energy density to melt the amorphous doped semiconductor layer is irradiated, the surface roughness of the amorphous doped semiconductor layer may increase due to the unevenness defined by the first portion P1 of the channel layer 123 and the first interlayer insulating layer 105. However, according to embodiments of this teaching, this can be prevented by using a laser beam with an energy density that prevents... Figure 8A The laser beam with a first energy density E1, which melts the amorphous doped semiconductor layer 185AL shown, forms a crystalline region 185A1 to avoid the aforementioned increase in surface roughness.

[0089] In step ST33C, the irradiation range of the laser beam can be controlled so that the amorphous region 185A2 can be retained between the crystalline region 185A1 and the first interlayer insulating layer 105.

[0090] As a result of step ST33C as described above, a doped semiconductor layer 185 comprising a crystalline region 185A1 and an amorphous region 185A2 can be defined.

[0091] Figure 8C It is shown Figure 6 A cross-sectional view of an embodiment of step ST33D shown.

[0092] Reference Figure 8CIn step ST33D, impurities in the doped semiconductor layer 185 can diffuse into the first portion P1 of the channel layer 123. Step ST33D can be performed by irradiating the doped semiconductor layer 185 with a laser beam having a second energy density E2. By irradiating the doped semiconductor layer 185 with a laser beam having the second energy density, impurities in the doped semiconductor layer 185 can be activated and diffused into the first portion P1 of the channel layer 123. As a result of step ST33D, the first portion P1 of the channel layer 123 can be defined as a doped region. The second energy density E2 can be controlled to be greater than the first energy density E1 to activate and diffuse impurities in the doped semiconductor layer 185. According to an embodiment, the second energy density E2 can be greater than the energy density that melts the amorphous region 185A2 of the doped semiconductor layer 185. The amorphous region 185A2 can be melted in step ST33D.

[0093] The second energy density E2 can be controlled to be lower than the energy density that melts the crystalline region 185A1 of the doped semiconductor layer 185. According to embodiments of this disclosure, even when the amorphous region 185A2 melts, the surface of the doped semiconductor layer 185 can be stabilized by the crystalline region 185A1. Therefore, the surface roughness of the doped semiconductor layer 185 can be improved. As the surface of the doped semiconductor layer 185 is planarized, impurities in the doped semiconductor layer 185 can be controlled to have a uniform diffusion depth. Therefore, according to embodiments of this disclosure, the doped region of the channel layer 123 can be controlled to be uniform, thereby improving the electrical characteristics of the channel layer 123.

[0094] By referring to the above Figure 7D and Figures 8A to 8C In the described process, the doped semiconductor layer 185 can contact the third portion P3 of the doped region forming the channel layer 123.

[0095] Selectively, p-type impurities can be implanted into the crystalline region 185A1 of the doped semiconductor layer 185.

[0096] Figure 9A , Figure 9B and Figure 9C It is shown as follows Figure 5 The cross-sectional view of step ST33 is shown. Figure 9A , Figure 9B and Figure 9C The process shown can be referenced as above. Figure 7A , Figure 7B and Figure 7C The process described will be executed afterward. Figures 9A to 9C It is by Figures 7A to 7C The diagram shows an enlarged view of the structure provided by the process. For example, Figures 9A to 9CThis is a partial view of the first portion P1 and the second portion P2 of the channel layer 123, the first interlayer insulating layer 105, the plurality of conductive patterns 107, the plurality of second interlayer insulating layers 109, the memory layer 121, and the core insulating layer 125 associated with the first portion P1 and the second portion P2.

[0097] Figure 9A It is shown Figure 6 A cross-sectional view of an embodiment of step ST33A shown.

[0098] Reference Figure 9A You can refer to the above. Figure 7A , Figure 7B and Figure 7C Step ST33A is performed after the described process. Step ST33A can be performed using a chemical mechanical polishing (CMP) method. CMP can remove substances such as... Figure 7C The substrate 101 shown can be used to remove a portion of the memory layer 121 and a portion of the first portion P1 of the channel layer 123. As a result, the core insulating layer 125 can be exposed.

[0099] Figure 9B It is shown as follows Figure 6 Cross-sectional view of examples of steps ST33B and ST33C shown.

[0100] Reference Figure 9B By executing the above reference Figure 8A and Figure 8B The described steps ST33B and ST33C involve forming a doped semiconductor layer 185', including crystalline regions 185A1' and amorphous regions 185A2', on the first surface SU1 of the first interlayer insulating layer 105. This can be achieved by applying the doped semiconductor layer 185' to the first surface SU1 of the first interlayer insulating layer 105 as described above. Figure 8B A laser beam having a first energy density E1 is irradiated onto the surface of the described amorphous semiconductor layer to define a crystalline region 185A1'. The irradiation range of the laser beam can be controlled such that an amorphous region 185A2' of the doped semiconductor layer 185' can be disposed between the remaining first portion P1 of the channel layer 123 and the crystalline region 185A1'.

[0101] Figure 9C It is shown Figure 6 A cross-sectional view of an embodiment of step ST33D shown.

[0102] Reference Figure 9C By executing the above reference Figure 8CIn step ST33D, impurities in the doped semiconductor layer 185' can diffuse into the first portion P1 of the channel layer 123, and the impurities in the doped semiconductor layer can be activated. For impurity diffusion and activation, the second energy density E2 of the laser beam can be controlled such that the second energy density E2 is higher than the first energy density E1 and lower than the energy density that melts the crystalline region 185A1' of the doped semiconductor layer 185'.

[0103] Selectively, p-type impurities can be implanted into the crystalline region 185A1' of the doped semiconductor layer 185'.

[0104] As described above, according to embodiments of the present disclosure, after crystallization on the surface of the amorphous doped semiconductor layer, impurities can diffuse into the channel layer, thereby uniformly controlling the diffusion range of impurities. Therefore, according to embodiments of the present disclosure, the electrical characteristics of the channel layer can be uniformly controlled.

[0105] Figure 10 This is a block diagram illustrating the configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0106] Reference Figure 10 The memory system 1100 may include a memory device 1120 and a memory controller 1110.

[0107] The memory device 1120 may be a multi-chip package including multiple flash memory chips. The memory device 1120 may include: a stacked structure including multiple interlayer insulating layers and multiple conductive patterns; a doped semiconductor layer including an amorphous region overlapping the stacked structure and a crystalline region overlapping the stacked structure, wherein the amorphous region is interposed between the stacked structure and the crystalline region; and a channel layer that passes through the stacked structure.

[0108] The storage controller 1110 is configured to control the memory device 1120 and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 serves as the operating memory for the CPU 1112, which performs overall control operations for data exchange with the storage controller 1110. The host interface 1113 may include a data exchange protocol for a host connected to the memory system 1100. Additionally, the error correction block 1114 detects and corrects errors included in data read from the memory device 1120, and the memory interface 1115 performs interfacing with the memory device 1120. Furthermore, the storage controller 1110 may also include a read-only memory (ROM) storing code data for interfacing with the host.

[0109] The memory system 1100 may be a memory card or solid-state drive (SSD) that integrates a memory device 1120 and a storage controller 1110. For example, when the memory system 1100 is used as an SSD, the storage controller 1110 may communicate with an external device (e.g., a host) via one of the following interface protocols: Universal Serial Bus (USB), Multimedia Card (MMC), High-Speed ​​Peripheral Component Interconnect (PCI-E), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE).

[0110] Figure 11 This is a block diagram illustrating the configuration of a computing system 1200 according to an embodiment of the present disclosure.

[0111] Reference Figure 11 The computing system 1200 may include a CPU 1220, random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210 electrically connected to a system bus 1260. Additionally, when the computing system 1200 is a mobile device, it may also include a battery for supplying operating voltage to the computing system 1200. Furthermore, it may include an application chipset, a graphics processor, mobile DRAM, etc.

[0112] The memory system 1210 may include a memory device 1212 and a memory controller 1211.

[0113] The memory device 1212 may include: a stacked structure including a plurality of interlayer insulating layers and a plurality of conductive patterns; a doped semiconductor layer including an amorphous region overlapping the stacked structure and a crystalline region overlapping the stacked structure, wherein the amorphous region is interposed between the stacked structure and the crystalline region; and a channel layer passing through the stacked structure.

[0114] Storage controller 1211 may have the same features as referenced above. Figure 10 The storage controller 1110 described has the same configuration.

[0115] According to embodiments of the present disclosure, the electrical characteristics of the channel layer can be uniformly controlled, thereby improving the operational reliability of the semiconductor memory device.

[0116] Cross-application of related applications

[0117] This application claims priority to Korean Patent Application No. 10-2021-0150102, filed with the Korean Intellectual Property Office on November 3, 2021, the full disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: Multiple conductive patterns and multiple second interlayer insulating layers are arranged alternately below a first interlayer insulating layer; A doped semiconductor layer comprising an amorphous region overlapping the first interlayer insulating layer and a crystalline region overlapping the first interlayer insulating layer, wherein the amorphous region is interposed between the first interlayer insulating layer and the crystalline region; A channel layer that contacts the doped semiconductor layer and extends through the first interlayer insulating layer, the plurality of second interlayer insulating layers, and the plurality of conductive patterns; as well as A memory layer is located between the various conductive patterns and the channel layer.

2. The semiconductor memory device according to claim 1, wherein, The portion of the channel layer adjacent to the doped semiconductor layer includes impurities.

3. The semiconductor memory device according to claim 2, wherein, The impurity is an n-type impurity.

4. The semiconductor memory device according to claim 1, wherein, The channel layer extends into the amorphous region of the doped semiconductor layer.

5. The semiconductor memory device according to claim 1, wherein, The amorphous region of the doped semiconductor layer is disposed between the channel layer and the crystalline region of the doped semiconductor layer.

6. A method for manufacturing a semiconductor memory device, the method comprising the following steps: A preliminary memory cell array structure is formed, which includes a first interlayer insulating layer, a plurality of conductive patterns and a plurality of second interlayer insulating layers, a channel layer and a memory layer. The first interlayer insulating layer has a first surface and a second surface facing opposite directions. The plurality of conductive patterns and the plurality of second interlayer insulating layers are alternately stacked on top of the second surface of the first interlayer insulating layer. The channel layer passes through the first interlayer insulating layer, the plurality of conductive patterns and the plurality of second interlayer insulating layers, and the memory layer is located between each of the plurality of conductive patterns and the channel layer. An amorphous doped semiconductor layer is formed on the first surface of the first interlayer insulating layer; A doped semiconductor layer comprising crystalline and amorphous regions is formed by crystallizing the surface of the amorphous doped semiconductor layer, wherein the amorphous regions are located between the crystalline regions and the first interlayer insulating layer. as well as This allows impurities in the doped semiconductor layer to diffuse into the channel layer.

7. The method according to claim 6, wherein, The step of crystallizing the surface of the amorphous doped semiconductor layer includes irradiating the surface of the amorphous doped semiconductor layer with a laser beam having a first energy density, and The step of diffusing the impurities in the doped semiconductor layer into the channel layer includes irradiating the doped semiconductor layer with a laser beam having a second energy density.

8. The method according to claim 7, wherein, The first energy density is controlled to be lower than the energy density that melts the amorphous doped semiconductor layer.

9. The method according to claim 7, wherein, The second energy density is controlled to be lower than the energy density that melts the crystalline region of the doped semiconductor layer.

10. The method according to claim 7, wherein, The second energy density is controlled to be higher than the first energy density.

11. The method according to claim 6, wherein, The step of diffusing the impurities in the doped semiconductor layer into the channel layer includes melting the amorphous regions of the doped semiconductor layer.

12. The method according to claim 6, wherein, The step of forming the preliminary memory cell array structure is performed on top of the substrate, and The channel layer and the memory layer extend into the substrate.

13. The method of claim 12, further comprising the step of: Before forming the amorphous doped semiconductor layer Remove portions of the substrate and the memory layer to expose the channel layer.

14. The method according to claim 13, wherein, The exposed area of ​​the trench layer protrudes above the first surface of the first interlayer insulation layer.

15. The method according to claim 13, wherein, The step of removing portions of the substrate and the memory layer is performed by a chemical mechanical polishing (CMP) method.

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