Semiconductor package including stacked semiconductor chips

Abstract

The present disclosure relates to semiconductor packages including stacked semiconductor chips. A semiconductor package can include a substrate having a first side and a second side on a same plane, a first semiconductor chip disposed above the second side of the substrate, a first one-side third semiconductor chip stack disposed above the first side of the substrate and spaced apart from the first semiconductor chip, a second semiconductor chip stack disposed above the first semiconductor chip and the first one-side third semiconductor chip stack, the second semiconductor chip stack including one or more second semiconductor chips, and a second one-side third semiconductor chip stack disposed above the second semiconductor chip stack, wherein each third semiconductor chip stack includes a plurality of third semiconductor chips offset stacked, the plurality of third semiconductor chips being offset toward the first side as the third semiconductor chips are further from the substrate, and each third semiconductor chip stack is electrically connected to the substrate.

Description

Technical Field

[0001] This patent document relates to semiconductor technology, and more specifically, to a semiconductor package in which multiple semiconductor chips are stacked vertically. Background Technology

[0002] Electronic products require multifunctionality and high-capacity data processing, while their size is becoming increasingly smaller. Therefore, semiconductor packages used in such electronic products need to include multiple semiconductor chips and be manufactured to a specified size or smaller.

[0003] Recently, a system-in-package (SIP) has been proposed that integrates the memory and memory controller together in a single package. Summary of the Invention

[0004] In one embodiment, a semiconductor package may include: a substrate having a first side and a second side, the first side and the second side being opposite sides of the substrate in a first direction; a first semiconductor chip disposed above the substrate; a first-side third semiconductor chip stack disposed above the substrate and spaced apart from the first semiconductor chip, the first-side third semiconductor chip stack being closer to the first side than the first semiconductor chip; a second semiconductor chip stack disposed above the first semiconductor chip and the first-side third semiconductor chip stack, the second semiconductor chip stack including one or more second semiconductor chips; and a second-side third semiconductor chip stack disposed above the second semiconductor chip stack, wherein each of the first-side third semiconductor chip stack and the second-side third semiconductor chip stack includes a plurality of offset stacked third semiconductor chips, the plurality of third semiconductor chips being offset toward the first side as the third semiconductor chips move further away from the substrate, such that chip pads disposed on the other edge region of the plurality of third semiconductor chips are exposed, and wherein each of the first-side third semiconductor chip stack and the second-side third semiconductor chip stack is electrically connected to the substrate by bonding leads extending to the substrate while connecting the chip pads of the plurality of third semiconductor chips to each other.

[0005] In another embodiment, a semiconductor package may include: a substrate having a first side and a second side, the first side and the second side being opposite sides of the substrate in a first direction; a first semiconductor chip disposed above the substrate; a first-side third semiconductor chip stack disposed above the substrate and spaced apart from the first semiconductor chip, the first-side third semiconductor chip stack being closer to the first side than the first semiconductor chip; a second semiconductor chip stack disposed above the first-side third semiconductor chip stack, the second semiconductor chip stack including one or more second semiconductor chips; and a second-side third semiconductor chip stack disposed above the first semiconductor chip, wherein each of the first-side third semiconductor chip stack and the second-side third semiconductor chip stack includes a plurality of offset stacked third semiconductor chips, the plurality of third semiconductor chips being offset toward the first side as the third semiconductor chips are further away from the substrate, such that chip pads disposed on the other edge region of the plurality of third semiconductor chips are exposed, and wherein each of the first-side third semiconductor chip stack and the second-side third semiconductor chip stack is electrically connected to the substrate by bonding leads extending to the substrate while connecting the chip pads of the plurality of third semiconductor chips to each other. Attached Figure Description

[0006] Figure 1 This is a schematic diagram illustrating an example of a data processing system that includes a memory system according to an embodiment of the present disclosure.

[0007] Figure 2A This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure.

[0008] Figure 2B It's viewed from above. Figure 2A Floor plan.

[0009] Figure 2C It is shown in a plan view Figure 2A A diagram showing the arrangement of the external connection electrodes.

[0010] Figure 3A This is a cross-sectional view showing a semiconductor package according to another embodiment of the present disclosure.

[0011] Figure 3B It's viewed from above. Figure 3A Floor plan.

[0012] Figure 3C It's viewed from above. Figure 3A Another plan view.

[0013] Figure 4A This is a cross-sectional view showing a semiconductor package according to another embodiment of the present disclosure.

[0014] Figure 4B It's viewed from above. Figure 4A Floor plan.

[0015] Figure 5A This is a cross-sectional view showing a semiconductor package according to another embodiment of the present disclosure.

[0016] Figure 5B It's viewed from above. Figure 5A Floor plan.

[0017] Figure 6 This is a cross-sectional view showing a semiconductor package according to another embodiment of the present disclosure. Detailed Implementation

[0018] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0019] The accompanying drawings are not necessarily drawn to scale. In some cases, the scale of at least some structures in the drawings may have been exaggerated in order to clearly show specific features of the described embodiments. When a particular example of a multilayer structure with two or more layers is presented in the drawings or description, the relative positioning of these layers or the order of their arrangement reflects a specific implementation of the described or illustrated example, and different relative positioning or order of layer arrangement may be possible. Furthermore, the described or illustrated example of a multilayer structure may not reflect all the layers present in that particular multilayer structure (e.g., one or more additional layers may exist between two illustrated layers). As a specific example, when the first layer in a described or illustrated multilayer structure is referred to as "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or the substrate, but it may also indicate a structure in which one or more other intermediate layers may exist between the first layer and the second layer or the substrate.

[0020] Figure 1 This is a schematic diagram illustrating an example of a data processing system that includes a memory system according to an embodiment of the present disclosure.

[0021] Reference Figure 1 The data processing system 100 may include a host 110 and a memory system 120.

[0022] Host 110 may include various wired and / or wireless electronic devices, such as mobile phones, MP3 players, laptops, desktop computers, game consoles, TVs, and projectors. Additionally, host 110 may include at least one operating system (OS). This operating system typically manages and controls the functions and operation of host 110 and can be executed using data processing system 100 or memory system 120 in response to user requests.

[0023] The memory system 120 can perform various operations in response to requests from the host 110. Specifically, the memory system 120 can store data accessed by the host 110. That is, the memory system 120 can be used as a main memory device or an auxiliary memory device of the host 110.

[0024] The memory system 120 may include one or more memory devices (e.g., a first memory device 140 and a second memory device 150) and a memory controller 130. In this embodiment, the operation of the first memory device 140 may be directly controlled by the host 110, and the operation of the second memory device 150 may be controlled by the memory controller 130.

[0025] The first memory device 140 may include volatile memory such as dynamic random access memory (DRAM) and static random access memory (SRAM). The second memory device 150 may include non-volatile memory such as NAND flash memory, resistive random access memory (RRAM), phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), and ferroelectric random access memory (FRAM). Specifically, in this embodiment, the first memory device 140 may include DRAM, and the second memory device 150 may include NAND flash memory. Non-volatile memory can be memory with relatively slow speed and relatively large capacity, and can perform the function of storing data or retaining stored data for a long time. Volatile memory can be memory with relatively high speed and relatively small capacity, and can perform the function of temporarily storing data.

[0026] The storage controller 130 can control the second storage device 150 in response to a request from the host 110. As an example, the storage controller 130 can provide data read from the second storage device 150 to the host 110, or it can store data provided from the host 110 into the second storage device 150. The storage controller 130 may include a central processing unit (CPU), a controller, an application-specific integrated circuit (ASIC), an application processor (AP), etc.

[0027] To enable the storage controller 130 to perform operations such as receiving commands from or transmitting data to the host 110, signals can be sent between the storage controller 130 and the host 110. Additionally, to enable the storage controller 130 to access the second memory device 150 under the control of the processor to perform read / write / erase operations, signals can be sent between the storage controller 130 and the second memory device 150. Furthermore, to enable the host 110 to access the first memory device 140 to perform operations, signals can be sent between the host 110 and the first memory device 140. These signal transmission paths are indicated by arrows between the storage controller 130 and the host 110, between the storage controller 130 and the second memory device 150, and between the host 110 and the first memory device 140.

[0028] Additionally, to enable operation of the first memory device 140 and the second memory device 150, power can be supplied to them. This power supply may include various levels of power supply voltage or ground voltage required for each of the first memory device 140 and the second memory device 150. Therefore, power can be supplied to each of the first memory device 140 and the second memory device 150 from a powered external device (not shown). These power supply paths are indicated by arrows between the first memory device 140 and the external device, and between the second memory device 150 and the external device.

[0029] In the data processing system 100 described above, the first memory device 140 may be implemented as one or more first memory chips, the second memory device 150 may be implemented as one or more second memory chips different from the first memory chips, and the memory controller 130 may be implemented as one or more controller chips. Furthermore, the memory system 120 including the first memory device 140, the second memory device 150, and the memory controller 130 may be implemented as a single package. This will be described in more detail with reference to the following figures.

[0030] Figure 2A This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure. Figure 2B It's viewed from above. Figure 2A Floor plan. Figure 2A Can correspond to Figure 2B Cross-sectional view in the first direction. Figure 2C It is shown in a plan view Figure 2A A diagram showing the arrangement of the external connection electrodes. For ease of description, in Figure 2B The image shows not only the substrate 200 and the third semiconductor chip stack 230, but also a second semiconductor chip stack 220 positioned below and partially covered by the third semiconductor chip stack 230. Additionally, Figure 2B It also shows Figure 2C The power connection electrode 240P in the external connection electrode 240 is used to supply power to the third semiconductor chip stack 230. For reference, since Figure 2A The external connection electrode 240 is schematically shown in the diagram. Figure 2A The exact arrangement of the external connection electrodes 240 is not shown in the diagram, so... Figure 2A The arrangement of the external connection electrodes 240 may be related to Figure 2B and Figure 2C The arrangement is mismatched. The arrangement of the external connection electrode 240 in the plan view will refer to... Figure 2B and Figure 2C describe.

[0031] First, refer to Figure 2A and Figure 2B The semiconductor package of this embodiment may include a substrate 200, a first semiconductor chip 210, a second semiconductor chip stack 220, a third semiconductor chip stack 230, and an external connection electrode 240. The first semiconductor chip 210, the second semiconductor chip stack 220, and the third semiconductor chip stack 230 may be disposed above one surface (e.g., the upper surface) of the substrate 200 and may be stacked in the vertical direction. The external connection electrode 240 may be disposed above another surface (e.g., the lower surface) of the substrate 200.

[0032] The substrate 200 may include circuitry and / or wiring structures for electrically connecting the first semiconductor chip 210, the second semiconductor chip stack 220, and the third semiconductor chip stack 230 to external connection electrodes 240. For example, the substrate 200 may include a printed circuit board (PCB), an interposer, a redistribution layer, etc. Various upper substrate pads for connecting to the first semiconductor chip 210, the second semiconductor chip stack 220, and the third semiconductor chip stack 230 may be disposed on the upper surface of the substrate 200, and various lower substrate pads for connecting to the external connection electrodes 240 may be disposed on the lower surface of the substrate 200. These upper and lower substrate pads may be part of the circuitry and / or wiring structures of the substrate 200, or may be electrically connected to the circuitry and / or wiring structures of the substrate 200. Figure 2AIn the cross-sectional view, for ease of description, only the upper substrate pads 202A and 202B, which are powered by connection to the third semiconductor chip stack 230, are shown. As described later, the third semiconductor chip stack 230 may include a first-side third semiconductor chip stack 230A and a second-side third semiconductor chip stack 230B respectively disposed on a first side and a second side of the substrate 200 in a first direction. The upper substrate pads 202A and 202B may include a first-side upper substrate pad 202A for powering the first-side third semiconductor chip stack 230A and a second-side upper substrate pad 202B for powering the second-side third semiconductor chip stack 230B. Additionally, in Figure 2A In the cross-sectional view, for ease of description, only the first-side wiring structure 204A and the second-side wiring structure 204B, respectively connected to the first-side upper substrate pad 202A and the second-side upper substrate pad 202B, are shown on substrate 200. Each of the first-side wiring structure 204A and the second-side wiring structure 204B may be formed based on a combination of various conductive patterns extending in the vertical and / or horizontal directions to connect from each of the first-side upper substrate pad 202A and the second-side upper substrate pad 202B to the corresponding power connection electrode 240P. The conductive pattern extending in the vertical direction may be, for example, a conductive via, and the conductive pattern extending in the horizontal direction may be, for example, a conductive trace or a conductive plate.

[0033] The first semiconductor chip 210 may be disposed above the upper surface of the substrate 200 and may be connected to the substrate 200 by a flip-chip bonding method based on a connection electrode 212 formed above the lower surface of the first semiconductor chip 210 directly contacting the upper surface of the substrate 200. The connection electrode 212 may have various shapes such as columnar, spherical, or combinations thereof, and may include various conductive materials such as solder, metal, or combinations thereof. However, this disclosure is not limited thereto, and the first semiconductor chip 210 may be electrically connected to the substrate 200 via various interconnects such as bonding leads.

[0034] The first semiconductor chip 210 may correspond to a controller chip for controlling the second semiconductor chip stack 220 and / or the third semiconductor chip stack 230. As an example, when the second semiconductor chip stack 220 and the third semiconductor chip stack 230 include memory chips, the first semiconductor chip 210 may correspond to the aforementioned... Figure 1 Storage controller 130.

[0035] The second semiconductor chip stack 220 may be disposed above the first semiconductor chip 210. The second semiconductor chip stack 220 may include one or more second semiconductor chips 220-1 and 220-2 stacked in the vertical direction. In this embodiment, the case of two second semiconductor chips 220-1 and 220-2 stacked is shown, but this disclosure is not limited thereto. Assuming that one or more second semiconductor chips are included in the second semiconductor chip stack 220, the number of second semiconductor chips stacked in the vertical direction can be modified differently. That is, the second semiconductor chip stack 220 may include only a single second semiconductor chip.

[0036] The second semiconductor chips 220-1 and 220-2 can be the same chip (specifically, the same memory chip). As an example, each of the second semiconductor chips 220-1 and 220-2 can be a volatile memory chip such as DRAM. That is, each of the second semiconductor chips 220-1 and 220-2 can correspond to the above-described... Figure 1 The first memory device 140. When the second semiconductor chips 220-1 and 220-2 are the same chips, they may have the same dimensions in the horizontal direction and the same thickness in the vertical direction.

[0037] In this embodiment, the second semiconductor chips 220-1 and 220-2 can be stacked with the active surface where the chip pads 222 are provided facing upwards and the passive surface facing downwards (i.e., face-up state). Furthermore, the second semiconductor chips 220-1 and 220-2 can be arranged such that their side surfaces are aligned with each other. The chip pads 222 can be provided in a first direction on a first side edge region (e.g., on the left edge region) of each of the second semiconductor chips 220-1 and 220-2, and can be electrically connected to the substrate 200 via bonding leads 224. However, this disclosure is not limited to this; the stacking configuration of the second semiconductor chips 220-1 and 220-2, the arrangement of the chip pads 222, and the interconnects connecting the substrate 200 to the second semiconductor chips 220-1 and 220-2 can be modified differently.

[0038] Each of the second semiconductor chips 220-1 and 220-2 can be attached to the upper surface of the first semiconductor chip 210 or the second semiconductor chip 220-1 directly below it via an adhesive layer 226 formed above its passive surface. The adhesive layer 226 may comprise an insulating adhesive material such as a die-attach film (DAF). The adhesive layer 226 beneath the upper second semiconductor chip 220-2 may be thick enough to cover the peaks of the bonding leads 224 of the chip pads 222 connected to the lower second semiconductor chip 220-1. For example, the adhesive layer 226 beneath the upper second semiconductor chip 220-2 may have a greater thickness than the adhesive layer 226 beneath the lower second semiconductor chip 220-1.

[0039] One or more second semiconductor chip stacks 220 may be arranged to be spaced apart from each other in a horizontal direction. As an example, such as... Figure 2B As shown in the plan view, two second semiconductor chip stacks 220 can be arranged in a second direction substantially perpendicular to the first direction. The first side is positioned in the second direction (e.g., Figure 2B The first of two second semiconductor chip stacks 220 (located on the lower side of the plan view) may be referred to as the first side second semiconductor chip stack 220A, which is disposed on the second side in the second direction (e.g., Figure 2B The second of the two second semiconductor chip stacks 220 (located on the upper side of the plan view) may be referred to as the second side second semiconductor chip stack 220B. However, this disclosure is not limited thereto, and the number and arrangement of the second semiconductor chip stacks 220 may be modified differently.

[0040] The first-side second semiconductor chip stack 220A and the second-side second semiconductor chip stack 220B can be connected to different channels. Here, a channel can refer to an independent path for sending signals such as commands or data to a corresponding semiconductor chip or semiconductor chip stack. Furthermore, the plurality of second semiconductor chips 220-1 and 220-2 included in the first-side second semiconductor chip stack 220A can be connected to different channels or to the same channel. Similarly, the plurality of second semiconductor chips 220-1 and 220-2 included in the second-side second semiconductor chip stack 220B can be connected to different channels or to the same channel.

[0041] The second semiconductor chip stack 220 may have a width corresponding to W2 in a first direction and a width corresponding to W2' in a second direction. As in this embodiment, when the second semiconductor chips 220-1 and 220-2 have side surfaces aligned with each other, each of the second semiconductor chips 220-1 and 220-2 may have a width corresponding to W2 in the first direction and a width corresponding to W2' in the second direction. If the second semiconductor chips 220-1 and 220-2 do not have side surfaces aligned with each other, each of the second semiconductor chips 220-1 and 220-2 may have a width smaller than W2 in the first direction and / or a width smaller than W2' in the second direction. In any case, the area occupied by the second semiconductor chip stack 220 in the horizontal direction may be larger than the area of ​​the first semiconductor chip 210. As an example, such as Figure 2A As shown in the cross-sectional view, in the first direction, the width W1 of the first semiconductor chip 210 may be smaller than the width W2 of the second semiconductor chip stack 220. Therefore, a tilting phenomenon may occur where the second semiconductor chip stack 220 is tilted above the first semiconductor chip 210. To prevent this phenomenon, a dummy semiconductor chip 215 may be further disposed in the space between the substrate 200 and the second semiconductor chip stack 220, and may be adjacent to the first semiconductor chip 210. The dummy semiconductor chip 215 may not perform any electrical function and may not be electrically connected to other components. The dummy semiconductor chip 215 may simply support the second semiconductor chip stack 220 below it. Although this figure shows two dummy semiconductor chips 215 disposed on both sides of the first semiconductor chip 210 in the first direction, the disclosure is not limited thereto, and the number and position of the dummy semiconductor chips 215 may be modified differently. The dummy semiconductor chip 215 may be attached to the upper surface of the substrate 200 by forming an adhesive layer 217 above its lower surface. The total thickness of the dummy semiconductor chip 215 and the adhesive layer 217 can be substantially the same as the total thickness of the first semiconductor chip 210 and the connecting electrode 212. Therefore, in the vertical direction, the upper surface of the dummy semiconductor chip 215 and the upper surface of the first semiconductor chip 210 can be positioned at substantially the same height. The adhesive layer 226 below the lower second semiconductor chip 220-1 can be attached to the upper surfaces of the dummy semiconductor chip 215 and the first semiconductor chip 210, which are positioned at the same height.

[0042] The third semiconductor chip stack 230 may be disposed above the second semiconductor chip stack 220. The third semiconductor chip stack 230 may include a plurality of third semiconductor chips 230-1 to 230-4 stacked in the vertical direction. In this embodiment, a case of four third semiconductor chips 230-1 to 230-4 stacked is shown, but the present disclosure is not limited thereto, and the number of third semiconductor chips stacked in the vertical direction may be modified in different ways.

[0043] The third semiconductor chips 230-1 to 230-4 can be the same chip (specifically, the same memory chip). As an example, each of the third semiconductor chips 230-1 to 230-4 can be a non-volatile memory chip such as NAND flash memory. That is, each of the third semiconductor chips 230-1 to 230-4 can correspond to the above-described... Figure 1 The second memory device 150. When the third semiconductor chips 230-1 to 230-4 are identical chips, they may have the same dimensions in the horizontal direction and the same thickness in the vertical direction. However, this disclosure is not limited thereto, and the thicknesses of the third semiconductor chips 230-1 to 230-4 may differ from each other in the vertical direction. For example, the thickness of the lowermost third semiconductor chip 230-1 may be greater than the thickness of each of the remaining third semiconductor chips 230-2 to 230-4.

[0044] Here, at least two third semiconductor chip stacks 230 can be arranged to be spaced apart from each other in a horizontal direction. As an example, the two third semiconductor chip stacks 230 can be arranged in a first direction. One of the two third semiconductor chip stacks 230 disposed on the first side (e.g., the left side in the first direction) can be referred to as a first-side third semiconductor chip stack 230A, and the other of the two third semiconductor chip stacks 230 disposed on the second side (e.g., the right side in the first direction) can be referred to as a second-side third semiconductor chip stack 230B. The first-side third semiconductor chip stack 230A and the second-side third semiconductor chip stack 230B can be connected to different channels.

[0045] In each of the first and third semiconductor chip stacks 230A and the second third semiconductor chip stack 230B, the third semiconductor chips 230-1 to 230-4 can be stacked with the active surface of the chip pad 232 facing upward and the passive surface facing downward (i.e., in the upward facing state).

[0046] Here, the chip pads 232 of the first-side third semiconductor chip stack 230A may be disposed on the edge region of the first side, for example, on the left edge region of each of the third semiconductor chips 230-1 to 230-4 in the first direction. Although not shown, a plurality of chip pads 232 may be arranged along the second direction in the edge region of the first side. The third semiconductor chips 230-1 to 230-4 of the first-side third semiconductor chip stack 230A may be stacked such that all chip pads 232 are exposed. For example, the third semiconductor chips 230-1 to 230-4 of the first-side third semiconductor chip stack 230A may be stacked such that as the third semiconductor chips in the first-side third semiconductor chip stack 230A move further away from the substrate 200, they are offset from the first side (e.g., from the left side where the chip pads 232 are disposed) toward the second side (e.g., toward the right side). The third semiconductor chip stack 230A on the first side can be electrically connected to the substrate 200 via bonding leads 234. The bonding leads 234 connect the exposed chip pads 232 of the third semiconductor chips 230-1 to 230-4 to each other and connect the chip pad 232 of the lowest third semiconductor chip 230-1 to the upper substrate pad 202A on the first side.

[0047] On the other hand, the chip pads 232 of the second-side third semiconductor chip stack 230B may be disposed on the edge region of the second side, for example, on the right edge region of each of the third semiconductor chips 230-1 to 230-4 in the first direction. Although not shown, a plurality of chip pads 232 may be arranged along the second direction in the edge region of the second side. The third semiconductor chips 230-1 to 230-4 of the second-side third semiconductor chip stack 230B may be stacked such that all chip pads 232 are exposed. For example, the third semiconductor chips 230-1 to 230-4 of the second-side third semiconductor chip stack 230B may be stacked such that as the third semiconductor chips in the first-side third semiconductor chip stack 230A move further away from the substrate 200, they are offset from the second side (e.g., from the right side where the chip pads 232 are disposed) toward the first side (e.g., toward the left side). The second-side third semiconductor chip stack 230B can be substantially mirrored from the first-side third semiconductor chip stack 230A along the vertical axis between the two third semiconductor chip stacks 230. The second-side third semiconductor chip stack 230B can be electrically connected to the substrate 200 via bonding leads 234, which connect the exposed chip pads 232 of the third semiconductor chips 230-1 to 230-4 to each other and connect the chip pad 232 of the lowest third semiconductor chip 230-1 to the second-side upper substrate pad 202B.

[0048] Each of the third semiconductor chips 230-1 to 230-4 may be attached to the upper surface of one of the third semiconductor chips 230-1 to 230-3 or the second semiconductor chip stack 220 directly positioned below it via an adhesive layer 236 formed above its passive surface. The adhesive layer 236 may comprise an insulating adhesive material such as DAF. The adhesive layer 236 below the lowermost third semiconductor chip 230-1 may be thick enough to cover the peaks of the bonding leads 224 of the chip pads 222 connected to the upper second semiconductor chip 220-2. For example, the thickness of the adhesive layer 236 below the lowermost third semiconductor chip 230-1 may be greater than the thickness of the adhesive layer 236 below each of the remaining third semiconductor chips 230-2 to 230-4.

[0049] The third semiconductor chip stack 230 may have a width corresponding to W4 in a first direction and a width corresponding to W3' in a second direction. In this embodiment, the third semiconductor chips 230-1 to 230-4 may be offset in the first direction to have side surfaces that are not aligned with each other, while having side surfaces that are aligned with each other in the second direction. In this case, each of the third semiconductor chips 230-1 to 230-4 may have a width corresponding to W3 (less than W4) in the first direction and a width corresponding to W3' in the second direction. If the third semiconductor chips 230-1 to 230-4 also have side surfaces that are not aligned with each other in the second direction, then each of the third semiconductor chips 230-1 to 230-4 may have a width less than W3' in the second direction. In any case, in the first direction, the width W4 of the third semiconductor chip stack 230 may be less than the width W2 of the second semiconductor chip stack 220. Furthermore, in the second direction, the width W3' of the third semiconductor chip stack 230 may be greater than the width W2' of the second semiconductor chip stack 220. As an example, such as Figure 2A Cross-sectional view and Figure 2B As shown in the plan view, in the first direction, twice the width W4 of the third semiconductor chip stack 230 may be equal to or less than the width W2 of the second semiconductor chip stack 220, and in the second direction, the width W3' of the third semiconductor chip stack 230 may be equal to or greater than twice the width W2' of the second semiconductor chip stack 220.

[0050] Multiple external connection electrodes 240 may be disposed above the lower surface of the substrate 200. The external connection electrodes 240 may have various shapes such as columnar, spherical, or combinations thereof, and may include various conductive materials such as solder materials, metallic materials, or combinations thereof.

[0051] Based on the above semiconductor packaging, different types of memory and controllers can be integrated into a single package while minimizing the package area and thickness.

[0052] Furthermore, in the plan view, Figure 2C The arrangement of external connection electrodes 240 in a semiconductor package is illustrated by way of example.

[0053] Reference Figure 2C External connection electrodes 240 may be arranged in a first direction and a second direction. Each external connection electrode 240 may be used as a terminal for exchanging signals with an external device or for powering a device from an external device. Specifically, some external connection electrodes 240 that supply power to the third semiconductor chips 230-1 to 230-4 may be shaded diagonally and referred to as power connection electrodes 240P.

[0054] In this configuration, the arrangement of the external connection electrodes 240 or the function of each external connection electrode 240 can be fixed according to a predetermined sphere diagram. According to this sphere diagram, the power connection electrode 240P for supplying power to the NAND flash memory that can be used as third semiconductor chips 230-1 to 230-4 can be configured to be relatively biased towards a second side (e.g., the right side) in a first direction. In other words, in the first direction, the power connection electrode 240P can be positioned closer to the second side (e.g., the right side) compared to the first side (e.g., the left side) of the substrate 200.

[0055] Refer to Figure 2A and Figure 2B Since the power connection electrode 240P is disposed opposite to the second side (e.g., the right side) in the first direction, the length of the first side wiring structure 204A can be greater than the length of the second side wiring structure 204B. The length of the first side wiring structure 204A can be the distance from the first side upper substrate pad 202A connected to the first side third semiconductor chip stack 230A via bonding lead 234 to the first corresponding power connection electrode in the power connection electrode 240P, and the length of the second side wiring structure 204B can be the distance from the second side upper substrate pad 202B connected to the second side third semiconductor chip stack 230B via bonding lead 234 to the second corresponding power connection electrode in the power connection electrode 240P.

[0056] As a result, power integrity may be degraded because it is relatively difficult to supply power to the third semiconductor chip stack 230A, which is set to be relatively far away from the power connection electrode 240P on the first side.

[0057] In addition, since the relatively long wiring structure 204A on one side of the substrate 200 must avoid other wiring structures, it may be difficult to design the circuit / wiring structure in the substrate 200.

[0058] The following will propose areas for further improvement. Figure 2A and Figure 2BThis describes the implementation method for improving the performance of semiconductor memory and facilitating the design of substrate 200.

[0059] Figure 3A This is a cross-sectional view showing a semiconductor package according to another embodiment of the present disclosure. Figure 3B It's viewed from above. Figure 3A A floor plan. For ease of description, Figure 3B Not only are substrate 300 and the second-side third semiconductor chip stack 330B shown, but also the second semiconductor chip stack 320 and the first-side third semiconductor chip stack 330A are shown, at least a portion of which are covered. The main description will be related to... Figure 2A and Figure 2B The differences between the above-described implementation methods.

[0060] Reference Figure 3A and Figure 3B The semiconductor package of this embodiment may include a substrate 300, a first semiconductor chip 310, a second semiconductor chip stack 320, a third semiconductor chip stack 330 including a third semiconductor chip stack 330A on a first side and a third semiconductor chip stack 330B on a second side, and an external connection electrode 340 including a power connection electrode 340P.

[0061] The substrate 300 may include a first-side upper substrate pad 302A for supplying power to a first-side third semiconductor chip stack 330A and a second-side upper substrate pad 302B for supplying power to a second-side third semiconductor chip stack 330B. Additionally, the substrate 300 may include a first-side wiring structure 304A connecting from the first-side upper substrate pad 302A to a first corresponding power connection electrode in the power connection electrode 340P, and a second-side wiring structure 304B connecting from the second-side upper substrate pad 302B to a second corresponding power connection electrode in the power connection electrode 340P.

[0062] The first semiconductor chip 310 may be disposed above the upper surface of the substrate 300 and connected to the substrate 300 via a connection electrode 312 formed on the lower surface of the first semiconductor chip 310. The first semiconductor chip 310 may be configured to be relatively biased toward a second side (e.g., to the right in the first direction). In other words, the first semiconductor chip 310 may be configured to be closer to the second side (e.g., the right side) of the substrate 300 in the first direction than to the first side (e.g., the left side). This may be to provide space in which a first-side third semiconductor chip stack 330A is disposed on the first side (e.g., the left side) of the first semiconductor chip 310. The structure and position of the first-side third semiconductor chip stack 330A will be described later.

[0063] A second semiconductor chip stack 320 may be disposed above a first semiconductor chip 310 and a first-side third semiconductor chip stack 330A. The second semiconductor chip stack 320 may include one or more second semiconductor chips 320-1 and 320-2 stacked in a vertical direction. Each of the second semiconductor chips 320-1 and 320-2 may be attached to the upper surface of the first semiconductor chip 310 or the second semiconductor chip 320-1 directly positioned below it via an adhesive layer 326 formed above its passive surface. The second semiconductor chips 320-1 and 320-2 may be electrically connected to the substrate 300 via bonding leads 324 connected to chip pads 322. The second semiconductor chip stack 320 may include a first-side second semiconductor chip stack 320A and a second-side second semiconductor chip stack 320B arranged spaced apart from each other in a second direction.

[0064] The first side of the third semiconductor chip stack 330, the third semiconductor chip stack 330A, can be disposed vertically between the substrate 300 and the second semiconductor chip stack 320. That is, the first side of the third semiconductor chip stack 330A can be positioned vertically at the same height as the first semiconductor chip 310. The thickness of the first side of the third semiconductor chip stack 330A can be substantially equal to the sum of the thicknesses of the first semiconductor chip 310 and the connecting electrode 312. Therefore, the upper surface of the first side of the third semiconductor chip stack 330A and the upper surface of the first semiconductor chip 310 can be positioned vertically at substantially the same height. The first side of the third semiconductor chip stack 330A can be configured to be spaced apart from the first semiconductor chip 310 on a first side (e.g., to the left of the first semiconductor chip 310 in a first direction).

[0065] On the other hand, the second side of the third semiconductor chip stack 330, the third semiconductor chip stack 330B, may be disposed above the second semiconductor chip stack 320. In the first direction, the second side of the third semiconductor chip stack 330B may be positioned closer to the second side of the substrate 300 than the first side of the third semiconductor chip stack 330A. As an example, the second side of the third semiconductor chip stack 330B may be positioned to overlap with the first semiconductor chip 310.

[0066] Each of the first-side third semiconductor chip stack 330A and the second-side third semiconductor chip stack 330B may include one or more third semiconductor chips 330-1 to 330-4 stacked in the vertical direction. The third semiconductor chips 330-1 to 330-4 can be stacked with the active surface where the chip pads 332 are provided facing upwards and the passive surface facing downwards (i.e., in the upward-facing state). Additionally, the chip pads 332 of the first-side third semiconductor chip stack 330A and the second-side third semiconductor chip stack 330B may be provided on the edge region of the second side (e.g., the right edge region of each of the third semiconductor chips 330-1 to 330-4 in the first direction). The third semiconductor chips 330-1 to 330-4 of the first-side third semiconductor chip stack 330A and the second-side third semiconductor chip stack 330B may be stacked such that all chip pads 332 are exposed. For example, in each of the third semiconductor chip stack 330A on the first side and the third semiconductor chip stack 330B on the second side, the third semiconductor chips 330-1 to 330-4 may be stacked with a predetermined offset from the second side (e.g., from the right side where the chip pad 332 is provided) toward the first side located opposite to the second side (e.g., to the left in a first direction). That is, the offset stacking direction of the third semiconductor chips 330-1 to 330-4 in the third semiconductor chip stack 330A on the first side may be the same as the offset stacking direction of the third semiconductor chips 330-1 to 330-4 in the third semiconductor chip stack 330B on the second side. The third semiconductor chip stack 330A on the first side is electrically connected to the substrate 300 via bonding leads 334. The bonding leads 334 connect the exposed chip pads 332 of the third semiconductor chips 330-1 to 330-4 to each other and connect the chip pad 332 of the lowest third semiconductor chip 330-1 to the upper substrate pad 302A on the first side. The third semiconductor chip stack 330B on the second side is electrically connected to the substrate 300 via bonding leads 334. The bonding leads 334 connect the exposed chip pads 332 of the third semiconductor chips 330-1 to 330-4 to each other and connect the chip pad 332 of the lowest third semiconductor chip 330-1 to the upper substrate pad 302B on the second side. Each of the third semiconductor chips 330-1 to 330-4 can be attached to an assembly positioned directly below it via an adhesive layer 336 formed above its passive surface.

[0067] According to the above semiconductor package, since the first-side third semiconductor chip stack 330A is positioned below the second semiconductor chip stack 320, and the chip pads 332 of the first-side third semiconductor chip stack 330A and the bonding leads 334 connected thereto are relatively close to the second side (e.g., the right side), the length of the first-side wiring structure 304A can be reduced. The length of the first-side wiring structure 304A can be the distance from the first-side upper substrate pad 302A connected to the first-side third semiconductor chip stack 330A via the bonding leads 334 to the corresponding power connection electrode 340P.

[0068] As a result, it is easy to supply power to the third semiconductor chip stack 330A on the first side, and power integrity can be improved.

[0069] In addition, since the area occupied by the first side wiring structure 304A in the substrate 300 is reduced, the degree of freedom in designing the circuit / wiring structure in the substrate 300 can be increased.

[0070] In addition, since the distance between the third semiconductor chip stack 330A and the first semiconductor chip 310 on the first side is also reduced, the integrity of the signals exchanged between them through the substrate 300 can be improved.

[0071] Furthermore, since the third semiconductor chip stack 330A on the first side supports the second semiconductor chip stack 320 together with the first semiconductor chip 310, the number of dummy semiconductor chips required can be reduced or may not be required.

[0072] Furthermore, the first semiconductor chip 310, the second semiconductor chip stack 320, and the third semiconductor chip stack 330 can be arranged in various shapes according to their area and / or dimensions in the plan view, and, as needed, one or more dummy semiconductor chips can be used for support. This will be further referred to... Figure 3C Described exemplarily.

[0073] Figure 3C It's viewed from above. Figure 3A Another floor plan. For ease of description, Figure 3C The planar shape and arrangement of the substrate 300, the first semiconductor chip 310, the second semiconductor chip stack 320 including a second semiconductor chip stack 320A on a first side and a second semiconductor chip stack 320B on a second side, the third semiconductor chip stack 330 including a third semiconductor chip stack 330A on a first side and a third semiconductor chip stack 330B on a second side, and the first dummy semiconductor chip 350A and the second dummy semiconductor chip 350B are shown.

[0074] Reference Figure 3Aand Figure 3C The first semiconductor chip 310 may have a width corresponding to W1 in a first direction and a width corresponding to W1' in a second direction. The second semiconductor chip stack 320 may have a width corresponding to W2 in a first direction and a width corresponding to W2' in a second direction. The third semiconductor chip stack 330 may have a width corresponding to W4 in a first direction and a width corresponding to W3' in a second direction.

[0075] In the first direction, the width W4 of the third semiconductor chip stack 330 may be smaller than the width W2 of the second semiconductor chip stack 320, while in the second direction, the width W3' of the third semiconductor chip stack 330 may be larger than the width W2' of the second semiconductor chip stack 320. The first semiconductor chip 310 may be a chip with a planar area smaller than that of the second semiconductor chip stack 320 and the third semiconductor chip stack 330. Therefore, in the first direction, the width W1 of the first semiconductor chip 310 may be smaller than the width W2 of the second semiconductor chip stack 320, and in the second direction, the width W1' of the first semiconductor chip 310 may be larger than the width W3' of the third semiconductor chip stack 330.

[0076] In this embodiment, in the first direction, the second semiconductor chip stack 320 may overlap with the entire upper surface of the first-side third semiconductor chip stack 330A and the entire upper surface of the first semiconductor chip 310. Therefore, the second semiconductor chip stack 320 can be sufficiently supported in the first direction by the first-side third semiconductor chip stack 330A and the first semiconductor chip 310. Furthermore, since the first-side third semiconductor chip stack 330A has a relatively large width W3' in the second direction, the second semiconductor chip stack 320 (specifically, the first-side second semiconductor chip stack 320A and the second-side second semiconductor chip stack 320B arranged in the second direction) can be supported by the first-side third semiconductor chip stack 330A. However, since the first semiconductor chip 310 has a relatively small width W1' in the second direction, it may be difficult to support the second semiconductor chip stack 320 (specifically, the first-side second semiconductor chip stack 320A and the second-side second semiconductor chip stack 320B arranged in the second direction). To address this difficulty, dummy semiconductor chips 350A and 350B can be disposed in the blank space between the substrate 300 and the second semiconductor chip stack 320, and can be positioned adjacent to the third semiconductor chip stack 330A and the first semiconductor chip 310 on the first side. In this embodiment, the first dummy semiconductor chip 350A and the second dummy semiconductor chip 350B are shown disposed on both sides of the first semiconductor chip 310 in the second direction, respectively. However, this disclosure is not limited to this, and the planar dimensions, positions, and numbers of the dummy semiconductor chips can be modified differently.

[0077] although Figure 3A As not shown in the cross-sectional view, dummy semiconductor chips 350A and 350B may be disposed between the substrate 300 and the second semiconductor chip stack 320, and may have a thickness substantially the same as the thickness of the third semiconductor chip stack 330A on the first side or the total thickness of the first semiconductor chip 310 and the connecting electrode 312. When the dummy semiconductor chips 350A and 350B are attached to the substrate 300 by an adhesive layer (not shown), the sum of the thickness of each of the dummy semiconductor chips 350A and 350B and the thickness of the adhesive layer may be the same as the thickness of the third semiconductor chip stack 330A on the first side or the total thickness of the first semiconductor chip 310 and the connecting electrode 312.

[0078] Figure 4A This is a cross-sectional view showing a semiconductor package according to another embodiment of the present disclosure. Figure 4B Therefore, with Figure 3C A similar approach viewed from above. Figure 4A The floor plan. The main description will be... Figures 3A to 3C The differences between the above-described implementation methods.

[0079] Reference Figure 4A and Figure 4B The semiconductor package of this embodiment may include a substrate 400, a first semiconductor chip 410, a second semiconductor chip stack 420, a third semiconductor chip stack 430 including a third semiconductor chip stack 430A on a first side and a third semiconductor chip stack 430B on a second side, and an external connection electrode 440 including a power connection electrode 440P.

[0080] The substrate 400 may include a first-side upper substrate pad 402A for supplying power to a first-side third semiconductor chip stack 430A and a second-side upper substrate pad 402B for supplying power to a second-side third semiconductor chip stack 430B. Additionally, the substrate 400 may include a first-side wiring structure 404A connecting from the first-side upper substrate pad 402A to a first corresponding power connection electrode in the power connection electrode 440P, and a second-side wiring structure 404B connecting from the second-side upper substrate pad 402B to a second corresponding power connection electrode in the power connection electrode 440P.

[0081] The first semiconductor chip 410 may be disposed above the upper surface of the substrate 400 and may be connected to the substrate 400 via a connection electrode 412 formed on the lower surface of the first semiconductor chip 410. The first semiconductor chip 410 may be configured to be relatively biased toward a second side (e.g., to the right in the first direction).

[0082] A second semiconductor chip stack 420 may be disposed above a first semiconductor chip 410 and a first-side third semiconductor chip stack 430A. The second semiconductor chip stack 420 may include one or more second semiconductor chips 420-1 and 420-2 stacked in a vertical direction. Each of the second semiconductor chips 420-1 and 420-2 may be attached to the upper surface of a component positioned directly below it via an adhesive layer 426 formed above its passive surface. The second semiconductor chips 420-1 and 420-2 may be electrically connected to a substrate 400 via bonding leads 424 connected to chip pads 422. The second semiconductor chip stack 420 may include a first-side second semiconductor chip stack 420A and a second-side second semiconductor chip stack 420B, which are arranged to be spaced apart from each other in a second direction.

[0083] The third semiconductor chip stack 430A on the first side can be disposed vertically between the substrate 400 and the second semiconductor chip stack 420. The third semiconductor chip stack 430A on the first side can be configured to be spaced apart from the first semiconductor chip 410 on the first side (e.g., to the left of the first semiconductor chip 410 in the first direction).

[0084] On the other hand, the second side of the third semiconductor chip stack 430, the third semiconductor chip stack 430B, may be disposed above the second semiconductor chip stack 420. In the first direction, the second side of the third semiconductor chip stack 430B may be positioned closer to the second side of the substrate 400 than the first side of the third semiconductor chip stack 430A. As an example, the second side of the third semiconductor chip stack 430B may be positioned to overlap with the first semiconductor chip 410.

[0085] Each of the first-side third semiconductor chip stack 430A and the second-side third semiconductor chip stack 430B may include one or more third semiconductor chips 430-1 to 430-4 stacked in a vertical direction. The third semiconductor chips 430-1 to 430-4 may be stacked with the active surface where the chip pads 432 are provided facing upwards and the passive surface facing downwards (i.e., in an upward-facing state). Additionally, the chip pads 432 of the first-side third semiconductor chip stack 430A and the second-side third semiconductor chip stack 430B may be provided on the edge region of the second side (e.g., the right edge region of each of the third semiconductor chips 430-1 to 430-4 in the first direction). The third semiconductor chips 430-1 to 430-4 of the first-side third semiconductor chip stack 430A and the second-side third semiconductor chip stack 430B may be offset in a direction from the second side toward the first side, such that all chip pads 432 are exposed. The first-side third semiconductor chip stack 430A and the second-side third semiconductor chip stack 430B can be electrically connected to the first-side upper substrate pad 402A and the second-side upper substrate pad 402B of the substrate 400, respectively, via bonding leads 434. Each of the third semiconductor chips 430-1 to 430-4 can be attached to an assembly directly positioned below via an adhesive layer 436 formed above its passive surface.

[0086] In this embodiment, the width W2 of the second semiconductor chip stack 420 in the first direction can be reduced compared to the embodiment described above. Therefore, in the first direction, the second semiconductor chip stack 420 can partially overlap with the upper surface of the first semiconductor chip 410, and simultaneously overlap with the entire upper surface of the third semiconductor chip stack 430A on the first side.

[0087] In this case, if the third semiconductor chip stack 430B on the second side exists in the same position as in the above embodiment, it may be difficult for the second semiconductor chip stack 420 to support the third semiconductor chip stack 430B on the second side in the first direction. Therefore, first to third dummy semiconductor chips 450A, 450B, and 450C may be provided to adequately support the third semiconductor chip stack 430B on the second side.

[0088] The second dummy semiconductor chip 450B, among the first to third dummy semiconductor chips 450A, 450B, and 450C, can be vertically disposed between the first semiconductor chip 410 and the second side third semiconductor chip stack 430B. That is, the second dummy semiconductor chip 450B can be vertically positioned at the same height as the second semiconductor chip stack 420. When the second dummy semiconductor chip 450B is attached to the upper surface of the first semiconductor chip 410 by an adhesive layer 456 formed on its lower surface, the sum of the thickness of the second dummy semiconductor chip 450B and the thickness of the adhesive layer 456 can be substantially the same as the thickness of the second semiconductor chip stack 420. If the adhesive layer 456 is omitted, the thickness of the second dummy semiconductor chip 450B can be substantially the same as the thickness of the second semiconductor chip stack 420.

[0089] The first dummy semiconductor chip 450A and the third dummy semiconductor chip 450C can be disposed between the substrate 400 and the second-side third semiconductor chip stack 430B. As described above, since the width W1' of the first semiconductor chip 410 in the second direction is relatively small, the first semiconductor chip 410 and the second dummy semiconductor chip 450B may not be sufficient to support the second-side third semiconductor chip stack 430B in the second direction. Therefore, the first dummy semiconductor chip 450A and the third dummy semiconductor chip 450C can be further disposed in the blank space below the second-side third semiconductor chip stack 430B. In this embodiment, the case where the first dummy semiconductor chip 450A and the third dummy semiconductor chip 450C are respectively disposed on both sides of the second dummy semiconductor chip 450B in the second direction is described, but this disclosure is not limited thereto. The size, position, and number of dummy semiconductor chips corresponding to the thickness of each of the first dummy semiconductor chip 450A and the third dummy semiconductor chip 450C can be modified differently.

[0090] The thickness of each of the first dummy semiconductor chip 450A and the third dummy semiconductor chip 450C is substantially the same as the sum of the thickness of the third semiconductor chip stack 430A on the first side and the thickness of the second semiconductor chip stack 420. When each of the first dummy semiconductor chip 450A and the third dummy semiconductor chip 450C is attached to the upper surface of the substrate 400 by an adhesive layer (not shown), the thickness of the adhesive layer and the sum of the thicknesses of each of the first dummy semiconductor chip 450A and the third dummy semiconductor chip 450C are substantially the same as the sum of the thicknesses of the third semiconductor chip stack 430A on the first side and the thickness of the second semiconductor chip stack 420.

[0091] Figure 5A This is a cross-sectional view showing a semiconductor package according to another embodiment of the present disclosure. Figure 5B Therefore, with Figure 3C and Figure 4B A similar approach viewed from above. Figure 5A The floor plan. The main description will be... Figures 3A to 3C as well as Figure 4A and Figure 4B The differences between the above-described implementation methods.

[0092] Reference Figure 5A and Figure 5B The semiconductor package of this embodiment may include a substrate 500, a first semiconductor chip 510, a second semiconductor chip stack 520, a third semiconductor chip stack 530 including a third semiconductor chip stack 530A on a first side and a third semiconductor chip stack 530B on a second side, and an external connection electrode 540 including a power connection electrode 540P.

[0093] The substrate 500 may include a first-side upper substrate pad 502A for supplying power to a first-side third semiconductor chip stack 530A and a second-side upper substrate pad 502B for supplying power to a second-side third semiconductor chip stack 530B. Additionally, the substrate 500 may include a first-side wiring structure 504A connecting from the first-side upper substrate pad 502A to a first corresponding power connection electrode in the power connection electrode 540P, and a second-side wiring structure 504B connecting from the second-side upper substrate pad 502B to a second corresponding power connection electrode in the power connection electrode 540P.

[0094] The first semiconductor chip 510 may be disposed above the upper surface of the substrate 500 and may be connected to the substrate 500 via a connection electrode 512 formed on the lower surface of the first semiconductor chip 510. The first semiconductor chip 510 may be configured to be relatively biased toward a second side (e.g., to the right in the first direction).

[0095] A second semiconductor chip stack 520 may be disposed above a third semiconductor chip stack 530A on a first side. The second semiconductor chip stack 520 may include one or more second semiconductor chips 520-1 and 520-2 stacked in a vertical direction. Each of the second semiconductor chips 520-1 and 520-2 may be attached to an assembly positioned directly below it via an adhesive layer 526 formed above its passive surface. The second semiconductor chips 520-1 and 520-2 may be electrically connected to a substrate 500 via bonding leads 524 connected to chip pads 522. The second semiconductor chip stack 520 may include a first-side second semiconductor chip stack 520A and a second-side second semiconductor chip stack 520B, which are arranged to be spaced apart from each other in a second direction.

[0096] The third semiconductor chip stack 530A on the first side can be disposed vertically between the substrate 500 and the second semiconductor chip stack 520. The third semiconductor chip stack 530A on the first side can be configured to be spaced apart from the first semiconductor chip 510 on the first side (e.g., to the left of the first semiconductor chip 510 in the first direction).

[0097] The third semiconductor chip stack 530B on the second side of the third semiconductor chip stack 530 can be disposed above the first semiconductor chip 510. The third semiconductor chip stack 530B on the second side can directly contact the first semiconductor chip 510. That is, unlike the above embodiment, the second semiconductor chip stack 520 may not be inserted between the third semiconductor chip stack 530B on the second side and the first semiconductor chip 510.

[0098] Each of the first-side third semiconductor chip stack 530A and the second-side third semiconductor chip stack 530B may include one or more third semiconductor chips 530-1 to 530-4 stacked in a vertical direction. The third semiconductor chips 530-1 to 530-4 may be stacked with the active surface where the chip pads 532 are provided facing upwards and the passive surface facing downwards (i.e., in an upward-facing state). Additionally, the chip pads 532 of the first-side third semiconductor chip stack 530A and the second-side third semiconductor chip stack 530B may be provided on the edge region of the second side (e.g., the right edge region of each of the third semiconductor chips 530-1 to 530-4 in the first direction). The third semiconductor chips 530-1 to 530-4 of the first-side third semiconductor chip stack 530A and the second-side third semiconductor chip stack 530B may be offset in a direction from the second side toward the first side, such that all chip pads 532 are exposed. The first-side third semiconductor chip stack 530A and the second-side third semiconductor chip stack 530B can be electrically connected to the first-side upper substrate pad 502A and the second-side upper substrate pad 502B of the substrate 500, respectively, via bonding leads 534. Each of the third semiconductor chips 530-1 to 530-4 can be attached to the component directly positioned below via an adhesive layer 536 formed above its passive surface.

[0099] In this embodiment, the width W2 of the second semiconductor chip stack 520 in the first direction can be further reduced compared to the above embodiment. Therefore, in the first direction, the second semiconductor chip stack 520 may not overlap with the upper surface of the first semiconductor chip 510, and may overlap with the entire upper surface of the third semiconductor chip stack 530A on the first side while being spaced apart from the first semiconductor chip 510.

[0100] In this configuration, since the third semiconductor chip stack 530B on the second side does not overlap with the second semiconductor chip stack 520, it can be formed above the first semiconductor chip 510 to directly contact the first semiconductor chip 510. However, since the width W3' of the third semiconductor chip stack 530B on the second side in the second direction is greater than the width W1' of the first semiconductor chip 510, the first dummy semiconductor chip 550A and the second dummy semiconductor chip 550B can be configured to adequately support the third semiconductor chip stack 530B on the second side.

[0101] The first dummy semiconductor chip 550A and the second dummy semiconductor chip 550B can be disposed between the substrate 500 and the third semiconductor chip stack 530B on the second side. Although Figure 5AAs not shown in the cross-sectional view, when each of the first dummy semiconductor chip 550A and the second dummy semiconductor chip 550B is attached to the upper surface of the substrate 500 by an adhesive layer (not shown) formed on its lower surface, the thickness of the adhesive layer and the sum of the thicknesses of each of the first dummy semiconductor chip 550A and the second dummy semiconductor chip 550B are substantially the same as the sum of the thickness of the first semiconductor chip 510 and the thickness of the connecting electrode 512. If the adhesive layer is omitted, the thickness of each of the first dummy semiconductor chip 550A and the second dummy semiconductor chip 550B is substantially the same as the sum of the thickness of the first semiconductor chip 510 and the thickness of the connecting electrode 512.

[0102] Figure 6 This is a cross-sectional view showing a semiconductor package according to another embodiment of the present disclosure. Due to the above... Figure 3C Basically the same, so omitted Figure 6 The floor plan. The main description will be... Figures 3A to 3C The differences between the above-described implementation methods.

[0103] Reference Figure 6 The semiconductor package of this embodiment may include a substrate 600, a first semiconductor chip 610, a second semiconductor chip stack 620, a third semiconductor chip stack 630 including a third semiconductor chip stack 630A on a first side and a third semiconductor chip stack 630B on a second side, and an external connection electrode 640 including a power connection electrode 640P.

[0104] The substrate 600 may include a first-side upper substrate pad 602A for supplying power to a first-side third semiconductor chip stack 630A and a second-side upper substrate pad 602B for supplying power to a second-side third semiconductor chip stack 630B. Additionally, the substrate 600 may include a first-side wiring structure 604A connecting from the first-side upper substrate pad 602A to a first corresponding power connection electrode in the power connection electrode 640P, and a second-side wiring structure 604B connecting from the second-side upper substrate pad 602B to a second corresponding power connection electrode in the power connection electrode 640P.

[0105] The first semiconductor chip 610 may be disposed above the upper surface of the substrate 600 and may be connected to the substrate 600 via a connection electrode 612 formed on the lower surface of the first semiconductor chip 610. The first semiconductor chip 610 may be configured to be relatively biased toward a second side (e.g., to the right in the first direction).

[0106] A second semiconductor chip stack 620 may be disposed above the first semiconductor chip 610 and a third semiconductor chip stack 630A on the first side. The second semiconductor chip stack 620 may include one or more second semiconductor chips 620-1 and 620-2 stacked in a vertical direction. Each of the second semiconductor chips 620-1 and 620-2 may be attached to an assembly positioned directly below it via an adhesive layer 626 formed above its passive surface. The second semiconductor chips 620-1 and 620-2 may be electrically connected to the substrate 600 via bonding leads 624 connected to chip pads 622.

[0107] The first side of the third semiconductor chip stack 630A can be disposed vertically between the substrate 600 and the second semiconductor chip stack 620. The first side of the third semiconductor chip stack 630A can be positioned on a first side (e.g., to the left of the first semiconductor chip 610 in a first direction) and spaced apart from the first semiconductor chip 610. In this case, the thickness of the first side of the third semiconductor chip stack 630A can be less than the total thickness of the first semiconductor chip 610 and the connecting electrode 612. Therefore, in the vertical direction, the upper surface of the first side of the third semiconductor chip stack 630A can be located below the upper surface of the first semiconductor chip 610. In this case, since it is difficult to form the second semiconductor chip stack 620, a dummy semiconductor chip 650 can be disposed between the first side of the third semiconductor chip stack 630A and the second semiconductor chip stack 620. The dummy semiconductor chip 650 can be attached to the upper surface of the first side of the third semiconductor chip stack 630A via an adhesive layer 656.

[0108] The third semiconductor chip stack 630B on the second side of the third semiconductor chip stack 630 can be disposed above the second semiconductor chip stack 620.

[0109] Each of the first-side third semiconductor chip stack 630A and the second-side third semiconductor chip stack 630B may include one or more third semiconductor chips 630-1 and 630-2 stacked in the vertical direction. In this embodiment, since each of the first-side third semiconductor chip stack 630A and the second-side third semiconductor chip stack 630B includes two third semiconductor chips 630-1 and 630-2, its thickness may be less than that of the above embodiment. The third semiconductor chips 630-1 and 630-2 may be stacked with the active surface where the chip pads 632 are provided facing upwards and the passive surface facing downwards (i.e., in the upward-facing state). In addition, the chip pads 632 of the first-side third semiconductor chip stack 630A and the second-side third semiconductor chip stack 630B may be provided on the edge region of the second side (e.g., the right edge region of each of the third semiconductor chips 630-1 and 630-2 in the first direction). The third semiconductor chips 630-1 and 630-2 of the first-side third semiconductor chip stack 630A and the second-side third semiconductor chip stack 630B can be offset in a direction from the second side toward the first side, so that all chip pads 632 are exposed. The first-side third semiconductor chip stack 630A and the second-side third semiconductor chip stack 630B can be electrically connected to the first-side upper substrate pad 602A and the second-side upper substrate pad 602B of the substrate 600, respectively, via bonding leads 634. Each of the third semiconductor chips 630-1 and 630-2 can be attached to an assembly positioned directly below it via an adhesive layer 636 formed above its passive surface.

[0110] According to the above embodiments of this disclosure, a semiconductor package can be provided that minimizes the area and thickness of the semiconductor package while integrating different types of memory and controller into one package and ensuring excellent operating characteristics.

[0111] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the teachings as defined in the following claims.

[0112] Cross-reference to related applications

[0113] This application claims priority to Korean Patent Application No. 10-2021-0149671, filed on November 3, 2021, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor package comprising: A substrate having a first side and a second side, the first side and the second side being opposite sides of the substrate in a first direction; A first semiconductor chip is disposed above the substrate; A first-side third semiconductor chip stack is disposed above the substrate and spaced apart from the first semiconductor chip, and the first-side third semiconductor chip stack is closer to the first side than the first semiconductor chip. A second semiconductor chip stack is disposed above the first semiconductor chip and the first side third semiconductor chip stack, and the second semiconductor chip stack includes one or more second semiconductor chips. as well as A second-side third semiconductor chip stack is disposed above the second semiconductor chip stack. Each of the first-side third semiconductor chip stack and the second-side third semiconductor chip stack includes a plurality of offset-stacked third semiconductor chips, which are offset toward the first side as they move further away from the substrate, thereby exposing chip pads disposed on the other edge region of the plurality of third semiconductor chips. Each of the third semiconductor chip stack on the first side and the third semiconductor chip stack on the second side is electrically connected to the substrate via bonding leads, which extend to the substrate while connecting the chip pads of the plurality of third semiconductor chips to each other. The semiconductor package further includes: Multiple power connection electrodes are disposed beneath the substrate and are used to supply power to the third semiconductor chip stack on the first side and the third semiconductor chip stack on the second side. The plurality of power connection electrodes are located closer to the second side of the substrate than to the first side of the substrate.

2. The semiconductor package according to claim 1, wherein, The substrate further includes: A first-side wiring structure, wherein the bonding lead connected to the third semiconductor chip stack on the first side is connected to a first corresponding power connection electrode among the plurality of power connection electrodes; and The second side wiring structure connects the bonding leads connected to the second side third semiconductor chip stack to the second corresponding power connection electrode among the plurality of power connection electrodes.

3. The semiconductor package according to claim 1, wherein, The second semiconductor chip stack includes volatile memory. Each of the first-side third semiconductor chip stack and the second-side third semiconductor chip stack includes non-volatile memory, and The first semiconductor chip includes a memory controller.

4. The semiconductor package according to claim 1, further comprising: A dummy semiconductor chip is disposed in the space between the substrate and the second semiconductor chip stack and is configured to be adjacent to the third semiconductor chip stack on the first side and the first semiconductor chip.

5. The semiconductor package according to claim 1, wherein, The second semiconductor chip stack partially overlaps with the first semiconductor chip and the third semiconductor chip stack on the second side in the vertical direction to provide a first space between the first semiconductor chip and the third semiconductor chip stack on the second side. The semiconductor package further includes a first dummy semiconductor chip disposed in the first space.

6. The semiconductor package according to claim 5, further comprising: The second dummy semiconductor chip is disposed in the second space between the substrate and the third semiconductor chip stack on the second side in the vertical direction and is adjacent to the first semiconductor chip and the second semiconductor chip stack.

7. The semiconductor package according to claim 6, wherein, The thickness of the second dummy semiconductor chip is greater than the thickness of the first dummy semiconductor chip.

8. The semiconductor package according to claim 1, wherein, In the vertical direction, the upper surface of the first semiconductor chip and the upper surface of the third semiconductor chip stack on the first side are positioned at the same height.

9. The semiconductor package according to claim 1, wherein, In the vertical direction, the upper surface of the third semiconductor chip stack on the first side is positioned below the upper surface of the first semiconductor chip.

10. The semiconductor package of claim 9, further comprising: A dummy semiconductor chip is disposed above the third semiconductor chip stack on the first side. The upper surface of the dummy semiconductor chip and the upper surface of the first semiconductor chip are positioned at the same height in the vertical direction.

11. The semiconductor package according to claim 1, wherein, In the first direction, the width of the second semiconductor chip stack is greater than the width of the first semiconductor chip and the width of the third semiconductor chip stack on the first side.

12. The semiconductor package of claim 11, wherein, In a second direction perpendicular to the first direction, the width of the second semiconductor chip stack is greater than the width of the first semiconductor chip and less than the width of each of the third semiconductor chip stack on the first side and the third semiconductor chip stack on the second side. At least two second semiconductor chip stacks are arranged in the second direction.

13. A semiconductor package comprising: A substrate having a first side and a second side, the first side and the second side being opposite sides of the substrate in a first direction; A first semiconductor chip is disposed above the substrate; A first-side third semiconductor chip stack is disposed above the substrate and spaced apart from the first semiconductor chip, and the first-side third semiconductor chip stack is closer to the first side than the first semiconductor chip. A second semiconductor chip stack is disposed above a third semiconductor chip stack on the first side, and the second semiconductor chip stack includes one or more second semiconductor chips. as well as A second-side third semiconductor chip stack is disposed above the first semiconductor chip. Each of the first-side third semiconductor chip stack and the second-side third semiconductor chip stack includes a plurality of offset-stacked third semiconductor chips, which are offset toward the first side as they move further away from the substrate, thereby exposing chip pads disposed on the other edge region of the plurality of third semiconductor chips. Each of the third semiconductor chip stack on the first side and the third semiconductor chip stack on the second side is electrically connected to the substrate via bonding leads, which extend to the substrate while connecting the chip pads of the plurality of third semiconductor chips to each other. The semiconductor package further includes: Multiple power connection electrodes are disposed beneath the substrate and are used to supply power to the third semiconductor chip stack on the first side and the third semiconductor chip stack on the second side. The plurality of power connection electrodes are located closer to the second side of the substrate than to the first side of the substrate.

14. The semiconductor package of claim 13, wherein, The substrate further includes: A first-side wiring structure, wherein the bonding lead connected to the third semiconductor chip stack on the first side is connected to a first corresponding power connection electrode among the plurality of power connection electrodes; and The second side wiring structure connects the bonding leads connected to the second side third semiconductor chip stack to the second corresponding power connection electrode among the plurality of power connection electrodes.

15. The semiconductor package according to claim 13, wherein, The second semiconductor chip stack includes volatile memory. Each of the first-side third semiconductor chip stack and the second-side third semiconductor chip stack includes non-volatile memory, and The first semiconductor chip includes a memory controller.

16. The semiconductor package of claim 13, wherein, The third semiconductor chip stack on the second side is spaced apart from the second semiconductor chip stack in the first direction.

17. The semiconductor package of claim 13, wherein, The third semiconductor chip stack on the second side is in direct contact with the upper surface of the first semiconductor chip.

18. The semiconductor package of claim 13, further comprising: A dummy semiconductor chip is disposed vertically in the space between the substrate and the third semiconductor chip stack on the second side and is adjacent to the first semiconductor chip.

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