A flat configuration light emitting transistor of a surface light source and a preparation method and application thereof

Abstract

The application discloses a plane light source emission plane light-emitting transistor device and a preparation method and application thereof. By inserting a charge buffer layer between a semiconductor charge transport layer and a light-emitting unit, the prepared plane light-emitting transistor can realize stable plane light source emission, and effectively overcomes the defect that the emission light of a traditional plane light-emitting transistor is linear or strip-shaped. The plane light source emission plane light-emitting transistor device has high integration, can realize stable plane light source emission, effectively improves the aperture ratio of the transistor device, has good gate tunable capacity, high loop stability and arbitrary tunability, is easy to miniaturize, can be mass-produced, has good compatibility with flexible wearable devices, and plays an important promoting role in application of the light-emitting transistor device to a light-emitting display field.

Description

[0001] This application claims priority to the earlier application filed by the applicant on November 2, 2021, with patent application number 202111288584.3, entitled "A planar light-emitting field-effect transistor emitting a surface light source, its fabrication method and application thereof". The entire contents of the earlier application are incorporated herein by reference. Technical Field

[0002] This invention belongs to the field of electroluminescent devices, specifically relating to a planar light-emitting transistor emitting from a surface light source, its fabrication method, and its application. Background Technology

[0003] The display industry has become a pillar industry of the information technology industry. As a highly integrated electroluminescent device, the light-emitting transistor combines the current amplification function of the organic transistor and the electroluminescence function of the organic light-emitting diode in a single device. It has unique advantages such as high integration and simple manufacturing process, and is considered to be an important component of the next generation of revolutionary display technology that realizes miniaturization, flexibility and high resolution.

[0004] The classic configurations of light-emitting transistors (LEDs) are currently divided into planar and vertical configurations. Vertical LEDs have short channels, making it easier to achieve low-voltage driving and surface light emission. However, their working mechanism requires the use of porous source electrodes that are difficult to fabricate, affecting the stability and uniformity of the device. Planar LEDs have better compatibility with existing industries and the devices are relatively stable. However, because electrons and holes generally recombine on one side of the channel and electrode, the light emission is a line light source, which is not suitable for display applications.

[0005] How to achieve both good device manufacturability and stability, as well as stable surface light source emission, through reasonable device structure design has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] The present invention provides a planar light-emitting transistor with a surface light source configuration, including a source electrode, a drain electrode, and a charge buffer layer disposed under the source electrode or the drain electrode.

[0007] According to an embodiment of the present invention, the planar light-emitting transistor of the surface light source further includes a semiconductor charge transport layer.

[0008] Preferably, the semiconductor charge transport layer is disposed below the source electrode. In one embodiment of the present invention, the charge buffer layer is disposed above the semiconductor charge transport layer.

[0009] According to an embodiment of the present invention, the transistor further includes a light-emitting unit, preferably the light-emitting unit is disposed below the drain electrode.

[0010] In one embodiment of the present invention, the charge buffer layer is disposed below the light-emitting unit. In another embodiment of the present invention, the charge buffer layer is disposed below the source electrode and the light-emitting unit.

[0011] According to an embodiment of the present invention, the charge buffer layer may be disposed between the drain electrode (or source electrode) and the semiconductor charge transport layer, or between the semiconductor charge transport layer and the light-emitting unit.

[0012] According to an embodiment of the present invention, the light-emitting surface (including the light-emitting unit) of the transistor is U-shaped, and the source electrode is disposed on the opening side of the U-shape.

[0013] According to one embodiment of the present invention, the drain electrode, the light-emitting unit and the charge buffer layer are U-shaped, and the source electrode is disposed on the opening side of the U-shape.

[0014] According to another embodiment of the present invention, the drain electrode and the light-emitting unit are U-shaped, the source electrode is disposed on the opening side of the U-shape, and preferably the charge buffer layer is disposed below the source electrode.

[0015] Preferably, the planar light-emitting transistor of the surface light source includes:

[0016] Support substrate;

[0017] A gate electrode is disposed on the surface of the supporting substrate;

[0018] A dielectric layer disposed above the gate electrode;

[0019] A semiconductor charge transport layer disposed on the dielectric layer;

[0020] The source electrode and the charge buffer layer are disposed on the semiconductor charge transport layer, preferably the source electrode and the charge buffer layer are disposed on different sides of the charge transport layer.

[0021] The light-emitting unit and the drain electrode are sequentially arranged on the charge buffer layer.

[0022] Preferably, the planar light-emitting transistor of the surface light source includes:

[0023] Support substrate;

[0024] A gate electrode is disposed on the surface of the supporting substrate;

[0025] A dielectric layer disposed above the gate electrode;

[0026] A semiconductor charge transport layer disposed on the dielectric layer;

[0027] A charge buffer layer disposed on the semiconductor charge transport layer;

[0028] A source electrode and a light-emitting unit are sequentially disposed on a charge buffer layer, preferably on different sides of the charge buffer layer;

[0029] The drain electrode is positioned above the light-emitting unit.

[0030] It should be noted that when a component such as a layer, film, crystal, region, or substrate is referred to as being "above" / "below" or "between" another component, it can be placed directly above / below another component, or one or more layers may be present in between.

[0031] According to an embodiment of the present invention, the source electrode and drain electrode are non-planar, i.e., there is a height difference between them. For example, both the source electrode and the charge buffer layer are located on the semiconductor charge transport layer, and there may be no gap between them, their thicknesses may be the same or different, the charge buffer layer may cover the source electrode, or they may be independent of each other. The drain electrode is disposed on the charge buffer layer (the drain electrode may completely or partially cover the charge buffer layer), and a conductive channel is formed between the drain electrode and the source electrode. Optionally, a light-emitting unit is disposed between the drain electrode and the charge buffer layer, and the light-emitting unit may completely or partially cover the charge buffer layer and / or the source electrode. For example, both the source electrode and the light-emitting power source are disposed on the charge buffer layer, the drain electrode is disposed on the light-emitting unit, and a conductive channel is formed between the drain electrode and the source electrode. The thicknesses of the source electrode and the light-emitting unit may be the same or different, there may be no gap between the light-emitting unit and the source electrode, the light-emitting unit may cover the source electrode, or they may be independent of each other. The light-emitting portion is the entire effective area of ​​the source electrode or the drain electrode, and the gate voltage can adjust the light emission brightness.

[0032] According to an embodiment of the present invention, the charge buffer layer and the source electrode can be disposed on different sides of the semiconductor charge transport layer. The inventors have for the first time proposed the introduction and location of the charge buffer layer; the thickness and area of ​​the charge buffer layer and other layers can be adjusted by those skilled in the art according to actual needs.

[0033] According to an embodiment of the present invention, the material in the semiconductor charge transport layer has good electrical properties, and preferably the mobility of the semiconductor charge transport layer is not less than 0.1 cm. 2 V -1 s -1 For example, the semiconductor charge transport layer comprises organic semiconductor materials and / or inorganic semiconductor materials, such as organic semiconductor materials selected from small molecule materials and / or polymer materials.

[0034] Preferably, the organic semiconductor material is selected from one or more of the following substances, including but not limited to: 2,7-dioctyl[1]benzothiophene[3,2-b]benzothiophene (C8-BTBT), 2,6-diphenylanthracene (DPA), 2,6-dinaphthylanthracene (dNaAnt), 2,6-bis(p-hexylbenzene)anthracene (C6-DPA), 2,6-bis(p-octylhexylbenzene)anthracene (C8-DPA), 2,6-bis(p-decylbenzene)anthracene (C8-B2 ... 10 -DPA), poly(3-hexylthiophene) (P3HT), 9,9-di-n-octylfluorene-benzothiadiazole copolymer (F8BT), poly[2,5-(2-octyldodecyl)-3,6-dionepyrrolopyrrole-alt-5,5-(2,5-di(thiophene-2-yl)thiopheno[3,2-b]thiophene)] (DPP-DTT), and preferably C8-BTBT.

[0035] Preferably, the inorganic semiconductor material is selected from one or more of the following substances, including but not limited to: carbon nanotubes (CNTs), zinc tin oxide (ZTO), gallium nitride (GaN), silicon carbide (SiC), and zinc selenide (ZnSe).

[0036] According to an embodiment of the present invention, the material in the charge buffer layer has suitable electrical properties, such as one or more selected from low-mobility organic materials, metallic materials, PNP junctions, etc.; preferably, the low mobility refers to a mobility 2-5 orders of magnitude smaller than that of the semiconductor charge transport layer. For example, the charge buffer layer is a layer formed from one or more low-mobility organic materials 4,4'-cyclohexylbis[N,N-di(4-methylphenyl)aniline] (TAPC), N,N'-diphenyl-N,N'-(1-naphthyl)-1,1'-biphenyl-4,4'-diamine (NPB), and polyvinylcarbazole (PVK), and is more preferably a layer formed from TAPC. For example, the work function of the metallic material matches the highest occupied molecular orbital (HOMO) energy level of the light-emitting unit, and the work function of the metallic material can be defined as 4.5 eV-6 eV; preferably, the charge buffer layer is a layer formed from one or more of the metallic material such as Au, Ni, Pt, etc., for example, an ultrathin layer with a thickness of 0.5-10 nm, such as 1 nm, 2 nm, or 3 nm. Also, the charge buffer layer is a layer formed from one or more of C60-pentaphenyl-C60, C70-tetraphenyl-C70, C60-tetraphenyl-C70, etc., in a pnp junction.

[0037] According to an embodiment of the present invention, when the material in the charge buffer layer is a low-mobility organic material or a pnp junction, the thickness of the charge buffer layer is 20-80 nm, for example 30 nm, 40 nm, or 50 nm.

[0038] According to an embodiment of the present invention, the light-emitting unit includes a light-emitting layer and an electron transport layer, a hole transport layer, an electron injection layer, and / or a hole injection layer that match the energy level of the light-emitting layer.

[0039] Furthermore, the light-emitting layer can be a layer formed of a light-emitting material with a light-emitting mechanism known in the art, for example, the light-emitting material is selected from one or more of fluorescent materials, phosphorescent materials and thermally active delayed fluorescence materials, including but not limited to fluorescent materials, phosphorescent materials and thermally active delayed fluorescence materials.

[0040] Preferably, the fluorescent material is selected from one or more of aluminum octahydroxyquinoline (Alq3), 5,6,11,12-tetraphenylbenzotetraphenyl (red fluorene), and 4,4'-bis[4-(diphenylamino)styryl]biphenyl (BDAVBi).

[0041] Preferably, the phosphorescent material is selected from one or more of tris(2-phenylpyridine)iridium (Ir(ppy)3), bis(2-phenylpyridine-C2,N)iridium acetylacetonate (Ir(ppy)2(acac)) and iridium(III)tris[N,N'-diphenylbenzimidazole-2-ylidene-C2,C2'] (Ir(dpbic)3).

[0042] Preferably, the thermally active delayed fluorescence material is selected from one or two of 9,9'-(5-(4,6-diphenyl-1,3,5-triazin-2-yl)-1,3-phenylene)bis(9Hcarbazole) (DCzTRZ) and (N-phenoxazine)phenyl]sulfone (PXZ-DPS).

[0043] Furthermore, the light emitted by the light-emitting unit has a spectrum between 390nm and 780nm.

[0044] For example, the light-emitting layer in the light-emitting unit can be a single light-emitting material or a guest-doped host material. In this invention, the term "doped" refers to a material in any layer having physical properties different from the material occupying the maximum weight percentage of the corresponding layer, added to the material occupying the maximum weight percentage in an amount corresponding to no more than 30% by weight. The matrix material and the dopant material in any layer are distinguishable from each other.

[0045] According to embodiments of the present invention, the single luminescent material is preferably Alq3, DPA, or dNaAnt; the guest dopant in the guest dopant host material can be one or more substances, and the host material can be a single substance or a mixture; the guest dopant is preferably 1,4-bis(10-phenylanthracene-9-yl)benzene (BD1), BDAVBi, perylene, bis(dimethyl-dihydroacrylidinephenylsulfone) (DMAC-DPS), bis[2-(5-cyano-4,6-difluorophenyl)pyridine-C2,N)]pyridinecarboxyiridium (FCNirPic), or iridium(III)bis[(2,3,4-difluorophenyl) [2,4-dimethyl-6-(4-methyl-2-quinolinyl-κN)phenyl-κC](2,2,6,6-tetramethyl-3,5-heptadecyl-κO3)(Ir(mphmq)2tmd), 4,4'-bis[4-(di-p-tolylamino)styryl]biphenyl (DPAVBi), 9,9'-(5-(4,6-diphenyl-1,3,5-triazin-2-yl)-1,3-phenyl)bis(9H-carbazole)(DCzTrz), 5,5-dibromo-4,4-tetracosyl-2,2-bithiophene (fac-Ir(dpb) ic)3), Tris(2-phenylpyridine)iridium(Ir(ppy)3), Tris[2-(p-tolyl)pyridine]iridium(III)(Ir(mppy)3), Di(2-phenylpyridine-C2,N)iridium(III)acetylacetonate(Ir(ppy)2(acac)), Bis(2-(naphthyl-2-yl)pyridine)(acetylacetonate)iridium(III)(Ir(npy)2acac), Tris[2-(3-methyl-2-pyridyl)phenyl]iridium(Ir(3mppy)3), Bis(2-(3,5-dimethylphenyl)quinoline-C2,N')(acetylacetonate)iridium(III)(Ir(dmpq)2ac One or more of the following: ac), bis(2-(2'-benzothiophene)-pyridine-N,C3')iridium(acetylacetone) (Ir(btp)2(acac)), 4-(dicyanomethylene)-2-methyl-6-[2-(2,3,6,7-tetrahydro-1H,5H-benzo[ij]quinazin-9-yl)vinyl]-4H-pyran (DCM2), Rubrene, tris(2-(3,5-dimethylphenyl)quinoline-C2,N')iridium(III) (Ir(dmpq)3), and 2,8-di-tert-butyl-5,11-bis(4-tert-butylphenyl)-6,12-diphenyltetraphenyl (TBRb);The preferred main materials are Alq3, 4,4'-bis(N-carbazole)-1,1'-biphenyl (CBP), 4,4′-bis(2,2-diphenyl-vinyl-1-yl)-4,4′-dimethylphenyl (p-DMDPVBi), 4,4'-bis(2,2-stilbeneyl)-1,1'-biphenyl (DPVBi), 2-tert-butyl-9,10-bis(2-naphthyl)anthracene (TBADN), diphenyl[4-(triphenylsilyl)phenyl]oxyphosphine (TSPO1), 3-(3-(9H-carbazole-9-yl)phenyl)benzofuran[2,3-b]pyridine (PCz-BFP), 2 One or more of the following: 4,6-tris[3-(diphenylphosphino)phenyl]-1,3,5-triazole (PO-T2T), 2,4,6-tris(3-(carbazole-9-yl)phenyl)-1,3,5-triazine (TCPZ), 4,4'-bis(triphenylsilyl)-1,1'-biphenyl (BSB), 2,7-bis[9,9-di(4-methylphenyl)fluorene-2-yl]-9,9-di(4-methylphenyl)fluorene (TDAF), and 3',3”,3”'-(1,3,5-triazine-2,4,6-triyl)tri(([1,1'-biphenyl]-3-nitrile))(CN-T2T.

[0046] Preferably, the light-emitting unit is a green light-emitting unit 10% Ir(ppy)3:CBP / 3TPYMB, a red light-emitting unit 5% Ir(mphmq)2tmd:CBP / Tmpypb, or a blue light-emitting unit 10% BD1:CBP / B3pypb; for example, it is 20nm 10% Ir(ppy)3:CBP / 40nm 3TPYMB, 20nm 5% Ir(mphmq)2tmd:CBP / 40nm Tmpypb, or 20nm 10% BD1:CBP / 40nm B3pypb.

[0047] According to embodiments of the present invention, the semiconductor charge transport layer, charge buffer layer, and light-emitting unit can be obtained using processing methods known in the art that are beneficial to charge transport and visible light emission. These processing methods include, but are not limited to, vacuum thermal evaporation, physical vapor transport, solution shearing, solution epitaxy, spin coating, and inkjet printing. Those skilled in the art will understand that the specific method used can be selected based on the physical properties (e.g., solubility, melting and boiling points) of the semiconductor material actually used.

[0048] For example, the method for preparing the active layer, including the semiconductor charge transport layer, charge buffer layer, and light-emitting unit, can be selected from any of the following methods:

[0049] Method 1: In the vapor deposition chamber, a thin film of the small molecule material is deposited on the dielectric layer and electrode by vacuum evaporation deposition to obtain the active layer;

[0050] Method 2: A solution of the active layer material is spin-coated onto the dielectric layer and electrodes to obtain the active layer;

[0051] Method 3: Preparation and growth of single-crystal thin films of the small molecule material by solution epitaxy: The small molecule material is dissolved in a solvent that is immiscible with water, and the resulting homogeneous solution is slowly added dropwise to the surface of water. The mixed solution spreads on the surface of the water, and the solvent evaporates to obtain the single-crystal thin film. A supporting substrate with a dielectric layer is inserted into the water to transfer the single-crystal thin film to the surface of the dielectric layer to obtain the active layer.

[0052] Method 4: Preparation of single-crystal thin films of the small molecule material by solution shearing: The small molecule material is dissolved in an organic solvent, and the resulting uniformly mixed solution is dropped onto a support substrate with a dielectric layer. The dropped solution is then slowly sheared and stretched to form an active layer.

[0053] Charge is injected from one end of the semiconductor charge transport layer (taking the source electrode as an example), and transported to the other end in an extremely thin conductive channel formed under the applied gate voltage. After passing through the charge buffer layer, a relatively uniform current injection is formed below the other electrode (taking the drain electrode as an example), which recombines with the electrons injected by the drain electrode to form a uniform surface light source emission.

[0054] According to an embodiment of the present invention, the thickness of the semiconductor charge transport layer, the charge buffer layer, and the light-emitting unit are all in the nanometer to submicrometer range. For example, the thickness of each layer can be independently 5-500 nm, such as 10-100 nm.

[0055] According to embodiments of the present invention, the number of light-emitting components (referring to the charge buffer layer and the light-emitting unit) is at least one, for example, two, three or more. When the number of light-emitting components is two, three or more, the charge buffer layer and the light-emitting unit may optionally be the same or different. The light-emitting components are connected to each other through a charge generating layer (CGL).

[0056] According to an embodiment of the present invention, the source electrode, drain electrode, and gate electrode of the planar light-emitting transistor of the surface light source can all be transparent electrodes or opaque electrodes, and are independently selected from any one or more of the following substances, including but not limited to: metals, such as magnesium, calcium, sodium, potassium, titanium, indium, yttrium, lithium, gadolinium, aluminum, silver, tin, nickel, gold, molybdenum, iron, and lead; alloys of the aforementioned metals; multilayer materials, such as LiF / Al, LiO2 / Al, or LiF / Al / Ag; and metal oxides, such as ITO, IZO, and MoO. x etc.; heavily doped silicon. Those skilled in the art will understand that the specific type of metal selected can be adjusted according to the energy band of the semiconductor material.

[0057] According to an embodiment of the present invention, the source electrode, drain electrode, and gate electrode are prepared using methods known in the art. For example, at least one of vacuum thermal evaporation, inkjet printing, and electron beam deposition methods can be selected.

[0058] According to embodiments of the present invention, there is no particular limitation on the type of dielectric layer, which can be an inorganic material dielectric layer and / or an organic material dielectric layer. Exemplarily, the dielectric layer is an inorganic material dielectric layer, such as a dielectric layer formed of inorganic oxides (Al2O3, SiO2); and / or, the dielectric layer is an organic material dielectric layer, such as a dielectric layer formed of polymethyl methacrylate (PMMA).

[0059] According to an embodiment of the present invention, the dielectric layer can be prepared by a method known in the art. For example, at least one of thermal growth, physical vapor deposition, spin coating, etc., can be selected.

[0060] According to embodiments of the present invention, there is no particular limitation on the thickness of the dielectric layer. Exemplarily, the thickness of the dielectric layer is 10-800 nm. Those skilled in the art can adjust the thickness of the dielectric layer according to actual needs.

[0061] According to an embodiment of the present invention, the supporting substrate is a rigid substrate (e.g., silicon dioxide, glass, or quartz) or a flexible substrate (e.g., PC, PMMA, PDMS).

[0062] According to an embodiment of the present invention, the planar light-emitting transistor of the surface light source can adopt a top-emitting or bottom-emitting device structure.

[0063] According to an embodiment of the present invention, the planar light-emitting transistor of the surface light source can emit planar light matching the color of the light-emitting unit under an applied voltage.

[0064] The present invention also provides a method for fabricating a planar light-emitting transistor emitting from the above-mentioned surface light source, comprising the following steps: setting a charge buffer layer under the drain electrode or the source electrode; the drain electrode, the source electrode and the charge buffer layer all have the meanings as described above.

[0065] According to an embodiment of the present invention, the preparation method includes the following steps: providing a charge buffer layer between the drain electrode (or source electrode) and the semiconductor charge transport layer, or providing a charge buffer layer between the semiconductor charge transport layer and the light-emitting unit;

[0066] The drain electrode, source electrode, semiconductor charge transport layer, light-emitting unit, and charge buffer layer all have the meanings described above.

[0067] Preferably, the structure including the semiconductor charge transport layer, the charge buffer layer, and the light-emitting unit is referred to as the active layer, which is prepared by the above scheme.

[0068] The transistor devices of this invention are highly compatible with low-temperature manufacturing processes, such as solution processing (inkjet printing, electrohydraulic inkjet printing, roll-to-roll, etc.).

[0069] The present invention also provides the application of the planar light-emitting transistor emitting the above-mentioned surface light source in wearable devices.

[0070] This invention also provides applications of the planar light-emitting transistor emitting from the aforementioned surface light source in fields such as lighting displays, optical communications, or novel optoelectronic integration. For example, other related application areas include lasers.

[0071] The planar light-emitting transistor emitting the above-mentioned surface light source can be a transistor containing one light-emitting component, or it can be a series transistor containing at least two light-emitting components.

[0072] The beneficial effects of this invention are:

[0073] Traditional planar light-emitting transistors (LEDs) mostly emit light in a linear or stripe pattern, failing to provide a good surface light source. To overcome these shortcomings, this invention proposes an LED with a charge buffer layer. The inventors have discovered that by inserting a charge buffer layer under the source or drain electrode, between the drain (or source) electrode and the semiconductor charge transport layer, or between the charge transport layer and the light-emitting unit, the current density can be redistributed within the transistor. The resulting planar LED can achieve stable surface light emission, providing uniform RGB region emission. Simultaneously, it exhibits good gate tunability (on / off ratio 10). 6It features high loop stability and arbitrary tunability, as well as a high aperture ratio that can be adjusted according to actual needs, for example, from no less than 10% in the prior art to over 94%. Due to the flexible nature of organic semiconductors, they can be integrated with wearable devices, which is more advantageous for expanding the functionality and application scenarios of wearable surface light source devices.

[0074] 1. The planar light-emitting transistor device for surface light source emission described in this invention can achieve surface light source emission unaffected by gate voltage, which is helpful for the application of the device in the display field.

[0075] 2. The planar light-emitting transistor device with surface light source described in this invention can realize the construction of high aperture ratio electroluminescent devices, can achieve good compatibility with flexible wearable devices, and plays an important role in promoting the development of light-emitting transistor devices.

[0076] 3. This invention develops a light-emitting transistor device based on an organic semiconductor surface light source, which can make the most of the advantages of the abundance, light weight, low cost and easy processing of organic semiconductor materials, and provides an effective solution for the large-area controllable and arrayed fabrication of light-emitting transistor devices.

[0077] "Aperture ratio" refers to the percentage of the area of ​​the light-emitting surface to the sum of the areas of the light-emitting surface and the aperture surface. By adjusting the area ratio of the light-emitting surface, a series of aperture ratios (e.g., aperture ratios of 10%, 15%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 82%, 85%, 88%, 90%, 94%) of transistors can be obtained. Attached Figure Description

[0078] Figure 1-1 This is a schematic diagram of the structure of the light-emitting transistor device with surface light source emission prepared in Examples 1-4.

[0079] Figure 1-2 This is a schematic diagram of the structure of the light-emitting transistor device with surface light source emission prepared in Example 5. Figure 2-1 Optical micrographs of the surface light source emission of the red, green, and blue primary color planar light-emitting transistor devices prepared in Examples 1, 2, and 3, respectively.

[0080] Figure 2-2 Typical transfer curves (a), output curves (b), and emission spectra (c) of the green planar light-emitting transistor device prepared in Example 1 are shown.

[0081] Figure 3 These are optical photographs of the planar light-emitting transistor with high aperture ratio and surface light source emission in Example 4, and optical photographs of its emission.

[0082] Figure 4The images show typical transfer curves and emission spectra of the planar light-emitting transistor with high aperture ratio and surface light source emission in Example 4.

[0083] Figure 5 This is a schematic diagram of the planar light-emitting tandem transistor containing three light-emitting components emitted from a surface light source in Example 8. Detailed Implementation

[0084] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of protection of the present invention. Furthermore, it should be understood that after reading the disclosure of this invention, those skilled in the art can make various modifications or alterations to the present invention, and these equivalent forms also fall within the scope of protection defined by this invention.

[0085] Unless otherwise specified, the experimental methods used in the following examples are conventional methods; unless otherwise specified, the reagents and materials used in the following examples are commercially available.

[0086] Example 1: Planar Light Emitting Transistor Device Based on CBP:Ir(ppy)3 Green Light Emitting Unit for Surface Light Source Emission

[0087] 1) Cleaning of Si / SiO2 wafers and modification of the water-soluble layer:

[0088] Before use, silicon wafers with a SiO2 oxide layer are first cleaned with a hydrogen peroxide:concentrated sulfuric acid solution (heated in an electric furnace and boiled for 15 minutes) in a volume ratio of approximately 1:2. Then, they are ultrasonically cleaned sequentially with deionized water, acetone, and isopropanol for approximately 10 minutes each, followed by rapid drying with nitrogen. The surface energy levels are then modified for 5 minutes in an O2 plasma cleaner to remove residual organic solvents. Subsequently, the wafers are dried in a 90°C oven for 90 minutes. Finally, a drop of octadecyltrichlorosilane (OTS) is placed in the center of a petri dish containing the silicon wafer using a capillary tube. This petri dish is then heated in a 120°C oven for 120 minutes and allowed to cool naturally.

[0089] 2) Fabrication of organic charge transport layer (i.e., semiconductor charge transport layer) C8-BTBT

[0090] The patterned metal mask was fixed to the substrate, and C8-BTBT at a thickness of 50 nm was thermally evaporated onto the Si / SiO2 wafer modified in step 1) using a vacuum deposition machine. Immediately after deposition, annealing was performed at 45 degrees Celsius for 20 minutes.

[0091] 3) Fabrication of the source electrode

[0092] After replacing the mask and fixing it to the substrate, 2 nm of MoO was thermally evaporated on one side of the organic charge transport layer using a vacuum deposition machine. xAnd 40nm Au.

[0093] 4) Fabrication of the charge buffer layer and light-emitting unit:

[0094] After replacing the mask and fixing it to the substrate, a 40nm charge buffer layer TAPC and a 20nm 10% Ir(ppy)3:CBP / 40nm 3TPYMB light-emitting unit are sequentially deposited on the other side of the organic charge transport layer using a vacuum coating machine.

[0095] 5) Fabrication of the drain electrode:

[0096] After replacing the mask and fixing it to the substrate, 0.5 nm LiF / 1 nm Al / 35 nm Ag were sequentially deposited on the light-emitting unit using a vacuum deposition machine as drain electrodes. The device fabrication was completed, and the device structure is shown in Figure 1.

[0097] 6) Performance testing and characterization of light-emitting transistors:

[0098] In a nitrogen atmosphere within a glove box, voltages were applied to the source, drain, and gate electrodes using probes. The gate electrode was heavily doped silicon, the source electrode was grounded, and the voltage between the source and drain electrodes was -70V. The voltage between the gate and source electrodes varied from 20V to -70V in a step of -2V. In a dark environment, the photocurrent of the device was measured using a photomultiplier tube at the 0.5V setting, and the current-photocurrent-voltage relationship curve was measured. The spectrum of the device was measured using a spectrometer, and a CCD was used to acquire luminescence images.

[0099] Example 2: Planar Light Emitting Transistor Device Based on CBP:Ir(mphmq)2tmd Red Light Emitting Unit Surface Light Source

[0100] 1) Cleaning of Si / SiO2 wafers and modification of the water-soluble layer:

[0101] Before use, silicon wafers with a SiO2 oxide layer are first cleaned with a hydrogen peroxide:concentrated sulfuric acid solution (heated in an electric furnace and boiled for 15 minutes) in a volume ratio of approximately 1:2. Then, they are ultrasonically cleaned sequentially with deionized water, acetone, and isopropanol for approximately 10 minutes each, followed by rapid drying with nitrogen. The surface energy levels are then modified for 5 minutes in an O2 plasma cleaner to remove residual organic solvents. Subsequently, the wafers are dried in a 90°C oven for 90 minutes. Finally, a drop of octadecyltrichlorosilane (OTS) is placed in the center of a petri dish containing the silicon wafer using a capillary tube. This petri dish is then heated in a 120°C oven for 120 minutes and allowed to cool naturally.

[0102] 2) Fabrication of organic charge transport layer (i.e., semiconductor charge transport layer) C8-BTBT

[0103] The patterned metal mask was fixed to the substrate, and C8-BTBT at a thickness of 50 nm was thermally evaporated onto the Si / SiO2 wafer modified in step 1) using a vacuum deposition machine. Immediately after deposition, annealing was performed at 45 degrees Celsius for 20 minutes.

[0104] 3) Fabrication of the source electrode

[0105] After replacing the mask and fixing it to the substrate, 2 nm of MoO was thermally evaporated on one side of the organic charge transport layer using a vacuum deposition machine. x And 40nm Au.

[0106] 4) Fabrication of charge buffer layer and light-emitting unit

[0107] After replacing the mask and fixing it to the substrate, a 40nm charge buffer layer TAPC and a 20nm 5%Ir(mphmq)2tmd:CBP / 40nm Tmpypb are sequentially deposited on the other side of the organic charge transport layer using a vacuum deposition machine.

[0108] 5) Preparation of the drain electrode

[0109] After replacing the mask and fixing it to the substrate, 0.5 nm LiF / 1 nm Al / 35 nm Ag were sequentially deposited on the light-emitting unit using a vacuum deposition machine as drain electrodes. The device fabrication was completed, and the device structure is shown in Figure 1.

[0110] 6) Performance testing and characterization of light-emitting transistors:

[0111] In a nitrogen atmosphere within a glove box, voltages were applied to the source, drain, and gate electrodes using probes. The gate electrode was heavily doped silicon, the source electrode was grounded, and the voltage between the source and drain electrodes was -70V. The voltage between the gate and source electrodes varied from 20V to -70V in a step of -2V. In a dark environment, the photocurrent of the device was measured using a photomultiplier tube at the 0.5V setting, and the current-photocurrent-voltage relationship curve was measured. The spectrum of the device was measured using a spectrometer, and a CCD was used to acquire luminescence images.

[0112] Example 3: Planar Light Emitting Transistor Device Based on CBP:BD1 Blue Light Emitting Unit Surface Light Source

[0113] 1) Cleaning of Si / SiO2 wafers and modification of the water-soluble layer:

[0114] Before use, silicon wafers with a SiO2 oxide layer are first cleaned with a hydrogen peroxide:concentrated sulfuric acid solution (heated in an electric furnace and boiled for 15 minutes) in a volume ratio of approximately 1:2. Then, they are ultrasonically cleaned sequentially with deionized water, acetone, and isopropanol for approximately 10 minutes each, followed by rapid drying with nitrogen. The surface energy levels are then modified for 5 minutes in an O2 plasma cleaner to remove residual organic solvents. Subsequently, the wafers are dried in a 90°C oven for 90 minutes. Finally, a drop of octadecyltrichlorosilane (OTS) is placed in the center of a petri dish containing the silicon wafer using a capillary tube. This petri dish is then heated in a 120°C oven for 120 minutes and allowed to cool naturally.

[0115] 2) Fabrication of organic charge transport layer (i.e., semiconductor charge transport layer) C8-BTBT

[0116] The patterned metal mask was fixed to the substrate, and C8-BTBT at a thickness of 50 nm was thermally evaporated onto the Si / SiO2 wafer modified in step 1) using a vacuum deposition machine. Immediately after deposition, annealing was performed at 45 degrees Celsius for 20 minutes.

[0117] 3) Fabrication of the source electrode

[0118] After replacing the mask and fixing it to the substrate, 2 nm of MoO was thermally evaporated on one side of the organic charge transport layer using a vacuum deposition machine. x And 40nm Au.

[0119] 4) Fabrication of the charge buffer layer and light-emitting unit:

[0120] After replacing the mask and fixing it to the substrate, a 40nm charge buffer layer TAPC and a 20nm 10% BD1:CBP / 40nm B3pypb light-emitting unit are sequentially deposited on the other side of the organic charge transport layer using a vacuum deposition machine.

[0121] 5) Fabrication of the drain electrode:

[0122] After replacing the mask and fixing it to the substrate, 0.5 nm LiF / 1 nm Al / 35 nm Ag were sequentially deposited on the light-emitting unit using a vacuum deposition machine as drain electrodes. The device fabrication was completed, and the device structure is shown in Figure 1.

[0123] 6) Performance testing and characterization of light-emitting transistors:

[0124] In a nitrogen atmosphere within a glove box, voltages were applied to the source, drain, and gate electrodes using probes. The gate electrode was heavily doped silicon, the source electrode was grounded, and the voltage between the source and drain electrodes was -70V. The voltage between the gate and source electrodes varied from 20V to -70V in a step of -2V. In a dark environment, the photocurrent of the device was measured using a photomultiplier tube at the 0.5V setting, and the current-photocurrent-voltage relationship curve was measured. The spectrum of the device was measured using a spectrometer, and a CCD was used to acquire luminescence images.

[0125] Figure 2-1 The images show optical micrographs of the red, green, and blue primary color planar light-emitting field-effect transistor devices prepared in Examples 1, 2, and 3, respectively, emitting light from a surface light source in the dark. The emission colors from left to right are red, green, and blue, and all of them achieve emission from a surface light source. Figure 2-2 The typical transfer curve, output curve, and emission spectrum of the green planar light-emitting field-effect transistor device prepared in Example 1 demonstrate the excellent gate voltage regulation characteristics (on / off ratio 10). 6 (and luminescence properties.)

[0126] Example 4: A high aperture ratio planar light-emitting transistor device based on CBP:Ir(ppy)3 green light-emitting unit for surface light emission.

[0127] 1) Cleaning of Si / SiO2 wafers and modification of the water-soluble layer:

[0128] Before use, silicon wafers with a SiO2 oxide layer are first cleaned with a hydrogen peroxide:concentrated sulfuric acid solution (heated in an electric furnace and boiled for 15 minutes) in a volume ratio of approximately 1:2. Then, they are ultrasonically cleaned sequentially with deionized water, acetone, and isopropanol for approximately 10 minutes each, followed by rapid drying with nitrogen. The surface energy levels are then modified for 5 minutes in an O2 plasma cleaner to remove residual organic solvents. Subsequently, the wafers are dried in a 90°C oven for 90 minutes. Finally, a drop of octadecyltrichlorosilane (OTS) is placed in the center of a petri dish containing the silicon wafer using a capillary tube. This petri dish is then heated in a 120°C oven for 120 minutes and allowed to cool naturally.

[0129] 2) Preparation of organic charge transport layer C8-BTBT

[0130] The patterned metal mask was fixed to the substrate, and C8-BTBT at a thickness of 50 nm was thermally evaporated onto the Si / SiO2 wafer modified in step 1) using a vacuum deposition machine. Immediately after deposition, annealing was performed at 45 degrees Celsius for 20 minutes.

[0131] 3) Fabrication of the source electrode

[0132] After replacing the mask and fixing it to the substrate, 2 nm of MoO was thermally evaporated on one side of the organic charge transport layer using a vacuum deposition machine.x And 40nm Au.

[0133] 4) Fabrication of the charge buffer layer and light-emitting unit:

[0134] After replacing the mask and fixing it to the substrate, a 40nm charge buffer layer TAPC and a 20nm 10% Ir(ppy)3:CBP / 40nm 3TPYMB light-emitting unit are sequentially deposited on the other side of the organic charge transport layer using a vacuum deposition machine.

[0135] 5) Fabrication of the drain electrode:

[0136] After replacing the mask and fixing it to the substrate, 0.5 nm LiF / 1 nm Al / 35 nm Ag were sequentially deposited on the light-emitting unit using a vacuum deposition machine as drain electrodes. The device fabrication was completed, and the device structure is shown in Figure 1. The optical photographs (left) and emission optical photographs (right) of the obtained device are shown below. Figure 3 As shown.

[0137] 6) Performance testing and characterization of light-emitting transistors:

[0138] In a nitrogen atmosphere within a glove box, voltages were applied to the source, drain, and gate electrodes using probes. The gate electrode was heavily doped silicon, the source electrode was grounded, and the voltage between the source and drain electrodes was -70V. The voltage between the gate and source electrodes varied from 20V to -70V in increments of -2V. In darkness, the photocurrent of the device was measured using a photomultiplier tube at a 0.5V setting, and the current-photocurrent-voltage relationship curve was determined. The device spectrum was measured using a spectrometer, and bright-field and dark-field emission images were acquired using a CCD. The test results are as follows: Figure 4 As shown, increasing the light-emitting area can improve the aperture ratio (approximately 90%) while still achieving good surface light source effect and luminous brightness. This type of planar light-emitting transistor can realize the construction of high aperture ratio devices.

[0139] Example 5

[0140] Referring to the transistor fabrication process of Example 4, the difference is that in this example, a semiconductor charge transport layer is first deposited on the modified Si / SiO2 wafer, followed by a charge buffer layer. Then, a source electrode and a light-emitting unit are deposited on the charge buffer layer, with the source electrode and light-emitting unit located on opposite sides of the charge buffer layer. Finally, a drain electrode is deposited on the light-emitting unit. The specific structure is as follows: Figure 1-2 As shown. Testing has shown that the transistor device obtained in this embodiment also exhibits good gate voltage regulation characteristics, light emission performance, large aperture ratio (at least 80%), and stability.

[0141] Examples 6-7

[0142] Transistors of Examples 6-7 were prepared by replacing TAPC in Example 4 with an ultrathin layer of metallic material Au, or by replacing TAPC in Example 4 with C60-pentaphenyl-C60. These transistors exhibit the same or similar performance as those of Example 4, namely, they are planar light-emitting transistors emitting surface light sources, and possess good gate voltage regulation characteristics, light-emitting performance, and stability.

[0143] Example 8

[0144] like Figure 5 As shown, the device in this embodiment includes a source electrode, an organic charge transport layer C8-BTBT, three light-emitting components: a first light-emitting component consisting of a charge buffer layer TAPC and a blue light-emitting unit BD1:CBP / TmPTPB; a second light-emitting component consisting of a charge buffer layer TAPC and a green light-emitting unit Ir(ppy)3:CBP / 3TPYMB; and a third light-emitting component consisting of a charge buffer layer TAPC and a red light-emitting unit Ir(mphmq)2tmd:CBP / Tmpypb, as well as a drain electrode LiF / Al / Ag. The light-emitting components are connected via a CGL layer.

[0145] The embodiments of the present invention have been described above. However, the present invention is not limited to the above embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A planar light-emitting transistor with a surface light source configuration, characterized in that, The planar light-emitting transistor of the surface light source includes a source electrode, a drain electrode, a semiconductor charge transport layer, a light-emitting unit, and a charge buffer layer disposed below the source electrode or the drain electrode. The charge buffer layer is disposed above the semiconductor charge transport layer and below the light-emitting unit. The light-emitting surface of the planar light-emitting transistor of the surface light source is U-shaped, and the source electrode is located on the opening side of the U-shape; The mobility of the semiconductor charge transport layer is not less than 0.1 cm. 2 V -1 s -1 The semiconductor materials include organic semiconductor materials and / or inorganic semiconductor materials, wherein the organic semiconductor materials are selected from one or more of the following substances: 2,7-dioctyl[1]benzothiophene[3,2-b]benzothiophene (C8-BTBT), 2,6-diphenylanthracene (DPA), 2,6-dinathynethracene (dNaAnt), 2,6-bis(p-hexylbenzene)anthracene (C6-DPA), 2,6-bis(p-octylhexylbenzene)anthracene (C8-DPA), 2,6-bis(p-decylbenzene)anthracene (C8-DPA). 10 -DPA), poly(3-hexylthiophene) (P3HT), 9,9-di-n-octylfluorene-benzothiadiazole copolymer (F8BT), poly[2,5-(2-octyldodecyl)-3,6-dionepyrrolopyrrole-alt-5,5-(2,5-di(thiophene-2-yl)thiopheno[3,2-b]thiophene)] (DPP-DTT); The inorganic semiconductor material is selected from one or more of the following substances: carbon nanotubes (CNTs), zinc tin oxide (ZTO), gallium nitride (GaN), silicon carbide (SiC), and zinc selenide (ZnSe); The mobility of the charge buffer layer is 2-5 orders of magnitude smaller than that of the semiconductor charge transport layer; the charge buffer layer is a layer formed from one or more of the organic materials 4,4'-cyclohexylbis[N,N-di(4-methylphenyl)aniline] (TAPC), N,N'-diphenyl-N,N'-(1-naphthyl)-1,1'-biphenyl-4,4'-diamine (NPB) and PVK; or, the charge buffer layer is a layer formed from one or more of the metallic materials Au, Ni, and Pt; or, the charge buffer layer is a layer formed from one or more of C60-pentaphenyl-C60, C70-tetraphenyl-C70, and C60-tetraphenyl-C70 in a pnp junction.

2. The planar light-emitting transistor with a surface light source configuration according to claim 1, characterized in that, The semiconductor charge transport layer is disposed below the source electrode; The light-emitting unit is disposed below the drain electrode; or, the charge buffer layer is disposed below the source electrode and the light-emitting unit.

3. The planar light-emitting transistor with a surface light source configuration according to claim 1, characterized in that, The charge buffer layer is disposed between the drain electrode and the semiconductor charge transport layer, between the source electrode and the semiconductor charge transport layer, or between the semiconductor charge transport layer and the light-emitting unit.

4. The planar light-emitting transistor with a surface light source configuration according to claim 1, characterized in that, The planar light-emitting transistor of the surface light source includes: Support substrate; A gate electrode is disposed on the surface of the supporting substrate; A dielectric layer disposed above the gate electrode; A semiconductor charge transport layer disposed on the dielectric layer; A source electrode and a charge buffer layer are disposed on the semiconductor charge transport layer, and the source electrode and the charge buffer layer are disposed on different sides of the charge transport layer. The light-emitting unit and the drain electrode are sequentially disposed on the charge buffer layer; Alternatively, the planar light-emitting transistor of the surface light source includes: Support substrate; A gate electrode is disposed on the surface of the supporting substrate; A dielectric layer disposed above the gate electrode; A semiconductor charge transport layer disposed on the dielectric layer; A charge buffer layer disposed on the semiconductor charge transport layer; The source electrode and the light-emitting unit are sequentially disposed on the charge buffer layer, with the source electrode and the light-emitting unit on different sides of the charge buffer layer. The drain electrode is positioned above the light-emitting unit.

5. The planar light-emitting transistor with a surface light source configuration according to any one of claims 1-4, characterized in that, The source electrode and drain electrode are arranged in a non-planar manner, the light-emitting part is the entire effective area of ​​the source electrode or drain electrode, and the gate voltage is used to control the light emission brightness.

6. The planar light-emitting transistor with a surface light source configuration according to any one of claims 1-4, characterized in that, The light-emitting unit includes a light-emitting layer and an electron transport layer, a hole transport layer, an electron injection layer, and / or a hole injection layer that match the energy level of the light-emitting layer.

7. The planar light-emitting transistor with a surface light source configuration according to claim 6, characterized in that, The light-emitting layer is a layer formed of a light-emitting material, which is selected from one or more of fluorescent materials, phosphorescent materials, and thermally active delayed fluorescence materials; The fluorescent material is selected from one or more of octahydroxyquinoline aluminum (Alq3), 5,6,11,12-tetraphenylbenzotetraphenyl (red fluorene), and 4,4'-bis[4-(diphenylamino)styryl]biphenyl (BDAVBi); The phosphorescent material is selected from one or more of tris(2-phenylpyridine)iridium (Ir(ppy)3), bis(2-phenylpyridine-C2,N)iridium acetylacetonate (Ir(ppy)2(acac)) and iridium(III)tris[N,N'-diphenylbenzimidazole-2-ylidene-C2,C2'] (Ir(dpbic)3); The thermally active delayed fluorescence material is selected from one or two of 9,9'-(5-(4,6-diphenyl-1,3,5-triazine-2-yl)-1,3-phenylene)bis(9Hcarbazole) (DCzTRZ) and (N-phenoxazine)phenyl]sulfone (PXZ-DPS).

8. The planar light-emitting transistor with a surface light source configuration according to any one of claims 1-4, characterized in that, The light emitted by the light-emitting unit has a spectrum between 390 nm and 780 nm.

9. The planar light-emitting transistor with a surface light source configuration according to any one of claims 1-4, characterized in that, The light-emitting layer in the light-emitting unit is formed by a single light-emitting material or by a guest-doped host material; The single luminescent material is Alq3, DPA, or dNaAnt; the guest dopant in the host material is one or more of the following substances: 1,4-bis(10-phenylanthracene-9-yl)benzene (BD1), BDAVBi, perylene, bis(dimethyl-dihydroacrylidinephenylsulfone) (DMAC-DPS), bis[2-(5-cyano-4,6-difluorophenyl)pyridine-C2,N)]pyridinecarboxyiridium (FCNirPic), iridium(III)bis[(2,3, 4-Difluorophenyl)-pyridine-N,C2']pyridine carboxylate (Ir(tfpd)2pic), bis[2,4-dimethyl-6-(4-methyl-2-quinolinyl-κN)phenyl-κC](2,2,6,6-tetramethyl-3,5-heptanedione-κO3)(Ir(mphmq)2tmd), 4,4'-bis[4-(di-p-tolylamino)styryl]biphenyl (DPAVBi), 9,9'-(5-(4,6-diphenyl-1,3,5-triazin-2-yl)-1,3-phenyl)bis(9H -Carbazole) (DCzTrz), 5,5-dibromo-4,4-tetracosyl-2,2-bithiophene (fac-Ir(dpbic)3), tris(2-phenylpyridine)iridium (Ir(ppy)3), tris[2-(p-tolyl)pyridine]iridium(III) (Ir(mppy)3), bis(2-phenylpyridine-C2,N)iridium(III) (Ir(ppy)2(acac)), bis(2-(naphthyl-2-yl)pyridine)(acetylacetone)iridium(III) (Ir(npy)2acac), tris[2-(3-methyl-2-pyridyl)phenyl]iridium (Ir(3mppy)3), bis(2-(3,5-dimethylphenyl)quinoline-C2,N')(acetylacetone)iridium(III) One or more of the following: (Ir(dmpq)2acac), bis(2-(2'-benzothiophene)-pyridine-N,C3')iridium(acetylacetone) (Ir(btp)2(acac)), 4-(dicyanomethylene)-2-methyl-6-[2-(2,3,6,7-tetrahydro-1H,5H-benzo[ij]quinazine-9-yl)vinyl]-4H-pyran (DCM2), Rubrene, tris(2-(3,5-dimethylphenyl)quinoline-C2,N')iridium(III) (Ir(dmpq)3), and 2,8-di-tert-butyl-5,11-bis(4-tert-butylphenyl)-6,12-diphenyltetraphenyl (TBRb); The main material is one or more of the following substances: Alq3, 4,4'-bis(N-carbazole)-1,1'-biphenyl (CBP), 4,4'-bis(2,2-diphenyl-vinyl-1-yl)-4,4'-dimethylphenyl (p-DMDPVBi), 4,4'-bis(2,2-stilbene)-1,1'-biphenyl (DPVBi), 2-tert-butyl-9,10-bis(2-naphthyl)anthracene (TBADN), diphenyl[4-(triphenylsilyl)phenyl]phosphine oxide (T SPO1), 3-(3-(9H-carbazole-9-yl)phenyl)benzofuran[2,3-b]pyridine (PCz-BFP), 2,4,6-tris[3-(diphenylphosphoxy)phenyl]-1,3,5-triazole (PO-T2T), 2,4,6-tris(3-(carbazole-9-yl)phenyl)-1,3,5-triazine (TCPZ), 4,4'-bis(triphenylsilyl)-1,1'-biphenyl (BSB), 2,7-bis[9,9-di(4-methylphenyl)fluorene-2-yl]-9,9-di(4-methylphenyl)fluorene (TDAF), 3',3'',3'''-(1,3,5-triazine-2,4,6-triyl)tri(([1,1'-biphenyl]-3-nitrile))(CN-T2T) or one or more of these.

10. The planar light-emitting transistor with a surface light source configuration according to any one of claims 1-4, characterized in that, The thickness of the semiconductor charge transport layer, charge buffer layer, and light-emitting unit is all in the nanometer to submicrometer range.

11. The planar light-emitting transistor with a surface light source configuration according to any one of claims 1-4, characterized in that, The planar configuration light-emitting transistor of the surface light source emits planar light that matches the color of the light-emitting unit under an applied voltage.

12. The planar light-emitting transistor with a surface light source configuration according to claim 1, characterized in that, The drain electrode, light-emitting unit, and charge buffer layer are U-shaped, with the source electrode located on the opening side of the U-shape. Alternatively, the drain electrode and the light-emitting unit have a U-shaped planar shape, with the source electrode located on the opening side of the U-shape.

13. The method for fabricating a planar light-emitting transistor with a surface light source according to any one of claims 1-12, characterized in that, The process includes the following steps: a charge buffer layer is disposed below the drain electrode or the source electrode, the charge buffer layer is disposed above the semiconductor charge transport layer, and the charge buffer layer is disposed below the light-emitting unit.

14. The application of the planar light-emitting transistor with surface light source configuration according to any one of claims 1-12 in wearable devices, lighting displays, and lasers.

Images