Semiconductor device and method of manufacturing the same

Abstract

The present invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device includes a plurality of memory cells each configured to include: a first electrode pattern; and a selector pattern disposed on the first electrode pattern, wherein the selector pattern can include silicon oxide having a dopant incorporated therein, which exhibits a higher density than that of silicon oxide formed by using a deposition process including a source gas of Si and O2.

Description

[0001] Cross-reference to related applications

[0002] This patent document claims priority to Korean Patent Application No. 10-2021-0151117, filed on November 5, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] The technologies and implementation methods disclosed in this patent document relate to storage circuits or devices and their applications in electronic devices or systems. Background Technology

[0004] Recently, with the trend towards miniaturization, low power consumption, high performance, and multifunctionality in electronic devices, there is a need in the prior art for semiconductor devices capable of storing information in various electronic devices such as computers and portable communication devices, and research has been conducted on such semiconductor devices. Such semiconductor devices can store data by switching between different resistance states according to the applied voltage or current. These semiconductor devices may include RRAM (Resistive Random Access Memory), PRAM (Phase Change Random Access Memory), FRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), E-fuse, etc. Summary of the Invention

[0005] The technologies disclosed in this patent document include storage circuits or devices and their applications in electronic devices or systems, as well as various implementation methods of electronic devices, which can improve the operating characteristics of semiconductor devices and prevent process defects.

[0006] In one aspect, a semiconductor device includes a plurality of memory cells, each of the plurality of memory cells including: a first electrode pattern; and a selector pattern disposed on the first electrode pattern. The selector pattern includes: silicon oxide having incorporated dopants, exhibiting a higher density than silicon oxide formed using a deposition process employing a source gas comprising Si and O2.

[0007] In another aspect, a method for manufacturing a semiconductor device comprising a plurality of memory cells is provided. The method may include: forming a first electrode layer; forming an initial Si-containing layer on the first electrode layer; performing a radical oxidation process to transform a first portion of the initial Si-containing layer into an oxide layer comprising silicon oxide (SiO2); forming a Si-containing layer below the oxide layer by using a second portion of the initial Si-containing layer; and incorporating a dopant into the oxide layer by an ion implantation process to form a selector pattern.

[0008] In another aspect, a method for manufacturing a semiconductor device comprising a plurality of memory cells may include: forming a first electrode layer on a substrate; forming an initial buffer layer on a first electrode pattern; forming an initial Si-containing layer on the initial buffer layer; performing a radical oxidation process to form an oxide layer comprising SiO2, the oxide layer being derived from at least a portion of the initial Si-containing layer, and any retained portion of the initial Si-containing layer forming a Si-containing layer; and incorporating a dopant into the oxide layer by an ion implantation process to form a selector pattern.

[0009] In another aspect, a method for manufacturing a semiconductor device comprising a plurality of memory cells may include: forming an initial capping layer on the plurality of memory cells; performing a radical oxidation process to transform a first portion of the initial capping layer into a second capping layer comprising oxides; and retaining a second portion of the initial capping layer as a first capping layer beneath the second capping layer. Attached Figure Description

[0010] Figures 1A to 1C Semiconductor devices based on some embodiments of the disclosed technology are shown.

[0011] Figure 1D Examples of magnetic tunnel junction (MTJ) structures included in variable resistor patterns based on some embodiments of the disclosed technology are shown.

[0012] Figures 2 to 7 This is a cross-sectional view illustrating an example method for forming a selector pattern based on some implementations of the disclosed technology.

[0013] Figures 8A to 8F This is a cross-sectional view illustrating examples of semiconductor devices and manufacturing methods thereof based on some embodiments of the disclosed technology. Detailed Implementation

[0014] In the following, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0015] Figure 1A and Figure 1B Semiconductor devices based on some embodiments of the disclosed technology are shown. Figure 1A It is a perspective view, and Figure 1B It is along Figure 1A A cross-sectional view taken from line A-A'.

[0016] refer to Figure 1A and Figure 1BThe semiconductor device may include: a crossover structure comprising: a substrate 100; a first line 110 formed on the substrate 100 and extending in a first direction; a second line 150 formed above the first line 110, spaced apart from the first line 110 and extending in a second direction intersecting the first direction; and a memory cell 120 disposed at the crossover point of the first line 110 and the second line 150 between the first line 110 and the second line 150.

[0017] Substrate 100 may include a semiconductor material such as silicon. The desired lower structure (not shown) may be formed in substrate 100. For example, substrate 100 may include a driving circuit (not shown) electrically connected to a first line 110 and / or a second line 150 to control the operation of memory cell 120.

[0018] The first line 110 and the second line 150 can be connected to the lower and upper ends of the memory cell 120, respectively, and can transmit voltage or current to the memory cell 120 to drive it. When the first line 110 is used as a word line, the second line 150 can be used as a bit line. Conversely, when the first line 110 is used as a bit line, the second line 150 can be used as a word line. The first line 110 and the second line 150 can include a single-layer or multi-layer structure comprising one or more various conductive materials. Examples of conductive materials can include metals, metal nitrides, or conductive carbon materials, or combinations thereof, but are not limited thereto. For example, the first line 110 and the second line 150 may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), or silicon carbon nitride (SiCN), or combinations thereof.

[0019] Storage cells 120 can be arranged in a matrix having rows and columns along a first direction and a second direction, thereby overlapping with the intersection regions between the first line 110 and the second line 150. In one embodiment, the size of each storage cell 120 can be substantially equal to or smaller than the size of the intersection region between each corresponding pair of first lines 110 and second lines 150. In another embodiment, the size of each storage cell 120 can be larger than the size of the intersection region between each corresponding pair of first lines 110 and second lines 150.

[0020] The space between the first line 110, the second line 150 and the storage unit 120 can be filled with dielectric material.

[0021] refer to Figure 1B A particular example of the storage cell 120 shown may include a stacked structure including a lower electrode pattern 121, a selector pattern 123 as a switching device for turning the storage cell 120 on or off, an intermediate electrode pattern 125, a variable resistor pattern 127 for storing data in the storage cell 120, and an upper electrode pattern 129.

[0022] A lower electrode pattern 121 can be inserted between the first line 110 and the selector pattern 123 and is disposed at the lowest part of each memory cell 120. The lower electrode pattern 121 can serve as a circuit node carrying voltage or current between the corresponding first line 110 and the rest of each memory cell 120 (e.g., elements 123, 125, 127, and 129). An intermediate electrode pattern 125 can be inserted between the selector pattern 123 and the variable resistor pattern 127. The intermediate electrode pattern 125 can electrically connect the selector pattern 123 and the variable resistor pattern 127 to each other while physically separating them. An upper electrode pattern 129 can be disposed at the highest part of the memory cell 120 and serve as a voltage or current transmission path between the rest of the memory cell 120 and the corresponding second line 150.

[0023] The lower electrode pattern 121, the intermediate electrode pattern 125, and the upper electrode pattern 129 may include single-layer or multi-layer structures, each comprising various conductive materials, such as metals, metal nitrides, or conductive carbon materials, or combinations thereof. For example, the lower electrode pattern 121, the intermediate electrode pattern 125, and the upper electrode pattern 129 may include tungsten (W), titanium (Ti), tantalum (Ta), platinum (Pt), aluminum (Al), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pb), tungsten nitride (WN), tungsten silicide (WSi), titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), or silicon carbon nitride (SiCN), or combinations thereof.

[0024] The lower electrode pattern 121, the intermediate electrode pattern 125, and the upper electrode pattern 129 may be made of the same material or different materials.

[0025] The lower electrode pattern 121, the middle electrode pattern 125 and the upper electrode pattern 129 may have the same thickness or different thicknesses.

[0026] By switching the conductive path on or off via selector pattern 123, selector pattern 123 can be used to control access to variable resistor pattern 127 and thus to control access to memory cell 120. For example, selector pattern 123 can be switched on to conduct electricity or switched off to not conduct electricity based on the voltage applied to selector pattern 123. When the applied voltage is less than a predetermined threshold, selector pattern 123 can be switched off to not conduct electricity and block or substantially limit the current flowing through selector pattern 123. When the applied voltage is equal to or greater than the predetermined threshold, selector pattern 123 can be switched on to conduct electricity and cause a sharp increase in the current flowing through memory cell 120. Selector pattern 123 may include: MIT (metal-insulator transition) materials, such as NbO2, TiO2, VO2, WO2, etc.; MIEC (mixed ion-electron conduction) materials, such as ZrO2 (Y2O3), Bi2O3-BaO, (La2O3). x (CeO2) 1-x Such as; including chalcogenide OTS (bidirectional threshold switch) materials, such as Ge2Sb2Te5, As2Te3, As2, As2Se3, etc.; or tunneling insulating materials, such as silicon oxide, silicon nitride, metal oxides, etc. The thickness of the tunneling insulating layer is small enough to allow electrons to tunnel under a given voltage or current. The selector pattern 123 may include a single-layer or multi-layer structure.

[0027] In one embodiment, selector pattern 123 can be configured to perform threshold switching operation, which means turning selector pattern 123 on or off while applying an external voltage to selector pattern 123. For example, selector pattern 123 can be turned on or off by increasing or decreasing the absolute value of the external voltage. When the absolute value of the external voltage applied to selector pattern 123 increases and becomes greater than a first threshold voltage, selector pattern 123 can be turned on to conduct electricity and allow current to flow. Once selector pattern 123 is turned on, the increase in external voltage causes the operating current flowing through to increase non-linearly. After selector pattern 123 is turned on, when the absolute value of the external voltage applied to selector pattern 123 decreases and becomes less than a second threshold voltage, selector pattern 123 can be turned off to not conduct electricity. Once selector pattern 123 is turned off, the decrease in external voltage causes the operating current flowing through to decrease non-linearly. Therefore, selector pattern 123 performing threshold switching operation can have non-memory operation characteristics.

[0028] In the material layer used for selector pattern 123, doped regions are provided to allow selector pattern 123 to perform threshold switching operations. The threshold switching operation of selector pattern 123 can be controlled based on the characteristics of the doped regions (e.g., the size of the doped regions). The dopant incorporated into selector pattern 123 can form traps for conductive charge carriers within selector pattern 123. The threshold switching operation of selector pattern 120 can be achieved by trapping charge carriers or making charge carriers conductive while they move between intermediate electrode pattern 125 and upper electrode pattern 129 in response to the application of an external voltage.

[0029] In some embodiments, selector pattern 123 may include a dielectric material having an incorporated dopant. Selector pattern 123 may include an oxide having a dopant, a nitride having a dopant, or an oxide oxynitride having a dopant, or combinations thereof, such as silicon oxide, titanium oxide, aluminum oxide, tungsten oxide, hafnium oxide, tantalum oxide, niobium oxide, silicon nitride, titanium nitride, aluminum nitride, tungsten nitride, hafnium nitride, tantalum nitride, niobium nitride, silicon oxynitride, titanium oxynitride, aluminum oxynitride, tungsten oxynitride, hafnium oxynitride, tantalum oxynitride, or niobium oxynitride, or combinations thereof. The dopant incorporated into selector pattern 123 may include an n-type dopant or a p-type dopant and may be incorporated, for example, by an ion implantation process. Examples of dopant may include one or more of boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), silicon (Si), or germanium (Ge).

[0030] In the comparative example, when the selector pattern 123 includes an oxide layer with dopants, the selector pattern 123 can be formed by forming the oxide layer and incorporating dopants into the oxide layer. The oxide layer can be formed using common deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). For example, a SiO2 layer can be formed by mixing a source gas including Si and O2 using the above-described deposition process. The oxide layer formed by the deposition process (referred to as a deposited oxide layer) has a relatively low density. The deposited oxide layer has a structure with a relatively large number of vacancies or voids. Therefore, when dopants are introduced into the oxide layer in subsequent processes, undesirable microvoids can be formed in the selector pattern 123, and a portion of the surface of the lower electrode pattern 121 can be disrupted due to the presence of microvoids. As a result, the interface between the selector pattern 123 and the lower electrode pattern 121 can become unclear, and the electrical connection at this interface can be damaged, thereby reducing the performance of the memory cell 120.

[0031] Recognizing the above-mentioned problems in the embodiments of the disclosed technology, a selector pattern for forming selector pattern 123 (see...) Figure 2 Appendix numeral 20 Figure 4 The attached figures 30 and Figure 6 (See attached figure 40) can be achieved by forming a high-density oxide layer relative to a deposited oxide layer (see attached figure 40). Figure 2 Appendix reference numeral 22 Figure 4 Figure 32 and Figure 6 The oxide layers 22, 32, and 42 are formed by incorporating dopants into the oxide layer (see Figure 42). Each of the oxide layers 22, 32, and 42 has relatively few vacancies or voids, thus exhibiting good TDDB (time-dependent dielectric breakdown) characteristics. A dielectric layer with excellent TDDB characteristics can be considered a robust and durable dielectric layer. Each of the oxide layers 22, 32, and 42 with high density can be formed by forming each initial Si-containing layer (see Figure 42). Figure 2 Appendix reference numeral 21 Figure 4 Figure reference 31 and Figure 6 Reference numeral 41) and these layers are formed by performing a radical oxidation process instead of forming oxide layers using deposition processes (e.g., CVD, PVD, or ALD). In embodiments, oxide layers 22, 32, and 42 with high density and desired thickness can be formed by a radical oxidation process, while a portion of the Si-containing layer (see reference numeral 41) is formed. Figure 2 Figure reference numerals 21A and Figure 6 (see attached figure 41A) or part of the initial buffer layer (see attached figure 41A) Figure 4 Figure 33 and Figure 6 (Ref. 43) can be maintained at a specific thickness. A portion containing the Si layer (see Figure 43) Figure 2 Figure reference numerals 21A and Figure 6 (see attached figure 41A) or part of the initial buffer layer (see attached figure 41A) Figure 4 Figure 33 and Figure 6 Reference numeral 43) can be disposed beneath oxide layers 22, 32, and 42. The high-density oxide layers 22, 32, and 42, along with the retained Si-containing layers 21A and 41A or the retained initial buffer layers 33 and 43, can be used to prevent the formation of microvoids in the selector pattern 123 or reduce their extent during subsequent ion implantation processes performed under harsh conditions, and to protect the electrode structure of the lower electrode pattern 121. This results in a better interface and electrical connection between the selector pattern 123 and the lower electrode pattern 121.

[0032] In some embodiments, the retained Si-containing layers 21A and 41A or the retained initial buffer layers 33 and 43 can be absorbed into the selector pattern 123 during a subsequent ion implantation process. Therefore, after the ion implantation process, the Si-containing layers 21A and 41A or the initial buffer layers 33 and 43 may be absent. In some embodiments, after the ion implantation process, a portion of the retained Si-containing layer 21A and a portion of the retained initial buffer layers 33 and 43 may be retained with a thickness small enough not to affect the electrical characteristics of the memory cell 120 (see [link to relevant documentation]). Figure 3 Appendix reference numeral 21B Figure 5 Figure reference 33A and Figure 7 (See attached figure 43A).

[0033] Reference Figure 2 , Figure 4 and Figure 6 The selector patterns 20, 30 and 40 used to form selector patterns 123 are described in detail.

[0034] The variable resistance pattern 127 can be used to store data by setting the variable resistance pattern 123 to a desired resistance state using different resistance states of the variable resistance pattern 123 (e.g., using high resistance states and low resistance states to represent digital levels "1" and "0"), and to change the stored data bits by switching between different resistance states according to the applied voltage or current. The variable resistance pattern 127 can have a single-layer or multi-layer structure including at least one material used for RRAM, PRAM, MRAM, FRAM, etc. For example, the variable resistance pattern 127 can include materials used for RRAM, PRAM, MRAM, FRAM, etc., such as materials with variable resistance characteristics used for RRAM, PRAM, MRAM, FRAM, etc. For example, the variable resistance pattern 127 can include metal oxides (e.g., transition metal oxides) or perovskite-based oxides, phase change materials (e.g., chalcogenide-based materials), ferromagnetic materials, ferroelectric materials, etc. However, the implementation is not limited to this, and the memory cell 120 can include other memory layers capable of storing data in various ways, not limited to the variable resistance pattern 127.

[0035] In some implementations, the variable resistor pattern 127 may include a magnetic tunnel junction (MTJ) structure. (Refer to...) Figure 1D Explain it.

[0036] Figure 1D An example of a magnetic tunnel junction (MTJ) structure included in the variable resistance pattern 127 is shown.

[0037] The variable resistance pattern 127 may include an MTJ structure, which includes: a free layer 12 having a variable magnetization direction; a pinned layer 14 having a pinned magnetization direction; and a tunnel barrier layer 13 inserted between the free layer 12 and the pinned layer 14.

[0038] Free layer 12 can have one of different magnetization directions or one of different electron spin directions to switch the polarity of free layer 12 in the MTJ structure, resulting in a change in resistance value. In some embodiments, the polarity of free layer 12 changes or flips when a voltage or current signal (e.g., a drive current above a certain threshold) is applied to the MTJ structure. As the polarity of free layer 12 changes, free layer 12 and pinned layer 14 have different magnetization directions or different electron spin directions, which allows variable resistance pattern 127 to store different data or represent different data bits. Free layer 12 can also be referred to as a storage layer. The magnetization direction of free layer 12 can be substantially perpendicular to the surfaces of free layer 12, tunnel barrier layer 13, and pinned layer 14. Therefore, the magnetization direction of free layer 12 can be substantially parallel to the stacking direction of free layer 12, tunnel barrier layer 13, and pinned layer 14. Therefore, the magnetization direction of free layer 12 can be changed between a downward direction and an upward direction. The change in the magnetization direction of the free layer 12 can be caused by the spin-shifting torque generated by the applied current or voltage.

[0039] The free layer 12 may have a single-layer or multi-layer structure comprising ferromagnetic materials. For example, the free layer 12 may comprise alloys based on Fe, Ni, or Co, such as Fe-Pt alloys, Fe-Pd alloys, Co-Pd alloys, Co-Pt alloys, Co-Fe alloys, Fe-Ni-Pt alloys, Co-Fe-Pt alloys, Co-Ni-Pt alloys, or Co-Fe-B alloys, or may comprise a stack of metals, such as Co / Pt or Co / Pd, etc.

[0040] In both data read and write operations, the tunnel barrier layer 13 allows electrons to tunnel through. In a write operation to store new data, a high write current can be directed through the tunnel barrier layer 13 to change the magnetization direction of the free layer 12 and thus alter the resistance state of the MTJ to write new data bits. In a read operation, a low read current can be directed through the tunnel barrier layer 13 without changing the magnetization direction of the free layer 12, to measure the resistance state of the existing MTJ under the existing magnetization direction of the free layer 12 and read the data bits stored in the MTJ. The tunnel barrier layer 13 may comprise a dielectric oxide, such as MgO, CaO, SrO, TiO, VO, or NbO.

[0041] Pinning layer 14 may have a pinning magnetization direction that remains unchanged when the magnetization direction of free layer 12 changes. Pinning layer 14 may be referred to as a reference layer. In some embodiments, the magnetization direction of pinning layer 14 may be fixed in the downward direction. In some embodiments, the magnetization direction of pinning layer 14 may be fixed in the upward direction.

[0042] The pinning layer 14 may have a single-layer or multi-layer structure comprising ferromagnetic materials. For example, the pinning layer 14 may comprise an alloy based on Fe, Ni, or Co, such as Fe-Pt alloy, Fe-Pd alloy, Co-Pd alloy, Co-Pt alloy, Co-Fe alloy, Fe-Ni-Pt alloy, Co-Fe-Pt alloy, Co-Ni-Pt alloy, or Co-Fe-B alloy, or may comprise a stack of metals, such as Co / Pt or Co / Pd, etc.

[0043] If a voltage or current is applied to the variable resistor pattern 127, the magnetization direction of the free layer 12 can be changed by a spin-shift torque. In some embodiments, when the magnetization directions of the free layer 12 and the pinned layer 14 are parallel to each other, the variable resistor pattern 127 can be in a low-resistance state, which can represent a digital data bit "0". Conversely, when the magnetization directions of the free layer 12 and the pinned layer 14 are antiparallel to each other, the variable resistor pattern 127 can be in a high-resistance state, which can represent a digital data bit "1". In some embodiments, the variable resistor pattern 127 can be configured to store a data bit "1" when the magnetization directions of the free layer 12 and the pinned layer 14 are parallel to each other and to store a data bit "0" when the magnetization directions of the free layer 12 and the pinned layer 14 are antiparallel to each other.

[0044] In some embodiments, the variable resistance pattern 127 may also include one or more layers that perform various functions to improve the characteristics of the MTJ structure. For example, the variable resistance pattern 127 may also include at least one of a lower layer 11, a spacer layer 15, a magnetic correction layer 16, or a protective layer 17.

[0045] The lower layer 11 can be disposed below the free layer 12 and is used to improve the perpendicular magnetocrystalline anisotropy of the free layer 12. The lower layer 11 can have a single-layer or multi-layer structure, which includes metals, metal alloys, metal nitrides, or metal oxides, or combinations thereof. For example, the lower layer 11 may include one or more of TaN, AlN, SiN, TiN, VN, CrN, GaN, GeN, ZrN, NbN, MoN, or HfN.

[0046] Spacer layer 15 can be inserted between pinning layer 14 and magnetic correction layer 16 and serves as a buffer between the magnetic correction layer 16 and pinning layer 14. Spacer layer 15 can be used to improve the characteristics of magnetic correction layer 16. Spacer layer 15 may include a noble metal, such as ruthenium (Ru).

[0047] The magnetic correction layer 16 can be used to compensate for the effects of stray magnetic fields generated by the pinning layer 14. In this case, the effects of the stray magnetic field of the pinning layer 14 can be reduced, and therefore the bias magnetic field of the free layer 12 can be reduced. The magnetic correction layer 16 can have a magnetization direction that is antiparallel to the magnetization direction of the pinning layer 14. In one embodiment, when the pinning layer 14 has a downward magnetization direction, the magnetic correction layer 16 can have an upward magnetization direction. Conversely, when the pinning layer 14 has an upward magnetization direction, the magnetic correction layer 16 can have a downward magnetization direction. The magnetic correction layer 16 can be coupled to the pinning layer 14 via the spacer layer 15 to form a synthetic antiferromagnetic (SAF) structure. The magnetic correction layer 16 can have a single-layer or multi-layer structure comprising ferromagnetic materials.

[0048] In this embodiment, the magnetic correction layer 16 is located above the pinning layer 14, but the magnetic correction layer 16 can be located in different positions. For example, the magnetic correction layer 16 can be located above, below, or beside the MTJ structure, and the magnetic correction layer 16 and the MTJ structure are patterned separately.

[0049] The protective layer 17 can be used to protect the variable resistor pattern 127. In some embodiments, the protective layer 17 may comprise various conductive materials or oxides. In some embodiments, the protective layer 17 may comprise a metallic material that has few or no pinholes and high resistance to wet and / or dry etching. In some embodiments, the protective layer 17 may comprise a metal, a nitride, or an oxide, or a combination thereof. For example, the protective layer 17 may comprise a noble metal, such as ruthenium (Ru).

[0050] The protective layer 17 may have a single-layer or multi-layer structure. In some embodiments, the protective layer 17 may have a multi-layer structure, which includes oxides or metals, or combinations thereof. For example, the protective layer 17 may have a multi-layer structure consisting of an oxide layer, a first metal layer, and a second metal layer.

[0051] A material layer (not shown) for addressing the lattice structure difference and lattice constant mismatch between the pinning layer 14 and the magnetic correction layer 16 can be inserted between the pinning layer 14 and the magnetic correction layer 16. For example, this material layer can be amorphous and can include metals, metal nitrides, or metal oxides.

[0052] In some embodiments, each memory cell 120 may include a lower electrode pattern 121, a selector pattern 123, an intermediate electrode pattern 125, a variable resistor pattern 127, and an upper electrode pattern 129 stacked sequentially. In some embodiments, the memory cells 120 may have different structures. For example, at least one of the lower electrode pattern 121, the intermediate electrode pattern 125, and the upper electrode pattern 129 may be omitted. In some embodiments, the positions of the selector pattern 123 and the variable resistor pattern 127 may be reversed. In some embodiments, besides... Figure 1B In addition to the layers 121, 123, 125, 127 and 129 shown, the storage cell 120 may also include one or more layers (not shown) for enhancing the characteristics of the storage cell 120 or improving the manufacturing process.

[0053] In some embodiments, adjacent memory cells among the plurality of memory cells 120 may be spaced apart from each other at a predetermined interval, and trenches may exist between the plurality of memory cells 120. The trenches between adjacent memory cells 120 may have an aspect ratio (i.e., aspect ratio) in the range of 1:1 to 40:1, 10:1 to 40:1, 10:1 to 20:1, 5:1 to 10:1, 10:1 to 15:1, 1:1 to 25:1, 1:1 to 30:1, 1:1 to 35:1, or 1:1 to 45:1.

[0054] In some embodiments, the trenches may have sidewalls that are substantially perpendicular to the upper surface of the substrate 100. In some embodiments, adjacent trenches may be spaced apart from each other by an equal or approximately equal distance.

[0055] In some embodiments, the semiconductor device may include one or more additional layers in addition to the first line 110, the memory cell 120, and the second line 150. For example, a lower electrode contact may also be formed between the first line 110 and the lower electrode pattern 121, and an upper electrode contact may also be formed between the second line 150 and the upper electrode pattern 129.

[0056] Although a single cross-point structure has been described as an example, two or more cross-point structures may be stacked in a vertical direction perpendicular to the top surface of substrate 100.

[0057] According to an embodiment, the selector pattern 123 can be formed by the following steps: depositing initial Si-containing layers 21, 31, and 41; performing a radical oxidation process to form high-density oxide layers 22, 32, and 42; and performing an ion implantation process to incorporate dopants into the high-density oxide layers 22, 32, and 42. High-density oxide layers 22, 32, and 42 refer to oxide layers having a higher density than those formed by the deposition process. After the radical oxidation process, a portion of the Si-containing layers 21A and 41A or a portion of the initial buffer layers 33 and 43 can be maintained at a specific thickness. Therefore, during subsequent ion implantation processes performed under harsh conditions, the formation of microvoids in the selector pattern 123 can be prevented, and the lower electrode pattern 121 can be protected. Furthermore, during the ion implantation process, because the retained Si-containing layers 21A and 41A or the retained initial buffer layers 33 and 43 can be absorbed into the selector pattern 123, it is beneficial for the resistance control of the memory cell 120. The finally formed selector pattern 123 may include a high-density oxide layer with dopants.

[0058] Figure 1C Semiconductor devices based on some embodiments of the disclosed technology are shown.

[0059] Figure 1C The semiconductor device shown may include a memory cell 120'. The memory cell 120' may include a stacked structure comprising a lower electrode pattern 121, a buffer layer pattern 122, a selector pattern 123', an intermediate electrode pattern 125, a variable resistor pattern 127, and an upper electrode pattern 129. In addition to the memory cell including a buffer layer pattern 122 inserted between the lower electrode pattern 121 and the selector pattern 123', Figure 1C The storage cell 120' shown can be similar to Figure 1B The storage unit 120 shown will be concentrated with... Figure 1B The differences in the implementation methods shown are described. Figure 1C The implementation method shown.

[0060] The buffer layer pattern 122 can be inserted between the lower electrode pattern 121 and the selector pattern 123'. The buffer layer pattern 122 can be patterned (see...). Figure 3 (See attached figure 21B) buffer layer, (see attached figure 21B) Figure 5 (See attached figure 33A) buffer layer and (see attached figure 33A) Figure 7 The buffer layer (as indicated by reference numeral 43A) is formed. The buffer layer pattern 122 can be formed using (see attached figure 43A). Figure 3 (See attached figure 21A) containing a Si layer and (see attached figure 21A) Figure 5 Figure 33 and Figure 7The initial buffer layer (reference numeral 43) is formed and maintained at a specific thickness after the ion implantation process. In one embodiment, although a portion of the Si-containing layer 21A and portions of the initial buffer layers 33 and 43 are retained after the ion implantation process to form buffer layers 21B, 33A, and 43A respectively, the thicknesses of buffer layers 21B, 33A, and 43A can be controlled to a degree that does not affect the electrical characteristics of the memory cell 120. Therefore, the resistance of the memory cell 120' can be easily controlled as needed.

[0061] Therefore, the buffer layer pattern 122 can have a thin thickness that does not affect the electrical characteristics of the memory cell 120 when current flows. Thus, the thickness of the buffer layer pattern 122 is small enough that it is not of electrical importance. For example, the buffer layer pattern 122 can have a thickness greater than... and less than or equal to The thickness within the range.

[0062] Buffer layer pattern 122 may include an initial Si-containing layer (see...) Figure 3 The material obtained from the attached reference numeral 21) or from the initial buffer layer (see attached reference numeral 21) Figure 5 Figure 33 or Figure 7 The material obtained is shown in the attached figure (43).

[0063] In some embodiments, the buffer layer pattern 122 may include a metal-free amorphous material. In some embodiments, the buffer layer pattern 122 may include a Si-containing material or a carbon-containing material, or a combination thereof. In some embodiments, the buffer layer pattern 122 may include Si3N4, SiO2, etc. x N y WSi x CoSi x The buffer layer pattern 122 may contain Si, SiC, SiCN, amorphous Si, polycrystalline Si, or carbon, or combinations thereof. In some embodiments, the buffer layer pattern 122 may include Si-containing materials or carbon materials, or combinations thereof, without containing metals. In some embodiments, the buffer layer pattern 122 may include Si3N4, SiO2, etc. x N y The buffer layer pattern 122 may be composed of SiOC, SiC, SiCN, amorphous Si, polycrystalline Si, or carbon, or combinations thereof. In some embodiments, the buffer layer pattern 122 may include a stacked structure having a carbon-containing layer and a Si3N4-containing layer.

[0064] Reference Figure 3 , Figure 5 and Figure 7 The buffer layers 21B, 33A and 43A used to form the buffer layer pattern 122 are described in detail.

[0065] Next, refer to Figures 1A to 1C Examples of methods for manufacturing semiconductor devices are described.

[0066] refer to Figures 1A to 1C A first line 110 can be formed on a substrate 100 in which a predetermined structure is formed. The first line 110 can be formed by forming a conductive layer for forming the first line 110 and etching the conductive layer using a mask pattern of a line extending in a first direction. A material layer for forming a lower electrode pattern 121 can be formed on the first line 110. Then, one of the selector patterns 20, 20', 30, 30', 40, and 40' can be formed on the material layer for forming the lower electrode pattern 121. (Refer to...) Figure 2 , Figure 4 and Figure 6 The formation of selector patterns 20, 30, and 40 used to form selector pattern 123 is described, and references are made to... Figure 3 , Figure 5 and Figure 7 Describes the formation of selector patterns 20', 30', and 40' used to form selection pattern 123'.

[0067] Figures 2 to 7 This is a cross-sectional view illustrating an example method for forming a selector pattern based on some implementations of the disclosed technology.

[0068] refer to Figure 2 In step (a), an initial Si-containing layer 21 may be formed on the structure (not shown) (e.g., on the material layer used to form the lower electrode pattern 121).

[0069] The initial Si-containing layer 21 can be used as a Si source for the silicon oxide included in the selector pattern 123. After the radical oxidation process in step (b), a portion of the initial Si-containing layer 21 can be retained as Si-containing layer 21A. The initial Si-containing layer 21 may include a Si-containing material. The Si-containing material can be selected with consideration of desired resistance and switching characteristics.

[0070] In some embodiments, the initial Si-containing layer 21 may include Si3N4, SiO2, etc. x N y WSi x CoSi x The Si-containing layer 21 may be SiOC, SiC, SiCN, amorphous Si, or polycrystalline Si, or a combination thereof. In some embodiments, the initial Si-containing layer 21 may comprise a Si-containing material that does not contain metal. In some embodiments, the initial Si-containing layer 21 may comprise Si3N4, SiO2, etc. x N ySiOC, SiC, SiCN, amorphous Si or polycrystalline Si, or combinations thereof.

[0071] The initial Si-containing layer 21 can be formed by a deposition process (e.g., PVD process).

[0072] The initial thickness T1 of the Si-containing layer 21 can be determined by taking into account the thickness T2 of the oxide layer 22 in step (b) and the thickness T3 of the retained Si-containing layer 21A.

[0073] In step (b), the radical oxidation process can be performed on a portion having a predetermined depth from the upper surface of the initial Si-containing layer 21. Through the radical oxidation process, an oxide layer 22 comprising SiO2 can be formed. Simultaneously, a portion of the initial Si-containing layer 21 may remain unoxidized and beneath the oxide layer 22. This retained initial Si-containing layer 21 may be referred to as Si-containing layer 21A.

[0074] According to the free radical oxidation process, free radicals such as H*, O*, and OH* can be formed from H2, O2, etc., in a low-pressure, high-temperature environment or under low-pressure plasma conditions. Therefore, the reactivity with Si can be maximized, and rapid oxidation of the initial Si-containing layer 21 can be achieved, thereby forming an oxide layer 22 comprising a high-density SiO2. At this time, by controlling the degree of oxidation (e.g., the thickness of the oxide layer 22 and the thickness of the Si-containing layer 21A), the material layer used to form the lower electrode pattern 121 can be protected during subsequent ion implantation processes.

[0075] In some embodiments, the radical oxidation process can be performed using H2 and O2 gases under a high-temperature and low-pressure environment. In this environment, the temperature can be approximately 700°C or higher, and the pressure can be at a level corresponding to a high vacuum, for example, in the range of approximately 10 Torr to 0.1 Torr. For example, the upper limit of the temperature can be determined based on the specific process conditions and common knowledge known to those skilled in the art. When the radical oxidation process is not performed under these conditions, radicals such as H*, O*, OH*, etc., cannot be properly formed, and therefore the oxide layer 22 cannot be properly formed.

[0076] In some embodiments, the radical oxidation process can be performed using a cryogenic plasma process. The cryogenic plasma process can be performed using H2 and O2 gases at a pressure of approximately 10 mTorr to 10 Torr, a temperature of approximately 100°C to 500°C, and a radio frequency power of approximately 100 W to 5 kW. When the radical oxidation process is not performed under these conditions, radicals such as H*, O*, OH*, etc., cannot be suitably formed, and therefore the oxide layer 22 cannot be suitably formed.

[0077] Compared to deposited oxide layers formed by mixing source gases including Si and O2 through deposition processes such as PVD, CVD or ALD, oxide layers 22 formed by free radical oxidation processes can have relatively high density.

[0078] The thickness T2 of the oxide layer 22 can be greater than the value obtained by subtracting the thickness T3 of the Si-containing layer 21A from the thickness T1 of the initial Si-containing layer 21. Therefore, the amount of the initial Si-containing layer 21 used to form the oxide layer 22 in terms of thickness can be expressed as T1-T3. The thickness T2 of the oxide layer 22 can be greater than the thickness T1-T3 corresponding to the amount of the initial Si-containing layer 21 used to form the oxide layer 22.

[0079] At this point, the amount of the initial Si-containing layer 21 used to form the oxide layer 22 can vary depending on the materials and processes used to form the initial Si-containing layer 21. The amount of Si required to form a SiO2 layer with a predetermined thickness can be specified. The Si content in the Si-containing layer 21 can vary depending on the materials used to form the initial Si-containing layer 21. Even when using the same materials, the Si content in the initial Si-containing layer 21 can vary depending on the processes used to form the initial Si-containing layer 21. The amount of the initial Si-containing layer 21 used to form the oxide layer 22 (which can be expressed as thickness) can be calculated experimentally. Therefore, the thickness T1 of the initial Si-containing layer 21 can be determined by considering the calculated thickness of the initial Si-containing layer 21 and the thickness T3 of the Si-containing layer 21A.

[0080] Then, in step (c), the selector pattern 20 can be formed by ion implantation process, by incorporating dopant into the oxide layer 22.

[0081] Selector pattern 20 may include SiO2 with dopants. The dopants incorporated by the ion implantation process may include one or more of boron (B), nitrogen (N), carbon (C), phosphorus (P), arsenic (As), aluminum (Al), or germanium (Ge).

[0082] Ion implantation processes utilize high energy and high doses, and ions, such as arsenic (As) ions, are heavy components with large masses. Therefore, ion implantation processes are performed under harsh conditions that are difficult for material layers to withstand. However, in this embodiment, because the oxide layer 22 formed by the radical oxidation process has a relatively high density, the oxide layer 22 can withstand the harsh conditions of the ion implantation process, thereby preventing the formation of defects such as microvoids. Furthermore, the Si-containing layer 21A retained beneath the oxide layer 22 can act as a buffer to minimize damage to the lower electrode pattern 121. The Si-containing layer 21A can be completely removed during the ion implantation process and absorbed into the selector pattern 20. Therefore, the Si-containing layer 21A may not be present after the ion implantation process.

[0083] The thickness T4 of selector pattern 20 can be equal to the sum of the thickness T2 of oxide layer 22 and the thickness T3 of Si layer 21A.

[0084] Selector pattern 20 can correspond to the pattern used to form Figure 1B The selector pattern shown is the selector pattern 123.

[0085] Except that a portion of the Si-containing layer 21A was not absorbed into the selector pattern 20' and remained there during the ion implantation process. Figure 3 The method shown for forming the selector pattern 20' can be similar to Figure 2 The method shown is for forming the selector pattern 20. The focus will be on... Figure 2 The differences in the implementation methods shown are described. Figure 3 The implementation method shown.

[0086] refer to Figure 3 In step (a), an initial Si-containing layer 21 may be formed on the structure (not shown) (e.g., on the material layer used to form the lower electrode pattern 121).

[0087] In step (b), a radical oxidation process may be performed to form an oxide layer 22 comprising SiO2. A portion of the initial Si-containing layer 21 may remain unoxidized and retained below the oxide layer 22 as a Si-containing layer 21A.

[0088] In step (c), the selector pattern 20' can be formed by ion implantation, by incorporating a dopant into the oxide layer 22. At this time, a portion of the Si-containing layer 21A can be removed and absorbed into the selector pattern 20', while another portion of the Si-containing layer 21A can remain beneath the selector pattern 20'. The retained portion of the Si-containing layer 21A can be referred to as the buffer layer 21B.

[0089] The buffer layer 21B can be thin enough not to affect the electrical characteristics of the memory cell 120'. Therefore, the thickness of the buffer layer 21B is not of electrical importance. In some embodiments, the thickness T5 of the buffer layer 21B can be greater than... and less than or equal to Within the range.

[0090] Selector pattern 20' may include SiO2 with dopants. The thickness T4' of selector pattern 20' may be less than Figure 2 The thickness T4 of the selector pattern 20 shown. The sum of the thickness T4' of the selector pattern 20' and the thickness T5 of the buffer layer 21B can be equal to the sum of the thickness T2 of the oxide layer 22 and the thickness T3 of the Si-containing layer 21A.

[0091] Selector pattern 20' can correspond to the pattern used to form Figure 1C The selector pattern 123' shown is a selector pattern, and the buffer layer 21B can correspond to the selector pattern used to form... Figure 1C The buffer layer shown is the buffer layer of the buffer layer pattern 122.

[0092] In addition to the formation of an initial buffer layer 33 below the initial Si-containing layer 31, and the complete oxidation of the initial Si-containing layer 31 by the free radical oxidation process, which was not retained after the free radical oxidation process, Figure 4 The method shown for forming the selector pattern 30 can be similar to Figure 2 The method shown is for forming the selector pattern 20. The focus will be on... Figure 2 The differences in the implementation methods shown are described. Figure 4 The implementation method shown.

[0093] refer to Figure 4 In step (a), an initial buffer layer 33 and an initial Si-containing layer 31 may be sequentially formed on a structure (not shown) (e.g., on a material layer used to form the lower electrode pattern 121).

[0094] The initial buffer layer 33 can be used to protect the lower electrode pattern 121 and prevent damage to it during the ion implantation process in subsequent step (c). In some embodiments, the initial buffer layer 33 may comprise a metal-free amorphous material. In some embodiments, the initial buffer layer 33 may comprise Si3N4 or carbon, or a combination thereof. In some embodiments, the initial buffer layer 33 may comprise a stacked structure of a carbon-containing layer and a Si3N4-containing layer.

[0095] The initial thickness T6 of the Si layer 31 can be determined by taking into account the thickness T8 of the oxide layer 32.

[0096] In step (b), a free radical oxidation process can be performed to transform the entire initial Si-containing layer 31 into an oxide layer 32 comprising SiO2. The initial buffer layer 33 can be completely retained beneath the oxide layer 32.

[0097] All of the initial Si-containing layer 31 can be used to form the oxide layer 32. Therefore, after the free radical oxidation process, the initial Si-containing layer 31 may not exist.

[0098] The thickness T8 of the oxide layer 32 can be greater than the thickness T6 of the initial Si-containing layer 31.

[0099] In step (c), the selector pattern 30 can be formed by ion implantation, by incorporating a dopant into the oxide layer 32. At this time, because the initial buffer layer 33 can act as a buffer during the ion implantation process, damage to the lower electrode pattern 121 can be minimized. The initial buffer layer 33 can be removed during the ion implantation process and absorbed into the selector pattern 30. Therefore, the initial buffer layer 33 may not be present after the ion implantation process.

[0100] Selector pattern 30 may include SiO2 with dopants. The thickness T9 of selector pattern 30 may be equal to the sum of the thickness T8 of oxide layer 32 and the thickness T7 of initial buffer layer 33.

[0101] Selector pattern 30 can correspond to the pattern used to form Figure 1B The selector pattern shown is the selector pattern 123.

[0102] Except that a portion of the initial buffer layer 33 is not absorbed into the selector pattern 30' and is retained during the ion implantation process. Figure 5 The method shown for forming the selector pattern 30' can be similar to Figure 4 The method shown is for forming the selector pattern 30. The focus will be on... Figure 4 The differences in the implementation methods shown are described. Figure 5 The implementation method shown.

[0103] refer to Figure 5 In step (a), an initial buffer layer 33 and an initial Si-containing layer 31 may be sequentially formed on a structure (not shown) (e.g., on a material layer used to form the lower electrode pattern 121).

[0104] In step (b), a free radical oxidation process can be performed to transform the entire initial Si-containing layer 31 into an oxide layer 32 comprising SiO2. The initial buffer layer 33 can be completely retained beneath the oxide layer 32.

[0105] In step (c), the selector pattern 30' can be formed by ion implantation, by incorporating a dopant into the oxide layer 32. At this time, a portion of the initial buffer layer 33 can be removed and absorbed into the selector pattern 30', while another portion of the initial buffer layer 33 can remain beneath the selector pattern 30'. The retained portion of the initial buffer layer 33 can be referred to as buffer layer 33A.

[0106] The buffer layer 33A can be thin enough not to affect the electrical characteristics of the memory cell 120'. Therefore, the thickness of the buffer layer 33A is not of electrical importance. In some embodiments, the thickness T10 of the buffer layer 33A can be greater than... and less than or equal to Within the range.

[0107] Selector pattern 30' may include SiO2 with dopants. The thickness T9' of selector pattern 30' may be less than Figure 4 The thickness T9 of the selector pattern 30 shown. The sum of the thickness T9' of the selector pattern 30' and the thickness T10 of the buffer layer 33A can be equal to the sum of the thickness T8 of the layer 32 and the thickness T7 of the initial buffer layer 33.

[0108] Selector pattern 30' can correspond to the pattern used to form Figure 1C The selector pattern 123' shown is a selector pattern, and the buffer layer 33A can correspond to the selector pattern used to form... Figure 1C The buffer layer shown is the buffer layer of the buffer layer pattern 122.

[0109] In addition to forming an initial buffer layer 43 below the initial Si-containing layer 41, Figure 6 The method shown for forming the selector pattern 40 can be similar to Figure 2 The method shown is for forming the selector pattern 20. The focus will be on... Figure 2 The differences in the implementation methods shown are described. Figure 6 The implementation method shown.

[0110] refer to Figure 6 In step (a), an initial buffer layer 43 and an initial Si-containing layer 41 may be sequentially formed on a structure (not shown) (e.g., on a material layer used to form the lower electrode pattern 121).

[0111] The initial buffer layer 43 can be used to protect the lower electrode pattern 121 and prevent damage to it during the ion implantation process in subsequent step (c). In some embodiments, the initial buffer layer 43 may comprise a metal-free amorphous material. In some embodiments, the initial buffer layer 43 may comprise Si3N4 or carbon, or a combination thereof. In some embodiments, the initial buffer layer 43 may comprise a stacked structure containing carbon layers and Si3N4 layers.

[0112] The initial thickness T11 of the Si-containing layer 41 can be determined by taking into account the thickness T13 of the oxide layer 42 and the thickness T14 of the Si-containing layer 41A.

[0113] In step (b), a free radical oxidation process can be performed to transform a portion of the initial Si-containing layer 41 into an oxide layer 42 comprising SiO2. At this time, another portion of the initial Si-containing layer 41 may remain unoxidized. This retained portion of the initial Si-containing layer 41 may be referred to as Si-containing layer 41A. The initial buffer layer 43 may be completely retained beneath Si-containing layer 41A.

[0114] The thickness T13 of the oxide layer 42 can be greater than the thickness T11 of the initial Si-containing layer 41.

[0115] In step (c), the selector pattern 40 can be formed by ion implantation, by incorporating dopant into the oxide layer 42. At this time, because the Si-containing layer 41A and the initial buffer layer 43 can act as buffers during the ion implantation process, damage to the lower electrode pattern 121 can be minimized. The Si-containing layer 41A and the initial buffer layer 43 can be completely removed and absorbed into the selector pattern 40 during the ion implantation process. Therefore, the Si-containing layer 41A and the initial buffer layer 43 may not be present after the ion implantation process.

[0116] Selector pattern 40 may include SiO2 with dopants. The thickness T15 of selector pattern 40 may be equal to the sum of the thickness T13 of oxide layer 42, the thickness T14 of Si layer 41A, and the thickness T12 of initial buffer layer 43.

[0117] Selector pattern 40 can correspond to the pattern used to form Figure 1B The selector pattern shown is the selector pattern 123.

[0118] Except that a portion of the initial buffer layer 43 is not absorbed into the selector pattern 40' and remains there during the ion implantation process. Figure 7 The method shown for forming the selector pattern 40' can be similar to Figure 6 The method shown is for forming the selector pattern 40. The focus will be on... Figure 6 The differences in the implementation methods shown are described. Figure 7 The implementation method shown.

[0119] refer to Figure 7 In step (a), an initial buffer layer 43 and an initial Si-containing layer 41 may be sequentially formed on a structure (not shown) (e.g., on a material layer used to form the lower electrode pattern 121).

[0120] In step (b), a free radical oxidation process can be performed to transform a portion of the initial Si-containing layer 41 into an oxide layer 42 comprising SiO2. At this time, another portion of the initial Si-containing layer 41 may remain unoxidized and retained beneath the oxide layer 42. This retained portion of the initial Si-containing layer 41 may be referred to as Si-containing layer 41A. The initial buffer layer 43 may be completely retained beneath Si-containing layer 41A.

[0121] The thickness T13 of the oxide layer 42 can be greater than the thickness T11 of the initial Si-containing layer 41.

[0122] In step (c), the selector pattern 40 can be formed by ion implantation, by incorporating a dopant into the oxide layer 42. At this time, because the Si-containing layer 41A and the initial buffer layer 43 can act as buffers during the ion implantation process, damage to the lower electrode pattern 121 can be minimized. The Si-containing layer 41A can be completely removed and absorbed into the selector pattern 40' during the ion implantation process. A portion of the initial buffer layer 43 can be removed and absorbed into the selector pattern 40' during the ion implantation process, while another portion of the initial buffer layer 43 can remain below the selector pattern 40' during the ion implantation process. The retained portion of the initial buffer layer 43 can be referred to as buffer layer 43A.

[0123] The buffer layer 43A can be thin enough not to affect the electrical characteristics of the memory cell 120'. Therefore, the thickness of the buffer layer 43A is not of electrical importance. In some embodiments, the thickness T16 of the buffer layer 43A can be greater than... and less than or equal to Within the range.

[0124] Selector pattern 40' may include SiO2 with dopants. The thickness T15' of selector pattern 40' may be less than the thickness T15 of selector pattern 40. The sum of the thickness T15' of selector pattern 40' and the thickness T16 of buffer layer 43A may be equal to the sum of the thickness T13 of oxide layer 42, the thickness T14 of Si-containing layer 41A and the thickness T12 of initial buffer layer 43.

[0125] Selector pattern 40 can correspond to the pattern used to form Figure 1B The selector pattern shown is the selector pattern 123.

[0126] Selector pattern 40' can correspond to the pattern used to form Figure 1C The selector pattern 123' shown is a selector pattern, and the buffer layer 43A can correspond to the selector pattern used to form... Figure 1C The buffer layer shown is the buffer layer of the buffer layer pattern 122.

[0127] exist Figure 7 In the illustrated embodiment, the Si-containing layer 41A is not retained after the ion implantation process. In some embodiments, a portion of the Si-containing layer 41A may be retained on the buffer layer 43A during the ion implantation process. In some embodiments, the Si-containing layer 41A and the buffer layer 43A may be retained below the selector pattern 40'.

[0128] Go back for reference Figures 1A to 1CThe memory cell 120 or 120' can be formed by the following steps: sequentially forming a material layer for forming the reserved portion (e.g., elements 125, 127, and 129) of the memory cell 120 or 120' on a selector pattern for forming the selector pattern 123 or 123'; and etching the material layer for forming the reserved portion (e.g., elements 125, 127, and 129), the selector pattern for forming the selector pattern 123, and the material layer for forming the lower electrode pattern 121 using a mask pattern. Then, the second line 150 can be formed by the following steps: forming a conductive layer for forming the second line 150 on the memory cell 120 or 120'; and etching the conductive layer using a mask pattern employing a line shape extending in a second direction. The space between the first line 110, the memory cell 120, and the second line 150 can be filled with a dielectric material.

[0129] Figures 8A to 8F This is a cross-sectional view illustrating examples of semiconductor devices and manufacturing methods thereof based on some embodiments of the disclosed technology.

[0130] refer to Figure 8A The first line 210 can be formed on a substrate 200 in which a predetermined structure is formed. The first line 110 can be formed by forming a conductive layer for forming the first line 110 and etching the conductive layer using a mask pattern of a line extending in a first direction.

[0131] The memory cell 220 can be formed by forming a material layer for forming the memory cell 220 and etching the material layer using a mask pattern. The memory cell 220 may include a lower electrode pattern 221, a selector pattern 223, an intermediate electrode pattern 225, a variable resistor pattern 227, and an upper electrode pattern 229.

[0132] refer to Figure 8B The initial capping layer 51 can be Figure 8A It is formed in a conformal manner on the structure.

[0133] The initial capping layer 51 may include a Si-containing material. For example, the initial capping layer 51 may include Si3N4, SiO2, etc. x N y WSi x CoSi x SiOC, SiC, SiCN, amorphous Si or polycrystalline Si, or combinations thereof.

[0134] The thickness T17 of the initial capping layer 51 can be considered for a second capping layer (see...). Figure 8C The thickness T18 of the figure (reference numeral 52) and the first capping layer (see Figure 52) Figure 8C The thickness T19 is determined by the reference numeral 51A in the attached figure.

[0135] refer to Figure 8C A free radical oxidation process can be performed to transform a portion of the initial capping layer 51 into a second capping layer 52 comprising SiO2. At this time, another portion of the initial capping layer 51 may remain unoxidized. The retained portion of the initial capping layer 51 may be referred to as the first capping layer 51A. The first capping layer 51A may be configured to cover the exposed surfaces of the memory cell 220 and the first line 210. The second capping layer 52 may be configured to cover the first capping layer 51A. Details of the free radical oxidation process can be similar to those in the reference. Figures 1A to 7 Those described.

[0136] According to these embodiments, a double-layer structure is formed, comprising a first capping layer 51A containing Si and a second capping layer 52 containing high-density SiO2. The double-layer structure can reduce stress on the memory cell 220, minimize the intrusion of various elements that can affect the memory cell 220, and protect the memory cell 220.

[0137] In some embodiments, the second capping layer 52 may include SiO2, and the first capping layer 51A may include Si3N4.

[0138] The thickness T18 of the second capping layer 52 can be greater than the thickness T17 of the initial capping layer 51.

[0139] In some embodiments, the thickness T19 of the first capping layer 51A may be greater than 0 and less than or equal to 20% of the thickness T18 of the second capping layer 52.

[0140] refer to Figure 8D The interlayer dielectric layer 240 can be Figure 8C The structure is formed on the interlayer dielectric layer 240. An interlayer dielectric layer 240 can be formed to fill the space between the memory cells 220 and cover the top of the memory cells 220. The interlayer dielectric layer 240 can have a single-layer or multi-layer structure comprising various dielectric materials (e.g., silicon oxide, silicon nitride, or combinations thereof).

[0141] refer to Figure 8E A planarization process, such as chemical mechanical polishing (CMP), can be performed until the top surface of the memory cell 220 is exposed.

[0142] refer to Figure 8F The second line 250 can be formed by the following steps: forming a conductive layer for the second line 250 on the memory cell 220; and etching the conductive layer by using a mask pattern of a line extending in a second direction. The space between the second lines 250 can be filled with a dielectric material.

[0143] The semiconductor device may include a first line 210, a memory cell 220, and a second line 250. The memory cell 220 may include a bottom electrode pattern 221, a selector pattern 223, an intermediate electrode pattern 225, a variable resistor pattern 227, and an upper electrode pattern 229, which are sequentially stacked. The semiconductor device may also include a first capping layer 51A and a second capping layer 52. The first capping layer 51A may be formed on the sidewalls of the memory cell 220 and on the exposed top surface of the first line 210, and the second capping layer 52 may be formed on the first capping layer 51A. The bilayer structure including a first capping layer 51A containing Si and a second capping layer 52 containing high-density SiO2 can alleviate stress on the memory cell 220, minimize the intrusion of various elements affecting the memory cell 220, and protect the memory cell 220.

[0144] In one embodiment, a portion of the initial capping layer 51 may be retained as a first capping layer 51A after the radical oxidation process. In some embodiments, the initial capping layer 51 may be completely oxidized and not retained during the radical oxidation process. Even if the first capping layer 51A is absent, the second capping layer 52, having a relatively high density, can still provide sufficient protection for the memory cell 220.

[0145] While this patent document contains many specific specifications for semiconductor devices, it should not be construed as limiting the scope of any disclosure or claim, but rather as a description of features that may be specifically used for particular embodiments of a particular disclosure. Some features described in the context of separate embodiments in this patent document may be implemented in combination in a single embodiment. Conversely, some features described in the context of a single embodiment may also be implemented individually or in certain suitable sub-combinations in multiple embodiments. Furthermore, while individual features may have been described above in certain combinations, one or more features derived from the combination may be removed from the combination in some cases.

[0146] Similarly, although the various operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown, or sequentially, or requiring the performance of all the shown operations to obtain the desired result. Furthermore, the separation of the various system components in the embodiments described in this patent document should not be construed as requiring such separation in all embodiments.

[0147] Only a few embodiments and examples have been described. Various modifications, variations, and other embodiments of the disclosed embodiments can be implemented based on what is described and shown in this patent document.

Claims

1. A method for manufacturing a semiconductor device comprising a plurality of memory cells, the method comprising: Form the first electrode layer; An initial Si-containing layer is formed on the first electrode layer; Performing a free radical oxidation process to transform a first portion of the initial Si-containing layer into an oxide layer comprising silicon oxide, and forming a Si-containing layer beneath the oxide layer by using a second portion of the initial Si-containing layer; and Dopant is incorporated into the oxide layer using an ion implantation process to form a selector pattern.

2. The method according to claim 1, wherein, The initial Si-containing layer thickness is determined by taking into account the thickness of the oxide layer and the thickness of the Si-containing layer.

3. The method according to claim 1, wherein, The initial Si-containing layer includes Si3N4 and SiO. x N y WSi x CoSi x SiOC, SiC, SiCN, amorphous Si or polycrystalline Si, or combinations thereof.

4. The method according to claim 1, wherein, The free radical oxidation process is performed via a low-temperature plasma process at a pressure of 10 mTorr to 10 Torr, a temperature of 100°C to 500°C, and a radio frequency power of 100 W to 5 kW, or via the use of H2 and O2 gases at a temperature of 700°C or higher and a pressure of 10 Torr to 0.1 Torr.

5. The method according to claim 1, wherein, The thickness of the oxide layer is greater than the value obtained by subtracting the thickness of the Si-containing layer from the thickness of the initial Si-containing layer.

6. The method according to claim 1, wherein, The dopant includes one or more of boron, nitrogen, carbon, phosphorus, arsenic, aluminum, or germanium.

7. The method according to claim 1, wherein, The Si-containing layer is completely removed during the ion implantation process and absorbed into the selector pattern.

8. The method according to claim 1, wherein, During the ion implantation process, a portion of the Si-containing layer is removed and absorbed into the selector pattern, while another portion of the Si-containing layer remains below the selector pattern as a buffer layer pattern.

9. The method according to claim 8, wherein, The buffer layer has a thickness in the range of greater than 0 Å and less than or equal to 10 Å.

10. A method for manufacturing a semiconductor device comprising a plurality of memory cells, the method comprising: A first electrode layer is formed on the substrate; An initial buffer layer is formed on the first electrode layer; An initial Si-containing layer is formed on the initial buffer layer; Performing a free radical oxidation process to form an oxide layer comprising SiO2, the oxide layer being derived from at least a portion of the initial Si-containing layer and any retained portion of the initial Si-containing layer forming the Si-containing layer; and Dopant is incorporated into the oxide layer using an ion implantation process to form a selector pattern.

11. The method according to claim 10, wherein, The initial Si-containing layer includes Si3N4 and SiO. x N y WSi x CoSi x SiOC, SiC, SiCN, amorphous Si or polycrystalline Si, or combinations thereof.

12. The method according to claim 10, wherein, The free radical oxidation process is performed via a low-temperature plasma process at a pressure of 10 mTorr to 10 Torr, a temperature of 100°C to 500°C, and a radio frequency power of 100 W to 5 kW, or via the use of H2 and O2 gases at a temperature of 700°C or higher and a pressure of 10 Torr to 0.1 Torr.

13. The method according to claim 10, wherein, The dopant includes one or more of boron, nitrogen, carbon, phosphorus, arsenic, aluminum, or germanium.

14. The method of claim 10, wherein, The Si-containing layer is completely removed during the ion implantation process and absorbed into the selector pattern.

15. The method according to claim 10, wherein, During the ion implantation process, a portion of the initial buffer layer is removed and absorbed into the selector pattern, while another portion of the initial buffer layer remains as a buffer layer beneath the selector pattern or the Si-containing layer; or the initial buffer layer is completely removed and absorbed into the selector pattern.

16. The method according to claim 15, wherein, The buffer layer has a thickness in the range of greater than 0 Å and less than or equal to 10 Å.

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