Phase change memory device and method of manufacturing the same

Abstract

The present disclosure relates to a phase change memory device and a method of fabricating the same. The phase change memory device includes a memory cell including: a conductive portion; a first electrode layer including a first portion disposed under a first portion of the conductive portion and a second portion disposed above the first portion of the conductive portion, the first portion and the second portion of the first electrode layer contacting to surround the first portion of the conductive portion and electrically connected with the first portion of the conductive portion; a phase change material layer including a first portion disposed under the first portion of the first electrode layer and a second portion disposed above the second portion of the first electrode layer, the first portion and the second portion of the phase change material layer contacting to surround the first electrode layer; and a second electrode layer including a first portion disposed under the first portion of the phase change material layer and a second portion disposed above the second portion of the phase change material layer, the first portion and the second portion of the second electrode layer contacting to surround the phase change material layer.

Description

Technical Field

[0001] This disclosure generally relates to the semiconductor field, and more specifically, to phase-change memory devices and methods for their fabrication. Background Technology

[0002] Phase-change memory (PCM), as a type of non-volatile memory, uses the difference in conductivity exhibited by materials when they transform between crystalline and amorphous states to store data. It has excellent characteristics such as no data loss when power is off, low power consumption, high read and write speed, and high integration. Furthermore, it is compatible with complementary metal-oxide-semiconductor (CMOS) technology and is expected to replace current mainstream products such as static random access memory (SRAM), dynamic random access memory (DRAM), and flash memory as the mainstream commercial product in the future. Summary of the Invention

[0003] According to one aspect of this disclosure, a phase change storage device is provided, including a storage cell, the storage cell comprising: a conductive portion; a first electrode layer including a first portion disposed below a first portion of the conductive portion and a second portion disposed above the first portion of the conductive portion, the first portion and the second portion of the first electrode layer contacting each other to surround and be electrically connected to the first portion of the conductive portion; a phase change material layer including a first portion disposed below the first portion of the first electrode layer and a second portion disposed above the second portion of the first electrode layer, the first portion and the second portion of the phase change material layer contacting each other to surround the first electrode layer; and a second electrode layer including a first portion disposed below the first portion of the phase change material layer and a second portion disposed above the second portion of the phase change material layer, the first portion and the second portion of the second electrode layer contacting each other to surround the phase change material layer.

[0004] In some embodiments, the angle between the side surface and the bottom surface of the conductive part is not greater than 90 degrees.

[0005] In some embodiments, the phase change memory device satisfies at least one of the following: the conductive portion comprises a metal; the first electrode layer and the second electrode layer each comprise titanium nitride; and the phase change material layer comprises a ferroelectric material.

[0006] In some embodiments, the conductive portion further includes a second portion on which the first electrode layer, the phase change material layer, and the second electrode layer are not disposed, the second portion of the conductive portion being electrically connected to the first portion of the conductive portion and thus electrically connected to the first electrode layer, and the phase change storage device further includes: a first dielectric layer on which the storage cell is disposed; and a second dielectric layer above the first dielectric layer on which the storage cell is covered, wherein the first dielectric layer includes a first conductive via electrically connected to a first portion of the second electrode layer, and the second dielectric layer includes a second conductive via electrically connected to a second portion of the conductive portion.

[0007] In some embodiments, the first conductive via is located below the first portion of the conductive part, the second conductive via is located above the second portion of the conductive part, and the first conductive via is laterally offset from the second conductive via.

[0008] In some embodiments, the phase-change memory device includes a plurality of memory cells disposed on the first dielectric layer and covered by the second dielectric layer.

[0009] In some embodiments, the thickness of the stack of the second portion of the first electrode layer, the second portion of the phase change material layer, and the second portion of the second electrode layer of the memory cell is the effective cell thickness of the memory cell, and wherein the spacing between the conductive portions of two adjacent memory cells in the plurality of memory cells exceeds twice the effective cell thickness.

[0010] In some embodiments, the first dielectric layer includes a plurality of first conductive vias corresponding to the plurality of memory cells, and the second dielectric layer includes a plurality of second conductive vias corresponding to the plurality of memory cells, wherein each of the plurality of memory cells is electrically connected to a corresponding first conductive via via a first portion of its second electrode layer, and is electrically connected to a corresponding second conductive via via a second portion of its conductive portion.

[0011] In some embodiments, the second dielectric layer includes a plurality of second conductive vias corresponding to the plurality of memory cells, wherein a first portion of the second electrode layer of each of the plurality of memory cells is electrically connected to each other and is commonly electrically connected to the first conductive via in the first dielectric layer, and wherein each of the plurality of memory cells is electrically connected to a corresponding second conductive via via a second portion of its conductive portion.

[0012] In some embodiments, the first dielectric layer includes a plurality of first conductive vias corresponding to the plurality of memory cells, wherein each of the plurality of memory cells is electrically connected to a corresponding first conductive via via a first portion of its second electrode layer, and wherein the second portions of the conductive portions of each of the plurality of memory cells are electrically connected to each other and are collectively electrically connected to the second conductive via in the second dielectric layer.

[0013] According to another aspect of this disclosure, a method for fabricating a phase change memory device is provided, the phase change memory device including a memory cell, the method comprising forming the memory cell of the phase change memory device by: forming a first electrode material layer; forming a first phase change material layer over the first electrode material layer; forming a second electrode material layer over the first phase change material layer; forming a conductive material layer over the second electrode material layer and etching the conductive material layer to form a conductive portion; forming a third electrode material layer over a first portion of the conductive portion, the third electrode material layer contacting the second electrode material layer to surround and electrically connect to the first portion of the conductive portion, and etching the third electrode material layer and the second electrode material layer to remove a region of each of the portion of the third electrode material layer not located above the first portion of the conductive portion and the portion of the second electrode material layer not located below the conductive portion, which extends from the conductive portion beyond the thickness of the third electrode material layer; forming a second phase change material layer over the third electrode layer, the second phase change material layer contacting the first phase change material layer to surround the first portion of the conductive portion. The process involves: surrounding the etched third electrode material layer and the etched second electrode material layer; forming a fourth electrode material layer on top of the second phase change material layer; and etching the fourth electrode material layer, the second phase change material layer, the first phase change material layer, and the first electrode material layer to remove the portion of the fourth electrode material layer not located above the first portion of the conductive portion, the portion of the second phase change material layer not located above the first portion of the conductive portion, the portion of the first phase change material layer not located below the conductive portion, and the portion of the first electrode material layer not located below the conductive portion, each of which is located beyond the effective cell thickness of the memory cell from the conductive portion, the effective cell thickness being the thickness of the stack of the third electrode material layer, the second phase change material layer, and the fourth electrode material layer; and forming a fifth electrode material layer on top of the fourth electrode material layer, and etching the fifth electrode material layer such that the etched fifth electrode material layer contacts both the etched first electrode material layer and the etched fourth electrode material layer to surround the etched first phase change material layer and the etched second phase change material layer.

[0014] In some embodiments, the conductive portion is formed such that the angle between the side surface and the bottom surface of the conductive portion is no greater than 90 degrees.

[0015] In some embodiments, the method satisfies at least one of the following: the conductive material layer comprises a metal; the first electrode material layer, the second electrode material layer, the third electrode material layer, the fourth electrode material layer, and the fifth electrode material layer each comprise titanium nitride; and the first phase change material layer and the second phase change material layer each comprise a ferroelectric material.

[0016] In some embodiments, after etching the conductive material layer to form the conductive portion and before forming the third electrode material layer, the method further includes: continuing to etch the second electrode material layer to remove the portion of the second electrode material layer that is not located below the conductive portion, wherein, after forming the third electrode material layer and before forming the second phase change material layer, only the third electrode material layer is etched without etching the second electrode material layer.

[0017] In some embodiments, before forming the memory cell, the method further includes: forming a first dielectric layer and forming a first conductive via in the first dielectric layer, wherein the memory cell is disposed on the first dielectric layer, and a portion of the first electrode material layer located below the conductive portion is electrically connected to the first conductive via; and after forming the memory cell, the method further includes: forming a second dielectric layer covering the memory cell and forming a second conductive via in the second dielectric layer, wherein the conductive portion further includes a second portion on which the third electrode material layer, the second phase change material layer, the fourth electrode material layer, and the fifth electrode material layer are not disposed, and the second portion of the conductive portion is electrically connected to the first portion of the conductive portion and electrically connected to the second conductive via.

[0018] In some embodiments, the first conductive via is located below the first portion of the conductive part, the second conductive via is located above the second portion of the conductive part, and the first conductive via is laterally offset from the second conductive via.

[0019] In some embodiments, the method further includes forming a plurality of the memory cells disposed on the first dielectric layer and covered by the second dielectric layer.

[0020] In some embodiments, etching the conductive material layer to form a conductive portion includes etching the conductive material layer to form a plurality of conductive portions, wherein forming the third electrode material layer includes forming a third electrode material layer over a first portion of each of the plurality of conductive portions, the third electrode material layer contacting a second electrode material layer to respectively surround the first portion of each of the plurality of conductive portions, and etching the third electrode material layer and the second electrode material layer to remove a region of each of the portions of the third electrode material layer not located above the first portion of each of the plurality of conductive portions and the portions of the second electrode material layer not located below the conductive portion that extends beyond the thickness of the third electrode material layer from the conductive portion, and wherein each of the plurality of conductive portions and the portions of each of the first electrode material layer, the first phase change material layer, the second electrode material layer, the third electrode material layer, the second phase change material layer, the fourth electrode material layer, and the fifth electrode material layer surrounding the conductive portion form a corresponding memory cell among the plurality of memory cells.

[0021] In some embodiments, the spacing between two adjacent conductive portions of the plurality of conductive portions exceeds twice the thickness of the effective unit.

[0022] In some embodiments, forming a first conductive via in the first dielectric layer includes forming a plurality of first conductive vias corresponding to the plurality of memory cells in the first dielectric layer, and forming a second conductive via in the second dielectric layer includes forming a plurality of second conductive vias corresponding to the plurality of memory cells in the second dielectric layer, wherein each of the plurality of memory cells is electrically connected to a corresponding first conductive via via a portion of the first electrode material layer located below a first portion of the conductive portion of the memory cell, and is electrically connected to a corresponding second conductive via via a second portion of the conductive portion of the memory cell.

[0023] In some embodiments, forming a second conductive via in the second dielectric layer includes forming a plurality of second conductive vias corresponding to the plurality of memory cells in the second dielectric layer, wherein the portion of the first electrode material layer located below a first portion of the conductive portion of each of the plurality of memory cells is electrically connected to each other and is commonly electrically connected to the first conductive via in the first dielectric layer, and wherein each of the plurality of memory cells is electrically connected to a corresponding second conductive via via a second portion of the conductive portion of the memory cell.

[0024] In some embodiments, forming a first conductive via in the first dielectric layer includes forming a plurality of first conductive vias corresponding to the plurality of memory cells in the first dielectric layer, wherein each of the plurality of memory cells is electrically connected to a corresponding first conductive via via a portion of the first electrode material layer located below a first portion of the conductive portion of the memory cell, and wherein a second portion of the conductive portion of each of the plurality of memory cells is electrically connected to each other and is jointly electrically connected to the second conductive via in the second dielectric layer.

[0025] According to another aspect of this disclosure, a phase change storage device is provided, including a storage cell, the storage cell comprising: a conductive portion serving as a first electrode layer; a phase change material layer including a first portion disposed below the first portion of the conductive portion and a second portion disposed above the first portion of the conductive portion, the first portion and the second portion of the phase change material layer contacting each other to surround the first portion of the conductive portion; and a second electrode layer including a first portion disposed below the first portion of the phase change material layer and a second portion disposed above the second portion of the phase change material layer, the first portion and the second portion of the second electrode layer contacting each other to surround the phase change material layer.

[0026] In some embodiments, the angle between the side surface and the bottom surface of the conductive part is not greater than 90 degrees.

[0027] In some embodiments, the phase change memory device satisfies at least one of the following: the conductive portion and the second electrode layer each comprise titanium nitride; the phase change material layer comprises a ferroelectric material.

[0028] In some embodiments, the conductive portion further includes a second portion on which the phase change material layer and the second electrode layer are not disposed, the second portion of the conductive portion being electrically connected to the first portion of the conductive portion, and the phase change storage device further includes: a first dielectric layer on which the storage cell is disposed; and a second dielectric layer above the first dielectric layer on which the storage cell is covered, wherein the first dielectric layer includes a first conductive via electrically connected to a first portion of the second electrode layer, and the second dielectric layer includes a second conductive via electrically connected to a second portion of the conductive portion.

[0029] In some embodiments, the first conductive via is located below the first portion of the conductive part, the second conductive via is located above the second portion of the conductive part, and the first conductive via is laterally offset from the second conductive via.

[0030] In some embodiments, the phase-change memory device includes a plurality of memory cells disposed on the first dielectric layer and covered by the second dielectric layer.

[0031] In some embodiments, the thickness of the stack of the second portion of the phase change material layer and the second portion of the second electrode layer of the memory cell is the effective cell thickness of the memory cell, and wherein the spacing between the conductive portions of two adjacent memory cells in the plurality of memory cells exceeds twice the effective cell thickness.

[0032] In some embodiments, the first dielectric layer includes a plurality of first conductive vias corresponding to the plurality of memory cells, and the second dielectric layer includes a plurality of second conductive vias corresponding to the plurality of memory cells, wherein each of the plurality of memory cells is electrically connected to a corresponding first conductive via via a first portion of its second electrode layer, and is electrically connected to a corresponding second conductive via via a second portion of its conductive portion.

[0033] In some embodiments, the second dielectric layer includes a plurality of second conductive vias corresponding to the plurality of memory cells, wherein a first portion of the second electrode layer of each of the plurality of memory cells is electrically connected to each other and is commonly electrically connected to the first conductive via in the first dielectric layer, and wherein each of the plurality of memory cells is electrically connected to a corresponding second conductive via via a second portion of its conductive portion.

[0034] In some embodiments, the first dielectric layer includes a plurality of first conductive vias corresponding to the plurality of memory cells, wherein each of the plurality of memory cells is electrically connected to a corresponding first conductive via via a first portion of its second electrode layer, and wherein the second portions of the conductive portions of each of the plurality of memory cells are electrically connected to each other and are collectively electrically connected to the second conductive via in the second dielectric layer.

[0035] According to another aspect of this disclosure, a method for fabricating a phase-change memory device is provided, the phase-change memory device including a memory cell, the method comprising forming the memory cell of the phase-change memory device by: forming a first electrode material layer; forming a first phase-change material layer over the first electrode material layer; forming a conductive material layer over the first phase-change material layer and etching the conductive material layer to form a conductive portion, the conductive portion serving as an electrode of the memory cell; forming a second phase-change material layer over a first portion of the conductive portion, the second phase-change material layer contacting the first phase-change material layer to surround the first portion of the conductive portion; forming a second electrode material layer over the second phase-change material layer and etching the second electrode material layer, the second phase-change material layer, the first phase-change material layer, and the first electrode material layer to deposit the memory cell into the memory cell. The portion of the second electrode material layer not located above the first portion of the conductive portion, the portion of the second phase change material layer not located above the first portion of the conductive portion, the portion of the first phase change material layer not located below the conductive portion, and the portion of the first electrode material layer not located below the conductive portion are all removed from the region of the conductive portion that exceeds the effective cell thickness of the memory cell, the effective cell thickness being the thickness of the stack of the second phase change material layer and the second electrode material layer; and a third electrode material layer is formed on the second electrode material layer and etched such that the etched third electrode material layer contacts both the etched first electrode material layer and the etched second electrode material layer to surround the etched first phase change material layer and the etched second phase change material layer.

[0036] In some embodiments, the conductive portion is formed such that the angle between the side surface and the bottom surface of the conductive portion is no greater than 90 degrees.

[0037] In some embodiments, the method satisfies at least one of the following: the conductive material layer, the first electrode material layer, the second electrode material layer, and the third electrode material layer each comprise titanium nitride; the first phase change material layer and the second phase change material layer each comprise a ferroelectric material.

[0038] In some embodiments, before forming the memory cell, the method further includes: forming a first dielectric layer and forming a first conductive via in the first dielectric layer, wherein the memory cell is disposed on the first dielectric layer, and a portion of the first electrode material layer located below the conductive portion is electrically connected to the first conductive via; and wherein, after forming the memory cell, the method further includes: forming a second dielectric layer covering the memory cell and forming a second conductive via in the second dielectric layer, wherein the conductive portion further includes a second portion on which the second phase change material layer, the second electrode material layer, and the third electrode material layer are not disposed, and the second portion of the conductive portion is electrically connected to the first portion of the conductive portion and electrically connected to the second conductive via.

[0039] In some embodiments, the first conductive via is located below the first portion of the conductive part, the second conductive via is located above the second portion of the conductive part, and the first conductive via is laterally offset from the second conductive via.

[0040] In some embodiments, the method further includes forming a plurality of the memory cells disposed on the first dielectric layer and covered by the second dielectric layer.

[0041] In some embodiments, etching the conductive material layer to form a conductive portion includes etching the conductive material layer to form a plurality of conductive portions, wherein forming the second phase change material layer includes forming the second phase change material layer over a first portion of each of the plurality of conductive portions, the second phase change material layer contacting the first phase change material layer to respectively surround the first portion of each of the plurality of conductive portions, and wherein each of the plurality of conductive portions and the portion of each of the first electrode material layer, the first phase change material layer, the second phase change layer, the second electrode material layer, and the third electrode material layer surrounding the conductive portion forms a corresponding memory cell among the plurality of memory cells.

[0042] In some embodiments, the spacing between two adjacent conductive portions of the plurality of conductive portions exceeds twice the thickness of the effective unit.

[0043] In some embodiments, forming a first conductive via in the first dielectric layer includes forming a plurality of first conductive vias corresponding to the plurality of memory cells in the first dielectric layer, and forming a second conductive via in the second dielectric layer includes forming a plurality of second conductive vias corresponding to the plurality of memory cells in the second dielectric layer, wherein each of the plurality of memory cells is electrically connected to a corresponding first conductive via via a portion of the first electrode material layer located below a first portion of the conductive portion of the memory cell, and is electrically connected to a corresponding second conductive via via a second portion of the conductive portion of the memory cell.

[0044] In some embodiments, forming a second conductive via in the second dielectric layer includes forming a plurality of second conductive vias corresponding to the plurality of memory cells in the second dielectric layer, wherein the portion of the first electrode material layer located below a first portion of the conductive portion of each of the plurality of memory cells is electrically connected to each other and is commonly electrically connected to the first conductive via in the first dielectric layer, and wherein each of the plurality of memory cells is electrically connected to a corresponding second conductive via via a second portion of the conductive portion of the memory cell.

[0045] In some embodiments, forming a first conductive via in the first dielectric layer includes forming a plurality of first conductive vias corresponding to the plurality of memory cells in the first dielectric layer, wherein each of the plurality of memory cells is electrically connected to a corresponding first conductive via via a portion of the first electrode material layer located below a first portion of the conductive portion of the memory cell, and wherein a second portion of the conductive portion of each of the plurality of memory cells is electrically connected to each other and is jointly electrically connected to the second conductive via in the second dielectric layer.

[0046] Other features and advantages of this disclosure will become clearer from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0047] The foregoing and other features and advantages of this disclosure will become clear from the following description of embodiments illustrated in conjunction with the accompanying drawings. The drawings, incorporated herein and forming a part of the specification, are further used to explain the principles of this disclosure and to enable those skilled in the art to make and use it. Wherein:

[0048] Figure 1A schematic cross-sectional view of an exemplary structure of a conventional phase-change memory device is shown;

[0049] Figure 2A A schematic cross-sectional view of a phase-change memory device according to some embodiments of the present disclosure is shown;

[0050] Figure 2B The observation along AA' is shown. Figure 2A A schematic side view of a phase-change memory device;

[0051] Figure 3 It shows when Figure 2A A schematic cross-sectional view of a phase-change memory device when there is a breakpoint in the first electrode layer of the memory cell.

[0052] Figure 4A A schematic cross-sectional view of a phase-change memory device according to some embodiments of the present disclosure is shown;

[0053] Figure 4B The observation along AA' is shown. Figure 4A A schematic side view of a phase-change memory device;

[0054] Figure 5 A schematic cross-sectional view of a phase-change memory device including multiple memory cells according to some embodiments of the present disclosure is shown;

[0055] Figure 6A A schematic cross-sectional view of a phase-change memory device including multiple memory cells according to other embodiments of the present disclosure is shown;

[0056] Figure 6B A schematic top view of a phase-change memory device including multiple memory cells according to further embodiments of the present disclosure is shown;

[0057] Figure 7 A flowchart of a method for fabricating a phase-change memory device according to some embodiments of the present disclosure is shown;

[0058] Figures 8A to 8J The diagram shows the preparation of Figure 5 A schematic cross-sectional view of the device corresponding to the corresponding step of a non-limiting example process of a phase-change memory device;

[0059] Figure 9A A schematic cross-sectional view of a phase-change memory device according to some embodiments of the present disclosure is shown;

[0060] Figure 9B The observation along BB' is shown. Figure 9A A schematic side view of a phase-change memory device;

[0061] Figure 10AA schematic cross-sectional view of a phase-change memory device according to some embodiments of the present disclosure is shown;

[0062] Figure 10B The observation along BB' is shown. Figure 10A A schematic side view of a phase-change memory device;

[0063] Figure 11 A schematic cross-sectional view of a phase-change memory device including multiple memory cells according to some embodiments of the present disclosure is shown;

[0064] Figure 12A A schematic cross-sectional view of a phase-change memory device including multiple memory cells according to other embodiments of the present disclosure is shown;

[0065] Figure 12B A schematic top view of a phase-change memory device including multiple memory cells according to further embodiments of the present disclosure is shown;

[0066] Figure 13 A flowchart of a method for fabricating a phase-change memory device according to some embodiments of the present disclosure is shown;

[0067] Figures 14A to 14H The diagram shows the preparation of Figure 11 A schematic cross-sectional view of the device corresponding to the corresponding step of a non-limiting example process of a phase-change memory device.

[0068] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts with the same function, and repeated descriptions are omitted. In some cases, similar reference numerals and letters are used to denote similar items, so once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0069] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, this disclosure is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Detailed Implementation

[0070] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0071] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this disclosure or its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in this disclosure. However, those skilled in the art will understand that they merely illustrate exemplary ways in which this disclosure can be implemented, and not exhaustive ways. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components.

[0072] In addition, techniques, methods and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods and equipment should be considered part of the specification.

[0073] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0074] Figure 1 A cross-sectional view schematically illustrating an exemplary structure of a conventional phase-change memory device 10 is shown. It should be understood that... Figure 1 Only the storage cells of the phase-change memory device 10 are shown; other components that may exist in the phase-change memory device 10 are not shown to avoid obscuring the focus of the discussion here. Figure 1 As shown, the storage cell of the phase-change memory device 10 typically consists of a first electrode layer 11, a second electrode layer 13, and a phase-change material layer 12 between the first electrode layer 11 and the second electrode layer 13. It is generally believed that the device performance of a phase-change memory device is directly proportional to its effective area, because a larger effective area allows the device to store a larger amount of charge at the same voltage. The effective area can be considered as the area of ​​the overlapping region of the first electrode layer 11, the phase-change material layer 12, and the second electrode layer 13. Therefore, increasing the area of ​​the overlapping region of the first electrode layer 11, the phase-change material layer 12, and the second electrode layer 13 is desirable to improve the device performance of the phase-change memory device. However, in... Figure 1 In the device structure shown, increasing the area of ​​the overlapping region of the first electrode layer 11, the phase change material layer 12, and the second electrode layer 13 will inevitably increase the footprint of the phase change memory device 10 on the chip that carries it. However, this will not only inhibit the miniaturization design of the chip, but also hinder the layout of other devices on the chip, thereby reducing the chip's integration density.

[0075] To this end, this disclosure provides an improved phase-change memory device, which introduces a conductive portion into the memory cell, so that the first electrode layer, the phase-change material layer and the second electrode layer of the memory cell are no longer two-dimensional planar structures, but have a three-dimensional structure extending around the conductive portion. This allows the effective area of ​​the phase-change memory device to be increased without increasing the footprint of the phase-change memory device, thereby improving the device performance of the phase-change memory device.

[0076] Phase-change memory devices according to some embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It will be understood that actual phase-change memory devices may contain other components, but these other components are not shown in the drawings and will not be discussed herein in order to avoid obscuring the key points of the disclosure.

[0077] Now for reference Figures 2A to 2B It shows a schematic cross-sectional view and a schematic side view of a phase-change memory device 100 according to some embodiments of the present disclosure. Figure 2A and Figure 2B As shown, the phase change storage device 100 may include a storage cell, which may include a conductive portion 110, a first electrode layer 120, a phase change material layer 130, and a second electrode layer 140. The first electrode layer 120 includes a first portion 121 disposed below a first portion 111 of the conductive portion 110 and a second portion 122 disposed above the first portion 111 of the conductive portion 110. The first portion 121 and the second portion 122 of the first electrode layer 120 contact each other to surround and be electrically connected to the first portion 111 of the conductive portion 110. The phase change material layer 130 includes a first portion 131 disposed below the first portion 121 of the first electrode layer 120 and a second portion 132 disposed above the second portion 122 of the first electrode layer 120. The first portion 131 and the second portion 132 of the phase change material layer 130 contact each other to surround the first electrode layer 120. The second electrode layer 140 includes a first portion 141 disposed below a first portion 131 of the phase change material layer 130 and a second portion 142 disposed above a second portion 132 of the phase change material layer 130. The first portion 141 and the second portion 142 of the second electrode layer 140 contact to surround the phase change material layer 130. In some embodiments, such as reference... Figure 2B (The dashed lines in the conductive portion 110 are virtual and not actually present.) In addition to the first portion 111 surrounded by the first electrode layer 120, the phase change material layer 130, and the second electrode layer 140, the conductive portion 110 may also include a second portion 112 on which the first electrode layer 120, the phase change material layer 130, and the second electrode layer 140 are not disposed. The second portion 112 of the conductive portion 110 is electrically connected to the first portion 111 of the conductive portion 110, and thus electrically connected to the first electrode layer 120. In some examples, such as... Figure 2B As shown, the second portion 112 of the conductive portion 110 is directly adjacent to the first portion 111 of the conductive portion 110. In other examples, the second portion 112 of the conductive portion 110 may be separated from the first portion 111 of the conductive portion 110 by other portions of the conductive portion 110. Figure 2B As can be seen, the conductive portion 110 extends beyond the area jointly surrounded by the first electrode layer 120, the phase change material layer 130, and the second electrode layer 140. This facilitates the placement of conductive components (e.g., Figure 4A and Figure 4B The second conductive via 161 is used to apply an electrical signal to the first electrode layer 120 via the conductive portion 110.

[0078] Combination Figure 2A and Figure 2B It is clear that, with the same device footprint, the presence of the conductive part 110 increases the effective area of ​​the phase change memory device 100 compared to the case where the conductive part 110 is not present. The increase is approximately equal to the sum of the lengths of all non-bottom sides of the cross-sectional shape of the first part 111 of the conductive part 110. This allows the phase change memory device 100 to store more charge under the same voltage, thereby improving the sensitivity, stability, reliability, and lifespan of the phase change memory device 100.

[0079] In some embodiments, the included angle α between the side surface and the bottom surface of the conductive portion 110 may not be greater than 90 degrees, and in some examples may be less than 90 degrees. This can facilitate the subsequent formation of a film layer on the conductive portion 110 using certain processes. Furthermore, although the cross-sectional shape of the conductive portion 110 is... Figure 2A The conductive portion 110 is illustrated as a trapezoid, but this is merely exemplary and not limiting. The cross-sectional shape of the conductive portion 110 can take any suitable shape, such as a triangle, rectangle, pentagon, etc. The cross-sectional shape of the conductive portion 110 is also not limited to a convex polygon; it can also be a suitable concave polygon, for example... Figure 2A The top edge of the cross-sectional shape of the conductive portion 110 shown can also be modified to a V-shape, M-shape, etc., which may achieve a larger sum of the lengths of all non-bottom edges of the cross-sectional shape of the conductive portion 110 compared to the original shape, thereby achieving a further increase in the effective area of ​​the device. In some embodiments, one or more corners of the conductive portion 110 can be chamfered or rounded. The dimensions of the conductive portion 110 can be appropriately designed according to the actual device requirements. Given a fixed device footprint, the aspect ratio of the conductive portion 110 can be designed to be as large as possible. For example, in some examples, the aspect ratio of the conductive portion 110 can be greater than 1:1, or greater than 1.5:1, or greater than 2:1, or greater than 3:1.

[0080] In some embodiments, the conductive portion 110 can be formed of any suitable conductive material, such as a metal (e.g., aluminum, copper, silver, etc.). The various locations of the contact conductive portions 110 of the first electrode layer 120 are electrically connected to each other via the conductive portions 110, which to some extent compensates for the problems caused by defects resulting from imperfect deposition of the first electrode layer 120 on the conductive portions 110. For example, in some cases, referring to... Figure 3 When depositing and forming the second portion 122 of the first electrode layer 120 on the conductive portion 110, one or more breakpoints 123 may undesirably be generated in the second portion 122 during actual processing. Breakpoints 123 may affect the conductive continuity of the second portion 122 of the first electrode layer 120. Specifically, in Figure 3 In this configuration, sub-parts S1 and S3 of the second portion 122 of the first electrode layer 120 are electrically connected to the first portion 121, namely S4, of the first electrode layer 120. However, sub-part S2 of the second portion 122 of the first electrode layer 120, being located between two breakpoints 123, cannot be electrically connected to S1, S3, and S4. This poses a risk that the device area corresponding to sub-part S2 may not contribute to the effective device area. However, since the conductive portion 110 is conductive, sub-part S2 can be electrically connected to each of S1, S3, and S4 via the conductive portion 110. This ensures that the device area corresponding to sub-part S2 can still contribute to the effective device area, resulting in a small or almost negligible change in the effective device area compared to when there are no breakpoints.

[0081] The thickness of each film layer of the phase change memory device 100 can be appropriately designed according to actual device requirements, typically on the order of tens to hundreds of angstroms. The first electrode layer 120 and the second electrode layer 140 can include any suitable material, such as, but not limited to, titanium, titanium nitride, silicon titanium nitride, aluminum titanium nitride, titanium carbonitride, tantalum nitride, silicon tantalum nitride, aluminum tantalum nitride, tungsten nitride, tungsten silicide, doped polycrystalline silicon, and transparent conductive oxides, as well as any combination thereof. In some embodiments, the first electrode layer 120 and the second electrode layer 140 can include the same material, such as both including titanium nitride. In some embodiments, the first electrode layer 120 and the second electrode layer 140 can include different materials, such as one including titanium nitride and the other including a metal. The phase change material layer 130 can include any suitable phase change material, such as, but not limited to, ferroelectric materials. In some embodiments, the ferroelectric material includes at least one of zirconium oxide, hafnium oxide, titanium oxide, aluminum oxide, nickel oxide, and iron oxide.

[0082] In some embodiments, such as Figure 4A and Figure 4BAs shown, the phase-change memory device 100 may further include a first dielectric layer 150 on which memory cells are disposed and / or a second dielectric layer 160 covering the memory cells. The second dielectric layer 160 may be located above the first dielectric layer 150. The first dielectric layer 150 may include a first conductive via 151 electrically connected to a first portion 141 of a second electrode layer 140 of the memory cells. The second dielectric layer 160 may also include a second conductive via 161 electrically connected to a second portion 112 of a conductive portion 110 of the memory cells. In some embodiments, for example, refer to Figure 4B The first conductive via 151 is located below the first portion 111 of the conductive portion 110, and the second conductive via 161 is located above the second portion 112 of the conductive portion 110. The first conductive via 151 is laterally offset from the second conductive via 161. In other embodiments, for example, the first portion 141 of the second electrode layer 140 extends from below the first portion 111 of the conductive portion 110 to below the second portion 112 of the conductive portion 110 (e.g., as shown in the example). Figure 4B As shown, the first conductive via 151 may also be located below the second portion 112 of the conductive portion 110, and the second conductive via 161 may be located above the second portion 112 of the conductive portion 110, so that the first conductive via 151 may be laterally offset from or aligned with the second conductive via 161. In some embodiments, the materials of the first dielectric layer 150 and the second dielectric layer 160 may include oxides (such as silicon oxide) or nitrides (such as silicon nitride), and the materials of the first conductive via 151 and the second conductive via 161 may include metals (such as tungsten).

[0083] Although Figure 4A and Figure 4B Only one storage cell is shown, but it is understood that the phase change memory device 100 can be configured to include two or more storage cells as needed, and these storage cells can be arranged in any suitable manner (e.g., but not limited to an array) in the phase change memory device 100.

[0084] In some embodiments, a phase-change memory device may include a plurality of memory cells disposed on a first dielectric layer 150 and covered by a second dielectric layer 160. For example, such as Figure 5As shown, the phase change memory device includes three memory cells disposed on a first dielectric layer 150 and covered by a second dielectric layer 160. The first memory cell includes a conductive portion (only the first portion 111 of the conductive portion is shown in the figure), a first electrode layer 120 (including the first portion 121 and the second portion 122), a phase change material layer 130 (including the first portion 131 and the second portion 132), and a second electrode layer 140 (including the first portion 141 and the second portion 142). The second memory cell includes a conductive portion (only the first portion 111' of the conductive portion is shown in the figure), a first electrode layer 120' (including the first portion 121 and the second portion 122), and a phase change material layer 130 (including the first portion 131 and the second portion 132). The third storage cell includes a first part 121' and a second part 122', a phase change material layer 130' (including the first part 131' and the second part 132'), a second electrode layer 140' (including the first part 141' and the second part 142'), and a conductive portion (only the first part 111" of the conductive portion is shown in the figure), a first electrode layer 120" (including the first part 121" and the second part 122"), a phase change material layer 130" (including the first part 131" and the second part 132"), and a second electrode layer 140" (including the first part 141" and the second part 142").

[0085] Multiple memory cells in a phase-change memory device can be spaced apart from each other. Assuming the thickness of the stack of the second portion of the first electrode layer, the second portion of the phase-change material layer, and the second portion of the second electrode layer of a memory cell is equal to the effective cell thickness Ts, in some embodiments, the spacing Dc between the conductive portions of two adjacent memory cells (e.g., the first memory cell and the second memory cell, the second memory cell and the third memory cell) can exceed twice the effective cell thickness Ts. If two adjacent memory cells have different effective cell thicknesses Ts, the spacing Dc between the conductive portions of the two adjacent memory cells can exceed the sum of the effective cell thicknesses Ts of the two adjacent memory cells.

[0086] In some embodiments, the first dielectric layer may include a plurality of first conductive vias corresponding to the plurality of memory cells, and the second dielectric layer may include a plurality of second conductive vias corresponding to the plurality of memory cells. Furthermore, each of the plurality of memory cells may be electrically connected to a corresponding first conductive via of the plurality of first conductive vias via a first portion of its second electrode layer, and electrically connected to a corresponding second conductive via of the plurality of second conductive vias via a second portion of its conductive portion. For example, as... Figure 5As shown, the first dielectric layer 150 includes three first conductive vias 151, 151', and 151' corresponding to the three memory cells. The second dielectric layer 160 includes three second conductive vias 161, 161', and 161' corresponding to the three memory cells. The first memory cell is electrically connected to the first conductive via 151 via a first portion 141 of its second electrode layer 140 and to the second conductive via 161 via a second portion (not shown) of its conductive portion. The second memory cell is electrically connected to the first conductive via 151' via a first portion 141' of its second electrode layer 140' and to the second conductive via 161' via a second portion (not shown) of its conductive portion. The third memory cell is electrically connected to the first conductive via 151' via a first portion 141' of its second electrode layer 140' and to the second conductive via 161' via a second portion (not shown) of its conductive portion.

[0087] exist Figure 5 In this architecture, each memory cell has its own dedicated via to bring out its top and bottom electrodes. In some cases, two or more memory cells can share a via to reduce circuit fabrication complexity, reduce circuit control complexity, and improve logic circuit diversity, while also ensuring independent control of each memory cell.

[0088] In some embodiments, the second dielectric layer may include a plurality of second conductive vias corresponding to a plurality of memory cells. A first portion of the second electrode layer of each of the plurality of memory cells may be electrically connected to each other and jointly electrically connected to a first conductive via in the first dielectric layer. Furthermore, each of the plurality of memory cells may be electrically connected to a corresponding second conductive via via a second portion of its conductive portion. For example, refer to… Figure 6A The second dielectric layer 160 includes three second conductive vias 161, 161', and 161' corresponding to the three memory cells. The first dielectric layer 150 includes a first conductive via 151. The first memory cell is electrically connected to the second conductive via 161 via a second portion (not shown) of its conductive portion. The second memory cell is electrically connected to the second conductive via 161' via a second portion (not shown) of its conductive portion. The third memory cell is electrically connected to the second conductive via 161' via a second portion (not shown) of its conductive portion. Furthermore, the first portion 141 of the second electrode layer 140 of the first memory cell, the first portion 141' of the second electrode layer 140' of the second memory cell, and the first portion 141' of the second electrode layer 140' of the third memory cell are electrically connected to each other and are collectively electrically connected to the first conductive via 151 in the first dielectric layer 150.

[0089] In other embodiments, the first dielectric layer may include a plurality of first conductive vias corresponding to a plurality of memory cells. Each memory cell may be electrically connected to a corresponding first conductive via via via a first portion of its second electrode layer, and a second portion of the conductive portion of each memory cell may be electrically connected to each other and jointly electrically connected to a second conductive via in the second dielectric layer. For example, see reference... Figure 6B The dark gray rectangle represents the region where the second part of the first electrode layer, the second part of the phase change material layer, and the second part of the second electrode layer of the memory cell are stacked. Figure 6B In this structure, the first dielectric layer 150 includes three first conductive vias 151, 151', and 151' corresponding to the three memory cells. The second dielectric layer 160 includes a second conductive via 161. The first memory cell is electrically connected to the first conductive via 151 via a first portion of its second electrode layer, the second memory cell is electrically connected to the first conductive via 151' via a first portion of its second electrode layer, and the third memory cell is electrically connected to the first conductive via 151' via a first portion of its second electrode layer. Furthermore, the second portions 112 of the conductive portion 110 of the first memory cell, the second portions 112' of the conductive portion 110' of the second memory cell, and the second portions 112' of the conductive portion 110' of the third memory cell are electrically connected to each other and are collectively electrically connected to the second conductive via 161 in the second dielectric layer 160. In some embodiments, the conductive portion 110 of the first storage cell, the conductive portion 110' of the second storage cell, and the conductive portion 110" of the third storage cell may be integrally formed, such that the second portion 112 of the conductive portion 110 of the first storage cell, the second portion 112' of the conductive portion 110' of the second storage cell, and the second portion 112" of the conductive portion 110" of the third storage cell are electrically connected to each other, for example, as shown in the figure. Figure 6B As shown. In some embodiments, the conductive portion 110 of the first storage cell, the conductive portion 110' of the second storage cell, and the conductive portion 110" of the third storage cell may be formed separately, such that the second portion 112 of the conductive portion 110 of the first storage cell, the second portion 112' of the conductive portion 110' of the second storage cell, and the second portion 112" of the conductive portion 110" of the third storage cell may be electrically connected to each other via additional conductive components.

[0090] This disclosure, in another aspect, provides a method for fabricating a phase-change memory device including memory cells. For example... Figure 7As shown, a method 200 for fabricating a phase-change memory device may include forming a memory cell of the phase-change memory device by the following operations: at step S202, forming a first electrode material layer; at step S204, forming a first phase-change material layer on top of the first electrode material layer; at step S206, forming a second electrode material layer on top of the first phase-change material layer; at step S208, forming a conductive material layer on top of the second electrode material layer and etching the conductive material layer to form a conductive portion; at step S210, forming a third electrode material layer on a first portion of the conductive portion, the third electrode material layer contacting the second electrode material layer to surround and electrically connect to the first portion of the conductive portion, and etching the third electrode material layer and the second electrode material layer to remove the region of each of the portion of the third electrode material layer not located above the first portion of the conductive portion and the portion of the second electrode material layer not located below the conductive portion that extends beyond the thickness of the third electrode material layer from the conductive portion; at step S212, forming a second phase-change material layer on top of the third electrode material layer, the second phase-change material layer and... The first phase change material layer contacts and surrounds the etched third electrode material layer and the etched second electrode material layer; in step S214, a fourth electrode material layer is formed on the second phase change material layer, and the fourth electrode material layer, the second phase change material layer, the first phase change material layer, and the first electrode material layer are etched to remove the portion of the fourth electrode material layer not located above the first portion of the conductive portion, the portion of the second phase change material layer not located above the first portion of the conductive portion, the portion of the first phase change material layer not located below the conductive portion, and the portion of the first electrode material layer not located below the conductive portion, where the distance from the conductive portion exceeds the effective cell thickness of the memory cell, the effective cell thickness being the thickness of the stack of the third electrode material layer, the second phase change material layer, and the fourth electrode material layer; in step S216, a fifth electrode material layer is formed on the fourth electrode material layer, and the fifth electrode material layer is etched such that the etched fifth electrode material layer contacts both the etched first electrode material layer and the etched fourth electrode material layer to surround the etched first phase change material layer and the etched second phase change material layer.

[0091] In some embodiments, at step S208, the conductive portion can be formed such that the angle between the side surface and the bottom surface of the conductive portion is no greater than 90 degrees. The contact points of the conductive portions of each of the first electrode material layer and the second electrode material layer are electrically connected to each other via the conductive portions. In some embodiments, the conductive material layer may include a metal. In some embodiments, the first electrode material layer, the second electrode material layer, the third electrode material layer, the fourth electrode material layer, and the fifth electrode material layer may each include titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbonitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, tungsten nitride, tungsten silicide, doped polycrystalline silicon, or a transparent conductive oxide, or any combination thereof. In some embodiments, the first phase change material layer and the second phase change material layer may include a ferroelectric material. In some embodiments, the ferroelectric material includes at least one of zirconium oxide, hafnium oxide, titanium oxide, aluminum oxide, nickel oxide, and iron oxide.

[0092] In some embodiments, after etching the conductive material layer to form the conductive portion (step S208) and before forming the third electrode material layer (step S210), method 200 may further include: continuing to etch the second electrode material layer to remove the portion of the second electrode material layer that is not located below the conductive portion. It is understood that if the above processing is performed before step S210, then step S210 only requires etching the third electrode material layer without further processing of the second electrode material layer.

[0093] In some embodiments, through Figure 7 Before forming the memory cell as shown in the steps, method 200 may further include: forming a first dielectric layer and forming a first conductive via in the first dielectric layer. Thus, through... Figure 7 When forming the memory cell using the steps shown, the memory cell can be disposed on the first dielectric layer, and the portion of the first electrode material layer located below the conductive portion can be configured to be electrically connected to the first conductive via.

[0094] In some embodiments, through Figure 7After forming the memory cell as shown in the steps, method 200 may further include: forming a second dielectric layer covering the memory cell, and forming a second conductive via in the second dielectric layer. In some embodiments, the first conductive via may be located below the first portion of the conductive portion, and the second conductive via may be located above the second portion of the conductive portion, with the first conductive via laterally offset from the second conductive via. In other embodiments, the first conductive via may be located below the second portion of the conductive portion, and the second conductive via may be located above the second portion of the conductive portion, with the first conductive via laterally offset from or aligned with the second conductive via. The conductive portion may further include a second portion where the third electrode material layer, the second phase change material layer, the fourth electrode material layer, and the fifth electrode material layer are not disposed, the second portion of the conductive portion may be configured to be electrically connected to the first portion of the conductive portion, and the second conductive via may be configured to be electrically connected to the second portion of the conductive portion.

[0095] Method 200 may further include forming a plurality of memory cells disposed on a first dielectric layer and covered by a second dielectric layer. To form the plurality of memory cells, in some embodiments, etching the conductive material layer to form conductive portions at step S208 may include etching the conductive material layer to form a plurality of conductive portions, and forming a third electrode material layer at step S210 may include forming a third electrode material layer on a first portion of each of the plurality of conductive portions, the third electrode material layer contacting the second electrode material layer to respectively surround the first portion of each of the plurality of conductive portions, and etching the third electrode material layer and the second electrode material layer to remove the portion of each of the third electrode material layer not located above the first portion of each of the plurality of conductive portions and the portion of the second electrode material layer not located below the conductive portion, where the distance from the conductive portion exceeds the thickness of the third electrode material layer. Thus, each of the plurality of conductive portions and the portion of each of the first electrode material layer, the first phase change material layer, the second electrode material layer, the third electrode material layer, the second phase change material layer, the fourth electrode material layer, and the fifth electrode material layer surrounding the conductive portion form a corresponding memory cell among the plurality of memory cells. In some embodiments, the spacing between two adjacent conductive portions of the plurality of conductive portions may exceed twice the effective cell thickness Ts of the storage cell.

[0096] In some embodiments, forming a first conductive via in a first dielectric layer may include forming a plurality of first conductive vias corresponding to a plurality of memory cells in the first dielectric layer, such that each memory cell can be electrically connected to a corresponding first conductive via of the plurality of first conductive vias via a portion of a first electrode material layer located below a first portion of the conductive portion of the memory cell. Similarly, forming a second conductive via in a second dielectric layer may include forming a plurality of second conductive vias corresponding to a plurality of memory cells in the second dielectric layer, such that each memory cell can be electrically connected to a corresponding second conductive via of the plurality of second conductive vias via a second portion of the conductive portion of the memory cell.

[0097] In other embodiments, portions of the first electrode material layer located below the first portion of the conductive portion of each memory cell are electrically connected to each other and are jointly electrically connected to a first conductive via in the first dielectric layer. Forming a second conductive via in the second dielectric layer may include forming a plurality of second conductive vias corresponding to a plurality of memory cells in the second dielectric layer, such that each memory cell can be electrically connected to a corresponding second conductive via in the plurality of second conductive vias via a second portion of the conductive portion of the memory cell. Specifically, in some examples, at least one of the first electrode material layer, the fourth electrode material layer, and the fifth electrode material layer can be formed to extend continuously across the plurality of memory cells. In this case, after forming the second phase change material layer (step S212), method 200 may, for example, replace step S214 by etching the fourth electrode material layer, the second phase change material layer, and the first phase change material layer to remove the region of each of the portions of the fourth electrode material layer not located above the first portion of the conductive portion, the portions of the second phase change material layer not located above the first portion of the conductive portion, and the portions of the first phase change material layer not located below the conductive portion that are beyond the effective cell thickness of the memory cell, thereby obtaining a first electrode material layer that extends continuously across the plurality of memory cells. Alternatively, step S216 may include: forming a fifth electrode material layer on top of the fourth electrode material layer, such that the fifth electrode material layer contacts the etched first electrode material layer and the etched fourth electrode material layer of each memory cell respectively to surround the etched first phase change material layer and the etched second phase change material layer of each memory cell, thereby obtaining a fifth electrode material layer that extends continuously across the plurality of memory cells. Alternatively, after forming the second phase change material layer (step S212) and before forming the fourth electrode material layer, method 200 may include: etching the second phase change material layer, the first phase change material layer, and optionally the first electrode material layer to remove the portion of the second phase change material layer not located above the first portion of the conductive portion, the portion of the first phase change material layer not located below the conductive portion, and the portion of the optional first electrode material layer not located below the conductive portion, where the distance from the conductive portion exceeds the stack thickness of the third electrode material layer and the second phase change material layer. In this case, since the fourth electrode material layer does not need to undergo etching and has already contacted the first electrode material layer (whether etched or not) to surround the etched first phase change material layer and the etched second phase change material layer of each memory cell, step S216 can be omitted, thus obtaining a fourth electrode material layer that extends continuously across the plurality of memory cells.

[0098] In some other embodiments, forming a first conductive via in the first dielectric layer may include forming a plurality of first conductive vias corresponding to a plurality of memory cells in the first dielectric layer, such that each memory cell can be electrically connected to a corresponding first conductive via via a portion of the first electrode material layer located below a first portion of the conductive portion of the memory cell, and the second portions of the conductive portions of each memory cell are electrically connected to each other and are collectively electrically connected to a second conductive via in the second dielectric layer.

[0099] Implementations of the method may be similar to the various embodiments of the aforementioned phase-change memory devices, and will not be repeated here.

[0100] The following are combined with Figures 8A to 8J Description for preparation Figure 5 This document presents a non-limiting example process for a phase-change memory device. For the sake of brevity, only one of similar components is labeled in the figure. In this document, the corresponding film can be formed using various suitable deposition methods (including but not limited to atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc.), and etching can be performed using any suitable etching method (including but not limited to dry etching or wet etching, etc.), which will not be elaborated upon here.

[0101] like Figure 8A As shown, a first dielectric layer 1500 is formed. The first dielectric layer 1500 can be formed on any suitable substrate (not shown in the figure, including but not limited to single-crystal silicon, polycrystalline silicon, gallium arsenide, sapphire, quartz, silicon carbide, silicon-on-insulator (SOI), etc.). Also... Figure 8A As shown, multiple vias are etched in the formed first dielectric layer 1500 and filled with a conductive material (such as, but not limited to, tungsten) to form multiple first conductive vias 1510. Figure 8B As shown, a first electrode material layer 1410, a first phase change material layer 1310, a second electrode material layer 1210, and a conductive material layer 1100 are sequentially formed on a first dielectric layer 1500. In some examples, when forming the first electrode material layer 1410, for example when the first electrode material layer 1410 includes titanium nitride, the lower portion of the first electrode material layer 1410 can be formed first by physical vapor deposition, and then the upper portion of the first electrode material layer 1410 can be formed by atomic layer deposition. In some examples, when forming the second electrode material layer 1210, for example when the second electrode material layer 1210 includes titanium nitride, the lower portion of the second electrode material layer 1210 can be formed first by atomic layer deposition, and then the upper portion of the second electrode material layer 1210 can be formed by physical vapor deposition. Figure 8C As shown, the conductive material layer 1100 is etched to form a plurality of conductive portions 110. For example... Figure 8DAs shown, a third electrode material layer 1220 is formed on a first portion of each of the plurality of conductive portions 110, and the third electrode material layer 1220 contacts a second electrode material layer 1210 to respectively surround the first portion of each conductive portion 110. Figure 8E As shown, the third electrode material layer 1220 and the second electrode material layer 1210 are etched to remove regions of each of the portions of the third electrode material layer 1220 not located above the first portion of the conductive portion 110 and the portions of the second electrode material layer 1210 not located below the conductive portion 110, extending beyond the thickness of the third electrode material layer 1220 from the conductive portion 110. In some examples, when forming the third electrode material layer 1220, for example when the third electrode material layer 1220 includes titanium nitride, the lower portion of the third electrode material layer 1220 can be formed first by physical vapor deposition, and then the upper portion of the third electrode material layer 1220 can be formed by atomic layer deposition. Figure 8F As shown, a second phase change material layer 1320 and a fourth electrode material layer 1420 are sequentially formed on top of the third electrode material layer 1220. In some examples, when forming the fourth electrode material layer 1420, for example when the fourth electrode material layer 1420 includes titanium nitride, the lower portion of the fourth electrode material layer 1420 can be formed first by atomic layer deposition, and then the upper portion of the fourth electrode material layer 1420 can be formed by physical vapor deposition. Subsequently, as... Figure 8G As shown, the fourth electrode material layer 1420, the second phase change material layer 1320, the first phase change material layer 1310, and the first electrode material layer 1410 are etched to remove the portion of each of the following: the portion of the fourth electrode material layer 1420 not located above the first portion of the conductive portion 110; the portion of the second phase change material layer 1320 not located above the first portion of the conductive portion 110; the portion of the first phase change material layer 1310 not located below the conductive portion 110; and the portion of the first electrode material layer 1410 not located below the conductive portion 110. This removes the portion of each of these layers that extends beyond the effective cell thickness Ts of the memory cell from the conductive portion, thereby spacing the resulting plurality of memory cells apart from each other. Figure 8H As shown, a fifth electrode material layer 1700 is formed on top of the fourth electrode material layer 1420, and as... Figure 8IAs shown, the fifth electrode material layer 1700 is etched (e.g., by an etch-back process) such that the etched fifth electrode material layer 1700 contacts both the etched first electrode material layer 1410 and the etched fourth electrode material layer 1420 to surround the etched first phase change material layer 1310 and the etched second phase change material layer 1320. At this time, the etched second electrode material layer 1210 and the etched third electrode material layer 1220 form an inner electrode portion that continuously surrounds and conforms to the conductive portion 110; the etched first phase change material layer 1310 and the etched second phase change material layer 1320 form an intermediate phase change material portion that continuously surrounds and conforms to the conductive portion 110; and the etched fifth electrode material layer 1700, the etched first electrode material layer 1410, and the etched fourth electrode material layer 1420 form an outer electrode portion that continuously surrounds and conforms to the conductive portion 110. This gives the inner electrode portion, intermediate phase change material portion, and outer electrode portion a three-dimensional structure, thereby resulting in a large effective device area. Further... Figure 8J As shown, a second dielectric layer 1600 can also be formed to cover the multiple memory cells formed, and multiple vias are etched in the second dielectric layer 1600 and filled with conductive material to form multiple second conductive vias 1610. Each memory cell can be electrically connected to a corresponding second conductive via 1610 via a second portion of its conductive portion 110.

[0102] In another aspect, this disclosure also provides an improved phase-change memory device, which introduces a conductive portion into the memory cell to directly serve as the first electrode layer of the memory cell. This makes the phase-change material layer and the second electrode layer of the memory cell no longer two-dimensional planar structures, but have a three-dimensional structure extending around the conductive portion serving as the first electrode layer. This allows the effective area of ​​the phase-change memory device to be increased without increasing the footprint of the phase-change memory device, thereby improving the device performance of the phase-change memory device.

[0103] Now for reference Figure 9A and Figure 9B It shows a schematic cross-sectional view and a schematic side view of a phase-change memory device 300 according to some embodiments of the present disclosure. Figure 9A and Figure 9BAs shown, the phase change memory device 100 may include a memory cell, which may include a conductive portion 310, a phase change material layer 330, and a second electrode layer 340. The conductive portion 310 serves as the first electrode layer of the memory cell. The phase change material layer 330 includes a first portion 331 disposed below the first portion 311 of the conductive portion 310 and a second portion 332 disposed above the first portion 311 of the conductive portion 310, with the first portion 331 and the second portion 332 of the phase change material layer 330 contacting each other to surround the first portion 311 of the conductive portion 310. The second electrode layer 340 includes a first portion 341 disposed below the first portion 331 of the phase change material layer 330 and a second portion 342 disposed above the second portion 332 of the phase change material layer 330, with the first portion 341 and the second portion 342 of the second electrode layer 340 contacting each other to surround the phase change material layer 330. In some embodiments, such as referring to... Figure 9B (The dashed lines in the conductive portion 310 are virtual and not actually present.) In addition to the first portion 311 surrounded by both the phase change material layer 330 and the second electrode layer 340, the conductive portion 310 may also include a second portion 312 on which the phase change material layer 330 and the second electrode layer 340 are not disposed. The second portion 312 of the conductive portion 310 is electrically connected to the first portion 311 of the conductive portion 310. In some examples, such as... Figure 9B As shown, the second portion 312 of the conductive portion 310 is directly adjacent to the first portion 311 of the conductive portion 310. In other examples, the second portion 312 of the conductive portion 310 may be separated from the first portion 311 of the conductive portion 310 by other portions of the conductive portion 310. Figure 9B As can be seen, the conductive portion 310 extends beyond the area jointly surrounded by the phase change material layer 330 and the second electrode layer 340, which facilitates the placement of conductive components (e.g., Figure 10A and Figure 10B The second conductive through-hole 361 is used to apply an electrical signal to the conductive part 310.

[0104] Combination Figure 9A and Figure 9B It is clear that, with the same device footprint, the presence of the conductive portion 310 increases the effective area of ​​the phase-change memory device 300 compared to the absence of the conductive portion 310. This increase is essentially equivalent to the sum of the lengths of all non-bottom sides of the cross-sectional shape of the first portion 311 of the conductive portion 310. This allows the phase-change memory device 300 to store more charge at the same voltage, thereby improving its sensitivity, stability, reliability, and extending its lifespan. Furthermore, using the conductive portion 310 as the first electrode layer in the phase-change memory device 300 simplifies the device structure and reduces the complexity of the device fabrication process.

[0105] In some embodiments, the included angle α between the side surface and the bottom surface of the conductive portion 310 may not be greater than 90 degrees, and in some examples may be less than 90 degrees. This can facilitate the subsequent formation of a film layer on the conductive portion 310 using certain processes. Furthermore, although the cross-sectional shape of the conductive portion 310 is... Figure 9A The conductive portion 310 is illustrated as a trapezoid, but this is merely exemplary and not limiting. The cross-sectional shape of the conductive portion 310 can take any suitable shape, such as a triangle, rectangle, pentagon, etc. The cross-sectional shape of the conductive portion 310 is also not limited to a convex polygon; it can also be a suitable concave polygon, for example... Figure 9A The top edge of the cross-sectional shape of the conductive portion 310 shown can also be modified to a V-shape, M-shape, etc., which may achieve a larger sum of the lengths of all non-bottom edges of the cross-sectional shape of the conductive portion 310 compared to the original shape, thereby further increasing the effective area of ​​the device. In some embodiments, one or more corners of the conductive portion 310 can be chamfered or rounded. The dimensions of the conductive portion 310 can be appropriately designed according to the actual device requirements. Given a fixed device footprint, the aspect ratio of the conductive portion 310 can be designed to be as large as possible. For example, in some examples, the aspect ratio of the conductive portion 310 can be greater than 1:1, or greater than 1.5:1, or greater than 2:1, or greater than 3:1.

[0106] The thickness of each film layer of the phase-change memory device 100 can be appropriately designed according to actual device requirements, typically ranging from tens to hundreds of angstroms. The conductive portion 310 and the second electrode layer 340 can include any suitable material, such as, but not limited to, titanium, titanium nitride, silicon titanium nitride, aluminum titanium nitride, titanium carbonitride, tantalum nitride, silicon tantalum nitride, aluminum tantalum nitride, tungsten nitride, tungsten silicide, doped polycrystalline silicon, and transparent conductive oxides, as well as any combination thereof. In some embodiments, the conductive portion 310 and the second electrode layer 340 can include the same material, such as both including titanium nitride. In some embodiments, the conductive portion 310 and the second electrode layer 340 can include different materials, such as one including titanium nitride and the other including a metal. The phase-change material layer 330 can include any suitable phase-change material, such as, but not limited to, ferroelectric materials. In some embodiments, the ferroelectric material includes at least one of zirconium oxide, hafnium oxide, titanium oxide, aluminum oxide, nickel oxide, and iron oxide.

[0107] In some embodiments, such as Figure 10A and Figure 10BAs shown, the phase-change memory device 300 may further include a first dielectric layer 350 on which memory cells are disposed and / or a second dielectric layer 360 covering the memory cells. The second dielectric layer 360 may be located above the first dielectric layer 350. The first dielectric layer 350 may include a first conductive via 351 electrically connected to a first portion 341 of a second electrode layer 340 of the memory cells. The second dielectric layer 360 may also include a second conductive via 361 electrically connected to a second portion 312 of a conductive portion 310 of the memory cells. In some embodiments, for example, refer to Figure 10B The first conductive via 351 is located below the first portion 311 of the conductive portion 310, and the second conductive via 361 is located above the second portion 312 of the conductive portion 310. The first conductive via 351 is laterally offset from the second conductive via 361. In other embodiments, for example, the first portion 341 of the second electrode layer 340 extends from below the first portion 311 of the conductive portion 310 to below the second portion 312 of the conductive portion 310 (e.g., as shown in the example). Figure 10B As shown, the first conductive via 351 may also be located below the second portion 312 of the conductive portion 310, and the second conductive via 361 may be located above the second portion 312 of the conductive portion 310. Thus, the first conductive via 351 may be laterally offset from or aligned with the second conductive via 361. In some embodiments, the materials of the first dielectric layer 350 and the second dielectric layer 360 may include oxides (such as silicon oxide) or nitrides (such as silicon nitride), and the materials of the first conductive via 351 and the second conductive via 361 may include metals (such as tungsten).

[0108] Although Figure 10A and Figure 10B Only one storage cell is shown, but it is understood that the phase change memory device 300 can be configured to include two or more storage cells as needed, and these storage cells can be arranged in any suitable manner (e.g., but not limited to an array) within the phase change memory device 300.

[0109] In some embodiments, a phase-change memory device may include a plurality of memory cells disposed on a first dielectric layer 350 and covered by a second dielectric layer 360. For example, such as Figure 11As shown, the phase change memory device includes three memory cells disposed on a first dielectric layer 350 and covered by a second dielectric layer 360. The first memory cell includes a conductive portion (only the first portion 311 of the conductive portion is shown in the figure), a phase change material layer 330 (including the first portion 331 and the second portion 332), and a second electrode layer 340 (including the first portion 341 and the second portion 342). The second memory cell includes a conductive portion (only the first portion 311' of the conductive portion is shown in the figure), a phase change material layer 330' (including the first portion 331' and the second portion 332'), and a second electrode layer 340' (including the first portion 341' and the second portion 342'). The third memory cell includes a conductive portion (only the first portion 311" of the conductive portion is shown in the figure), a phase change material layer 330" (including the first portion 331" and the second portion 332"), and a second electrode layer 340" (including the first portion 341" and the second portion 342").

[0110] Multiple memory cells in a phase-change memory device can be spaced apart from each other. Assuming the thickness of the stack of the second portion of the phase-change material layer and the second portion of the second electrode layer of a memory cell is the effective cell thickness Ts', in some embodiments, the spacing Dc' between the conductive portions of two adjacent memory cells (e.g., the first memory cell and the second memory cell, the second memory cell and the third memory cell) can exceed twice the effective cell thickness Ts. If two adjacent memory cells have different effective cell thicknesses Ts, the spacing Dc' between the conductive portions of two adjacent memory cells can exceed the sum of the effective cell thicknesses Ts of these two adjacent memory cells.

[0111] In some embodiments, the first dielectric layer may include a plurality of first conductive vias corresponding to the plurality of memory cells, and the second dielectric layer may include a plurality of second conductive vias corresponding to the plurality of memory cells. Furthermore, each of the plurality of memory cells may be electrically connected to a corresponding first conductive via of the plurality of first conductive vias via a first portion of its second electrode layer, and electrically connected to a corresponding second conductive via of the plurality of second conductive vias via a second portion of its conductive portion. For example, as... Figure 11As shown, the first dielectric layer 350 includes three first conductive vias 351, 351', and 351' corresponding to the three memory cells. The second dielectric layer 360 includes three second conductive vias 361, 361', and 361' corresponding to the three memory cells. The first memory cell is electrically connected to the first conductive via 351 via a first portion 341 of its second electrode layer 340 and to the second conductive via 361 via a second portion (not shown) of its conductive portion. The second memory cell is electrically connected to the first conductive via 351' via a first portion 341' of its second electrode layer 340' and to the second conductive via 361' via a second portion (not shown) of its conductive portion. The third memory cell is electrically connected to the first conductive via 351' via a first portion 341' of its second electrode layer 340' and to the second conductive via 361' via a second portion (not shown) of its conductive portion.

[0112] exist Figure 11 In this architecture, each memory cell has its own dedicated via to bring out its top and bottom electrodes. In some cases, two or more memory cells can share a via to reduce circuit fabrication complexity, reduce circuit control complexity, and improve logic circuit diversity, while also ensuring independent control of each memory cell.

[0113] In some embodiments, the second dielectric layer may include a plurality of second conductive vias corresponding to a plurality of memory cells. A first portion of the second electrode layer of each of the plurality of memory cells may be electrically connected to each other and jointly electrically connected to a first conductive via in the first dielectric layer. Furthermore, each of the plurality of memory cells may be electrically connected to a corresponding second conductive via via a second portion of its conductive portion. For example, refer to… Figure 12A The second dielectric layer 360 includes three second conductive vias 361, 361', and 361' corresponding to the three memory cells. The first dielectric layer 350 includes a first conductive via 351. The first memory cell is electrically connected to the second conductive via 361 via a second portion (not shown) of its conductive portion. The second memory cell is electrically connected to the second conductive via 361' via a second portion (not shown) of its conductive portion. The third memory cell is electrically connected to the second conductive via 361' via a second portion (not shown) of its conductive portion. Furthermore, the first portion 341 of the second electrode layer 340 of the first memory cell, the first portion 341' of the second electrode layer 340' of the second memory cell, and the first portion 341' of the second electrode layer 340' of the third memory cell are electrically connected to each other and are collectively electrically connected to the first conductive via 351 in the first dielectric layer 350.

[0114] In other embodiments, the first dielectric layer may include a plurality of first conductive vias corresponding to a plurality of memory cells. Each memory cell may be electrically connected to a corresponding first conductive via via via a first portion of its second electrode layer, and a second portion of the conductive portion of each memory cell may be electrically connected to each other and jointly electrically connected to a second conductive via in the second dielectric layer. For example, see reference... Figure 12B The dark gray rectangle represents the region where the second part of the phase change material layer and the second part of the second electrode layer of the memory cell are stacked. Figure 12B In this structure, the first dielectric layer 350 includes three first conductive vias 351, 351', and 351' corresponding to the three memory cells. The second dielectric layer 360 includes a second conductive via 361. The first memory cell is electrically connected to the first conductive via 351 via a first portion of its second electrode layer, the second memory cell is electrically connected to the first conductive via 351' via a first portion of its second electrode layer, and the third memory cell is electrically connected to the first conductive via 351' via a first portion of its second electrode layer. Furthermore, the second portions 312 of the conductive portions 310 of the first memory cell, the second portions 312' of the conductive portions 310' of the second memory cell, and the second portions 312' of the conductive portions 310' of the third memory cell are electrically connected to each other and are collectively electrically connected to the second conductive via 361 in the second dielectric layer 360. In some embodiments, the conductive portion 310 of the first storage cell, the conductive portion 310' of the second storage cell, and the conductive portion 310" of the third storage cell may be integrally formed, such that the second portion 312 of the conductive portion 310 of the first storage cell, the second portion 312' of the conductive portion 310' of the second storage cell, and the second portion 312" of the conductive portion 310" of the third storage cell are electrically connected to each other, for example, as shown in the figure. Figure 12B As shown. In some embodiments, the conductive portion 310 of the first storage cell, the conductive portion 310' of the second storage cell, and the conductive portion 310" of the third storage cell may be formed separately, such that the second portion 312 of the conductive portion 310 of the first storage cell, the second portion 312' of the conductive portion 310' of the second storage cell, and the second portion 312" of the conductive portion 310" of the third storage cell may be electrically connected to each other via additional conductive members.

[0115] This disclosure, in another aspect, provides a method for fabricating a phase-change memory device including memory cells. For example... Figure 13As shown, a method 400 for fabricating a phase-change memory device may include forming a memory cell of the phase-change memory device by the following operations: at step S402, forming a first electrode material layer; at step S404, forming a first phase-change material layer on top of the first electrode material layer; at step S406, forming a conductive material layer on top of the first phase-change material layer and etching the conductive material layer to form a conductive portion, the conductive portion serving as an electrode of the memory cell; at step S408, forming a second phase-change material layer on a first portion of the conductive portion, the second phase-change material layer contacting the first phase-change material layer to surround the first portion of the conductive portion; at step S410, forming a second electrode material layer on top of the second phase-change material layer and etching the second electrode material layer, the second phase-change material layer, the first phase-change material layer, and the first phase-change material layer. An electrode material layer is used to remove the portion of each of the following: the portion of the second electrode material layer not located above the first portion of the conductive portion, the portion of the second phase change material layer not located above the first portion of the conductive portion, the portion of the first phase change material layer not located below the conductive portion, and the portion of the first electrode material layer not located below the conductive portion, from the conductive portion beyond the effective cell thickness of the memory cell. The effective cell thickness is the thickness of the stack of the second phase change material layer and the second electrode material layer. In step S412, a third electrode material layer is formed on the second electrode material layer and etched, such that the etched third electrode material layer contacts both the etched first electrode material layer and the etched second electrode material layer to surround the etched first phase change material layer and the etched second phase change material layer.

[0116] In some embodiments, at step S406, the conductive portion may be formed such that the angle between the side surface and the bottom surface of the conductive portion is no greater than 90 degrees. In some embodiments, the conductive material layer, the first electrode material layer, the second electrode material layer, and the third electrode material layer may each include titanium, titanium nitride, titanium silicon nitride, titanium aluminum nitride, titanium carbonitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, tungsten nitride, tungsten silicide, doped polycrystalline silicon, or a transparent conductive oxide, or any combination thereof. In some embodiments, the first phase change material layer and the second phase change material layer may each include a ferroelectric material. In some embodiments, the ferroelectric material includes at least one of zirconium oxide, hafnium oxide, titanium oxide, aluminum oxide, nickel oxide, and iron oxide.

[0117] In some embodiments, through Figure 13 Before forming the memory cell as shown in the steps, method 400 may further include: forming a first dielectric layer and forming a first conductive via in the first dielectric layer. Thus, through... Figure 13 When forming the memory cell using the steps shown, the memory cell can be disposed on the first dielectric layer, and the portion of the first electrode material layer located below the conductive portion can be configured to be electrically connected to the first conductive via.

[0118] In some embodiments, through Figure 13 After forming the memory cell as shown in the steps, method 400 may further include: forming a second dielectric layer covering the memory cell, and forming a second conductive via in the second dielectric layer. In some embodiments, the first conductive via may be located below the first portion of the conductive portion, and the second conductive via may be located above the second portion of the conductive portion, with the first conductive via laterally offset from the second conductive via. In other embodiments, the first conductive via may be located below the second portion of the conductive portion, and the second conductive via may be located above the second portion of the conductive portion, with the first conductive via laterally offset from or aligned with the second conductive via. The conductive portion may further include a second portion where the second phase change material layer, the second electrode material layer, and the third electrode material layer are not disposed, the second portion of the conductive portion may be configured to be electrically connected to the first portion of the conductive portion, and the second conductive via may be configured to be electrically connected to the second portion of the conductive portion.

[0119] Method 400 may further include forming a plurality of memory cells disposed on a first dielectric layer and covered by a second dielectric layer. To form the plurality of memory cells, in some embodiments, etching the conductive material layer at step S406 to form conductive portions may include etching the conductive material layer to form a plurality of conductive portions, and forming a second phase change material layer at step S408 may include forming a second phase change material layer on a first portion of each of the plurality of conductive portions, the second phase change material layer contacting the first phase change material layer to respectively surround the first portion of each of the plurality of conductive portions. Thus, each of the plurality of conductive portions and the portion of each of the first electrode material layer, the first phase change material layer, the second phase change material layer, the second electrode material layer, and the third electrode material layer surrounding the conductive portion form a corresponding memory cell among the plurality of memory cells. In some embodiments, the spacing between two adjacent conductive portions of the plurality of conductive portions exceeds twice the effective cell thickness.

[0120] In some embodiments, forming a first conductive via in a first dielectric layer may include forming a plurality of first conductive vias corresponding to a plurality of memory cells in the first dielectric layer, such that each memory cell can be electrically connected to a corresponding first conductive via of the plurality of first conductive vias via a portion of a first electrode material layer located below a first portion of the conductive portion of the memory cell. Similarly, forming a second conductive via in a second dielectric layer may include forming a plurality of second conductive vias corresponding to a plurality of memory cells in the second dielectric layer, such that each memory cell can be electrically connected to a corresponding second conductive via of the plurality of second conductive vias via a second portion of the conductive portion of the memory cell.

[0121] In other embodiments, portions of the first electrode material layer located below the first portion of the conductive portion of each memory cell are electrically connected to each other and are jointly electrically connected to a first conductive via in the first dielectric layer. Forming a second conductive via in the second dielectric layer may include forming a plurality of second conductive vias corresponding to a plurality of memory cells in the second dielectric layer, such that each memory cell can be electrically connected to a corresponding second conductive via in the plurality of second conductive vias via a second portion of the conductive portion of the memory cell. Specifically, in some examples, at least one of the first electrode material layer, the second electrode material layer, and the third electrode material layer can be formed to extend continuously across the plurality of memory cells. In this case, after forming the second phase change material layer (step S408), method 400 may also replace step S410 by etching the second electrode material layer, the second phase change material layer, and the first phase change material layer to remove the region of each of the portions of the second electrode material layer not located above the first portion of the conductive portion, the portions of the second phase change material layer not located above the first portion of the conductive portion, and the portions of the first phase change material layer not located below the conductive portion that are beyond the effective cell thickness of the memory cell, thereby obtaining a first electrode material layer that extends continuously across the plurality of memory cells. Alternatively, step S412 may include: forming a third electrode material layer on top of the second electrode material layer, such that the third electrode material layer contacts the etched first electrode material layer and the etched fourth electrode material layer of each memory cell to surround the etched first phase change material layer and the etched second phase change material layer of each memory cell, thereby obtaining a third electrode material layer that extends continuously across the plurality of memory cells. Alternatively, after forming the second phase change material layer (step S408) and before forming the second electrode material layer, method 400 may include: etching the second phase change material layer, the first phase change material layer, and optionally the first electrode material layer to remove the portion of the second phase change material layer not located above the first portion of the conductive portion, the portion of the first phase change material layer not located below the conductive portion, and the portion of the optional first electrode material layer not located below the conductive portion, each of which is located beyond the thickness of the second phase change material layer from the conductive portion. In this case, since the second electrode material layer does not need to undergo etching and has already contacted the first electrode material layer (whether etched or not) to surround the etched first phase change material layer and the etched second phase change material layer of each memory cell respectively, step S412 can be omitted, thus obtaining a second electrode material layer that extends continuously across the plurality of memory cells.

[0122] In some other embodiments, forming a first conductive via in the first dielectric layer may include forming a plurality of first conductive vias corresponding to a plurality of memory cells in the first dielectric layer, such that each memory cell can be electrically connected to a corresponding first conductive via via a portion of the first electrode material layer located below a first portion of the conductive portion of the memory cell, and the second portions of the conductive portions of each memory cell are electrically connected to each other and are collectively electrically connected to a second conductive via in the second dielectric layer.

[0123] Implementations of the method may be similar to the various embodiments of the aforementioned phase-change memory devices, and will not be repeated here.

[0124] The following are combined with Figures 14A to 14H Description for preparation Figure 11 This is a non-limiting example process for a phase-change memory device. For the sake of brevity, only one of similar components is labeled in the figure.

[0125] like Figure 14A As shown, a first dielectric layer 3500 is formed. The first dielectric layer 3500 can be formed on any suitable substrate (not shown in the figure, including but not limited to single-crystal silicon, polycrystalline silicon, gallium arsenide, sapphire, quartz, silicon carbide, silicon-on-insulator (SOI), etc.). Also... Figure 14A As shown, multiple vias are etched in the formed first dielectric layer 3500 and filled with a conductive material (such as, but not limited to, tungsten) to form multiple first conductive vias 3510. Figure 14B As shown, a first electrode material layer 3410, a first phase change material layer 3310, and a conductive material layer 3100 are sequentially formed on a first dielectric layer 3500. In some examples, when forming the first electrode material layer 3410, for example when the first electrode material layer 3410 includes titanium nitride, the lower portion of the first electrode material layer 3410 can be formed first by physical vapor deposition, and then the upper portion of the first electrode material layer 3410 can be formed by atomic layer deposition. Figure 14C As shown, the conductive material layer 3100 is etched to form a plurality of conductive portions 310. For example... Figure 14DAs shown, a second phase change material layer 3320 and a second electrode material layer 3420 are sequentially formed on a first portion of each of the plurality of conductive portions 310. The second phase change material layer 3320 contacts the first phase change material layer 3310 to respectively surround the first portion of each of the plurality of conductive portions 310. In some examples, when forming the second electrode material layer 3420, for example when the second electrode material layer 3420 includes titanium nitride, the lower portion of the second electrode material layer 3420 can be formed first by atomic layer deposition, and then the upper portion of the second electrode material layer 3420 can be formed by physical vapor deposition. Subsequently, as Figure 14E As shown, the second electrode material layer 3420, the second phase change material layer 3320, the first phase change material layer 3310, and the first electrode material layer 3410 are etched to remove the portion of the second electrode material layer 3420 that is not located above the first portion of each of the plurality of conductive portions 310, the portion of the second phase change material layer 3320 that is not located above the first portion of each of the plurality of conductive portions 310, the portion of the first phase change material layer 3310 that is not located below each of the plurality of conductive portions 310, and the portion of the first electrode material layer 3410 that is not located below each of the plurality of conductive portions 310, from which the distance from the corresponding conductive portion exceeds the effective cell thickness Ts' of the memory cell, so that the formed plurality of memory cells are spaced apart from each other. Figure 14F As shown, a third electrode material layer 3700 is formed on top of the second electrode material layer 3420, and as... Figure 14G As shown, the third electrode material layer 3700 is etched (e.g., by a back-etching process), such that the etched third electrode material layer 3700 contacts the etched first electrode material layer 3410 and the etched second electrode material layer 3420 to surround the etched first phase change material layer 3310 and the etched second phase change material layer 3320. At this time, the conductive portion 310 acts as the inner electrode portion, the etched first phase change material layer 3310 and the etched second phase change material layer 3320 form a continuous surrounding intermediate phase change material portion conforming to the conductive portion 310, and the etched third electrode material layer 3700 and the etched first electrode material layer 3410 and the etched second electrode material layer 3420 form a continuous surrounding outer electrode portion conforming to the conductive portion 310. This results in a three-dimensional structure for the inner electrode portion, the intermediate phase change material portion, and the outer electrode portion, thereby increasing the effective area of ​​the entire device. Further as... Figure 14HAs shown, a second dielectric layer 3600 can also be formed to cover the multiple memory cells formed, and multiple vias are etched in the second dielectric layer 3600 and filled with conductive material to form multiple second conductive vias 3610. Each memory cell can be electrically connected to a corresponding second conductive via 3610 via a second portion of its conductive portion 310.

[0126] The terms “left,” “right,” “front,” “back,” “top,” “bottom,” “upper,” “lower,” “high,” “lower,” etc., used in the specification and claims, if present, are for descriptive purposes and not necessarily for describing unchanging relative positions. It should be understood that such terms are interchangeable where appropriate, enabling the embodiments of this disclosure described herein to operate, for example, in orientations different from those shown or otherwise described herein. For example, when the device in the drawings is reversed, a feature previously described as “above” other features may now be described as “below” other features. The device may also be oriented in other ways (rotated 90 degrees or in other orientations), in which case the relative spatial relationships will be interpreted accordingly.

[0127] In the specification and claims, when an element is described as being "on top of," "attached" to, "connected" to, "coupled" to, "coupled to," or "in contact with" another element, the element may be directly located on top of, directly attached to, directly connected to, directly coupled to, directly coupled to, or directly in contact with the other element, or one or more intermediate elements may be present. Conversely, when an element is described as being "directly" located on top of, directly attached to, directly connected to, directly coupled to, directly coupled to, or directly in contact with another element, no intermediate elements are present. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that a feature has a portion overlapping with the adjacent feature or a portion located above or below the adjacent feature.

[0128] As used herein, the term “exemplary” means “serving as an example, instance, or illustration” and not as a “model” to be precisely copied. Any implementation described herein by example is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not limited to any theory expressed or implied as given in the technical field, background art, summary of the invention, or detailed description. Additionally, terms such as “first,” “second,” etc., may be used herein for reference only and are not intended to be limiting. For example, the terms “first,” “second,” and other such numerical terms relating to structures or elements do not imply order or sequence unless the context clearly indicates otherwise. It should also be understood that the term “comprising / including,” as used herein, indicates the presence of the indicated feature, integral, step, operation, unit, and / or component, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, units, and / or components, and / or combinations thereof.

[0129] As used herein, the term “and / or” includes any and all combinations of one or more of the listed items in association. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0130] Those skilled in the art will recognize that the boundaries between the above operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are equally possible. Aspects and elements of all the embodiments disclosed above may be combined in any way and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0131] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. The various embodiments disclosed herein can be combined in any way without departing from the spirit and scope of this disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A phase-change storage device, comprising a storage unit, the storage unit comprising: Conductive parts; The first electrode layer includes a first portion disposed below the first portion of the conductive portion and a second portion disposed above the first portion of the conductive portion, wherein the first portion and the second portion of the first electrode layer are in contact to surround the first portion of the conductive portion and are electrically connected to the first portion of the conductive portion. A phase change material layer includes a first portion disposed below a first portion of the first electrode layer and a second portion disposed above a second portion of the first electrode layer, wherein the first portion and the second portion of the phase change material layer are in contact to surround the first electrode layer; as well as The second electrode layer includes a first portion disposed below the first portion of the phase change material layer and a second portion disposed above the second portion of the phase change material layer, wherein the first portion and the second portion of the second electrode layer are in contact to surround the phase change material layer. The angle between the side surface and the bottom surface of the conductive part is less than 90 degrees. The conductive portion further includes a second portion on which the first electrode layer, the phase change material layer, and the second electrode layer are not disposed. The second portion of the conductive portion is electrically connected to the first portion of the conductive portion, thereby being electrically connected to the first electrode layer. Wherein, the first portion of the first electrode layer, the first portion of the phase change material layer, and the first portion of the second electrode layer extend from below the first portion of the conductive portion to below the second portion of the conductive portion.

2. The phase-change memory device as claimed in claim 1, wherein, The phase-change storage device satisfies at least one of the following: The conductive part includes metal; The first electrode layer and the second electrode layer each comprise titanium nitride; The phase change material layer includes ferroelectric materials.

3. The phase-change memory device as described in claim 1, wherein, The phase-change storage device further includes: A first dielectric layer, wherein the storage unit is disposed on the first dielectric layer; and A second dielectric layer is located above the first dielectric layer, and the memory cell is covered by the second dielectric layer. The first dielectric layer includes a first conductive via electrically connected to a first portion of the second electrode layer, and the second dielectric layer includes a second conductive via electrically connected to a second portion of the conductive portion.

4. The phase-change memory device as described in claim 3, wherein, The first conductive via is located below the first portion of the conductive part, and the second conductive via is located above the second portion of the conductive part. The first conductive via is laterally offset from the second conductive via.

5. The phase-change memory device as described in claim 3, wherein, The phase-change memory device includes a plurality of memory cells disposed on the first dielectric layer and covered by the second dielectric layer.

6. The phase-change memory device as claimed in claim 5, wherein, The thickness of the stack of the second portion of the first electrode layer, the second portion of the phase change material layer, and the second portion of the second electrode layer of the memory cell is the effective cell thickness of the memory cell, and wherein the spacing between the conductive portions of two adjacent memory cells in the plurality of memory cells exceeds twice the effective cell thickness.

7. The phase-change memory device as described in claim 5, in, The first dielectric layer includes a plurality of first conductive vias corresponding to the plurality of memory cells, and the second dielectric layer includes a plurality of second conductive vias corresponding to the plurality of memory cells. Each of the plurality of memory cells is electrically connected to a corresponding first conductive via of the plurality of first conductive vias via a first portion of its second electrode layer, and is electrically connected to a corresponding second conductive via of the plurality of second conductive vias via a second portion of its conductive portion.

8. The phase-change memory device as described in claim 5, in, The second dielectric layer includes a plurality of second conductive vias corresponding to the plurality of memory cells. In this configuration, the first portion of the second electrode layer of each of the plurality of memory cells is electrically connected to each other and is commonly electrically connected to the first conductive via in the first dielectric layer. Each of the plurality of storage cells is electrically connected to a corresponding second conductive via via a second portion of its conductive portion.

9. The phase-change memory device as described in claim 5, in, The first dielectric layer includes a plurality of first conductive vias corresponding to the plurality of memory cells. Each of the plurality of memory cells is electrically connected to a corresponding first conductive via of the plurality of first conductive vias via a first portion of its second electrode layer, and The second portion of the conductive portion of each of the plurality of memory cells is electrically connected to each other and is jointly electrically connected to the second conductive via in the second dielectric layer.

10. A method for fabricating a phase-change memory device, the phase-change memory device comprising memory cells, the method comprising forming the memory cells of the phase-change memory device by: Forming the first electrode material layer; A first phase change material layer is formed on top of the first electrode material layer; A second electrode material layer is formed on top of the first phase change material layer; A conductive material layer is formed on top of the second electrode material layer, and the conductive material layer is etched to form a conductive portion; A third electrode material layer is formed on the first portion of the conductive portion, the third electrode material layer being in contact with the second electrode material layer to surround and be electrically connected to the first portion of the conductive portion, and the third electrode material layer and the second electrode material layer are etched to remove the portion of the third electrode material layer that is not located above the first portion of the conductive portion and the portion of the second electrode material layer that is not located below the conductive portion, the region of each of these portions being located beyond the thickness of the third electrode material layer from the conductive portion. A second phase change material layer is formed on the third electrode material layer, and the second phase change material layer contacts the first phase change material layer to surround the etched third electrode material layer and the etched second electrode material layer. A fourth electrode material layer is formed on top of the second phase change material layer, and the fourth electrode material layer, the second phase change material layer, the first phase change material layer, and the first electrode material layer are etched to remove the portion of the fourth electrode material layer that is not located above the first portion of the conductive portion, the portion of the second phase change material layer that is not located above the first portion of the conductive portion, the portion of the first phase change material layer that is not located below the conductive portion, and the portion of the first electrode material layer that is not located below the conductive portion, from the conductive portion a region that exceeds the effective cell thickness of the memory cell, wherein the effective cell thickness is the thickness of the stack of the third electrode material layer, the second phase change material layer, and the fourth electrode material layer; as well as A fifth electrode material layer is formed on the fourth electrode material layer, and the fifth electrode material layer is etched such that the etched fifth electrode material layer contacts both the etched first electrode material layer and the etched fourth electrode material layer to surround the etched first phase change material layer and the etched second phase change material layer.

11. The method of claim 10, wherein, The conductive portion is formed such that the angle between the side surface and the bottom surface of the conductive portion is no greater than 90 degrees.

12. The method of claim 10, wherein, Satisfy at least one of the following: The conductive material layer includes a metal; The first electrode material layer, the second electrode material layer, the third electrode material layer, the fourth electrode material layer, and the fifth electrode material layer each comprise titanium nitride; The first phase change material layer and the second phase change material layer each comprise ferroelectric materials.

13. The method of claim 10, wherein, After etching the conductive material layer to form the conductive portion and before forming the third electrode material layer, the method further includes: continuing to etch the second electrode material layer to remove the portion of the second electrode material layer that is not located below the conductive portion. Specifically, after the formation of the third electrode material layer and before the formation of the second phase change material layer, only the third electrode material layer is etched without etching the second electrode material layer.

14. The method as described in claim 10, in, Before forming the storage cell, the method further includes: Forming the first dielectric layer, and A first conductive via is formed in the first dielectric layer. The storage cell is disposed on the first dielectric layer, and the portion of the first electrode material layer located below the conductive portion is electrically connected to the first conductive via; and After forming the storage unit, the method further includes: A second dielectric layer is formed covering the memory cell, and A second conductive via is formed in the second dielectric layer. The conductive portion further includes a second portion on which the third electrode material layer, the second phase change material layer, the fourth electrode material layer, and the fifth electrode material layer are not disposed. The second portion of the conductive portion is electrically connected to the first portion of the conductive portion and is electrically connected to the second conductive via.

15. The method of claim 14, wherein, The first conductive via is located below the first portion of the conductive part, and the second conductive via is located above the second portion of the conductive part. The first conductive via is laterally offset from the second conductive via.

16. The method of claim 14, further comprising forming a plurality of said memory cells disposed on the first dielectric layer and covered by the second dielectric layer.

17. The method of claim 16, in, Etching the conductive material layer to form conductive portions includes etching the conductive material layer to form a plurality of conductive portions. The formation of the third electrode material layer includes forming a third electrode material layer over a first portion of each of the plurality of conductive portions, the third electrode material layer contacting a second electrode material layer to respectively surround the first portion of each of the plurality of conductive portions, and etching the third electrode material layer and the second electrode material layer to remove the portion of the third electrode material layer not located above the first portion of each of the plurality of conductive portions and the portion of the second electrode material layer not located below the conductive portion, where the distance from the conductive portion exceeds the thickness of the third electrode material layer. Each of the plurality of conductive portions and the portion of each of the first electrode material layer, the first phase change material layer, the second electrode material layer, the third electrode material layer, the second phase change material layer, the fourth electrode material layer, and the fifth electrode material layer surrounding the conductive portion form a corresponding memory cell among the plurality of memory cells.

18. The method of claim 17, wherein, The spacing between two adjacent conductive parts in the plurality of conductive parts exceeds twice the thickness of the effective unit.

19. The method of claim 17, in, Forming a first conductive via in the first dielectric layer includes forming a plurality of first conductive vias corresponding to the plurality of memory cells in the first dielectric layer, and forming a second conductive via in the second dielectric layer includes forming a plurality of second conductive vias corresponding to the plurality of memory cells in the second dielectric layer. Each of the plurality of storage cells is electrically connected to a corresponding first conductive via via a portion of the first electrode material layer located below a first portion of the conductive portion of the storage cell, and is electrically connected to a corresponding second conductive via via a second portion of the conductive portion of the storage cell.

20. The method of claim 17, in, Forming a second conductive via in the second dielectric layer includes forming a plurality of second conductive vias corresponding to the plurality of memory cells in the second dielectric layer. Wherein, the portion of the first electrode material layer located below the first portion of the conductive portion of each of the plurality of memory cells is electrically connected to each other, and is commonly electrically connected to the first conductive via in the first dielectric layer, and Each of the plurality of storage cells is electrically connected to a corresponding second conductive via via a second portion of the conductive portion of the storage cell.

21. The method of claim 17, in, Forming a first conductive via in the first dielectric layer includes forming a plurality of first conductive vias corresponding to the plurality of memory cells in the first dielectric layer. Each of the plurality of memory cells is electrically connected to a corresponding first conductive via via a portion of the first electrode material layer located below the first portion of the conductive part of the memory cell, and The second portion of the conductive portion of each of the plurality of memory cells is electrically connected to each other and is jointly electrically connected to the second conductive via in the second dielectric layer.

22. A phase-change storage device, comprising a storage cell, the storage cell comprising: The conductive portion serves as the first electrode layer; A phase change material layer includes a first portion disposed below a first portion of the conductive portion and a second portion disposed above the first portion of the conductive portion, wherein the first portion and the second portion of the phase change material layer are in contact to surround the first portion of the conductive portion; as well as The second electrode layer includes a first portion disposed below the first portion of the phase change material layer and a second portion disposed above the second portion of the phase change material layer, wherein the first portion and the second portion of the second electrode layer are in contact to surround the phase change material layer. The angle between the side surface and the bottom surface of the conductive part is less than 90 degrees. The conductive portion further includes a second portion on which the phase change material layer and the second electrode layer are not disposed, and the second portion of the conductive portion is electrically connected to the first portion of the conductive portion. The first portion of the phase change material layer and the first portion of the second electrode layer extend from below the first portion of the conductive portion to below the second portion of the conductive portion, respectively.

23. The phase-change memory device of claim 22, wherein, The phase-change storage device satisfies at least one of the following: The conductive portion and the second electrode layer each comprise titanium nitride; The phase change material layer includes ferroelectric materials.

24. The phase-change memory device of claim 22, wherein, The phase-change storage device further includes: A first dielectric layer, wherein the storage unit is disposed on the first dielectric layer; and A second dielectric layer is located above the first dielectric layer, and the memory cell is covered by the second dielectric layer. The first dielectric layer includes a first conductive via electrically connected to a first portion of the second electrode layer, and the second dielectric layer includes a second conductive via electrically connected to a second portion of the conductive portion.

25. The phase-change memory device of claim 24, wherein, The first conductive via is located below the first portion of the conductive part, and the second conductive via is located above the second portion of the conductive part. The first conductive via is laterally offset from the second conductive via.

26. The phase-change memory device of claim 24, wherein, The phase-change memory device includes a plurality of memory cells disposed on the first dielectric layer and covered by the second dielectric layer.

27. The phase-change memory device of claim 26, wherein, The thickness of the stack of the second portion of the phase change material layer and the second portion of the second electrode layer of the memory cell is the effective cell thickness of the memory cell, and wherein the spacing between the conductive portions of two adjacent memory cells in the plurality of memory cells exceeds twice the effective cell thickness.

28. The phase-change memory device as claimed in claim 26, in, The first dielectric layer includes a plurality of first conductive vias corresponding to the plurality of memory cells, and the second dielectric layer includes a plurality of second conductive vias corresponding to the plurality of memory cells. Each of the plurality of memory cells is electrically connected to a corresponding first conductive via of the plurality of first conductive vias via a first portion of its second electrode layer, and is electrically connected to a corresponding second conductive via of the plurality of second conductive vias via a second portion of its conductive portion.

29. The phase-change memory device as claimed in claim 26, in, The second dielectric layer includes a plurality of second conductive vias corresponding to the plurality of memory cells. In this configuration, the first portion of the second electrode layer of each of the plurality of memory cells is electrically connected to each other and is commonly electrically connected to the first conductive via in the first dielectric layer. Each of the plurality of storage cells is electrically connected to a corresponding second conductive via via a second portion of its conductive portion.

30. The phase-change memory device as claimed in claim 26, in, The first dielectric layer includes a plurality of first conductive vias corresponding to the plurality of memory cells. Each of the plurality of memory cells is electrically connected to a corresponding first conductive via of the plurality of first conductive vias via a first portion of its second electrode layer, and The second portion of the conductive portion of each of the plurality of memory cells is electrically connected to each other and is jointly electrically connected to the second conductive via in the second dielectric layer.

31. A method for fabricating a phase-change memory device, the phase-change memory device comprising memory cells, the method comprising forming the memory cells of the phase-change memory device by: Forming the first electrode material layer; A first phase change material layer is formed on top of the first electrode material layer; A conductive material layer is formed on the first phase change material layer, and the conductive material layer is etched to form a conductive portion, which serves as an electrode of the memory cell; A second phase change material layer is formed on the first portion of the conductive portion, and the second phase change material layer is in contact with the first phase change material layer to surround the first portion of the conductive portion; A second electrode material layer is formed on top of the second phase change material layer, and the second electrode material layer, the second phase change material layer, the first phase change material layer, and the first electrode material layer are etched to remove the portion of the second electrode material layer that is not located above the first portion of the conductive portion, the portion of the second phase change material layer that is not located above the first portion of the conductive portion, the portion of the first phase change material layer that is not located below the conductive portion, and the portion of the first electrode material layer that is not located below the conductive portion, the region of each of these portions that is located beyond the effective cell thickness of the memory cell from the conductive portion, wherein the effective cell thickness is the thickness of the stack of the second phase change material layer and the second electrode material layer; as well as A third electrode material layer is formed on the second electrode material layer and the third electrode material layer is etched such that the etched third electrode material layer contacts both the etched first electrode material layer and the etched second electrode material layer to surround the etched first phase change material layer and the etched second phase change material layer.

32. The method of claim 31, wherein, The conductive portion is formed such that the angle between the side surface and the bottom surface of the conductive portion is no greater than 90 degrees.

33. The method of claim 31, wherein, Satisfy at least one of the following: The conductive material layer, the first electrode material layer, the second electrode material layer, and the third electrode material layer each comprise titanium nitride; The first phase change material layer and the second phase change material layer each comprise ferroelectric materials.

34. The method as described in claim 31, in, Before forming the storage cell, the method further includes: Forming the first dielectric layer, and A first conductive via is formed in the first dielectric layer. The storage cell is disposed on the first dielectric layer, and the portion of the first electrode material layer located below the conductive portion is electrically connected to the first conductive via; and After forming the storage unit, the method further includes: A second dielectric layer is formed covering the memory cell, and A second conductive via is formed in the second dielectric layer. The conductive portion further includes a second portion on which the second phase change material layer, the second electrode material layer, and the third electrode material layer are not disposed. The second portion of the conductive portion is electrically connected to the first portion of the conductive portion and electrically connected to the second conductive via.

35. The method of claim 34, wherein, The first conductive via is located below the first portion of the conductive part, and the second conductive via is located above the second portion of the conductive part. The first conductive via is laterally offset from the second conductive via.

36. The method of claim 34, further comprising forming a plurality of said memory cells disposed on the first dielectric layer and covered by the second dielectric layer.

37. The method of claim 36, in, Etching the conductive material layer to form conductive portions includes etching the conductive material layer to form a plurality of conductive portions. The formation of the second phase change material layer includes forming a second phase change material layer on a first portion of each of the plurality of conductive portions, the second phase change material layer contacting the first phase change material layer to respectively surround the first portion of each of the plurality of conductive portions, and Each of the plurality of conductive portions and the portion of each of the first electrode material layer, the first phase change material layer, the second phase change material layer, the second electrode material layer, and the third electrode material layer surrounding the conductive portion form a corresponding memory cell among the plurality of memory cells.

38. The method of claim 37, wherein, The spacing between two adjacent conductive parts in the plurality of conductive parts exceeds twice the thickness of the effective unit.

39. The method of claim 37, in, Forming a first conductive via in the first dielectric layer includes forming a plurality of first conductive vias corresponding to the plurality of memory cells in the first dielectric layer, and forming a second conductive via in the second dielectric layer includes forming a plurality of second conductive vias corresponding to the plurality of memory cells in the second dielectric layer. Each of the plurality of storage cells is electrically connected to a corresponding first conductive via via a portion of the first electrode material layer located below a first portion of the conductive portion of the storage cell, and is electrically connected to a corresponding second conductive via via a second portion of the conductive portion of the storage cell.

40. The method of claim 37, in, Forming a second conductive via in the second dielectric layer includes forming a plurality of second conductive vias corresponding to the plurality of memory cells in the second dielectric layer. Wherein, the portion of the first electrode material layer located below the first portion of the conductive portion of each of the plurality of memory cells is electrically connected to each other, and is commonly electrically connected to the first conductive via in the first dielectric layer, and Each of the plurality of storage cells is electrically connected to a corresponding second conductive via via a second portion of the conductive portion of the storage cell.

41. The method of claim 37, in, Forming a first conductive via in the first dielectric layer includes forming a plurality of first conductive vias corresponding to the plurality of memory cells in the first dielectric layer. Each of the plurality of memory cells is electrically connected to a corresponding first conductive via via a portion of the first electrode material layer located below the first portion of the conductive part of the memory cell, and The second portion of the conductive portion of each of the plurality of memory cells is electrically connected to each other and is jointly electrically connected to the second conductive via in the second dielectric layer.

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