Memory protection for vector operations

Abstract

Systems and methods for memory protection for vector operations are disclosed. For example, a method includes obtaining, using a processor core (220) that includes a pipeline (230) configured to execute instructions, a vector memory instruction, the instruction including a constant stride vector memory instruction; splitting a vector identified by the vector memory instruction into a sub-vector of a maximum length greater than one and one or more additional sub-vectors of a length less than or equal to the maximum length; checking, using a memory protection circuit (270), whether accessing an element of the sub-vector will result in a memory protection violation; and accessing the element of the sub-vector prior to checking, using the memory protection circuit, whether accessing an element of one of the one or more additional sub-vectors will result in a memory protection violation.

Description

Technical Field

[0001] This disclosure relates to memory protection for vector operations. Background Technology

[0002] Researchers including Roger Espasa and Mateo Valero have investigated schemes that record step operations as a base + range and distribute / aggregate the entire address range for the purpose of detecting memory hazards in program ordering. Attached Figure Description

[0003] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, by convention, the various features in the drawings are not drawn to scale. Rather, for clarity, the dimensions of the various features have been arbitrarily enlarged or reduced.

[0004] Figure 1 This is a block diagram of an example of a memory-protected integrated circuit that supports vector operations.

[0005] Figure 2 This is a block diagram of an example of a memory-protected integrated circuit that supports vector operations.

[0006] Figure 3 This is a memory mapping example of a vector memory instruction.

[0007] Figure 4 This is a flowchart illustrating an example of a memory protection process used for vector operations.

[0008] Figure 5 This is a flowchart illustrating an example of a memory protection process used for vector operations.

[0009] Figure 6 This is a flowchart illustrating an example of a memory protection process for vector operations using a memory protection circuit with two input address ports.

[0010] Figure 7 This is a flowchart illustrating an example of a memory protection process for vector operations using a memory protection circuit with a single input address port. Detailed Implementation

[0011] Overview

[0012] This paper describes systems and methods for memory protection for vector operations. Some processor architectures can implement ordered or unordered vector machines. Vector memory instructions can require several cycles to execute. Even for ordered vector machines, it is advantageous to allow subsequent instructions to begin execution before the current vector instruction has completed, even when accessing memory and potentially causing exceptions. It may also be useful to determine whether subsequent memory instructions pose any read-after-write (RAW), read-after-write (WAR), or write-after-write (WAW) dangers to the current vector memory instruction.

[0013] To achieve fast scanning of vectors against memory protection violations, it is advantageous to use minimal hardware to quickly check vector memory instructions for any memory protection violations. Each vector memory instruction may involve many elements at many different addresses and may require many cycles to execute. When the address range is known at the time the instruction is issued (e.g., for a vector with a constant stride of one unit or larger), the possible range of addresses can be calculated at the time of issuance as follows:

[0014] Range = [base part, base part + (VL-1) * stride + (byte per element - 1)]

[0015] Here, the base part is the base address of the vector in memory, and VL is the active vector length of the instruction. Hardware in the processor architecture can then be optimized to examine only the range rather than the address of each element within the range. Traditional designs would be conservative and assume that any address can be involved when the address is not known until execution time (e.g., for scatter-cluster instructions).

[0016] For unit stride or other constant stride vector memory instructions, if C is the number of individual hardware memory checks possible per cycle, a traditional system will process only C elements per cycle. For a given C, some processor architectures and methods described in this paper can increase the number of elements processed per cycle K to allow greater throughput from the same hardware. Checking fewer memory addresses / cycles (e.g., C=1 or C=2) allows for simpler hardware, higher frequencies, and / or lower power consumption.

[0017] With C=2, performance can be improved by choosing K>2 based on the step size and protection granularity, so that only two memory addresses need to be checked for the group, where these two memory addresses correspond to the first and last byte addresses involved by the group. For example, the maximum number of elements per group or subvector can be determined as:

[0018] K = f1(step size, protection granularity, machine width)

[0019] Where f1() is an arbitrary function that maps stride, width, and guard granularity to a maximum number of elements. In some implementations, K can be restricted to a power of 2 to simplify the hardware.

[0020] With C=1, the check can be further optimized by considering the base address (e.g., K=f2(base, stride, protection granularity, machine width)), so that for groups of size K>=1, checking only C=1 memory addresses is sufficient. The address range involved in the K-element group can be limited to a single protection granularity, i.e., the last byte address is at the same protection granularity as the base address. In this case of C=1, either all elements will cause a protection violation, or none of the elements will cause a protection violation, which simplifies exception handling.

[0021] In some architectures, scatter / cluster vector memory operations can be contained within memory protection granularity. If the width of the address index element is limited to 8 bits or 16 bits, or any known value smaller than the full address width, the range is limited to be independent of the data value. For unsigned n-bit indices:

[0022] Range = [fundamental part, fundamental part + 2^n - 1 + byte per element - 1]

[0023] Independent of the base address, if the index range fits within a single protection granularity, a C=2 protection check can be used to check the entire range (e.g., check the first and last byte addresses in the range). If the base is known, it can be optimized to use only a single memory check (C=1) when the base and the last byte of the range fall into the same protection granularity.

[0024] In some architectures, if n is unknown or very large, it is still possible to optimize memory protection violation checks for scatter / cluster instructions by remembering the range of addresses that might be referenced when the vector register is used as the index vector for scatter / cluster instructions. When writing to the vector register, the minimum and maximum elements in the vector can be recorded. This then ensures that the elements involved by the instruction are stored within the following range:

[0025] The range = [base + minimum, base + maximum + byte per element - 1] depends on the values ​​of the base, minimum, and maximum, and can efficiently handle memory protection checks on C=2 or C=1 machines.

[0026] As used in this paper, the term "memory" means that the minimum / maximum value is calculated at runtime because the vector registers are written to and recorded in the side microarchitectural structure (e.g., registers). The granularity of the memory information may be finer (e.g., a sub-section of a vector register) or coarser (e.g., a group of vector registers).

[0027] In some implementations, to save space instead of having a side structure to hold the minimum / maximum value, but still using fast and small circuitry to calculate the minimum / maximum value, approximations of minimum = (bitwise AND of all elements in the index vector) and maximum = (bitwise OR of all elements) can be used. If VL is less than the maximum possible VL, the tail elements are left undisturbed, or if some elements are masked and left undisturbed, the previous range is expanded instead of overwritten. If VL is less than the maximum possible VL, the tail elements are set to their maximum possible value using a tail-independent strategy, or if some elements are masked, the masked elements are set to their maximum possible value using a mask-independent strategy, and then the upper bound of the memory is set to its maximum possible value. If VL is less than the maximum possible VL, the tail elements are set to their minimum possible value using a tail-independent strategy, or if some elements are masked, the masked elements are set to their minimum possible value using a mask-independent strategy, and then the lower bound of the memory is set to its minimum possible value.

[0028] When programmers know the minimum / maximum values, more efficient risk checks can be implemented. Instead of recording the minimum / maximum values, explicit parameters for the minimum / maximum values ​​can be provided. It's possible to assume all elements are within the minimum / maximum range and then raise an exception at runtime if this assumption is violated.

[0029] In some implementations, memory protection techniques for vector operations can be used to achieve one or more advantages over conventional processors. For example, the structures and techniques described herein can be used to achieve fast memory protection scans for vector memory operations using simple memory protection circuitry with small circuit area and low power consumption.

[0030] As used herein, the term "circuit" refers to an arrangement of electronic components (e.g., transistors, resistors, capacitors, and / or inductors) configured to perform one or more functions. For example, a circuit may include one or more transistors interconnected to form logic gates that collectively perform a logic function.

[0031] Detailed description

[0032] Figure 1This is a block diagram of an example integrated circuit 110 for executing instructions using memory protection for vector memory operations. Integrated circuit 110 includes a processor core 120. Processor core 120 includes vector partitioning circuitry 130 configured to partition vectors in memory into subvectors to facilitate fast memory protection scans for vector memory instructions. Processor core 120 is configured to fetch instructions from memory 140 external to integrated circuit 110 and / or memory 142 internal to integrated circuit 110 and access data stored therein. Integrated circuit 110 includes memory protection circuitry 150 which can be configured to perform memory protection checks on one or more addresses with protection granularity. Integrated circuit 110 can provide advantages over conventional processor architectures, such as, for example, achieving fast memory protection scans for vector memory operations using simple memory protection circuitry with small circuit area and power consumption. For example, integrated circuit 110 can implement… Figure 4 The process 400. For example, integrated circuit 110 can implement... Figure 6 The process 500. For example, integrated circuit 110 can implement... Figure 6 The process 600. For example, integrated circuit 110 can implement... Figure 7 The process is 700.

[0033] Integrated circuit 110 includes processor core 120, which may include a pipeline configured to execute instructions, including constant-step vector memory instructions. Pipeline stages include fetch, decode, rename, dispatch, issue, execute, memory access, and write-back stages. For example, processor core 120 may be configured to execute instructions of the RISC V instruction set.

[0034] Processor core 120 can be configured to fetch instructions from memory 140 external to integrated circuit 110, which stores instructions and / or data. Processor core 120 can be configured to access data in memory 140 in response to instructions, including vector memory instructions (e.g., vector load instruction 310 or vector store instruction 330). For example, processor core 120 can access data in memory directly or via one or more caches. Processor core 120 can also be configured to fetch instructions from memory 142 internal to integrated circuit 110, which stores instructions and / or data. Processor core 120 can be configured to access data in memory 142 in response to instructions including vector memory instructions. Although... Figure 1 Although not shown in the figure, in some embodiments the integrated circuit 110 may include multiple processor cores.

[0035] Integrated circuit 110 includes memory protection circuitry 150 configured to check for memory protection violations using protection granularity. Memory protection circuitry 150 can allow privileged software to define memory regions and assign memory access permissions to each of them. The protection granularity of memory protection circuitry 150 limits the size of these memory regions with associated access permissions and thus limits resolution. For example, the protection granularity may correspond to memory pages (e.g., 4kB or 8kB pages). In some embodiments, memory protection circuitry 150 also specifies memory attributes for these memory regions, which may specify sorting and merging behavior of these regions, as well as cache and buffer attributes. Memory protection circuitry 150 can be used to monitor transactions, including instruction fetching and data access of processor core 120, which can trigger fault exceptions when memory protection violations are detected. For example, attempting to access unauthorized memory may lead to hardware failure (e.g., segmentation fault, memory violation exception, or aberrant termination of an attacking process). Memory protection circuitry 150 can be used to prevent processes from accessing memory that has not yet been allocated to them, which can prevent errors or malware within a process from affecting other processes or the operating system. In this example, the memory protection circuitry 150 is part of the processor core 120. In some implementations, the memory protection circuitry 150 may be located outside the processor core 120 (e.g., part of an external memory system).

[0036] The memory protection circuit 150 can have various sizes and complexities. In some embodiments, the memory protection circuit 150 is configured to check two addresses per clock cycle. For example, the memory protection circuit 150 may have two address ports, allowing it to receive two addresses and independently check for memory protection violations at the two addresses in memory during a single clock cycle. For example, the address can be checked by comparing the memory protection key or ring of the memory region including the address with the memory protection key or ring number associated with a process that is being executed by processor core 120 and attempting to access the memory at that address. In some embodiments, the memory protection circuit 150 is configured to check a single address per clock cycle, thus requiring less circuit area and consuming less power. In some embodiments, the memory protection circuit 150 may have more than two address ports or be otherwise configured to check more than two addresses or address ranges per clock cycle for memory protection violations.

[0037] Integrated circuit 110 includes vector segmentation circuitry 130. Vector segmentation circuitry 130 can be configured to segment vectors accessed in memory (e.g., memory 140 or memory 142) to allow memory protection scans of subvectors to be performed in parallel with memory accesses to other subvectors of the vector, and to increase the throughput of vector memory instructions. Vector segmentation circuitry 130 can be configured to segment a vector identified by vector memory instructions into subvectors with a maximum length greater than one, and one or more additional subvectors with a length less than or equal to the maximum length. In some embodiments, the maximum length can be determined based on the protection granularity and the stride of the vector identified by vector memory instructions (e.g., vector load instruction 310 or vector store instruction 330). For example, vector segmentation circuitry 130 can be configured to determine the maximum length such that the maximum length is proportional to the protection granularity and inversely proportional to the stride of the vector. For example, the maximum length can be determined as g / s, where g is the protection granularity (e.g., in bytes) and s is the stride of the vector (e.g., in bytes). In some implementations, the maximum length is limited to a power of two (e.g., the maximum power of two is less than or equal to g / s). The maximum length may also depend on the element width of the vector. The maximum length may also depend on the machine width of processor core 120, i.e., how many elements of the vector the processor core can process per clock cycle. For example, the maximum length may be determined as min(w, (g / s)), where w is the machine width of processor core 120. For example, the vector may be a unit stride vector, such that the stride is one. For example, the vector may have a constant stride greater than one (e.g., the stride may correspond to the length of rows in a matrix to access column vectors in a matrix data structure stored as a row sequence). Vector partitioning circuitry 130 may be configured to use memory protection circuitry 150 to check whether accessing an element of a subvector would result in a memory protection violation. Vector partitioning circuitry 130 may be configured to access elements of a subvector before using memory protection circuitry 150 to check whether accessing an element of one of one or more additional subvectors would result in a memory protection violation. For example, vector partitioning circuitry 130 may be part of an execution phase of the pipeline of processor core 120.

[0038] In some implementations, memory protection circuitry 150 is configured to check two addresses per clock cycle, and vector segmentation circuitry 130 checks whether accessing an element of a subvector would result in a memory protection violation by inputting the address of the first element and the address of the last element of the subvector to memory protection circuitry 150 during a single clock cycle. In some implementations, memory protection circuitry 150 is configured to check a single address per clock cycle, and vector segmentation circuitry 130 is configured to determine the maximum length based on the base address of the vector. For example, considering the base address of the vector can enable the determination of subvectors that are segmented into protection granularity boundaries aligned with those in memory, ensuring that the subvectors are contained within a single protection granularity, and thus enabling a check for memory protection violations using a single reference to memory protection circuitry 150 with the address associated with any element of the subvector.

[0039] For example, integrated circuit 110 may be configured to raise an exception in response to detecting a memory protection violation associated with an element of one of the one or more additional subvectors. In some implementations, raising an exception may halt execution in processor core 120. In some implementations, raising an exception may cause a page to be moved from disk to memory 140 or memory 142.

[0040] Figure 2 This is a block diagram of an example integrated circuit 210 for executing instructions using memory protection for vector operations. Integrated circuit 210 includes a processor core 220. Processor core 220 includes a processor pipeline 230, which includes vector partitioning circuitry 280 configured to partition vectors in memory into subvectors to facilitate fast memory protection scans for vector memory instructions. Processor core 220 includes one or more register files 240, which may include vector registers. Processor core 220 includes an L1 instruction cache 250 and an L1 data cache 252. Integrated circuit 210 includes an external memory system 260, which may include memory for storing instructions and data and / or provide access to memory 262 external to integrated circuit 210 that stores instructions and / or data. External memory system 260 includes memory protection circuitry 270, which can be configured to perform memory protection checks on one or more addresses with protection granularity. Integrated circuit 210 can offer advantages over traditional processor architectures, such as, for example, enabling fast memory protection scans for vector memory operations using simple memory protection circuitry with small circuit area and low power consumption. For instance, integrated circuit 210 can achieve... Figure 4 The process 400. For example, integrated circuit 210 can implement... Figure 6 The process 500. For example, integrated circuit 210 can implement... Figure 6 The process 600. For example, integrated circuit 210 can implement... Figure 7 The process is 700.

[0041] Integrated circuit 210 includes a processor core 220, which includes a pipeline 230 configured to execute instructions, including constant stride vector memory instructions. Pipeline 230 includes one or more fetch stages configured to retrieve instructions from the memory system of integrated circuit 210. For example, pipeline 230 may fetch instructions via L1 instruction cache 250. Pipeline 230 may include additional stages such as decode, rename, dispatch, issue, execute, memory access, and write-back stages. For example, processor core 220 may include pipeline 230 configured to execute instructions of the RISC V instruction set.

[0042] Integrated circuit 210 includes one or more register files 240 for processor core 220. The one or more register files 240 may store some or all of the processor core 220's architectural state. For example, the one or more register files 240 may include a set of vector registers. For example, the one or more register files 240 may include a set of control and status registers (CSRs). For example, the one or more register files 240 may include a set of scalar registers.

[0043] Integrated circuit 210 includes an L1 instruction cache 250 for processor core 220. The L1 instruction cache 250 may be a set-associative cache for instruction memory. To avoid the long latency of cascading reads of the tag array and data array, and the high power consumption of the parallel read array, a path predictor can be used. The path predictor can be accessed in an early fetch phase, and the hit path can be encoded into the read index of the data array. The tag array can be accessed in a later fetch phase and can be used to verify the path predictor.

[0044] Integrated circuit 210 includes an L1 data cache 252 for processor core 220. For example, the L1 data cache 252 may be a set-associative VIPT cache, meaning it utilizes only virtual address bits VA[set] indexing and fully tags all translated physical address bits PA[msb:12]. For low power consumption, tags and data arrays can be serially looked up so that at most a single data SRAM path is accessed. For example, the row size of the L1 data cache 252 may be 64 bytes, and the tick size may be 26 bytes.

[0045] Integrated circuit 210 includes an external memory system 260, which may include memory for storing instructions and data and / or memory 262 providing access to external memory for storing instructions and / or data. For example, the external memory system 260 may include an L2 cache, which may be configured to implement a cache coherence protocol / policy to maintain cache coherence across multiple L1 caches. Although Figure 2 Although not shown in the diagram, in some embodiments, integrated circuit 210 may include multiple processor cores. For example, external storage system 260 may include multiple layers.

[0046] External memory system 260 includes memory protection circuitry 270 configured to check for memory protection violations using protection granularity. Memory protection circuitry 270 can allow privileged software to define memory regions and assign memory access permissions to each of them. The protection granularity of memory protection circuitry 270 limits the size of these memory regions with associated access permissions and thus limits resolution. For example, the protection granularity may correspond to memory pages (e.g., 4kB or 8kB pages). In some implementations, memory protection circuitry 270 also specifies memory attributes for these memory regions, which may specify sorting and merging behavior of these regions, as well as cache and buffer attributes. Memory protection circuitry 270 can be used to monitor transactions, including instruction fetching and data access of processor core 220, which can trigger fault exceptions when memory protection violations are detected. For example, attempting to access unauthorized memory may lead to hardware failure (e.g., segmentation fault, memory violation exception, or aberrant termination of the violating process). Memory protection circuitry 270 can be used to prevent processes from accessing memory that has not yet been allocated to them, which can prevent errors or malware within a process from affecting other processes or the operating system.

[0047] The memory protection circuit 270 can have various sizes and complexities. In some embodiments, the memory protection circuit 270 is configured to check two addresses per clock cycle. For example, the memory protection circuit 270 may have two address ports, allowing it to receive two addresses and independently check for memory protection violations at the two addresses in memory during a single clock cycle. For example, the address can be checked by comparing a memory protection key or ring that includes the memory region containing the address with a memory protection key or ring number associated with a process being executed by processor core 220 and attempting to access it. In some embodiments, the memory protection circuit 270 is configured to check a single address per clock cycle, and therefore can occupy less circuit area and consume less power. In some embodiments, the memory protection circuit 270 may have more than two address ports or be otherwise configured to check more than two addresses or address ranges per clock cycle for memory protection violations.

[0048] Pipeline 230 includes vector segmentation circuitry 280. Vector segmentation circuitry 280 can be configured to segment vectors accessed in memory to allow memory protection scans for sub-vectors to be executed in parallel with memory accesses for other sub-vectors of the vector and to increase the throughput of vector memory instructions. Vector segmentation circuitry 280 can be configured to determine a maximum length greater than one, corresponding to the number of vector elements to be accessed in a single clock cycle. The maximum length can be determined based on the protection granularity and the stride of the vector as identified by vector memory instructions (e.g., vector load instruction 310 or vector store instruction 330). For example, the maximum length can be proportional to the protection granularity and inversely proportional to the stride. For example, the maximum length can be determined as g / s, where g is the protection granularity (e.g., in bytes) and s is the stride of the vector (e.g., in bytes). In some implementations, the maximum length is limited to a power of two (e.g., the largest power of two is less than or equal to g / s). The maximum length can also depend on the element width of the vector. The maximum length can also depend on the machine width of pipeline 230, i.e., how many elements of the vector the pipeline can process per clock cycle. For example, the maximum length can be determined as min(w, (g / s)), where w is the machine width of pipeline 230. For example, the vector can be a unit stride vector, such that the stride is one. For example, the vector can have a constant stride greater than one (e.g., the stride can correspond to the length of a row in a matrix to access a column vector of a matrix data structure stored as a row sequence). Vector partitioning circuit 280 can be configured to partition the vector into a subvector of the maximum length and one or more additional subvectors of length less than or equal to the maximum length. Vector partitioning circuit 280 can be configured to use memory protection circuit 270 to check whether accessing an element of a subvector would result in a memory protection violation. Vector partitioning circuit 280 can be configured to access elements of a subvector before using memory protection circuit 270 to check whether accessing an element of one of the one or more additional subvectors would result in a memory protection violation. For example, vector partitioning circuit 280 can be part of the execution phase of pipeline 230.

[0049] In some implementations, memory protection circuitry 270 is configured to check two addresses per clock cycle, and vector segmentation circuitry 280 checks whether accessing an element of a subvector would result in a memory protection violation by inputting the address of the first element and the address of the last element of the subvector into memory during a single clock cycle. In some implementations, memory protection circuitry 270 is configured to check a single address per clock cycle, and vector segmentation circuitry 280 is configured to determine the maximum length based on the vector's base address. For example, considering the vector's base address allows for determining subvectors that are aligned with the protection granularity boundaries in memory, ensuring that the subvectors are contained within a single protection granularity, and thus enabling memory protection violation checks against memory protection circuitry 270 using the address associated with any element of the subvector.

[0050] For example, integrated circuit 210 may be configured to raise an exception in response to detecting a memory protection violation associated with an element of one of the one or more additional subvectors. In some implementations, raising an exception may halt execution in processor core 220. In some implementations, raising an exception may result in a page being loaded from disk.

[0051] Figure 3This is a memory mapping of an example vector memory instruction 300, including a vector load instruction 310 and a vector store instruction 330. The vector load instruction 310 includes an opcode 312; a destination register field 314 that identifies a schema register used to store the result of the vector load instruction 310; a width field 316 that specifies the size of the memory element of the vector loaded from memory; a base register field 318 that identifies a schema register storing the base address of the vector in memory; a span register field 320 that identifies a schema register storing the stride of the vector in memory (e.g., one or another constant stride for unit stride vector loading); and a mode field 322 that specifies additional or optional parameters for the vector load instruction 310 (e.g., including memory addressing mode and / or multiple fields in each segment). The vector store instruction 330 includes an opcode 332; a source register field 334 that identifies the architecture register holding the vector data for storage; a width field 336 that specifies the size of the memory element of the vector stored in memory; a base register field 338 that identifies the architecture register storing the base address of the vector in memory; a stride register field 340 that identifies the architecture register of the stride of the vector stored in memory; and a mode field 342 that specifies additional or optional parameters for the vector store instruction 330 (e.g., including memory addressing mode and / or multiple fields in each segment). For example, in a RISC-V processor core, the vector load instruction 310 may be a LOAD-FP instruction with vector coding extensions and the vector store instruction 330 may be a STORE-FP instruction with vector coding extensions.

[0052] Figure 4 This is a flowchart illustrating an example of a memory protection process 400 for vector operations. Process 400 includes: fetching a vector memory instruction 410 using the processor core; segmenting the vector identified by the vector memory instruction 420 into subvectors with a maximum length greater than one, and one or more additional subvectors with a length less than or equal to the maximum length; checking 430 whether accessing an element of a subvector would result in a memory protection violation; if a memory protection violation is detected (in step 435), raising an exception 440; and if no memory protection violation is detected (in step 435), accessing an element of the subvector before checking whether accessing an element of one of the one or more additional subvectors would result in a memory protection violation using memory protection circuitry 450. Process 400 can provide advantages over conventional techniques, such as, for example, implementing a fast memory protection scan for vector memory operations using simple memory protection circuitry with small circuit area and power consumption. For example, process 400 can use... Figure 1 This is implemented using integrated circuit 110. For example, process 400 can be implemented using... Figure 2It is implemented using the integrated circuit 210.

[0053] Process 400 includes using a processor core (e.g., processor core 220) to fetch 410 vector memory instructions, the processor core including a pipeline configured to execute instructions (including constant stride vector memory instructions). For example, the vector memory instruction may be a vector load instruction 310. For example, the vector memory instruction may be a vector store instruction 330. In some implementations, the 410 vector memory instructions are fetched from memory (e.g., memory 262) via one or more caches (e.g., L1 instruction cache 250).

[0054] Process 400 includes segmenting a vector identified by a vector memory instruction 420 into subvectors with a maximum length greater than one, and one or more long additional subvectors with a length less than or equal to the maximum length. For example, the vectors may be identified in part by parameters of the vector memory instruction, including a base address in memory, element width, and / or a stride specifying where the vector is stored or will be stored in memory. In some embodiments, the maximum length may be determined based on the protection granularity and the stride of the vector (e.g., vector load instruction 310 or vector store instruction 330). For example, process 400 may include determining a maximum length such that the maximum length is proportional to the protection granularity of memory protection circuitry (e.g., memory protection circuitry 150) and inversely proportional to the stride of the vector. For example, the maximum length may be determined as g / s, where g is the protection granularity (e.g., in bytes) and s is the stride of the vector (e.g., in bytes). In some embodiments, the maximum length is limited to a power of two (e.g., the largest power of two is less than or equal to g / s). The maximum length may also depend on the element width of the vector. The maximum length can also depend on the machine width of the processor core executing the instructions, i.e., how many elements of the vector the processor core can process per clock cycle. For example, the maximum length can be determined as min(w,(g / s)), where w is the machine width of the processor core. For example, the vector can be a unit stride vector, such that the stride is one. For example, the vector can have a constant stride greater than one (e.g., the stride can correspond to the length of a row in a matrix to access a column vector of a matrix data structure stored as a row sequence). In some implementations, the maximum length is determined based on the base address of the vector, which can align the subvectors resulting from the vector's partition 420 with the protection granularity in memory, ensuring that all elements of the subvector are located in a single protection granularity to simplify memory protection scanning of the subvector. For example, this simplification can be achieved using memory protection circuitry configured to check a single address per clock cycle, thus requiring less circuit area and consuming less power.

[0055] Process 400 includes using memory protection circuitry to check whether accessing an element of the subvector at 430 would result in a memory protection violation. In some implementations, the memory protection circuitry (e.g., memory protection circuitry 150) is configured to check two addresses per clock cycle. Checking whether accessing an element of the subvector at 430 would result in a memory protection violation involves inputting the address of the first element and the address of the last element of the subvector into the memory protection circuitry during a single clock cycle. For example, this approach may be effective where the maximum length of the subvector ensures that the elements of the subvector can be located in no more than two adjacent protection granularities. In some implementations, where the elements of the subvector are known to be located in a single protection granularity, checking whether accessing an element of the subvector at 430 would result in a memory protection violation can be accomplished by inputting a single address associated with an element of the subvector (e.g., the first element or any other element) into the memory protection circuitry. In some implementations, when using larger subvectors, the complexity associated with checking for memory protection violations of the elements of the subvector at 430 may scale with the number of protection granularities involved. For example, a larger memory protection circuitry with more input address ports could be used to check more elements per clock cycle to improve the execution performance of vector memory instructions.

[0056] If a memory protection violation is detected (in step 435), an exception 440 is raised in response to the detection of a memory protection violation associated with an element of the subvector. In some implementations, raising an exception may halt execution in a processor core (e.g., processor core 120). In some implementations, raising an exception may result in pages being moved from disk to memory (e.g., memory 140 or memory 142).

[0057] If no memory protection violation is detected (in step 435), elements of subvector 450 are accessed before (e.g., using memory protection circuitry 150) a check is performed to determine whether accessing an element of one of the additional subvectors would result in a memory protection violation. For example, accessing elements 450 could include reading the values ​​of those elements from memory (e.g., from memory 140) during the execution of a vector load instruction. Alternatively, accessing elements 450 could include writing the values ​​of those elements to memory (e.g., from memory 140) during the execution of a vector store instruction. Dividing the vector 420 into subvectors for memory protection scans thus allows for greater parallelism in the execution of vector memory instructions and improves the performance of the processing core. While not in Figure 4The document explicitly states that memory protection violations of subvectors of vector 430 can be checked sequentially in series, while previously checked subvectors of 430 continue to be accessed in memory by subsequent stages in the processor core pipeline 450 until all subvectors have been checked 430 and accessed 450 or an exception has been triggered 440.

[0058] Figure 5 This is a flowchart of an example of a memory protection process 500 for vector operations. Process 500 includes determining 510 a maximum length greater than one, corresponding to the number of vector elements to be accessed in a single clock cycle; dividing the vector 520 into subvectors of the maximum length and one or more additional subvectors of length less than or equal to the maximum length; checking 530 whether accessing an element of a subvector would result in a memory protection violation; if a memory protection violation is detected (in step 535), raising an exception 540; and if no memory protection violation is detected (in step 535), accessing an element of the subvector 450, and then using memory protection circuitry to check whether accessing an element of one of the one or more additional subvectors would result in a memory protection violation. Process 500 can provide advantages over conventional techniques, such as, for example, implementing fast memory protection scans for vector memory operations using simple memory protection circuitry with small circuit area and power consumption. For example, process 500 can use... Figure 1 This is implemented using integrated circuit 110. For example, process 500 can be implemented using... Figure 2 It is implemented using the integrated circuit 210.

[0059] Process 500 includes determining a maximum length 510 greater than one, corresponding to the number of vector elements to be accessed in a single clock cycle. The maximum length can be determined based on a protection granularity (e.g., the protection granularity of memory protection circuitry 150) and the stride of the vector identified by the vector memory instructions. In some implementations, the maximum length is proportional to the protection granularity and inversely proportional to the stride. For example, the maximum length 510 can be determined as g / s, where g is the protection granularity (e.g., in bytes) and s is the stride of the vector (e.g., in bytes). In some implementations, the maximum length is limited to a power of two (e.g., the largest power of two is less than or equal to g / s). The maximum length can also depend on the element width of the vector. The maximum length can also depend on the machine width of the processor core executing the instructions, i.e., how many elements of the vector the processor core can process per clock cycle. For example, the maximum length can be determined as min(w, (g / s)), where w is the machine width of the processor core. For example, the vector can be a unit stride vector, such that the stride is one. For example, a vector can have a constant stride greater than one (e.g., the stride can correspond to the length of a row in a matrix to access column vectors in a matrix data structure stored as a row sequence). In some implementations, the maximum length is determined based on the vector's base address 510, which can align the subvectors generated by the vector's partition 520 with the protection granularity in memory, ensuring that all elements of the subvectors are within a single protection granularity, thereby simplifying memory protection scans of the subvectors. For example, this simplification can be achieved using memory protection circuitry configured to check a single address every clock cycle 530, thus requiring less circuit area and consuming less power.

[0060] Process 500 includes partitioning a vector 520 into a subvector of maximum length and one or more additional subvectors of length less than or equal to the maximum length. In some embodiments, partitioning the vector 520 includes assigning groups of consecutive elements of the maximum length of the vector to the corresponding subvectors until all elements of the vector have been assigned to subvectors. For example, if the number of elements in the vector is not divisible by the maximum length, the number of elements in the subvectors may be less than the maximum length. In some embodiments, partitioning the vector 520 includes assigning groups of consecutive elements of the vector of size less than or equal to the maximum length to the corresponding subvectors, wherein each group is known (e.g., based on the base address of the vector, and consequently the addresses of the elements in the group) to be within the boundaries of a single protection granularity of the memory protection circuitry. For example, if the first or last element of a subvector is far from the protection granularity boundary, the number of elements in the subvector may be less than the maximum length.

[0061] Process 500 includes checking whether accessing an element of a subvector by 530 (e.g., using memory protection circuitry) would result in a memory protection violation. In some implementations, the memory protection circuitry (e.g., memory protection circuitry 150) is configured to check two addresses per clock cycle, and checking whether accessing an element of a subvector by 530 would result in a memory protection violation includes inputting the address of the first element and the address of the last element of the subvector to the memory protection circuitry during a single clock cycle. For example, this approach may be effective where the maximum length of the subvector ensures that the elements of the subvector can be located in no more than two adjacent protection granularities. In some implementations, where it is known that the elements of the subvector are in a single protection granularity, checking whether accessing an element of a subvector by 530 would result in a memory protection violation can be done by inputting a single address (e.g., the first element or any other element) associated with an element of the subvector to the memory protection circuitry. In some implementations using larger subvectors, the complexity associated with checking for memory protection violations of the elements of the subvector by 530 can scale with the number of protection granularities involved. For example, a larger memory protection circuit with more input address ports can be used to check more elements per clock cycle to improve the execution performance of vector memory instructions.

[0062] If a memory protection violation is detected (in step 535), an exception is raised at 540 in response to the detection of a memory protection violation associated with an element of the subvector. In some implementations, raising an exception may halt execution in a processor core (e.g., processor core 120). In some implementations, raising an exception may result in pages being moved from disk to memory (e.g., memory 140 or memory 142).

[0063] If no memory protection violation is detected (in step 535), elements of subvector 550 are accessed before (e.g., using memory protection circuitry 150) it is checked whether accessing an element of one of the additional subvectors would result in a memory protection violation. For example, accessing elements 550 could include reading the values ​​of those elements from memory (e.g., from memory 140) during the execution of a vector load instruction. Alternatively, accessing elements 550 could include writing the values ​​of those elements to memory (e.g., from memory 140) during the execution of a vector store instruction. Dividing the vector 520 into subvectors for memory protection scans thus allows for greater parallelism in the execution of vector memory instructions and improves the performance of the processing core. Although not explicitly stated in... Figure 5It is clearly stated that, however, memory protection violations of subvectors of vector 530 can be performed in series, while subvectors previously checked by 530 continue to be accessed in memory by subsequent stages in the processor core pipeline until all subvectors have been checked and accessed or an exception has been triggered.

[0064] Figure 6 This is a flowchart illustrating an example of a memory protection process 600 for vector operations using a memory protection circuit with two input address ports. Process 600 includes determining the maximum length of a subvector 610 such that the elements of the subvector are stored in memory at most two adjacent protection granularities; during a single clock cycle, the addresses of the first and last elements of the subvector 620 are input to check the entire subvector for memory protection violations. By limiting the size of the subvectors in the processed segmented vector, the complexity of performing a memory protection scan for each subvector can be reduced. By adjusting the subvector size limit to the memory protection granularity of the memory protection circuit and the stride and / or element width of the vector, the parallelism and performance of vector memory instruction execution can be increased. Process 600 can provide advantages over conventional techniques, such as, for example, implementing fast memory protection scans for vector memory operations using a simple memory protection circuit with small circuit area and power consumption. For example, Process 600 can use... Figure 1 This is implemented using integrated circuit 110. For example, process 600 can be implemented using... Figure 2 It is implemented using the integrated circuit 210.

[0065] Figure 7 This is a flowchart illustrating an example of a memory protection process 700 for vector operations using a memory protection circuit with a single input address port. Process 700 includes determining sub-vectors segmented at 710 based on the protection granularity of the memory protection circuit and the stride, width, and base address of the vector, such that each sub-vector has an element in only one protection granularity of the memory; and inputting the address of any element (e.g., the first element) of the sub-vector to the memory protection circuit at 720 to check the entire sub-vector for memory protection violations. The segmentation at 710 is determined by comparing the addresses of the vector's elements with the addresses corresponding to the boundaries of the protection granularity of the memory protection circuit, ensuring that all elements of the sub-vector are within a single protection granularity. This reduces the complexity of memory protection scanning for each sub-vector. Process 700 can provide advantages over conventional techniques, such as enabling fast memory protection scanning for vector memory operations using a simple memory protection circuit with small circuit area and power consumption. For example, process 700 can use... Figure 1 This is implemented using integrated circuit 110. For example, process 700 can be implemented using... Figure 2It is implemented using the integrated circuit 210.

[0066] In a first aspect, the subject matter described herein can be embodied in an integrated circuit for executing instructions, the integrated circuit comprising: a processor core including a pipeline configured to execute instructions including constant-step vector memory instructions; memory protection circuitry configured to check for memory protection violations using protection granularity; and vector segmentation circuitry. The vector segmentation circuitry is configured to: determine a maximum length greater than one, corresponding to the number of vector elements to be accessed in a single clock cycle, wherein the maximum length is determined based on the protection granularity and the step size of the vector identified by the vector memory instructions; segment the vector into subvectors of the maximum length and one or more additional subvectors of length less than or equal to the maximum length; check using the memory protection circuitry whether accessing an element of a subvector would result in a memory protection violation; and access the elements of the subvector before checking using the memory protection circuitry whether accessing an element of one of the one or more additional subvectors would result in a memory protection violation.

[0067] In a second aspect, the subject matter described in this specification can be embodied in a method comprising: fetching a vector memory instruction using a processor core, the processor core including a pipeline configured to execute instructions including a constant-step vector memory instruction; segmenting a vector identified by the vector memory instruction into a subvector with a maximum length greater than one, and one or more additional subvectors with a length less than or equal to the maximum length; checking with memory protection circuitry whether accessing an element of a subvector would result in a memory protection violation; and accessing an element of a subvector before checking with memory protection circuitry whether accessing an element of one of the one or more additional subvectors would result in a memory protection violation.

[0068] In a third aspect, the subject matter described herein can be embodied in an integrated circuit for executing instructions, the integrated circuit including a processor core including a pipeline configured to execute instructions including constant-step vector memory instructions; memory protection circuitry configured to check for memory protection violations using protection granularity; and vector segmentation circuitry. The vector segmentation circuitry is configured to: segment a vector identified by the vector memory instructions into subvectors with a maximum length greater than one, and one or more additional subvectors with a length less than or equal to the maximum length; check using the memory protection circuitry whether accessing an element of a subvector would result in a memory protection violation; and access the elements of the subvectors before checking using the memory protection circuitry whether accessing an element of one of the one or more additional subvectors would result in a memory protection violation.

[0069] While this disclosure has been described in conjunction with certain embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments, but rather is intended to cover various modifications and equivalent arrangements included within the scope of the appended claims, which will be given the broadest interpretation to cover all such modifications and equivalent structures.

Claims

1. An integrated circuit for executing instructions, comprising: A processor core, the processor core including a pipeline configured to execute instructions, the instructions including constant stride vector memory instructions; A memory protection circuit, configured to check for memory protection violations using protection granularity; as well as Vector segmentation circuit, the vector segmentation circuit being configured to: A maximum length greater than one is determined, the maximum length corresponding to the number of vector elements to be accessed in a single clock cycle, wherein the maximum length is determined based on the protection granularity and the stride of the vector identified by the vector memory instruction; The vector is divided into a subvector of the maximum length and one or more additional subvectors of a length less than or equal to the maximum length; The memory protection circuitry is used to check whether accessing an element of the subvector would result in a memory protection violation; and Before accessing an element of one of the one or more additional subvectors, the memory protection circuitry checks whether accessing that element would result in a memory protection violation.

2. The integrated circuit according to claim 1, wherein, The memory protection circuit is configured to check two addresses every clock cycle, and the vector segmentation circuit checks whether accessing an element of the sub-vector would result in a memory protection violation, including: During a single clock cycle, the address of the first element of the subvector and the address of the last element of the subvector are input to the memory protection circuit.

3. The integrated circuit according to claim 1, wherein, The memory protection circuit is configured to check a single address every clock cycle, and the vector segmentation circuit is configured to: The maximum length is determined based on the base address of the vector.

4. The integrated circuit according to claim 1, wherein, The maximum length is directly proportional to the protection granularity and inversely proportional to the stride.

5. The integrated circuit according to claim 1, wherein, The maximum length is a power of two.

6. The integrated circuit according to claim 1, wherein, The vector is a unit stride vector, such that the stride is one.

7. The integrated circuit according to claim 1, wherein, The vector segmentation circuit is part of the execution phase of the pipeline.

8. The integrated circuit according to claim 1, wherein, The integrated circuit is configured as follows: An exception is raised in response to the detection of a memory protection violation associated with an element of one of the one or more additional subvectors.

9. A method comprising: Using a processor core to fetch vector memory instructions, the processor core including a pipeline configured to execute instructions including constant stride vector memory instructions; The vector identified by the vector memory instruction is divided into sub-vectors with a maximum length greater than one, and one or more additional sub-vectors with a length less than or equal to the maximum length; Use memory protection circuitry to check whether accessing an element of the subvector would result in a memory protection violation; as well as Before accessing an element of one of the one or more additional subvectors, the memory protection circuitry checks whether accessing that element would result in a memory protection violation.

10. The method according to claim 9, wherein, The memory protection circuit is configured to check two addresses every clock cycle, and to check whether accessing an element of the subvector would result in a memory protection violation, including: During a single clock cycle, the address of the first element of the subvector and the address of the last element of the subvector are input to the memory protection circuit.

11. The method according to claim 9, wherein, The memory protection circuit is configured to check a single address every clock cycle and includes: The maximum length is determined based on the base address of the vector.

12. The method of claim 9, comprising: The maximum length is determined such that it is proportional to the protection granularity of the memory protection circuit and inversely proportional to the step size of the vector.

13. The method according to claim 9, wherein, The maximum length is a power of two.

14. The method according to claim 9, wherein, The vector is a unit stride vector.

15. The method of claim 9, comprising: An exception is raised in response to the detection of a memory protection violation associated with an element of one of the one or more additional subvectors.

16. An integrated circuit for executing instructions, comprising: A processor core, the processor core including a pipeline configured to execute instructions, the instructions including constant stride vector memory instructions; A memory protection circuit, configured to check for memory protection violations using protection granularity; as well as Vector segmentation circuit, the vector segmentation circuit being configured to: The vector identified by the vector memory instruction is divided into sub-vectors with a maximum length greater than one, and one or more additional sub-vectors with a length less than or equal to the maximum length; The memory protection circuitry is used to check whether accessing an element of the subvector would result in a memory protection violation. as well as Before accessing an element of one of the one or more additional subvectors, the memory protection circuitry checks whether accessing that element would result in a memory protection violation.

17. The integrated circuit according to claim 16, wherein, The memory protection circuit is configured to check two addresses every clock cycle, and the vector segmentation circuit checks whether accessing an element of the sub-vector would result in a memory protection violation, including: During a single clock cycle, the address of the first element of the subvector and the address of the last element of the subvector are input to the memory protection circuit.

18. The integrated circuit according to claim 16, wherein, The memory protection circuit is configured to check a single address every clock cycle, and the vector segmentation circuit is configured to: The maximum length is determined based on the base address of the vector.

19. The integrated circuit according to claim 16, wherein, The vector segmentation circuit is configured as follows: The maximum length is determined such that it is proportional to the protection granularity and inversely proportional to the step size of the vector.

20. The integrated circuit according to claim 16, wherein, The vector is a unit step vector.

21. The integrated circuit according to claim 16, wherein, The maximum length is a power of two.

22. The integrated circuit according to claim 16, wherein, The vector segmentation circuit is part of the execution phase of the pipeline.

23. The integrated circuit according to claim 16, wherein, The integrated circuit is configured as follows: An exception is raised in response to the detection of a memory protection violation associated with an element of one of the one or more additional subvectors.

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