Efficient handling of shielded memory accesses

Abstract

Disclosed herein are systems and methods for handling masked memory accesses that include handling fault exceptions and checking memory attributes of the memory region(s) to be accessed. Implementations target a two-level memory protection violation scheme for masked vector memory instructions. A first level memory check ignores the masking information associated with the masked vector memory instruction and operates on the memory occupancy associated with the masked vector memory instruction. If a memory protection violation is detected or a speculative access is denied with respect to the memory occupancy, a second level memory check evaluates the masking information at the vector element level to determine whether a fault exception should be raised. If the masking bit for a vector element is set and a memory violation is detected, a fault exception is raised for the masked vector memory instruction. If the masking bit is not set, execution of the masked vector memory instruction can continue.

Description

Technical Field

[0001] This disclosure relates to the execution of instructions in a processor, specifically the process of masking memory accesses. Background Technology

[0002] Processor cores can include scalar and vector processing units or machines to efficiently process scalar and vector instructions respectively, thereby supporting a wide range of implementations and use cases, such as the Internet of Things (IoT), edge processing, and data center processing. These processor cores can execute instructions in sequence or out of order.

[0003] Vector processing units can execute vector memory instructions, such as vector loads or vector stores, in several cycles. Therefore, both in-order and out-of-order processor cores and vector processing units allow multiple vector instructions to be processed in the processing pipeline. That is, the next vector instruction can begin processing before the current vector instruction has finished. This can happen even when the vector instructions are all vector memory instructions requiring memory access and are subject to fault exceptions.

[0004] Some vector memory instructions are masked vector memory instructions. Masked vector memory instructions, such as masked vector loads and / or masked vector stores, can be complex operations that require many clock cycles to execute. Masking can be used to mask elements of N-element vector memory instructions that are unnecessary or should not be executed.

[0005] Given fault exceptions and mask vectors, the execution of memory instructions can be complex. Current techniques cannot provide efficient processing of mask vector memory instructions that include fault exception handling and checking the memory properties of the memory(s)(s) to be accessed. Summary of the Invention Attached Figure Description

[0006] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, by convention, the various features in the drawings are not drawn to scale. Instead, for clarity, the dimensions of the various features have been arbitrarily enlarged or reduced.

[0007] Figure 1 This is a block diagram of an example integrated circuit for executing instructions for efficiently processing masked vector memory accesses according to embodiments of the present disclosure.

[0008] Figure 2 This is a block diagram of an example integrated circuit for executing instructions for efficiently processing masked vector memory accesses according to embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart illustrating an example of a process for efficiently processing masked vector memory access according to embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart illustrating an example of a process for efficiently processing masked vector memory access according to embodiments of the present disclosure.

[0011] Figure 5 This is a flowchart illustrating an example of a process for efficiently processing masked vector memory access according to embodiments of the present disclosure. Detailed Implementation

[0012] This article discloses a system and method for efficiently handling masked memory access, including fault and exception handling and inspecting memory properties of memory(s) regions to be accessed.

[0013] The implementation described in this paper can be used to increase throughput and efficiency by implementing a two-level memory protection violation scheme for masked vector memory instructions. The first-level or conservative memory check ignores masking information associated with the masked vector memory instruction and operates on the memory occupancy associated with the instruction. If no memory protection violation is detected relative to the memory occupancy and the memory attributes within the occupancy indicate idempotency, execution of the masked vector memory instruction can continue. This results in optimized execution of the masked vector memory instruction. If a memory protection violation is detected relative to the memory occupancy or speculative access is not allowed, the second-level or precise memory check evaluates information at the vector element level to determine whether a fault exception should be raised. That is, vector elements are processed individually and sequentially. If the mask bit of a vector element is set and a memory protection violation for that vector element is detected, a fault exception is raised for the masked vector memory instruction. If the mask bit of a vector element is set and no memory protection violation is detected, the corresponding memory access is performed and execution can continue. If the mask bit is not set, no memory access is performed, and execution of the masked vector memory instruction can continue. The two-level memory protection violation scheme can improve throughput and efficiency by analyzing information only when a potential memory protection violation is detected, rather than checking the masking information for each masked vector memory instruction.

[0014] The implementation described in this paper checks the idempotency of memory usage associated with masked vector memory instructions. Idempotency indicates whether speculative access is allowed for a memory usage or memory region(s). That is, whether a read / write access to a memory usage or memory region(s) has side effects. For example, whether it's an access to a cacheable device or an input / output (I / O) device. If the access is non-idempotent, i.e., accessing the memory region has potential side effects, speculative access is not allowed.

[0015] In this implementation, fault handling and memory attribute checks can be performed in parallel or sequentially. For example, fault handling can be performed after memory attribute checks.

[0016] These and other aspects of this disclosure are disclosed in the following detailed description, the appended claims, and the accompanying drawings.

[0017] As used herein, the term “processor” refers to one or more processors, such as one or more dedicated processors, one or more digital signal processors, one or more microprocessors, one or more controllers, one or more microcontrollers, one or more application processors, one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more application-specific integrated circuits (ASICs), one or more dedicated standard products, one or more field-programmable gate arrays, any other type of integrated circuit or combination thereof, one or more state machines or any combination thereof.

[0018] The term "circuit" refers to an arrangement of electronic components (e.g., transistors, resistors, capacitors, and / or inductors) configured to perform one or more functions. For example, a circuit may include one or more interconnected transistors to form logic gates that collectively perform a logic function.

[0019] As used herein, the terms “determine” and “identify” or any variations thereof include selecting, confirming, calculating, searching, receiving, determining, establishing, obtaining or otherwise identifying or determining using one or more devices and methods shown and described herein.

[0020] As used herein, the terms “example,” “implementation,” “aspect,” “feature,” or “element” indicate that they serve as examples, instances, or illustrations. Unless expressly indicated, any example, embodiment, implementation, aspect, feature, or element is independent of other examples, embodiments, implementations, aspects, features, or elements and may be used in conjunction with any other example, embodiment, implementation, aspect, feature, or element.

[0021] As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise stated or clear from the context, “X includes A or B” is intended to indicate any natural inclusion arrangement. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A or B” is satisfied in any of the foregoing cases. Additionally, the articles “a” and “an” used in this application and the appended claims should generally be interpreted as meaning “one or more” unless otherwise stated or clearly indicated from the context to the singular form.

[0022] Furthermore, for the sake of simplicity of explanation, although the accompanying drawings and descriptions may include a sequence or series of steps or stages, the elements of the methods disclosed herein may occur in various orders or simultaneously. Furthermore, the elements of the methods disclosed herein may occur together with other elements not explicitly presented and described herein. Moreover, not all elements of the methods described herein are required to implement the methods according to this disclosure. Although aspects, features, and elements are described herein in specific combinations, each aspect, feature, or element may be used independently or in various combinations, together or separately, with other aspects, features, and elements.

[0023] It should be understood that the accompanying drawings and descriptions of the embodiments have been simplified to illustrate elements relevant to clear understanding, while many other elements found in typical processors have been omitted for clarity. Those skilled in the art will recognize that other elements and / or steps are desirable and / or necessary in implementing this disclosure. However, because such elements and steps are not conducive to a better understanding of this disclosure, a discussion of these elements and steps is not provided herein.

[0024] Figure 1 This is a block diagram of an example of an integrated circuit 1100 for efficient processing of masked vector memory accesses, which includes efficient handling of exceptions to masked vector memory accesses and checking the memory attributes of the memory region(s) to be accessed. The integrated circuit 1100 includes at least one processor core 1200, which can include a scalar processing unit 1210, a vector processing unit 1220, a register file(s) 1230, an L1 instruction cache 1240, an L1 data cache 1250, an L2 cache 1260, and memory protection circuitry 1270. At least one processor core 1200 can be connected to or communicate with memory 1500 (collectively, "connected to") via the L1 instruction cache 1240, L1 data cache 1250, L2 cache 1260, interconnect unit 1300, and memory controller 1400, as appropriate and applicable. In one implementation, the memory protection circuitry 1270 can be external to the processor core 1200 and internal to the integrated circuit 1100. In one implementation, the memory 1500 is external to the integrated circuit 1100. The integrated circuit 1100 and each element or component within it are illustrative and can include additional, fewer, or different devices, entities, elements, components, etc., which may be constructed similarly or differently without departing from the scope of this specification and claims. Furthermore, the illustrated devices, entities, elements, and components are capable of performing other functions without departing from the scope of this specification and claims.

[0025] Integrated circuit 1100 and / or processor core 1200 can be configured to decode and execute instructions of an instruction set architecture (ISA) (e.g., RISC-V instruction set). Instructions can be executed speculatively and out of order within integrated circuit 1100 and / or processor core 1200. Integrated circuit 1100 and / or processor core 1200 can implement a pipelined architecture that includes pipeline stages such as fetch, decode, rename, dispatch, release, execution, memory access, and write-back stages.

[0026] Processor core 1200 and / or scalar processing unit 1210 can be configured to fetch instructions from L1 instruction cache 1240, L1 data cache 1250, L2 cache 1260 and / or memory 1500 and access data stored therein, when appropriate and applicable. Processor core 1200 and / or scalar processing unit 1210 can be configured to fetch instructions from L1 instruction cache 1240, L2 cache 1260 and / or memory 1500, when appropriate and applicable. Processor core 1200, scalar processing unit 1210, and / or vector processing unit 1220 can be configured to access data in L1 data cache 1250, L2 cache 1260 and / or memory 1500, when appropriate and applicable, in response to instructions. For example, the vector processing unit 1220 can be configured to access data in the L1 data cache 1250, the L2 cache 1260 and / or the memory 1500 as vector instructions, which include, but are not limited to, vector memory instructions, such as vector load instructions, vector store instructions, masked vector load instructions, or masked vector store instructions.

[0027] The memory protection circuit 1270 can be used to monitor transactions, including instruction fetching and data access of the processor core 1200, scalar processing unit 1210, and / or vector processing unit 1220, and can trigger a fault exception when a memory protection violation relative to a transaction is detected. For example, attempting to access unauthorized memory may result in hardware failure (e.g., segmentation fault, memory violation exception, or abnormal termination of the violating process). The memory protection circuit 1270 can be used to prevent processes from accessing memory not allocated to them, which can prevent errors or malware within a process from affecting other processes or the operating system.

[0028] Memory protection circuit 1270 can be configured to perform memory protection checks on one or more addresses using protection granularity, or to check for memory protection violations using protection granularity. Memory protection circuit 1270 can allow privileged software to define memory regions and assign memory access permissions to each of them. The protection granularity of memory protection circuit 1270 limits the size and therefore resolution of these memory regions with associated access permissions. For example, the protection granularity may correspond to a memory page (e.g., 4kB or 8kB page). In some implementations, memory protection circuit 1270 also specifies memory attributes for these memory regions, which may specify sorting and merging behavior, cache and buffer attributes, and idempotency attributes. Memory protection circuit 1270 can check idempotency memory attributes to determine whether speculative access is allowed for the memory region(s) or memory occupancy(s) associated with an instruction.

[0029] The memory protection circuit 1270 can have various sizes and complexities. In some implementations, the memory protection circuit 1270 is configured to check two addresses per clock cycle. For example, the memory protection circuit 1270 may have two address ports that allow it to receive two addresses during a single clock cycle and independently check two addresses in memory for memory protection violations. For example, the address can be checked by comparing a memory protection key or ring number of the memory region including the address with a memory protection key or ring number associated with a process executed by the processor core 1200 that attempts to access the memory at that address. In some implementations, the memory protection circuit 1270 is configured to check a single address per clock cycle, and therefore can occupy less circuit area and consume less power. In some implementations, the memory protection circuit 1270 may have two or more address ports, or otherwise be configured to check two or more addresses or address ranges for memory protection violations per clock cycle.

[0030] The memory protection circuit 1270 can be configured to perform two-level or two-stage memory protection checks on masked vector memory instructions. That is, the memory protection circuit 1270 can perform a conservative-level memory protection violation check without considering masking information, and, if necessary, perform a precise-level memory protection violation check on the masked vector memory instructions with consideration of masking information. In one implementation, the conservative-level memory protection violation check can be based on memory occupancy and without considering masking information. In another implementation, the precise-level memory protection violation check can be an element-by-element check that considers masking information.

[0031] In the first level, the memory protection circuit 1270 can be configured to monitor masked vector memory instructions relative to or at the scalar processing unit 1210. When a memory protection violation is detected, the memory protection circuit 1270 can trigger a fault exception without considering the masking information associated with the vector identified by the masked vector memory instructions. In an implementation, the memory protection circuit 1270 can determine whether a memory occupation of a memory address or address range associated with the vector constitutes a memory protection violation by checking whether the memory occupation is based on the protection granularity, a defined subset of the memory address or memory address range, the start and end memory addresses, the defined memory region, and / or other techniques for defining memory occupations that ignore masking information and are not performed at the element-by-element level for the entire memory address or memory address range associated with the vector. If the memory protection circuit 1270 does not trigger a fault exception based on memory occupation, and speculative access is permitted relative to the memory occupation, the masking information can be ignored and the execution of the masked vector memory instructions can continue (which can be performed in parallel or sequentially after exception handling). If the memory protection circuit 1270 detects a memory protection violation based on memory occupancy or determines that speculative access is not allowed, during processing at the scalar processing unit 1210, the memory protection circuit 1270 can perform a precise level memory protection violation check while taking into account masking information.

[0032] The memory protection circuit 1270 can be configured to wait until the mask register is loaded with masking information by the vector processing unit 1220. For example, the mask register can be one of the register files 1230. Therefore, a second or more precise level of memory protection violation checking can be performed relative to or at the vector processing unit 1220. The memory protection circuit 1270 can be configured to determine the presence of a memory protection violation element-by-element using masking information associated with the element under consideration. For example, if a mask bit is enabled or set for a vector element, and a memory protection violation is detected for that vector element, the memory protection circuit 1270 can trigger a fault exception for the masked vector memory instruction. For example, if a mask bit is enabled or set for a vector element, and no memory protection violation is detected for that vector element, the corresponding memory access is performed, and the execution of the masked vector memory instruction can continue to be masked. For example, if a mask bit is disabled or not set for a vector element, no memory access is performed for that vector element, and the execution of the masked vector memory instruction can continue to be masked. In the event of a fault or abnormality caused by the memory protection circuit 1270, the operating system running on the integrated circuit 1100 and / or the processor core 1200 can stop execution in the processor core 1200, and can cause pages to move from the disk to the memory 1500 and / or eventually to the L1 data cache 1250 and / or the L2 cache 1260, and / or perform other fault or abnormality handling.

[0033] Memory protection circuit 1270 can be configured to perform memory attribute checks on masked vector memory instructions. Memory protection circuit 1270 can be configured to monitor masked vector memory instructions relative to or at scalar processing unit 1210. Without considering masking information, memory protection circuit 1270 can check whether memory attributes associated with memory occupancy of a memory address or address range associated with a vector allow speculative access or are idempotent. If speculative access is allowed for memory occupancy, i.e., access to cacheable memory is being made, execution of the masked vector memory instruction can continue. If the access is non-idempotent, i.e., there are potential side effects from accessing the memory region and speculative access is not allowed, a precise level of memory protection violation check considering masking information is performed.

[0034] Integrated circuit 1100 can offer advantages over conventional processor architectures, such as efficient fault handling for masked vector memory operations using simple memory protection circuitry with small circuit area and low power consumption. In its implementation, integrated circuit 1100 can achieve... Figure 3 Process 3000 Figure 4 The process 4000, and / or a combination thereof.

[0035] Figure 2 This is a block diagram of an example integrated circuit 2100 for processing masked vector memory access according to embodiments of the present disclosure, including efficient handling of exceptions to masked vector memory access and checking memory attributes of the memory region(s) to be accessed.

[0036] Integrated circuit 2100 includes a processor core 2200. The processor core 2200 includes a processor pipeline 2220 that includes efficient fault exception handling for masked vector memory instructions. The processor core 2200 includes one or more register files 2210, which may include scalar registers, vector registers, control and status registers (CSRs), and / or vector mask registers capable of storing masking information of vectors identified in masked vector memory instructions. The processor core 2200 includes an L1 instruction cache 2230 and an L1 data cache 2240. Integrated circuit 2100 includes an external memory system 2300, which may include memory for storing instructions and data and / or provide access to memory 2400 external to integrated circuit 2100 for storing instructions and / or data. External memory system 2300 includes memory protection circuitry 2310, which can be configured to use a two-level memory protection violation detection scheme and check the memory attributes of the memory region(s)(s) to be accessed to perform efficient fault handling for masked vector memory instructions. Integrated circuit 2100 can provide advantages over conventional processor architectures, such as achieving efficient fault handling for masked vector memory instructions using a simple memory protection circuit with small circuit area and low power consumption. For example, integrated circuit 2100 can implement... Figure 3 Process 3000 Figure 4 The process 4000, or a combination thereof.

[0037] Pipeline 2220 can be configured to execute instructions, including masked vector memory instructions. Pipeline 2220 includes one or more fetch stages configured to retrieve instructions from the memory system of integrated circuit 2100. For example, pipeline 2220 can fetch instructions via L1 instruction cache 2230 and access data from L1 data cache 2240. Pipeline 2220 can include additional stages such as decoding, renaming, dispatching, issuing, executing, memory accessing, and write-back stages. For example, pipeline 2220 can be configured to execute instructions from the RISC V instruction set.

[0038] The L1 instruction cache 2230 can be a set-associative cache for instruction memory. To avoid the long latency of serial reads of the tag array and data array, and the high power consumption of the parallel read array, a route predictor can be used. The route predictor can be accessed in the early fetch stage and the hit route can be encoded into the read index of the data array. The tag array can be accessed in a later fetch stage and can be used to verify the route predictor.

[0039] The L1 data cache 2240 can be a set-associative VIPT cache, meaning it is indexed purely using virtual address bits VA[set] and fully labeled using all translated physical address bits PA[msb:12]. For low power consumption, tags and data arrays can be looked up serially, allowing access to at most a single data SRAM path. For example, the L1 data cache 252 can have a row size of 64 bytes and a tick size of 26 bytes.

[0040] External memory system 2300 may include memory for storing instructions and data and / or provide access to memory 2400 for storing instructions and / or data. For example, external memory system 2300 may include an L2 cache, which may be configured to implement a cache coherence protocol / policy to maintain cache coherence across multiple L1 caches. Although Figure 2 Although not shown in the diagram, in some implementations, integrated circuit 2100 can include multiple processor cores. For example, external memory system 2300 can include multiple layers.

[0041] The memory protection circuit 2310 can be configured to monitor transactions, including instruction fetching and data access of the processor core 2200, and can trigger a fault exception when a memory protection violation is detected relative to a transaction. For example, attempting to access unauthorized memory may result in hardware failure (e.g., segmentation fault, memory violation exception, or abnormal termination of the violating process). The memory protection circuit 2310 can be used to prevent processes from accessing memory not allocated to them, which can prevent errors or malware within a process from affecting other processes or the operating system.

[0042] Memory protection circuit 2310 can be configured to perform memory protection violation checks on one or more addresses using protection granularity, or to check for memory protection violations using protection granularity. Memory protection circuit 2310 can allow privileged software to define memory regions and assign memory access permissions to each of them. The protection granularity of memory protection circuit 2310 limits the size and therefore resolution of these memory regions with associated access permissions. For example, the protection granularity may correspond to a page of memory (e.g., 4kB or 8kB pages). In some implementations, memory protection circuit 2310 also specifies memory attributes for these memory regions, which may specify sorting and merging behavior, cache and buffer attributes, and idempotency attributes. Memory protection circuit 2310 is able to check idempotency attributes to determine whether speculative access is permitted for the memory region(s) or memory occupancy(s) associated with an instruction.

[0043] The memory protection circuit 2310 can have various sizes and complexities. In some implementations, the memory protection circuit 2310 is configured to check two addresses per clock cycle. For example, the memory protection circuit 2310 may have two address ports that allow it to receive two addresses during a single clock cycle and independently check two addresses in memory for memory protection violations. For example, the address can be checked by comparing the memory protection key or ring number of the memory region including the address with the memory protection key or ring number associated with a process executed by processor core 2200 that attempts to access memory at that address. In some implementations, the memory protection circuit 2310 is configured to check a single address per clock cycle, and therefore can occupy less circuit area and consume less power. In some implementations, the memory protection circuit 2310 may have two or more address ports, or be otherwise configured to check two or more addresses or address ranges for memory protection violations per clock cycle.

[0044] The memory protection circuit 2310 can be configured to perform two-level or two-stage memory protection violation checks on masked vector memory instructions. That is, the memory protection circuit 2310 can perform conservative-level memory protection violation checks without considering masking information, and, if necessary, perform precise-level memory protection violation checks on masked vector memory instructions with consideration of masking information. In one implementation, the conservative-level memory protection violation check can be based on memory occupancy and without considering masking information. In another implementation, the precise-level memory protection violation check can be an element-by-element check that considers masking information.

[0045] In the first stage, memory protection circuitry 2310 can be configured to monitor masked vector memory instructions at the execution phase of pipeline 2220, and specifically, monitor processing being executed relative to scalar units in processor core 2200. When a memory protection violation is detected, memory protection circuitry 2310 can trigger a fault exception, regardless of masking information associated with the vector identified by the masked vector memory instructions. In an implementation, memory protection circuitry 2310 can determine whether memory occupancy of the memory address or address range associated with the vector would result in a fault exception, regardless of masking information. For example, memory occupancy can be based on protection granularity, a defined subset of memory addresses or memory address ranges, start and end memory addresses, defined memory regions, and / or other techniques used to define memory occupancy that ignores masking information and is not performed at the element-by-element level for the entire memory address or memory address range associated with the vector. If the memory protection circuit 2310 does not cause a fault exception based on memory occupancy, and speculative access is permitted for memory occupancy, then the masking information can be ignored and the execution of vector memory instructions can continue to be masked (this can be performed in parallel or sequentially after exception handling). If the memory protection circuit 2310 detects a memory protection violation based on memory occupancy or determines that speculative access is not permitted during processing at a scalar unit, then the memory protection circuit 2310 can perform a precise level memory protection check while taking into account the masking information.

[0046] The memory protection circuit 2310 can be configured to wait until masking information is loaded into the mask register during processing of vector units in processor core 2200. The memory protection circuit 2310 can be configured to determine element-by-element whether a memory protection violation exists using the masking information associated with the element under consideration. For example, if a mask bit is enabled or set for a vector element and a memory protection violation is detected for that vector element, the memory protection circuit 2310 can trigger a fault exception for the masked vector memory instruction. For example, if a mask bit is enabled or set for a vector element and no memory protection violation is detected for that vector element, the corresponding memory access is performed, and the execution of the masked vector memory instruction can continue to be masked. For example, if a mask bit is disabled or not set for a vector element, no memory access is performed for that vector element, and the execution of the masked vector memory instruction can continue to be masked.

[0047] In the event of a fault caused by the memory protection circuit 2310, the operating system running on the integrated circuit 2100 and / or the processor core 2200 can stop execution in the pipeline 2220 and / or the processor core 2200, and can cause pages to move from the disk to the memory 2400, external memory 2300, and / or eventually to the L1 data cache 2240, and / or perform other fault handling.

[0048] Memory protection circuit 2310 can be configured to perform memory attribute checks at the execution stage in pipeline 2220, and specifically, to perform memory attribute checks relative to scalar units in processor core 2200. Memory protection circuit 2310 can perform memory attribute checks without considering masking information associated with a vector identified by a masked vector memory instruction. In an implementation, memory protection circuit 2310 can check the memory attributes of memory occupancy associated with the vector without considering masking information. Memory protection circuit 1270 can check whether the memory attributes of memory occupancy associated with the vector allow speculative access or are idempotent without considering masking information. If speculative access is allowed for memory occupancy, i.e., access to cacheable memory is being made, execution of the masked vector memory instruction can continue. If the access is non-idempotent, i.e., there are potential side effects from accessing the memory region and speculative access is not allowed, a precise level memory protection violation check considering masking information is performed.

[0049] Integrated circuit 2100 offers advantages over conventional processor architectures, such as efficient fault handling for masked vector memory operations using simple memory protection circuitry with small circuit area and low power consumption. In its implementation, integrated circuit 2100 can achieve... Figure 3 Process 3000 Figure 4 The process 4000, and / or combinations thereof.

[0050] Figure 3 This is a diagram of an exemplary technique 3000 for efficiently handling exceptions on masked vector memory accesses according to embodiments of the present disclosure. Technique 3000 includes: monitoring 3100 a masked vector memory instruction; performing a 3200 memory protection violation check based on memory occupancy of the masked vector memory instruction, and ignoring masking information associated with a vector identified by the masked vector memory instruction; performing a 3300 memory protection violation check on vector elements of the vector in the event of a memory protection violation based on memory occupancy; triggering a 3400 fault exception if a mask bit is enabled for the vector element; and continuing execution of the 3500 masked vector memory instruction if no memory protection violation is detected for the vector element. It can be used where applicable and appropriate. Figure 1 Integrated circuit 1100, Figure 1 Processor core 1200, Figure 1 Scalar processing unit 1210 Figure 1 Vector processing unit 1220 Figure 1 (Multiple) register files 1230, Figure 1 Memory protection circuit 1270 Figure 2 Integrated circuit 2100, Figure 2 Processor core 2200, Figure 2 Assembly line 2220 Figure 2 The (multiple) register files 2210, and / or Figure 2 The memory protection circuit 2310 is used to implement the technology 3000.

[0051] Technology 3000 includes monitoring 3100 masked vector memory instructions. The memory protection circuitry is capable of monitoring vector memory instructions, including masked vector memory instructions. The memory protection circuitry is capable of monitoring vector memory instructions in the processor core during scalar unit processing or operation and during vector unit processing or operation.

[0052] Technique 3000 includes performing a 3200 memory protection violation check based on memory occupancy of a masked vector memory instruction, and ignoring masking information associated with a vector identified by the masked vector memory instruction. A vector can have N vector elements. The memory protection circuitry is capable of performing a memory violation check during scalar processing without considering masking information. The memory protection circuitry uses memory occupancy associated with a memory address range related to the masked vector memory instruction. Various techniques can be used to determine memory occupancy as described herein and as described in U.S. Provisional Patent Application Serial No. 63 / 073,916, filed September 2, 2020, entitled “Memory Protection for Vector Operations” (which is incorporated herein by reference in its entirety).

[0053] Technique 3000 includes performing a 3300 memory protection violation check on vector elements of a vector in the event of a memory protection violation based on memory occupancy. Instead of triggering a fault exception after a memory protection violation is detected based on memory occupancy, the memory protection circuitry waits for the vector processing unit to complete loading masking information into the mask or vector register. In this implementation, the loading of the mask register is independent of memory protection violation handling. In this implementation, other operations have already initiated the loading of the mask register. After the masking information of the vector is loaded into the mask register, the memory protection circuitry determines whether mask bits are enabled for each vector element in the vector. Enabled mask bits indicate that the memory address(s) associated with the vector element are relevant, for example, that the memory address(s) will be used or processed. Unenabled bits indicate that the memory address is not relevant.

[0054] Technique 3000 includes triggering a 3400 fault exception if the mask bit is enabled and a memory violation is detected for a vector element. If the mask bit is enabled and a memory violation is detected for a vector element, the memory protection circuitry triggers a fault exception. The operating system performs fault exception handling relative to the mask vector memory instruction, which includes various procedures such as suspending the execution of the mask vector memory instruction and troubleshooting page faults from the disk.

[0055] Technique 3000 includes continuing execution of the mask vector memory instruction if no memory protection violation is detected for a vector element. If the mask bit of a vector element is set and no memory protection violation is detected for that vector element, the corresponding memory access is performed, and execution can continue. The memory protection circuitry ignores any memory protection violations associated with vector elements whose mask bits are not enabled or set. Memory attribute checks can be performed in parallel or sequentially after fault exception handling. Memory attribute checks (e.g., based on memory occupancy) can be performed without considering masking information. If speculative access is denied, a memory protection violation check is performed for the vector elements of the vector. If speculative access to memory occupancy or memory region(s) is allowed, i.e., it is cacheable memory, the execution of the mask vector memory instruction can continue. Optimized execution occurs when execution is performed without considering masking information and when memory violation checks and memory attribute checks are passed. If the access without considering masking information is non-idempotent, i.e., accessing the memory region has potential side effects, speculative access is not allowed.

[0056] Figure 4This is a diagram of an exemplary technique 4000 for efficiently handling exceptions on masked vector memory accesses according to embodiments of the present disclosure. Technique 4000 includes: processing 4100 a masked vector memory instruction at a scalar unit; monitoring 4200 the scalar processing of the masked vector memory instruction; performing 4300 a first-level memory protection violation check during scalar processing, which ignores masking information associated with a vector identified by the masked vector memory instruction; waiting 4400 until the mask register is loaded during vector processing of the masked vector memory instruction; performing 4500 a second-level memory protection violation check on vector elements of the vector during vector processing, in the case of memory protection violation detection from the first-level memory check; triggering 4600 a fault exception if a mask bit is enabled for a vector element; and continuing 4700 execution of the masked vector memory instruction if no memory protection violation is detected for a vector element. It can be used where applicable and appropriate. Figure 1 Integrated circuit 1100, Figure 1 Processor core 1200, Figure 1 Scalar processing unit 1210 Figure 1 Vector processing unit 1220 Figure 1 (Multiple) register files 1230, Figure 1 Memory protection circuit 1270 Figure 2 Integrated circuit 2100, Figure 2 Processor core 2200, Figure 2 Assembly line 2220 Figure 2 The (multiple) register files 2210, and / or Figure 2 The memory protection circuit 2310 is used to implement the technology 4000.

[0057] Technology 4000 includes processing 4100 masked vector memory instructions at scalar units. The scalar processing unit in the processing system fetches instructions from the memory system and decodes the fetched instructions for execution.

[0058] Technology 4000 includes monitoring scalar processing of 4200 masked vector memory instructions. The memory protection circuitry is capable of monitoring vector memory instructions, including masked vector memory instructions. The memory protection circuitry can monitor vector memory instructions in the processor core during both scalar unit processing or operation and vector unit processing or operation.

[0059] Technique 4000 includes performing a Level 1 memory protection violation check (4300) during scalar processing, which ignores masking information associated with a vector identified by a masked vector memory instruction. The vector can have N vector elements. The memory protection circuitry is capable of performing a memory violation check during scalar processing without considering masking information. The memory protection circuitry uses memory occupancy associated with the memory address range associated with the masked vector memory instruction. Various techniques can be used to determine memory occupancy as described herein and in U.S. Provisional Patent Application Serial No. 63 / 073,916, filed September 2, 2020, entitled “Memory Protection for Vector Operations” (which is incorporated herein by reference in its entirety).

[0060] Technique 4000 includes waiting 4400 during vector processing of the masked vector memory instruction until the mask register is loaded. Instead of triggering a fault exception after a memory protection violation is detected based on memory occupancy, the memory protection circuitry waits for the vector processing unit to complete loading the masking information into the mask or vector register. In this implementation, the loading of the mask register is independent of memory protection violation handling. In this implementation, other operations have already initiated the loading of the mask register.

[0061] Technique 4000 includes performing a Level 4500 second-level memory protection violation check on vector elements during vector processing, in the event of a memory protection violation detection from a Level 1 memory check. After the mask register is loaded with the mask information of the vector, the memory protection circuitry determines whether mask bits are enabled for each vector element in the vector. Enabled mask bits indicate that the memory address(s) associated with the vector element is relevant, for example, that the memory address(s) will be used or processed. Unenabled bits indicate that the memory address is not relevant.

[0062] Technique 4000 includes triggering a 4600 fault exception if the mask bit is enabled and a memory violation is detected for a vector element. If the mask bit is enabled and a memory violation is detected for a vector element, the memory protection circuitry triggers a fault exception. The operating system performs fault exception handling relative to the mask vector memory instruction, which includes various procedures such as suspending the execution of the mask vector memory instruction and troubleshooting page faults from the disk.

[0063] Technique 4000 includes continuing execution of the mask vector memory instruction 4700 if no memory protection violation is detected for a vector element. If the mask bit of a vector element is set and no memory protection violation is detected for that vector element, the corresponding memory access is performed, and execution can continue. The memory protection circuitry ignores any memory protection violations associated with vector elements whose mask bits are not enabled or set. Memory attribute checks can be performed in parallel or sequentially after fault exception handling. Memory attribute checks (e.g., based on memory occupancy) can be performed without considering masking information. If speculative access is denied, a memory protection violation check is performed on the vector elements of the vector. If speculative access is allowed for memory occupancy or memory region(s), i.e., it is cacheable memory, the execution of the mask vector memory instruction can continue. Optimized execution occurs when execution is performed without considering masking information and passes memory violation and memory attribute checks. If the access without considering masking information is non-idempotent, i.e., accessing the memory region has potential side effects, speculative access is not allowed.

[0064] Figure 5 This is a diagram of an exemplary technique 5000 for efficiently handling exceptions on masked vector memory accesses according to embodiments of the present disclosure. Technique 5000 includes: monitoring 5100 a masked vector memory instruction; performing 5200 a memory protection violation check and memory attribute check based on memory occupancy of the masked vector memory instruction, and ignoring masking information associated with a vector identified by the masked vector memory instruction; performing 5300 a memory protection violation check on vector elements of the vector in the event of a memory protection violation or speculative access being denied based on memory occupancy; triggering 5400 a fault exception if a mask bit is enabled for the vector element and a memory violation is detected; and continuing 5500 execution of the masked vector memory instruction if no memory protection violation is detected for the vector element. It can be used where applicable and appropriate. Figure 1 Integrated circuit 1100, Figure 1 Processor core 1200, Figure 1 Scalar processing unit 1210 Figure 1 Vector processing unit 1220 Figure 1 (Multiple) register files 1230, Figure 1 Memory protection circuit 1270 Figure 2 Integrated circuit 2100, Figure 2 Processor core 2200, Figure 2 Assembly line 2220 Figure 2 The (multiple) register files 2210, and / or Figure 2 The memory protection circuit 2310 is used to implement the technology 5000.

[0065] Technology 5000 includes monitoring 5100 masked vector memory instructions. The memory protection circuitry is capable of monitoring vector memory instructions, including masked vector memory instructions. The memory protection circuitry is capable of monitoring vector memory instructions in the processor core during scalar unit processing or operation and during vector unit processing or operation.

[0066] Technique 5000 includes performing 5200 memory protection violation checks and memory attribute checks based on memory occupancy of masked vector memory instructions, ignoring masking information associated with vectors identified by the masked vector memory instructions. A vector can have N vector elements. The memory protection circuitry can perform memory violation checks during scalar processing without considering masking information. The memory protection circuitry uses memory occupancy associated with memory address ranges related to the masked vector memory instructions. Various techniques as described herein and in U.S. Provisional Patent Application Serial No. 63 / 073,916, filed September 2, 2020, entitled “Memory Protection for Vector Operations” (which is incorporated herein by reference in its entirety), can be used to determine memory occupancy. Memory attribute checks can be performed in parallel or sequentially after fault exception handling. Memory attribute checks (e.g., based on memory occupancy) can be performed without considering masking information. If speculative access to a memory occupancy or memory region is permitted, i.e., it is cacheable memory, the execution of the masked vector memory instructions can continue. Optimized execution occurs when execution passes memory violation checks and memory attribute checks without considering masking information.

[0067] Technique 5000 includes performing a 5300 memory protection violation check on vector elements of a vector in the event of a memory protection violation or speculative access being denied based on memory occupancy. Speculative access is not permitted if the memory access is non-idempotent without considering masking information, i.e., accessing the memory region has potential side effects. Instead of triggering a fault exception after a memory protection violation is detected based on memory occupancy or if speculative access is denied, the memory protection circuitry waits for the vector processing unit to complete loading the masking information into the mask or vector register. In the implementation, loading the mask register is independent of memory protection violation handling. In the implementation, other operations have already initiated the loading of the mask register. After the masking information of the vector is loaded into the mask register, the memory protection circuitry determines whether mask bits are enabled for vector elements in the vector. Enabled mask bits indicate that the memory address(s) associated with the vector element are relevant, e.g., the memory address(s) will be used or processed. Unenabled bits indicate that the memory address is not relevant.

[0068] Technique 5000 includes triggering a 5400 fault exception if the mask bit is enabled and a memory violation is detected for a vector element. If the mask bit is enabled and a memory violation is detected for a vector element, the memory protection circuitry triggers a fault exception. The operating system performs fault exception handling relative to the mask vector memory instruction, which includes various procedures such as suspending the execution of the mask vector memory instruction and troubleshooting page faults from the disk.

[0069] Technique 5000 includes continuing execution of a mask vector memory instruction if no memory protection violation is detected for a vector element. If the mask bit of a vector element is set and no memory protection violation is detected for that vector element, the corresponding memory access is performed, and execution can continue. The memory protection circuitry ignores any memory protection violations associated with vector elements whose mask bits are not enabled or set.

[0070] While some embodiments herein relate to methods, those skilled in the art will understand that they can also be embodied as systems or computer program products. Therefore, aspects of the invention can take the form of entirely hardware embodiments, entirely software embodiments (including firmware, resident software, microcode, etc.), or embodiments combining software and hardware aspects, which can be collectively referred to herein as “processor,” “device,” or “system.” Furthermore, aspects of the invention can take the form of a computer program product embodied in one or more computer-readable media, on which computer-readable program code is embodied. Any combination of one or more computer-readable media can be utilized. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium can be, for example (but not limited to), an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More specific examples (not an exhaustive list) of computer-readable storage media include: electrical connections having one or more wires, portable computer floppy disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact optical disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In the context of this document, a computer-readable storage medium can be any tangible medium capable of containing or storing programs used by or in connection with an instruction execution system, apparatus, or device.

[0071] Computer-readable signal media may include propagated data signals embodying computer-readable program code therein, for example, in baseband or as part of a carrier wave. Such propagated signals may take any of a variety of forms, including, but not limited to, electromagnetic, optical, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium that is not a computer-readable storage medium and is capable of conveying, propagating, or transmitting a program used by or in connection with an instruction execution system, apparatus, or device.

[0072] Program code embodied on a computer-readable medium may be transmitted using any suitable medium, including but not limited to CD, DVD, wireless, wired, fiber optic cable, RF, or any suitable combination thereof.

[0073] The computer program code used to perform the operations of various aspects of this invention can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer, partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or can connect to an external computer (e.g., via the Internet provided by an Internet service provider).

[0074] The various aspects of the present invention will now be described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions.

[0075] These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create parts for implementing the functions / actions specified in the flowchart and / or block diagram boxes. These computer program instructions may also be stored in a computer-readable medium that can instruct a computer, other programmable data processing apparatus, or other device to operate in a particular manner, such that the instructions stored in the computer-readable medium produce an article of writing including instructions that implement the functions / actions specified in the flowchart and / or block diagram boxes or blocks.

[0076] Computer program instructions may also be loaded onto a computer, other programmable data processing apparatus or other equipment to cause a series of operational steps to be performed on the computer, other programmable apparatus or other equipment to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide a process for implementing the function / action specified in the flowchart and / or block diagram boxes or blocks.

[0077] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each box in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function(s). It should also be noted that in some alternative implementations, the functions indicated in the boxes may not occur in the order shown in the figures.

[0078] While this disclosure has been described in conjunction with certain embodiments, it should be understood that this disclosure is not limited to the disclosed embodiments. Rather, this disclosure is intended to cover various modifications, combinations, and equivalent arrangements included within the scope of the appended claims, which is subject to the broadest interpretation to include all such modifications and equivalent structures permitted by law.

Claims

1. An integrated circuit for executing instructions, comprising: A processor core, the processor core including a pipeline configured to execute masked vector memory instructions; as well as A memory protection circuit, configured to check for memory protection violations, is configured to: Monitor the shielded vector memory instructions; Based on the memory occupancy of the masked vector memory instruction, a memory protection violation check is performed during scalar processing, and masking information associated with the vectors identified by the masked vector memory instruction is ignored; In the event of a memory protection violation or speculative access being denied based on the memory occupancy, a memory protection violation check is performed on the vector elements of the vector during vector processing; When the mask bit is enabled and a memory violation is detected for a vector element, a fault exception is triggered. as well as If no memory protection violation is detected for the vector element, the execution of the mask vector memory instruction continues.

2. The integrated circuit according to claim 1, wherein, The memory occupancy is an indicator of the memory address range associated with the masked vector memory instruction.

3. The integrated circuit according to claim 1, wherein, The memory protection circuit is also configured to: Wait until the mask register is loaded with mask information by the vector processor of the processor core.

4. The integrated circuit according to claim 1, wherein, The memory protection circuit is also configured to: When the mask bit is not set, detected memory protection violations for vector elements are ignored.

5. The integrated circuit according to claim 1, wherein, The memory protection circuit monitors the masked vector memory instructions during the scalar processing and during the vector processing.

6. The integrated circuit according to claim 1, wherein, The memory protection circuit is also configured to: If no memory protection violation is detected relative to the memory occupancy and speculative access is permitted, then execution of the masked vector memory instruction continues.

7. The integrated circuit according to claim 1, wherein, The scalar unit of the processor core is configured to extract and decode the masked vector memory instructions.

8. An integrated circuit for executing instructions, comprising: A processor core, wherein the processor core includes at least a scalar processor and a vector processor; as well as Memory protection circuit, the memory protection circuit being configured to: Monitor the processing of masked vector memory instructions by the scalar processor; During scalar processing, a Level 1 memory protection violation check and an idempotent memory attribute check are performed, ignoring masking information associated with vectors identified by the masking vector memory instructions; During vector processing of the masked vector memory instructions by the vector processor, wait until the mask register is fully loaded; In the event that a memory protection violation detection or speculative access from the first-level memory check is rejected based on the check of the idempotent memory property, a second-level memory protection violation check is performed on the vector elements of the vector during the vector processing. If the mask bit is enabled and a memory violation is detected for a vector element, a fault exception is triggered; as well as If no memory protection violation is detected for the vector element, the execution of the mask vector memory instruction continues.

9. The integrated circuit according to claim 8, wherein, The first level of memory protection violation check is based on memory occupancy indicating the memory address range associated with the mask vector memory instruction.

10. The integrated circuit according to claim 8, wherein, The memory protection circuit is also configured to: When the mask bit is not set, detected memory protection violations for vector elements are ignored.

11. The integrated circuit according to claim 8, wherein, The memory protection circuit monitors the masked vector memory instructions during the vector processing.

12. The integrated circuit according to claim 8, wherein, The memory protection circuit is also configured to: If no memory protection violation is detected relative to the first-level memory protection violation check element and speculative access is permitted, then the execution of the masked vector memory instruction continues.

13. The integrated circuit according to claim 8, wherein, The scalar processor is configured to extract and decode the masked vector memory instructions.

14. A method comprising: Monitor the masked vector memory instructions; Based on the memory occupancy of the masked vector memory instruction, a memory protection violation check is performed during scalar processing, and masking information associated with the vectors identified by the masked vector memory instruction is ignored; In the event of a memory protection violation or speculative access being denied based on the memory occupancy, a memory protection violation check is performed on the vector elements of the vector during vector processing; When the mask bit is enabled and a memory violation is detected for a vector element, a fault exception is triggered. as well as If no memory protection violation is detected for the vector element, the execution of the mask vector memory instruction continues.

15. The method according to claim 14, wherein, The memory occupancy is an indicator of the memory address range associated with the masked vector memory instruction.

16. The method of claim 14, further comprising: Wait until the mask register is loaded with mask information by the vector processor.

17. The method of claim 14, further comprising: When the mask bit is not set, detected memory protection violations for vector elements are ignored.

18. The method according to claim 14, wherein, The surveillance also includes: Monitor the masked vector memory instructions during the scalar processing; and The masked vector memory instructions are monitored during the vector processing.

19. The method of claim 14, further comprising: If no memory protection violation is detected relative to the memory occupancy and speculative access is permitted, then execution of the masked vector memory instruction continues.

20. The method of claim 19, further comprising: Based on the memory usage, a memory attribute check is performed during scalar processing, and the masking information associated with the vector identified by the masking vector memory instruction is ignored.

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