Indium phosphide substrate

Abstract

This invention provides an indium phosphide substrate that, after mirror polishing of the wafer surface, effectively suppresses the generation of debris when the polishing plate is peeled off from the back side of the wafer. In this indium phosphide substrate, when a plane A parallel to the main surface is taken in the wafer, the angle θ formed by a plane B (including the intersection of the wafer edge and plane A and tangent to the wafer edge) and a plane A extending outward from the wafer on the main surface side is 0° < θ ≤ 120° for all planes A with a distance of 100 μm or more and 200 μm or less from the main surface. In a cross-section orthogonal to the wafer edge, it has rounded edges on the main surface side and the opposite side of the main surface, with a chamfer width X from the wafer edge on the main surface side. f For wafers with a diameter of 50μm or larger and 130μm or smaller, the chamfer width X is measured from the wafer edge on the opposite side of the main surface. b The thickness of the indium phosphide substrate is 330 μm or more and 700 μm or less, and the thickness is 150 μm or more and 400 μm or less.

Description

Technical Field

[0001] This invention relates to an indium phosphide substrate. Background Technology

[0002] Indium phosphide (InP) is a group III-V compound semiconductor material composed of group III indium (In) and group V phosphorus (P). As a semiconductor material, it possesses the following characteristics: a band gap of 1.35 eV at room temperature and an electron mobility of 4600 cm⁻¹. 2 With an electron mobility of approximately / V·s under a high electric field, it achieves a value higher than that of other common semiconductor materials such as silicon and gallium arsenide. Furthermore, it possesses the following characteristics: its stable crystal structure at room temperature and pressure is a cubic zincblende type structure, and its lattice constant is larger than that of compound semiconductors such as gallium arsenide (GaAs) and gallium phosphide (GaP).

[0003] Indium phosphide ingots, which are used as raw materials for indium phosphide substrates, are typically sliced ​​to a specified thickness, ground into the desired shape, and then subjected to appropriate mechanical polishing to remove polishing debris and damage caused by polishing, and are then used for etching, precision grinding (polishing), etc.

[0004] Sometimes, an epitaxial crystal layer is formed on the main surface of an indium phosphide substrate by epitaxial growth (Patent Document 1).

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent Application Publication No. 2003-218033 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] After epitaxial growth, when further processing is performed, since substrate thickness is not required, the substrate is thinned to, for example, 100 μm or more but less than 200 μm by grinding from the back side of the wafer using methods such as back lap. Here, the wafer edges are generally sharp, which presents the following problem: when grinding from the back side of the wafer using methods such as back lap, the edges become even sharper, making the wafer more prone to breakage.

[0010] To address this problem, the following technique exists: by controlling the chamfer width and the radius R of the arc portion of the wafer's surface chamfer, the sharpness of the edges during grinding from the back side of the wafer using methods such as back grinding can be suppressed. In this case, the grinding of the wafer's chamfer portion is generally designed to be symmetrical top and bottom, thus the back side of the wafer is also ground into the same shape.

[0011] Typically, indium phosphide substrates are mirror-polished for epitaxial growth. From a flatness perspective, this mirror polishing generally involves melting resin wax onto a ceramic plate, uniformly coating it to the back side of the wafer with a thickness of 1-2 μm using spin coating or similar methods, and polishing while the wafer is attached to the ceramic plate. Ideally, even when mirror polishing both sides of the wafer, polishing can be performed by holding it between upper and lower platforms while it rotates and revolves, again to minimize processing damage during double-sided polishing and remove minor surface scratches, by polishing with the back side of the wafer attached to the ceramic plate using the same method. After polishing, the wafer is peeled off the ceramic plate and cleaned. Peeling methods include: melting the resin wax by heating; inserting a scraper or similar clamp into the back side and using a lever principle for peeling; since this is simpler to perform, a scraper is generally used for peeling.

[0012] At this point, when controlling the chamfer width of the chamfered portion of the wafer surface and the radius R of the arc portion as described above, if the back side of the wafer is also ground into the same shape, the chamfer width on the back side becomes the same size as the chamfer width on the surface side. Here, if the chamfer width on the surface side is narrow, the chamfer width on the back side also becomes narrower. Therefore, when the wafer is peeled from the ceramic substrate after mirror polishing, chipping may occur on the back side of the wafer.

[0013] The present invention was made to solve the above-mentioned problems, and its purpose is to provide an indium phosphide substrate that, after mirror polishing of the wafer surface, can effectively suppress the generation of debris when the plate used for polishing is peeled off from the back side of the wafer.

[0014] Solution for solving the problem

[0015] The embodiments of the present invention are specified by the following (1) to (5).

[0016] (1) An indium phosphide substrate, wherein, when a plane A parallel to a main surface is taken in the wafer, the angle θ formed by a plane B, which includes the intersection of the wafer edge and the plane A and is tangent to the wafer edge, and a plane A extending outward in the direction of the wafer from the plane A on the main surface side is 0° < θ ≤ 120° for all planes A that are 100 μm or more and 200 μm or less from the main surface, and in a cross-section orthogonal to the wafer edge, an edge rounding is provided on the main surface side and the opposite side of the main surface, and the chamfer width X from the wafer edge on the main surface side is... f The chamfer width X, which is 50 μm or more and 130 μm or less, originating from the wafer edge on the opposite side of the main surface. bThe thickness of the indium phosphide substrate is 330 μm or more and 700 μm or less, and the thickness is 150 μm or more and 400 μm or less.

[0017] (2) The indium phosphide substrate according to (1), wherein the angle θ formed is 60°≤θ≤120° for all planes A that are 100μm or more and 200μm or less from the main surface.

[0018] (3) An indium phosphide substrate, wherein, when a plane A parallel to a main surface is taken in the wafer, the angle θ formed by a plane B, which includes the intersection of the wafer edge and the plane A and is tangent to the wafer edge, and a plane A extending outward in the direction of the wafer from the plane A on the main surface side is 60°≤θ≤110° for all planes A that are 100μm or more and 200μm or less from the main surface, and in a cross-section orthogonal to the wafer edge, the main surface side and the opposite side of the main surface have rounded edges, and the chamfer width X from the wafer edge on the main surface side is... f The chamfer width X, which is 80μm or more and 110μm or less, originating from the wafer edge on the opposite side of the main surface. b The diameter of the indium phosphide substrate is 50.8 mm or less and the thickness is 330 μm or more and 380 μm or less. The thickness is 150 μm or more and 210 μm or less.

[0019] (4) An indium phosphide substrate, wherein, when a plane A parallel to a main surface is taken in the wafer, the angle θ formed by a plane B, which includes the intersection of the wafer edge and the plane A and is tangent to the wafer edge, and a plane A extending outward in the direction of the wafer from the plane A on the main surface side is 90°≤θ≤120° for all planes A that are 100μm or more and 200μm or less from the main surface, and in a cross-section orthogonal to the wafer edge, the main surface side and the opposite side of the main surface have rounded edges, and the chamfer width X from the wafer edge on the main surface side is... f The chamfer width X, which is 80μm or more and 110μm or less, originating from the wafer edge on the opposite side of the main surface. b The diameter of the indium phosphide substrate is 50.8 mm or less and the thickness is 480 μm or more and 530 μm or less. The thickness is 180 μm or more and 230 μm or less.

[0020] (5) An indium phosphide substrate, wherein, when a plane A parallel to a main surface is taken in the wafer, the angle θ formed by a plane B, which includes the intersection of the wafer edge and the plane A and is tangent to the wafer edge, and a plane A extending outward in the direction of the wafer from the plane A on the main surface side is 90°≤θ≤120° for all planes A that are 100μm or more and 200μm or less from the main surface, and in a cross-section orthogonal to the wafer edge, the main surface side and the opposite side of the main surface have rounded edges, and the chamfer width X from the wafer edge on the main surface side is... f The chamfer width X, which is 90μm or more and 130μm or less, originating from the wafer edge on the opposite side of the main surface. b The diameter of the indium phosphide substrate is 76.2 mm or less and the thickness is 570 μm or more and 630 μm or less. The thickness is 270 μm or more and 350 μm or less.

[0021] (6) An indium phosphide substrate according to any one of (1) to (5), wherein the chamfer width X from the wafer edge on the main surface side is... f The chamfer width X from the wafer edge on the opposite side of the main surface b Ratio: X b / X f It is between 1.25 and 8.0.

[0022] (7) The indium phosphide substrate according to (6), wherein the X b / X f It is between 1.70 and 3.0.

[0023] Invention Effects

[0024] According to an embodiment of the present invention, an indium phosphide substrate can be provided, which, after mirror polishing of the wafer surface, can effectively suppress the generation of debris when the plate used for polishing is peeled off from the back side of the wafer. Attached Figure Description

[0025] Figure 1 This is a cross-sectional view of the area near the edge of an indium phosphide substrate.

[0026] Figure 2 This is a cross-sectional view of the area near the edge of an indium phosphide substrate.

[0027] Figure 3 This is a cross-sectional view of the area near the edge of an indium phosphide substrate.

[0028] Figure 4 This is a cross-sectional schematic diagram used to illustrate the edge fillets of an indium phosphide substrate.

[0029] Figure 5This is a schematic cross-sectional view of the indium phosphide substrate near the wafer edge in an embodiment. Detailed Implementation

[0030] [Indium phosphide substrate]

[0031] The structure of the indium phosphide substrate in this embodiment will be described below.

[0032] The indium phosphide (InP) substrate of this embodiment has a main surface for forming an epitaxial crystal layer and a back surface opposite to the main surface.

[0033] The main surface used to form the epitaxial crystal layer is the surface on which epitaxial growth is actually performed when the indium phosphide substrate of this embodiment is used as a substrate for epitaxial growth in order to form a semiconductor device structure.

[0034] The maximum diameter of the main surface of the indium phosphide substrate is not particularly limited and can be 49–151 mm or 49–101 mm. The planar shape of the indium phosphide substrate can be circular or rectangular or other quadrilateral shapes.

[0035] The thickness of the indium phosphide substrate is not particularly limited, but is preferably 300–900 μm, and more preferably 300–700 μm. Especially when the aperture is large, if the thickness of the indium phosphide substrate is less than 300 μm, it may break, and if the thickness of the indium phosphide substrate exceeds 900 μm, it may sometimes result in waste of the parent material crystals.

[0036] In the case of the indium phosphide substrate of this embodiment, the carrier concentration can be 1×10⁻⁶ as a dopant (impurity). 16 cm －3 Above and 1×10 19 cm －3 The following methods include Zn, and the carrier concentration can also be 1×10⁻⁶. 16 cm －3 Above and 1×10 19 cm －3 The following methods include S, and the carrier concentration can also be 1×10. 16 cm －3 Above and 1×10 19 cm －3 The following methods include Sn, and the carrier concentration can also be 1×10. 6 cm －3 Above and 1×10 9 cm －3 The following methods include Fe.

[0037] In one embodiment of the indium phosphide substrate, when a plane A parallel to the main surface is taken in the wafer, the angle θ formed by a plane B, which includes the intersection of the wafer edge and the plane A and is tangent to the wafer edge, and a plane A extending outward in the direction of the wafer on the main surface side, is 0°<θ≤120° for all planes A that are 100μm or more and 200μm or less from the main surface.

[0038] To understand the plane A, plane B, and angle θ mentioned above, in Figures 1-3 The diagram shows cross-sectional views of the indium phosphide substrate near the wafer edge. The cross-section of the indium phosphide substrate wafer edge is shown below. Figures 1-3 As shown, the corners of the rectangle are cut (beveled) to create a curved shape. Therefore, the size of angle θ varies depending on which part of the wafer plane A is taken from. Furthermore, the closer angle θ is to 180°, the sharper the wafer edge becomes. It should be noted that... Figures 1-3 The accompanying drawings are for understanding plane A, plane B, the intersection line, and angle θ in the indium phosphide substrate of the present invention. They do not directly represent the indium phosphide substrate of the present invention. Furthermore, in the present invention, "wafer edge" refers to the side surface of the indium phosphide substrate, that is, the outer surface other than the main surface and the back surface.

[0039] exist Figure 1 In the example shown, plane A is taken at the center of the wafer in the thickness direction. Therefore, the angle θ between plane B, which contains the intersection of the wafer edge and plane A and is tangent to the wafer edge, and the surface of plane A extending outward in the wafer direction, is 90°.

[0040] exist Figure 2 In the example shown, plane A is taken at the upper part of the wafer in the thickness direction. Thus, when plane A is taken at the upper part of the wafer in the thickness direction, the angle θ formed by plane B, which includes the intersection of the wafer edge and plane A and is tangent to the wafer edge, and the surface of plane A extending outward in the wafer direction, is an obtuse angle (90° < θ < 180°).

[0041] exist Figure 3 In the example shown, plane A is taken at the lower part of the wafer in the thickness direction. Thus, when plane A is taken at the lower part of the wafer in the thickness direction, the angle θ formed by plane B, which includes the intersection of the wafer edge and plane A and is tangent to the wafer edge, and the surface of plane A extending outward in the wafer direction, is an acute angle (0° < θ < 90°).

[0042] Furthermore, regarding the indium phosphide substrate of this embodiment, the angle θ is controlled such that for all planes A with a distance of 100 μm or more and 200 μm or less from the main surface, 0° < θ ≤ 120°. With this configuration, when the indium phosphide substrate is ground from the back side of the wafer to plane A by methods such as back grinding, the sharpness of the wafer edge is suppressed. Therefore, for example, damage such as cracks at the wafer edge can be well suppressed during the process. Preferably, the angle θ is controlled such that for all planes A with a distance of 100 μm or more and 200 μm or less from the main surface, 60° ≤ θ ≤ 120°.

[0043] As described above, plane B is a plane that includes the intersection line of the wafer edge and plane A and is tangent to the wafer edge. Even if the intersection line of the wafer edge and plane A is determined, the value of the angle θ formed by the surfaces of plane B and plane A extending outward in the wafer direction on the main surface will vary to some extent depending on the degree of surface roughness of the wafer edge. Regarding the change in angle θ caused by the surface roughness of the wafer edge, it can be considered that the impact on the suppression of sharpness of the wafer edge produced by back grinding or other methods, which is an effect of the present invention, is very small. It should be noted that the angles θ specified in the embodiments of the present invention are values ​​measured by observing the shape of the wafer edge using a Wafer Edge Profile Checker (EPRO-212EO manufactured by Hsiung Fei Electronics Co., Ltd.), as described later. Regardless of the degree of surface roughness of the wafer edge, plane B can be a plane measured with the accuracy that can be measured using the Wafer Edge Profile Checker.

[0044] In this embodiment, plane A is defined as all planes A with a distance of 100 μm or more and 200 μm or less from the main surface. This is because the aforementioned effect can be obtained for indium phosphide substrates that have been ground from the back of the wafer to a thickness of 100 μm or more and 200 μm or less from the main surface by methods such as back grinding. Furthermore, the thickness of the indium phosphide substrate in this embodiment is 330 μm or more and 700 μm or less.

[0045] The indium phosphide substrate of this embodiment is as follows: Figure 4 As shown, in a cross-section orthogonal to the wafer edge, there are rounded edges on the main face side and the opposite side (back face side). Furthermore, the chamfer width X from the wafer edge on the main face side... f The chamfer width X, controlled to be between 50μm and 130μm, is measured from the wafer edge on the back side. b It is controlled to be above 150μm and below 400μm.

[0046] Thus, the chamfer width X from the edge of the wafer on the main side...f The diameter is controlled to be between 50 μm and 130 μm, thus suppressing the sharpness of the wafer edge when grinding the indium phosphide substrate from the back side of the wafer to plane A using methods such as back grinding. Therefore, damage such as cracks at the wafer edge can be effectively suppressed, for example, during the process. Furthermore, the chamfer width X from the wafer edge on the back side... b The diameter is controlled to be between 150μm and 400μm. Thus, by asymmetrically designing the chamfer shapes on the main and back sides of the wafer and increasing the chamfer width on the back side, it is possible to ensure sufficient space for inserting jigs such as scrapers on the back side. Therefore, after mirror polishing, the wafer can be easily peeled from the ceramic plate without producing debris. If the chamfer width from the wafer edge on the back side X... b For diameters greater than 150 μm, the space for inserting jigs such as scrapers into the back side becomes wider, effectively suppressing debris generation. If the chamfer width X from the wafer edge on the back side... b If the chamfer width is below 400μm, it can suppress excessive erosion of the back edge shape of the substrate towards the surface, ensuring the chamfer width on the surface and suppressing the loss of polishing allowance. The chamfer width X from the wafer edge on the back side... b Preferably, the size is 160μm or larger and 340μm or smaller.

[0047] Furthermore, the wafer edge can be configured to include: a tapered portion formed in a manner that reduces the wafer thickness from the main face side and / or the back face side respectively; and an edge rounded corner that smoothly connects to the tapered portion. Figure 4 In the case of an indium phosphide substrate, the tapered portion is formed on the back side.

[0048] In another embodiment, the indium phosphide substrate of this embodiment is an indium phosphide substrate as follows: When a plane A parallel to the main surface is taken in the wafer, the angle θ formed by a plane B containing the intersection of the wafer edge and plane A and tangent to the wafer edge, and a plane A extending outward in the wafer direction on the main surface side, is 60°≤θ≤110° for all planes A with a distance of 100μm or more and 200μm or less from the main surface. In a cross-section orthogonal to the wafer edge, it has edge rounded corners on the main surface side and the opposite side of the main surface, and the chamfer width X from the wafer edge on the main surface side is... f For wafers with a diameter of 80μm or larger and 110μm or smaller, the chamfer width X is measured from the wafer edge on the opposite side of the main surface. b The diameter of the indium phosphide substrate is 50.8 mm or less and the thickness is 330 μm or more and 380 μm or less. The thickness is 150 μm or more and 210 μm or less.

[0049] Based on this configuration, when grinding an indium phosphide substrate with a diameter of 50.8 mm or less and a thickness of 330 μm or more but less than 380 μm from the back side of the wafer to plane A using methods such as back grinding, the sharpness of the wafer edge is suppressed. Therefore, damage such as cracks at the wafer edge can be effectively suppressed, for example, during the process. Furthermore, by asymmetrically designing the chamfer shapes on the main and back sides of the wafer and increasing the chamfer width on the back side, space can be ensured for inserting fixtures such as scrapers into the back side. Therefore, after mirror polishing, the wafer can be easily peeled from the ceramic substrate without generating debris. If the chamfer width X from the wafer edge on the back side... b For diameters greater than 150 μm, the space for inserting jigs such as scrapers into the back side becomes wider, effectively suppressing debris generation. If the chamfer width X from the wafer edge on the back side... b If the chamfer width is below 210μm, it can suppress excessive erosion of the back edge shape of the substrate towards the surface, ensuring the chamfer width on the surface and suppressing the loss of polishing allowance. The chamfer width X from the wafer edge on the back side... b Preferably, the size is 160μm or larger and 180μm or smaller.

[0050] In another embodiment, the indium phosphide substrate of this embodiment is an indium phosphide substrate as follows: When a plane A parallel to the main surface is taken in the wafer, the angle θ formed by a plane B containing the intersection of the wafer edge and plane A and tangent to the wafer edge, and a plane A extending outward in the wafer direction on the main surface side, is 90°≤θ≤120° for all planes A with a distance of 100μm or more and 200μm or less from the main surface. In a cross-section orthogonal to the wafer edge, it has edge rounded corners on the main surface side and the opposite side of the main surface, and the chamfer width X from the wafer edge on the main surface side is... f For wafers with a diameter of 80μm or larger and 110μm or smaller, the chamfer width X is measured from the wafer edge on the opposite side of the main surface. b The diameter of the indium phosphide substrate is 50.8 mm or less and the thickness is 480 μm or more and 530 μm or less. The thickness is 180 μm or more and 230 μm or less.

[0051] Based on this configuration, when grinding an indium phosphide substrate with a diameter of 50.8 mm or less and a thickness of 480 μm or more but less than 530 μm from the back side of the wafer to plane A using methods such as back grinding, the sharpness of the wafer edge is suppressed. Therefore, damage such as cracks at the wafer edge can be effectively suppressed, for example, during the process. Furthermore, by asymmetrically designing the chamfer shapes on the main and back sides of the wafer and increasing the chamfer width on the back side, space can be ensured for inserting fixtures such as scrapers into the back side. Therefore, after mirror polishing, the wafer can be easily peeled from the ceramic substrate without generating debris. If the chamfer width X from the wafer edge on the back side... bFor diameters greater than 180μm, the space for inserting jigs such as scrapers into the back side becomes wider, effectively suppressing debris generation. If the chamfer width X from the wafer edge on the back side... b If the thickness is below 230μm, it can suppress excessive erosion of the edge shape on the back side of the substrate towards the surface, ensuring the chamfer width on the surface side and suppressing the loss of polishing allowance. The chamfer width X from the wafer edge on the back side... b Preferably, the micrometer size is 190μm or larger and 210μm or smaller.

[0052] In another embodiment, the indium phosphide substrate of this embodiment is an indium phosphide substrate as follows: When a plane A parallel to the main surface is taken in the wafer, the angle θ formed by a plane B containing the intersection of the wafer edge and plane A and tangent to the wafer edge, and a plane A extending outward in the wafer direction on the main surface side, is 90°≤θ≤120° for all planes A with a distance of 100μm or more and 200μm or less from the main surface. In a cross-section orthogonal to the wafer edge, it has edge rounded corners on the main surface side and the opposite side of the main surface, and the chamfer width X from the wafer edge on the main surface side is... f For wafers with a diameter of 90μm or larger and 130μm or smaller, the chamfer width X is measured from the wafer edge on the opposite side of the main surface. b The diameter of the indium phosphide substrate is 76.2 mm or less and the thickness is 570 μm or more and 630 μm or less. The thickness is 270 μm or more and 350 μm or less.

[0053] Based on this configuration, when grinding an indium phosphide substrate with a diameter of 76.2 mm or less and a thickness of 570 μm or more but less than 630 μm from the back side of the wafer to plane A using methods such as back grinding, the sharpness of the wafer edge is suppressed. Therefore, damage such as cracks at the wafer edge can be effectively suppressed, for example, during the process. Furthermore, by asymmetrically designing the chamfer shapes on the main and back sides of the wafer and increasing the chamfer width on the back side, space can be ensured for inserting fixtures such as scrapers into the back side. Therefore, after mirror polishing, the wafer can be easily peeled from the ceramic substrate without generating debris. If the chamfer width X from the wafer edge on the back side... b For diameters greater than 270μm, the space for inserting jigs such as scrapers into the back side becomes wider, effectively suppressing debris generation. If the chamfer width X from the wafer edge on the back side... b If the thickness is below 350μm, it can suppress excessive erosion of the edge shape on the back side of the substrate towards the surface, ensuring the chamfer width on the surface side and suppressing the loss of polishing allowance. The chamfer width X from the wafer edge on the back side... b Preferably, the size is above 280μm and below 340μm.

[0054] In the indium phosphide substrate of the embodiment of the present invention, the chamfer width X from the wafer edge on the main surface side is... fThe chamfer width X from the wafer edge on the opposite side of the main face b Ratio: X b / X f Preferably, the value is 1.25 or higher and 8.0 or lower. Furthermore, X... b / X f More preferably, it is 1.70 or higher and 3.0 or lower.

[0055] [Indium phosphide substrate manufacturing method]

[0056] Next, the manufacturing method of the indium phosphide substrate according to an embodiment of the present invention will be described.

[0057] As a method for manufacturing indium phosphide substrates, firstly, indium phosphide ingots are produced using known methods.

[0058] Next, the indium phosphide ingot is ground to form a cylinder.

[0059] Next, wafers with a front and back face are cut from the ground indium phosphide ingot. At this point, a wire saw is used to cut the two ends of the indium phosphide ingot along the specified crystal plane to cut multiple wafers to a specified thickness.

[0060] Next, in order to remove the processing-induced altered layer generated during the cutting process using a wire saw, the cut wafer is etched on both sides (single etching) using a prescribed etching solution. The wafer can be etched by immersing the entire wafer in the etching solution.

[0061] Next, the outer periphery of the wafer is chamfered, and preferably both sides of at least one surface of the chamfered wafer are polished. This polishing process is also known as a lapping process, which removes the unevenness of the wafer surface by polishing with a specified abrasive while maintaining the flatness of the wafer.

[0062] Next, the polished wafer is etched on both sides (secondary etching) using a prescribed etching solution. The wafer can be etched by immersing the entire wafer in the etching solution.

[0063] Next, with a ceramic plate or similar material attached to the back of the wafer, the main surface of the wafer is polished to a mirror finish using a mirror polishing material. Alternatively, when mirror polishing both sides of the wafer, polishing can be performed by clamping the wafer with an upper and lower platform while it rotates and revolves. To reduce processing damage during double-sided polishing and remove minor surface scratches, polishing can be performed with the wafer attached to a ceramic plate or similar material using the same method described above.

[0064] Next, a scraper or other clamps are inserted into the back side to peel the plate off.

[0065] Next, the substrate is cleaned to produce the indium phosphide substrate according to the embodiment of the present invention.

[0066] In the indium phosphide substrate of this embodiment, in order to control the angle θ formed by the plane B tangent to the wafer edge and the surface of plane A extending outward in the wafer direction on the main surface side in all planes A within a predetermined distance from the main surface, the shape of the wafer edge can be controlled by appropriately adjusting the chamfer amount based on the amount of wafer removed during the aforementioned grinding, etching, and polishing processes. More specifically, the chamfer amount (chamfer width from the wafer edge) on the main surface side of the wafer is set to a range of 150 to 320 μm, and the chamfer amount on the back side side of the wafer is set to a range of 320 to 580 μm. Furthermore, the amount of material removed on the main surface side after chamfering is reduced to a range of 80 μm or less in the wafer thickness direction, and the amount of material removed on the back side side is reduced to a range of 70 μm or less in the wafer thickness direction. As a result, the angle θ formed by the plane B tangent to the wafer edge and the surface of plane A extending outward in the wafer direction on the main surface side can be appropriately controlled in all planes A within a predetermined distance from the main surface. In addition, it can suppress the generation of debris on the back side when peeling the wafer from a ceramic plate or the like attached to the back side of the wafer.

[0067] [Semiconductor epitaxial wafer]

[0068] By using known methods to epitaxially grow a semiconductor thin film, an epitaxial crystal layer is formed on the main surface of the indium phosphide substrate according to embodiments of the present invention, thereby enabling the fabrication of a semiconductor epitaxial wafer. As an example of this epitaxial growth, a HEMT (High Electron Mobility Transistor) structure can be formed by epitaxially growing an InAlAs buffer layer, an InGaAs channel layer, an InAlAs spacer layer, and an InP electron supply layer on the main surface of the indium phosphide substrate. In fabricating a semiconductor epitaxial wafer with such a HEMT structure, the mirror-polished indium phosphide substrate is typically etched using an etchant such as sulfuric acid / hydrogen peroxide solution to remove impurities such as silicon (Si) adhering to the substrate surface. With the back side of the etched indium phosphide substrate in contact with a susceptor and supported, an epitaxial film is formed on the main surface of the indium phosphide substrate using molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD).

[0069] Example

[0070] The following are embodiments provided to better understand the present invention and its advantages, but the present invention is not limited to these embodiments.

[0071] Examples 1-4 and Comparative Examples 1-2 were prepared as follows.

[0072] First, single crystal ingots of indium phosphide grown to a specified diameter were prepared.

[0073] Next, the outer periphery of the indium phosphide single crystal ingot is ground to form a cylinder.

[0074] Next, wafers with a front and back face are cut from the ground indium phosphide ingot. At this point, a wire saw is used to cut the crystal ends of the indium phosphide ingot along a specified crystal plane, cutting out multiple wafers to a specified thickness. During the wafer cutting process, a new wire is continuously fed while the wire is reciprocating, and the indium phosphide is moved toward the wire saw.

[0075] Next, in order to remove the processing-induced altered layer generated during the cutting process using a wire saw, the cut wafer was etched from both sides using a mixed solution of 85% by mass phosphoric acid aqueous solution and 30% by mass hydrogen peroxide solution (single etching). The wafer was etched by immersing the entire wafer in the etching solution.

[0076] Next, the outer periphery of the wafer is chamfered. Then, both sides of the chamfered wafer are ground (polished). At this time, by using an abrasive, the unevenness on the wafer surface is removed while maintaining the flatness of the wafer.

[0077] Next, the polished wafer was etched on both sides using a mixed solution of 85% by mass phosphoric acid aqueous solution, 30% by mass hydrogen peroxide solution, and ultrapure water (secondary etching). The wafer was etched by immersing the entire wafer in the etching solution.

[0078] Next, with the ceramic plate attached to the back of the wafer, the main surface is polished using a mirror polishing material to achieve a mirror finish. Furthermore, for a portion of the wafers, they are clamped by an upper and lower platform while rotating, thus performing double-sided polishing. To reduce processing damage during double-sided polishing and remove minor surface scratches, polishing is performed with the back of the wafer attached to the ceramic plate using the same method. Next, a scraper or other clamping device is inserted into the back side to peel the plate off. Finally, cleaning is performed, thereby fabricating an indium phosphide substrate.

[0079] In Examples 1-4, when each wafer is manufactured to a plane A parallel to the main surface of the wafer, the angle θ between plane B (which includes the intersection of the wafer edge and plane A and is tangent to the wafer edge) and the surface of plane A extending outward from the wafer becomes a predetermined range relative to plane A at a predetermined distance from the main surface. Furthermore, the chamfer width X of each wafer is adjusted from the wafer edge on the front and back sides. f X b This falls within the defined range. For the wafer shapes in Table 1, please refer to... Figure 5 A schematic cross-sectional view of the indium phosphide substrate near the wafer edge.

[0080] (evaluate)

[0081] The edge shapes of the wafers in Examples 1-4 and Comparative Examples 1-2 were measured using a Wafer Edge Profile Checker (EPRO-212EO manufactured by Hsiung Fei Electronics Co., Ltd.). The angles (θ1, θ2, θ3) were calculated as follows: a straight line A (corresponding to plane A) parallel to the main surface and corresponding to the back-polished thickness was drawn; a tangent line B (corresponding to plane B) was drawn with the intersection of straight line A and the wafer edge as the tangent point; and the angle between straight line A and tangent line B was calculated.

[0082] The shape of the manufactured wafer and the above evaluation results are shown in Table 1.

[0083] [Table 1]

[0084]

[0085] Regarding the substrates of Examples 1 to 4, the sharpness of the wafer edges after backside removal was well suppressed, and the generation rate of debris on the backside was 0% when the wafer was peeled off from the ceramic plate after mirror polishing. In contrast, regarding the substrates of Comparative Examples 1 and 2, although the sharpness of the wafer edges after backside removal was suppressed, the generation rate of debris on the backside was high when the wafer was peeled off from the ceramic plate after mirror polishing.

[0086] It should be noted that the debris on the back side is only affected by the chamfer width X from the edge of the wafer on the back side. b The influence of two factors, namely wafer thickness, is considered. Therefore, it can be assumed that for wafers with a larger aperture than those in Examples 3 and 4, only the chamfer width X needs to be controlled. b The two factors of wafer thickness can suppress the generation of debris.

Claims

1. An indium phosphide substrate, When a plane A parallel to the main surface is taken in the wafer, the angle θ formed by plane B, which includes the intersection of the wafer edge and plane A and is tangent to the wafer edge, and the surface of plane A extending outward in the wafer direction on the main surface side, is 0°<θ≤120° for all planes A that are 100μm or more but less than 200μm from the main surface. In a cross-section orthogonal to the edge of the wafer, there are rounded edges on the main face side and the opposite face side of the main face. A chamfer width X from the wafer edge on the main surface side f is 50 μm or more and 130 μm or less, A chamfer width X from a wafer edge on the opposite side of the main surface b is 150 μm or more and 400 μm or less, The thickness of the indium phosphide substrate is greater than 330 μm and less than 700 μm. Chamfer width X from the wafer edge of the main surface side f Chamfer width X from the wafer edge of the opposite side of the main surface b Ratio: X b / X f is 1.25 or more and 3.0 or less.

2. The indium phosphide substrate according to claim 1, wherein, The angle θ formed is 60°≤θ≤120° for all planes A whose distance from the main surface is greater than 100μm and less than 200μm.

3. An indium phosphide substrate, When a plane A parallel to the main surface is taken in the wafer, the angle θ formed by plane B, which includes the intersection of the wafer edge and plane A and is tangent to the wafer edge, and the surface of plane A extending outward in the wafer direction on the main surface side, is 60°≤θ≤110° for all planes A that are 100μm or more but less than 200μm from the main surface. In a cross-section orthogonal to the edge of the wafer, there are rounded edges on the main face side and the opposite face side of the main face. A chamfer width X from the wafer edge on the main surface side f is 80 μm or more and 110 μm or less, A chamfer width X from a wafer edge on the opposite side of the main surface b is 150 μm or more and 210 μm or less, The indium phosphide substrate has a diameter of 50.8 mm or less and a thickness of 330 μm or more but less than 380 μm. Chamfer width X from the edge of the wafer on the main surface side f The chamfer width X from the wafer edge on the opposite side of the main surface b Ratio: X b / X f It is between 1.25 and 3.

0.

4. An indium phosphide substrate, When a plane A parallel to the main surface is taken in the wafer, the angle θ formed by plane B, which includes the intersection of the wafer edge and plane A and is tangent to the wafer edge, and the surface of plane A extending outward in the wafer direction on the main surface side, is 90°≤θ≤120° for all planes A that are 100μm or more but less than 200μm from the main surface. In a cross-section orthogonal to the edge of the wafer, there are rounded edges on the main face side and the opposite face side of the main face. Chamfer width X from the edge of the wafer on the main surface side f The size is between 80μm and 110μm. The chamfer width X from the wafer edge on the opposite side of the main surface. b The size is between 180μm and 230μm. The indium phosphide substrate has a diameter of 50.8 mm or less and a thickness of 480 μm or more but less than 530 μm. Chamfer width X from the edge of the wafer on the main surface side f The chamfer width X from the wafer edge on the opposite side of the main surface b Ratio: X b / X f It is between 1.25 and 3.

0.

5. An indium phosphide substrate, When a plane A parallel to the main surface is taken in the wafer, the angle θ formed by plane B, which includes the intersection of the wafer edge and plane A and is tangent to the wafer edge, and the surface of plane A extending outward in the wafer direction on the main surface side, is 90°≤θ≤120° for all planes A that are 100μm or more but less than 200μm from the main surface. In a cross-section orthogonal to the edge of the wafer, there are rounded edges on the main face side and the opposite face side of the main face. Chamfer width X from the edge of the wafer on the main surface side f It is between 90μm and 130μm. The chamfer width X from the wafer edge on the opposite side of the main surface. b The size is above 270μm and below 350μm. The indium phosphide substrate has a diameter of 76.2 mm or less and a thickness of 570 μm or more and 630 μm or less. Chamfer width X from the edge of the wafer on the main surface side f The chamfer width X from the wafer edge on the opposite side of the main surface b Ratio: X b / X f It is between 1.25 and 3.

0.

6. The indium phosphide substrate according to any one of claims 1 to 5, wherein, The X b / X f It is between 1.70 and 3.0.

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