Power semiconductor device having a multilayer gate dielectric layer including an etch stop / field control layer and method of forming the same

Abstract

A semiconductor device includes: a semiconductor layer structure comprising silicon carbide; a gate dielectric layer on the semiconductor layer structure, the gate dielectric layer including a base gate dielectric layer on the semiconductor layer structure and a capped gate dielectric layer on the base gate dielectric layer opposite to the semiconductor layer structure; and a gate electrode on the gate dielectric layer opposite to the semiconductor layer structure. The dielectric constant of the capped gate dielectric layer is higher than the dielectric constant of the base gate dielectric layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Patent Application Serial No. 16 / 922,192, filed July 7, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to semiconductor devices, and more particularly, to power semiconductor switching devices. Background Technology

[0004] A metal-insulating semiconductor field-effect transistor (“MISFET”) is a well-known type of semiconductor transistor that can be used as a switching device. A MISFET is a three-terminal device having a gate, drain, and source terminal as well as a semiconductor body. The source and drain regions are formed in the semiconductor body, separated by a channel region, and the gate electrode (which can act as a gate terminal or be electrically connected to a gate terminal) is separated from the channel region by a thin insulating layer called the “gate dielectric layer”. The MISFET can be turned on or off by applying a bias voltage to the gate electrode. When the MISFET is on (i.e., it is in its “on state”), current flows through the channel region of the MISFET between the source and drain regions. When the bias voltage is removed from the gate electrode (or reduced below a threshold level), current stops flowing through the channel region. For example, an n-type MISFET has n-type source and drain regions and a p-type channel. Therefore, an n-type MISFET has an “npn” design. When a gate bias voltage sufficient to generate a conductive n-type reverse layer in the p-type channel region electrically connecting the n-type source and drain regions is applied to the gate electrode, the n-type MISFET is turned on, thereby allowing majority carrier conduction between the n-type source and drain regions.

[0005] In most cases, the gate dielectric layer separating the gate electrode of a power MISFET from the channel region is implemented as a thin oxide layer (e.g., a silicon oxide layer). MISFETs with oxide gate dielectric layers are referred to as metal-oxide-semiconductor field-effect transistors (“MOSFETs”). Since oxide-based gate dielectric layers are almost always used due to their superior properties, this discussion will focus on MOSFETs rather than MISFETs; however, it will be appreciated that the techniques described herein according to embodiments of the invention are equally applicable to devices having gate dielectric layers formed from materials other than oxides.

[0006] Because the gate electrode of a MOSFET is insulated from the channel region through a gate dielectric layer, a minimal gate current is required to keep the MOSFET in its on-state or to switch it between its on-state and off-state. Since the gate and channel regions form a capacitor, the gate current remains small during switching. Therefore, only minimal charging and discharging current is required during switching, allowing for simpler gate drive circuitry and faster switching speeds. A MOSFET can be a standalone device or combined with other circuitry. For example, an insulated-gate bipolar transistor (“IGBT”) is a semiconductor device that combines a MOSFET and a bipolar junction transistor (“BJT”), integrating the high-impedance gate electrode of the MOSFET with the low on-state conduction losses that can be provided by the BJT. For example, an IGBT can be implemented as a Darlington pair comprising a high-voltage n-channel MOSFET at the input and a BJT at the output. The base current of the BJT is supplied through the channel of the MOSFET, allowing for simplified external drive circuitry (since the drive circuit only charges and discharges the gate electrode of the MOSFET).

[0007] The demand for high-power semiconductor switching devices that can carry large currents in their on-state and block large voltages (e.g., thousands of volts) in their reverse-blocking state is increasing. To support high current densities and block such high voltages, power MOSFETs and IGBTs typically have a vertical structure where the source and drain are located on opposite sides of a thick semiconductor layer structure (e.g., at the top and bottom) to block higher voltage levels. In very high-power applications, semiconductor switching devices are typically formed in wide-bandgap semiconductor material systems (hereinafter, the term "wide-bandgap semiconductor" includes any semiconductor having a bandgap of at least 1.4 electron volts ("eV")), such as, for example, silicon carbide ("SiC"). Wide-bandgap semiconductor material systems possess several advantageous properties, including, for example, high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity. Compared to devices formed using other semiconductor materials such as silicon, electronic devices formed using silicon carbide can have the ability to operate at higher temperatures, higher power densities, higher speeds, higher power levels, and / or at high radiation densities.

[0008] One failure mechanism of power MOSFETs is so-called "breakdown" of the gate oxide layer. When a power MOSFET is in its conducting or on state, the gate oxide layer is subjected to a high electric field. The stress on the gate oxide layer caused by these electric fields generates defects in the oxide material that accumulate over time. When the defect concentration reaches a critical value, a so-called "penetration path" can be created through the gate oxide layer, electrically connecting the gate electrode to the source region below the semiconductor layer structure, thus short-circuiting the gate electrode and the source region, which can damage the device. The "lifetime" of the gate oxide layer (i.e., how long the device can operate before breakdown occurs) depends, among other things, on the magnitude of the electric field applied to the gate oxide layer and the length of time the electric field is applied. Figure 1 is a schematic semi-logarithmic graph illustrating the relationship between the operating time until breakdown occurs ("gate oxide lifetime") and the level of the electric field applied to the gate oxide layer. This graph assumes that the same electric field is always applied (which is not necessarily the case) and that the gate oxide layer has a certain thickness. An important point that can be seen from Figure 1 is that the logarithm of the gate oxide lifetime and the electric field can have a linear relationship, so the gate oxide lifetime may decrease as the electric field level increases. The lifetime of the gate oxide layer can be increased by increasing the thickness of the gate oxide layer, but the performance of the MOSFET also depends on the thickness of the gate oxide layer. Therefore, increasing the thickness of the gate oxide layer is generally not an acceptable way to increase the lifetime of the gate oxide layer.

[0009] Power silicon carbide MOSFETs are currently used in applications requiring high voltage blocking. For example, silicon carbide MOSFETs are commercially available with a rated current density of 10 A / cm². 2 Or higher, blocking voltages from 300V to 20kV or higher. To form such a device, multiple “unit cells” are typically formed, each unit cell comprising a MOSFET transistor. In high-power applications, a large number of such unit cells (e.g., hundreds or thousands) are typically provided on / in a semiconductor layer structure, and a gate electrode layer is formed on the top side of the semiconductor layer structure, serving as the gate electrode for all unit cells. The opposite (bottom) side of the semiconductor layer structure serves as the common drain for all unit cells of the device. Multiple source contacts are formed on the source regions of the semiconductor layer structure exposed in the openings in the gate electrode layer. These source contacts are also electrically connected to each other to serve as a common source. The resulting device has three terminals: a common source terminal, a common drain terminal, and a common gate electrode, which act as terminals for hundreds or thousands of individual unit cell transistors connected in parallel.

[0010] Figure 2 is a schematic cross-sectional view of a conventional silicon carbide vertical power MOSFET 100 having the above-described unit cell structure. Figure 2 is a cross-section of a single unit cell of the device. As shown in Figure 2, the MOSFET 100 includes a heavily doped (n+)n-type silicon carbide semiconductor substrate 110. A lightly doped n-type (n-) silicon carbide drift layer 120 is disposed on the silicon carbide substrate 110. A region called a "well" or "p-well" 130, doped to have p-type conductivity, is formed in the upper portion of the n-type silicon carbide drift layer 120. The p-well 130 can be formed, for example, by dedoping a portion of the n-type silicon drift layer 120 with a p-type dopant. A heavily doped (n+)n-type silicon carbide source region 140 is disposed in the upper portion of the p-well 130. The n-type source region 140 can be formed, for example, by dedoping a portion of the p-well 130 with an n-type dopant. The drift layer 120 and the substrate 110 together serve as the common drain region of the device 100. The n-type silicon carbide substrate 110, the n-type silicon carbide drift layer 120, the p-type silicon carbide p-well 130, and the n-type silicon carbide source region 140 together constitute the semiconductor layer structure 150 of the MOSFET 100. A silicon dioxide (SiO2) gate oxide layer 160 is formed on the upper surface of the semiconductor layer structure 150. A gate electrode 170 is provided on the gate oxide layer 160 opposite to the semiconductor layer structure 150. The gate electrode 170 is typically formed of polysilicon. A dielectric isolation pattern 180 is formed on the gate oxide layer 160 and the gate electrode 170, and a source metallization 190 is formed on the dielectric isolation pattern 180 and the exposed source region 140. A drain contact (not shown) is typically provided on the lower surface of the substrate 110 opposite to the drift layer 120. Summary of the Invention

[0011] According to embodiments of the present invention, a semiconductor device is provided, comprising a semiconductor layer structure comprising silicon carbide, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite to the semiconductor layer structure. The gate dielectric layer includes a base gate dielectric layer on the semiconductor layer structure and a capped gate dielectric layer on the base gate dielectric layer opposite to the semiconductor layer structure. The dielectric constant of the capped gate dielectric layer is higher than that of the base gate dielectric layer.

[0012] In some embodiments, the cap gate dielectric layer is thinner than the base gate dielectric layer.

[0013] In some embodiments, the base gate dielectric layer may be a silicon oxide layer.

[0014] In some embodiments, the thickness of the base gate dielectric layer may be at least five times that of the cap gate dielectric layer, and the dielectric constant of the cap gate dielectric layer may be at least three times that of the base gate dielectric layer.

[0015] In some embodiments, the gate electrode may include silicon.

[0016] In some embodiments, the semiconductor layer structure further includes a first well region and a second well region separated by the JFET region, and the cap gate dielectric layer is not on the upper surface of the JFET region.

[0017] In some embodiments, the gate electrode may have a stepped lower surface.

[0018] In some embodiments, the opposite upper edge of the gate electrode may be further above the semiconductor layer structure than the center portion of the upper surface of the gate electrode.

[0019] In some embodiments, the cap gate dielectric layer may be present only on a portion of the base gate dielectric layer.

[0020] In some embodiments, the semiconductor layer structure may include a drift layer having a first conductivity type, a well having a second conductivity type in the upper portion of the drift layer, and a source region having a first conductivity type in the upper portion of the well. A channel region may be disposed in the well between the source region and a portion of the drift layer that is directly in contact with the gate dielectric layer.

[0021] In some embodiments, the capped gate dielectric layer may be formed on the source region and may not be formed on the portion of the drift layer that directly contacts the gate dielectric layer.

[0022] In some embodiments, the semiconductor device may be configured such that during on-state operation, the peak electric field value in the gate dielectric layer will be substantially located at the upper surface of the base gate dielectric layer below the side edge of the gate electrode.

[0023] In some embodiments, the semiconductor device may be configured such that during on-state operation, the peak electric field value in the base gate dielectric layer is at least 50% greater than the peak electric field value in the cap gate dielectric layer.

[0024] In some embodiments, the semiconductor device may be a MISFET or an IGBT.

[0025] In some embodiments, the thickness of the gate dielectric layer may be at least 25 nanometers.

[0026] In some embodiments, the capped gate dielectric layer may include an etch stop layer relative to the gate electrode.

[0027] In some embodiments, the ratio of the thickness of the base gate dielectric layer divided by the dielectric constant of the material of the base gate dielectric layer to the thickness of the cap gate dielectric layer divided by the dielectric constant of the material of the cap gate dielectric layer can be at least ten.

[0028] In some embodiments, the semiconductor layer structure may include trenches in its upper surface, and the gate dielectric layer and the gate electrode may each be at least partially within the trenches.

[0029] In some embodiments, at least some corners of the trench may be rounded.

[0030] According to another embodiment of the present invention, a semiconductor device is provided, the semiconductor device including a semiconductor layer structure comprising silicon carbide, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite to the semiconductor layer structure. The semiconductor device is configured such that during on-state operation, the peak electric field in the gate dielectric layer is below the top surface of the gate dielectric layer.

[0031] In some embodiments, the gate layer may include a base gate dielectric layer on the semiconductor layer structure and a cap gate dielectric layer on the base gate dielectric layer opposite to the semiconductor layer structure.

[0032] In some embodiments, the semiconductor device may be configured such that the peak electric field in the gate dielectric layer is in the base gate dielectric layer during on-state operation.

[0033] In some embodiments, the semiconductor device may be configured such that during on-state operation, the peak electric field value in the gate dielectric layer is substantially located at the upper surface of the base gate dielectric layer below the side edge of the gate electrode.

[0034] In some embodiments, the semiconductor device may be configured such that the peak electric field in the gate dielectric layer is at least 2 nm below the top surface of the gate dielectric layer during on-state operation.

[0035] In some embodiments, the cap gate dielectric layer may be thinner than the base gate dielectric layer.

[0036] In some embodiments, the base gate dielectric layer may include a silicon oxide layer and the gate electrode may include silicon.

[0037] In some embodiments, the thickness of the base gate dielectric layer may be at least five times that of the cap gate dielectric layer, and the dielectric constant of the cap gate dielectric layer may be at least three times that of the base gate dielectric layer.

[0038] In some embodiments, the semiconductor layer structure may include a drift layer having a first conductivity type, first and second wells each having a second conductivity type in the spaced upper portion of the drift layer, first and second source regions having a first conductivity type in the upper portion of the respective first and second wells, a JFET region having a first conductivity type between the first and second wells, and first and second channel regions disposed in the respective first and second wells between the respective first and second source regions and the JFET region.

[0039] In some embodiments, the capped gate dielectric layer may not be located on the upper surface of the JFET region.

[0040] In some embodiments, the gate electrode may have a stepped lower surface.

[0041] In some embodiments, the opposite upper edge of the gate electrode may be further above the semiconductor layer structure than the center portion of the upper surface of the gate electrode.

[0042] In some embodiments, the cap gate dielectric layer may be formed only on a portion of the base gate dielectric layer.

[0043] In some embodiments, the semiconductor device may be configured such that during on-state operation, the peak electric field value in the gate dielectric layer will be substantially located at the upper surface of the base gate dielectric layer below the side edge of the gate electrode.

[0044] In some embodiments, the semiconductor device may be configured such that during on-state operation, the peak electric field value in the base gate dielectric layer is at least 50% greater than the peak electric field value in the cap gate dielectric layer.

[0045] In some embodiments, the ratio of the thickness of the base gate dielectric layer divided by the dielectric constant of the material of the base gate dielectric layer to the thickness of the cap gate dielectric layer divided by the dielectric constant of the material of the cap gate dielectric layer may be at least ten or at least fifteen.

[0046] In some embodiments, the semiconductor layer structure may include trenches in its upper surface, and the gate dielectric layer and the gate electrode may each be at least partially within the trenches.

[0047] In some embodiments, the upper corner of the trench may be a rounded corner, and the gate dielectric layer may be conformally disposed on the semiconductor layer structure and within the trench.

[0048] In some embodiments, the lower corner of the trench may be a rounded corner, and the gate dielectric layer may be conformally disposed within the trench.

[0049] According to an additional embodiment of the present invention, a semiconductor device is provided, comprising: a semiconductor layer structure including a silicon carbide drift layer having a first conductivity type, first and second silicon carbide wells each having a second conductivity type in respective upper portions of the drift layer, first and second silicon carbide source regions having the first conductivity type in the upper portions of the respective first and second wells, and a JFET region having the first conductivity type between the first and second wells; a gate dielectric layer on the semiconductor layer structure, the gate dielectric layer including a silicon oxide base gate dielectric layer on the semiconductor layer structure and a capped gate dielectric layer on the base gate dielectric layer opposite to the semiconductor layer structure; and a silicon gate electrode on the gate dielectric layer opposite to the semiconductor layer structure. The semiconductor device is configured such that during on-state operation, the peak electric field value in the base gate dielectric layer is at least 50% greater than the peak electric field value in the capped gate dielectric layer.

[0050] In some embodiments, the thickness of the base gate dielectric layer may be at least five times that of the cap gate dielectric layer, and the dielectric constant of the cap gate dielectric layer may be at least three times that of the base gate dielectric layer.

[0051] In some embodiments, the semiconductor device may be configured such that the peak electric field in the gate dielectric layer is in the base gate dielectric layer during on-state operation.

[0052] In some embodiments, the semiconductor device may be configured such that during on-state operation, the peak electric field value in the gate dielectric layer is substantially located at the upper surface of the base gate dielectric layer below the side edge of the gate electrode.

[0053] In some embodiments, the capped gate dielectric layer is not located above the upper surface of the JFET region.

[0054] In some embodiments, the gate electrode may have a stepped lower surface.

[0055] In some embodiments, the opposite upper edge of the gate electrode may be further above the semiconductor layer structure than the center portion of the upper surface of the gate electrode.

[0056] In some embodiments, the cap gate dielectric layer is formed only on a portion of the base gate dielectric layer.

[0057] In some embodiments, the semiconductor layer structure may include trenches in its upper surface, wherein the gate dielectric layer and the silicon gate electrode are each at least partially within the trenches.

[0058] In some embodiments, the ratio of the thickness of the base gate dielectric layer divided by the dielectric constant of the material of the base gate dielectric layer to the thickness of the cap gate dielectric layer divided by the dielectric constant of the material of the cap gate dielectric layer can be at least ten.

[0059] According to another embodiment of the present invention, a method for forming a semiconductor device is provided, wherein a semiconductor layer structure is formed, the semiconductor layer structure including a silicon carbide drift layer having a first conductivity type, first and second silicon carbide wells each having a second conductivity type in their respective upper portions of the drift layer, first and second silicon carbide source regions having the first conductivity type in their upper portions of the respective first and second wells, and a JFET region having the first conductivity type between the first and second wells. A base gate dielectric layer is formed on the semiconductor layer structure. A capped gate dielectric layer is formed on the base gate dielectric layer, the dielectric constant of the capped gate dielectric layer being greater than the dielectric constant of the base gate dielectric layer. A gate electrode comprising silicon is formed on the capped gate dielectric layer opposite to the semiconductor layer structure. Portions of the base gate dielectric layer and the capped gate dielectric layer are removed to form a base gate dielectric layer and a capped gate dielectric layer that together form at least a portion of the gate dielectric layer.

[0060] In some embodiments, forming a capped gate dielectric layer on a base gate dielectric layer includes forming a mask on a semiconductor layer structure after forming the base gate dielectric layer, forming a capped gate dielectric layer on both the mask and the base gate dielectric layer, and removing a portion of the mask layer and the capped gate dielectric layer to expose a portion of the base gate dielectric layer.

[0061] In some embodiments, the exposed portion of the base gate dielectric layer includes a portion of the base gate dielectric layer above the JFET region.

[0062] In some embodiments, the cap gate dielectric layer may be thinner than the base gate dielectric layer.

[0063] In some embodiments, the thickness of the base gate dielectric layer may be at least five times that of the cap gate dielectric layer, and the dielectric constant of the cap gate dielectric layer may be at least three times that of the base gate dielectric layer.

[0064] In some embodiments, forming a gate electrode comprising silicon on a capped gate dielectric layer relative to a semiconductor layer structure includes blanket deposition of a gate electrode layer on a base gate dielectric layer and a capped gate dielectric layer, and then using the capped gate dielectric layer as an etch stop layer to etch the gate electrode layer to form a gate electrode.

[0065] In some embodiments, the gate electrode may have a stepped lower surface.

[0066] In some embodiments, the semiconductor device may be configured such that during on-state operation, the peak electric field value in the base gate dielectric layer is at least 50% greater than the peak electric field value in the cap gate dielectric layer.

[0067] According to an embodiment of the present invention, a semiconductor device is provided, the semiconductor device comprising: a semiconductor layer structure comprising silicon carbide, the semiconductor layer structure including trenches formed therein, wherein at least some corners of the trenches are rounded; a gate dielectric layer on the semiconductor layer structure and within the trenches, the gate dielectric layer including a lower corner and an upper corner, wherein at least one of the lower corner and the upper corner includes a rounded corner; and a gate electrode on the gate dielectric layer opposite to the semiconductor layer structure.

[0068] In some embodiments, the gate dielectric layer may include a silicon oxide base gate dielectric layer and a capping gate dielectric layer on the upper surface of the base gate dielectric layer.

[0069] In some embodiments, the dielectric constant of the cap gate dielectric layer may be at least three times that of the base gate dielectric layer.

[0070] In some embodiments, the semiconductor layer structure may include a drift layer having a first conductivity type, a well having a second conductivity type located above the drift layer, and a source region having a first conductivity type located above the well.

[0071] In some embodiments, the semiconductor device may be configured such that during on-state operation, the peak electric field value in the base gate dielectric layer is at least 50% greater than the peak electric field value in the cap gate dielectric layer.

[0072] In some embodiments, the thickness of the cap gate dielectric layer can be between two and fifteen nanometers. Attached Figure Description

[0073] Figure 1 is a semi-logarithmic graph illustrating the relationship between the lifetime of the gate dielectric layer and the applied electric field strength.

[0074] Figure 2 is a schematic cross-sectional view of a unit cell of a conventional silicon carbide MOSFET.

[0075] Figure 3A This is an enlarged view of part A of a conventional silicon carbide MOSFET in Figure 2, showing the electric field values ​​in the gate dielectric layer and its dielectric isolation pattern.

[0076] Figure 3B This is a graph showing the simulated electric field strength in the gate dielectric layer along line 3B-3B of a conventional silicon carbide MOSFET in Figure 2 during on-state operation.

[0077] Figure 4 This is a schematic cross-sectional view of a unit cell of a silicon carbide MOSFET according to an embodiment of the present invention.

[0078] Figure 5A This is an enlarged cross-sectional view of a portion of a conventional silicon carbide MOSFET in Figure 2.

[0079] Figure 5B This indicates that during operation in the on state, along Figure 5A The simulated electric field strength curve of a conventional silicon carbide MOSFET line 5B-5B is shown.

[0080] Figure 5C This indicates that during operation in the on state, along Figure 5A The simulated electric field strength curve of a conventional silicon carbide MOSFET at line 5C-5C is shown in the figure.

[0081] Figure 6A yes Figure 4 An enlarged cross-sectional view of portion C of a silicon carbide MOSFET according to an embodiment of the present invention.

[0082] Figure 6B This indicates that during operation in the on state, along Figure 6A The simulated electric field strength curve of the silicon carbide MOSFET line 6B-6B is shown in the figure.

[0083] Figure 6C This indicates that during operation in the on state, along Figure 6A The simulated electric field strength curve of the silicon carbide MOSFET line 6C-6C is shown in the figure.

[0084] Figure 7 It shows that it is aimed at Figure 5A Conventional silicon carbide MOSFETs and those targeting Figure 6A A simulated drain current versus gate voltage response curve of a silicon carbide MOSFET according to an embodiment of the present invention.

[0085] Figure 8 This is a schematic cross-sectional view of a silicon carbide MOSFET according to a further embodiment of the present invention.

[0086] Figures 9A-9D The illustration is for manufacturing. Figure 8 A schematic cross-sectional view of a method for making silicon carbide MOSFETs.

[0087] Figure 10 This is a schematic cross-sectional view of a silicon carbide MOSFET according to an additional embodiment of the present invention.

[0088] Figure 11 yes Figure 10A schematic cross-sectional view of a modified version of a silicon carbide MOSFET.

[0089] Figure 12 This is a schematic cross-sectional view of the gate trench region of a MOSFET according to an embodiment of the present invention, illustrating how the corners of the gate trench can be rounded. Detailed Implementation

[0090] When a MOSFET is in its conduction or on state, an electric field is generated within the gate dielectric layer of the device. The strength of this electric field can be particularly high in the portion of the gate dielectric layer directly below the sidewall of the gate electrode. As discussed above, the lifetime of the gate dielectric layer depends on the strength of the electric field within it. Therefore, because the portion of the gate dielectric layer below the sidewall of the gate electrode experiences the highest electric field, these regions will typically be the first to experience breakdown.

[0091] As discussed above with reference to Figure 2, power silicon carbide MOSFETs typically include a polysilicon gate electrode 170. The polysilicon gate electrode 170 is formed by blanket deposition of a polysilicon layer on the upper surface of the device followed by etching to form a gate electrode layer including the individual gate electrode 170. Since the gate dielectric layer is formed of silicon oxide and the gate electrode is formed of silicon, the etchant(s) used to etch away unwanted portions of the gate electrode layer may also tend to easily etch the silicon oxide due to the similarity between the two materials. Typically, if over-etching occurs during this etching step, the portion of the silicon oxide gate dielectric layer 160 directly below the sidewall of the gate electrode 170 may be partially etched away due to over-etching. Therefore, the potentially over-etched portion of the gate dielectric layer 160 is also the portion of the gate dielectric layer 160 that experiences the highest electric field value during on-state operation, making this portion of the gate dielectric layer 160 particularly susceptible to breakdown. Moreover, this portion of the gate dielectric layer 160 directly overlaps the source region 140. Since the failure mechanism of MOSFET breakdown is a short circuit between the gate electrode 170 and the source region 140, the fact that the portion of the gate dielectric layer 160 directly covering the source region 140 is the most vulnerable to breakdown tends to shorten the time of device failure due to breakdown.

[0092] According to embodiments of the present invention, a power semiconductor device having a multilayer gate dielectric layer is provided, which will exhibit increased lifetime. Specifically, the gate dielectric layer may include at least a silicon oxide base gate dielectric layer (or a base gate dielectric layer formed of some other dielectric material such as silicon nitride) formed on a semiconductor layer structure and a high-k dielectric capping gate dielectric layer formed on at least a portion of the silicon oxide base gate dielectric layer. Additional layers may also be included. For example, a multilayer base gate dielectric layer may be provided. As another example, a second capping gate dielectric layer may be provided, for example, directly on or opposite to the first capping gate dielectric layer on the base gate dielectric layer. The high-k dielectric capping gate dielectric layer may be formed of a material that acts as an etch stop layer during the etching of the gate electrode layer to form the gate electrode of the device. In particular, most high-k dielectric gate dielectric materials are chemically very different from silicon, and therefore etchants that will easily etch silicon without etching these high-k dielectric gate dielectric materials are readily available. Therefore, the high-dielectric-constant capped gate dielectric layer can protect the underlying silicon oxide base gate dielectric layer from over-etching during this etching step. Furthermore, the electric field level in the gate dielectric layer decreases as the dielectric constant increases, depending on the dielectric constant of the materials used to form the gate dielectric layer. Therefore, the electric field strength in the high-dielectric-constant capped gate dielectric layer will be less than the electric field strength in the same portion of the silicon oxide gate dielectric layer of a conventional power semiconductor device. Additionally, as discussed above, the location where the electric field in the conventional gate dielectric layer 160 reaches its maximum value during on-state operation is the top of the gate dielectric layer 160, located below the outer edge of the gate electrode 170. Since the top of the gate dielectric layer according to an embodiment of the invention is formed using a high-dielectric-constant material, the electric field strength in these regions will be reduced compared to the conventional gate dielectric layer 160. Due to the reduced peak electric field value, the lifetime of the gate dielectric layer can be extended, as discussed above with reference to FIG. 1.

[0093] Typically, the thickness of a conventional gate dielectric layer is based on the desired equivalent electrooxide thickness to optimize various performance characteristics of the device. If the equivalent electrooxide thickness is to be maintained when adding a high-dielectric-constant capped gate dielectric layer, it becomes necessary to reduce the thickness of the original or silicon oxide "base" gate dielectric layer. This reduction in the thickness of the base gate dielectric layer is used to increase the electric field strength in the silicon oxide of the base gate dielectric layer. To keep this increase in electric field strength in the silicon oxide base gate dielectric layer at an acceptable level, the high-dielectric-constant capped gate dielectric layer can be a very thin layer, substantially thinner than the silicon oxide base gate dielectric layer (e.g., approximately 1 / 4 the thickness in the example embodiment). In some embodiments, the thickness of the high-dielectric-constant capped gate dielectric layer can be less than ten nanometers.

[0094] The material for the high-dielectric-constant capped gate dielectric layer can be selected based on several factors. The chemical properties of the high-dielectric-constant material should be chemically compatible with the materials of the underlying and overlay / patterning layers in the device. The dielectric constant of the material can also be considered, as a higher dielectric constant allows for a thicker capped gate dielectric layer and / or a greater reduction in the electric field intensity within the high-dielectric-constant capped gate dielectric layer. Furthermore, the effectiveness of the high-dielectric-constant capped gate dielectric layer as an etch stop layer is another factor to consider, taking into account the etch chemistry used for patterning the gate electrode. The high-dielectric-constant capped gate dielectric layer is also preferably substantially amorphous during any subsequent high-temperature processing steps, preventing grain boundaries from forming across layers that could act as diffusion paths for the etchant.

[0095] The multilayer gate dielectric layer according to embodiments of the present invention can be used in planar MOSFETs (and similar devices) and devices having gate trench structures. When the gate dielectric layer according to embodiments of the present invention is used in a device having a gate trench structure, techniques can be used to round the corners of the gate trench before the gate dielectric layer is formed therein. By rounding the corners of the gate trench (including both the lower and upper corners), electric field congestion effects can be reduced, which can further reduce the peak electric field value experienced in the gate dielectric layer during on-state operation, which can increase the device lifetime. The techniques disclosed herein for rounding the corners of the gate trench can also be used independently of the multilayer gate dielectric layer to improve the performance of conventional power semiconductor devices.

[0096] Power semiconductor devices according to embodiments of the present invention can perform almost identically to conventional power semiconductor devices including conventional silicon oxide gate dielectric layers, while exhibiting significantly improved device reliability. For example, the peak electric field in the gate dielectric layer of a power semiconductor device according to embodiments of the present invention can be 20%, 30%, 40%, 50%, or more lower than the peak electric field in the gate dielectric layer of a comparable conventional power semiconductor device. Moreover, the gate dielectric layer in a power semiconductor device according to embodiments of the present invention is significantly less susceptible to etch damage during the etching of the gate electrode layer, thus resulting in both a longer expected lifetime and fewer instances of premature device failure.

[0097] According to some embodiments of the present invention, a power semiconductor device is provided, comprising a semiconductor layer structure including silicon carbide, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite to the semiconductor layer structure. The gate dielectric layer includes a base gate dielectric layer on the semiconductor layer structure and a capped gate dielectric layer on the base gate dielectric layer opposite to the semiconductor layer structure. The dielectric constant of the capped gate dielectric layer is higher than that of the base gate dielectric layer. The capped gate dielectric layer may be thinner than the base gate dielectric layer.

[0098] According to another embodiment of the present invention, a power semiconductor device is provided, the power semiconductor device including a semiconductor layer structure comprising silicon carbide, a gate dielectric layer on the semiconductor layer structure, and a gate electrode on the gate dielectric layer opposite to the semiconductor layer structure. The semiconductor device is configured such that during on-state operation, the peak electric field in the gate dielectric layer is below the top surface of the gate dielectric layer.

[0099] According to further embodiments of the present invention, a power semiconductor device is provided, comprising a semiconductor layer structure including a silicon carbide drift layer having a first conductivity type, first and second silicon carbide wells each having a second conductivity type in respective upper portions of the drift layer, first and second silicon carbide source regions having the first conductivity type in the upper portions of the respective first and second wells, and a JFET region having the first conductivity type between the first and second wells. These devices also include a gate dielectric layer on the semiconductor layer structure and a silicon gate electrode on the gate dielectric layer opposite to the semiconductor layer structure, the gate dielectric layer including a silicon oxide base gate dielectric layer on the semiconductor layer structure and a capped gate dielectric layer on the base gate dielectric layer opposite to the semiconductor layer structure. The semiconductor device is configured such that during on-state operation, the peak electric field value in the base gate dielectric layer is at least 50% greater than the peak electric field value in the capped gate dielectric layer.

[0100] According to another embodiment of the present invention, a method for forming a semiconductor device is provided, wherein the semiconductor layer structure includes a silicon carbide drift layer having a first conductivity type, first and second silicon carbide wells each having a second conductivity type in their respective upper portions of the drift layer, first and second silicon carbide source regions having the first conductivity type in their upper portions of the respective first and second wells, and a JFET region having the first conductivity type between the first and second wells. A base gate dielectric layer is formed on the semiconductor layer structure. A capped gate dielectric layer is formed on the base gate dielectric layer, the dielectric constant of which is greater than that of the base gate dielectric layer. A gate electrode comprising silicon is formed on the capped gate dielectric layer opposite to the semiconductor layer structure.

[0101] Now refer to Figures 3A-12 A semiconductor device according to embodiments of the present invention will be described in more detail.

[0102] As discussed above, a common failure mechanism in power semiconductor devices is device failure due to breakdown of the gate dielectric layer. Since the lifetime of the gate dielectric layer (i.e., the time until breakdown) depends on the strength of the electric field in the gate dielectric layer during device operation, one way to reduce instances of device failure is to design the device with a reduced peak electric field value in the gate dielectric layer. While there are known methods to achieve this, such as forming the gate dielectric layer with a material having a high dielectric constant, the available techniques for reducing the electric field value often negatively impact the electrical performance of the device.

[0103] The electric field strength generated in the gate dielectric layer of a conventional power semiconductor device during on-state operation is not constant. The gate dielectric layer of the conventional power semiconductor device in Figure 2 can be considered as the dielectric of a parallel-plate capacitor, where the gate electrode acts as the first plate, and the portion of the semiconductor layer structure below the gate electrode acts as the other plate. During on-state operation, the electric field will have a substantially constant value throughout the "parallel-plate" region of the gate dielectric layer, which refers to the central region of the portion of the gate dielectric layer below the gate electrode. However, in the "corner regions" of the gate dielectric layer, i.e., the portions of the gate dielectric layer directly below or near the side edge of the gate electrode, electric field congestion increases the electric field level, particularly in the upper part of the gate dielectric layer.

[0104] This phenomenon Figure 3A and Figure 3B As shown in the image. Specifically, Figure 3A This is an enlarged view of part "A" in Figure 2, showing the electric field values ​​in the gate dielectric layer and its dielectric isolation pattern. Figure 3AIn the diagram, different fill patterns indicate different electric field intensities in the gate dielectric layer and dielectric isolation pattern, and the illustration shows the relative values ​​of different shades. Figure 3B This indicates that during operation in the on state, along Figure 3A The graph shows the simulated electric field strength in the gate dielectric layer of line 3B-3B. As can be seen, the electric field strength is relatively constant in the "parallel plate" region of the gate dielectric layer 160. However, the electric field strength increases sharply in the corner region. Figure 3A The peak electric field is reached in the region marked "B," which is the top surface of the portion of the gate dielectric layer 160 directly below the sidewall of the gate electrode 170. Since the peak electric field in this corner region is approximately 25% larger than the peak electric field in the parallel plate region of the gate dielectric layer 160, this corner region is the part of the gate dielectric layer 160 most likely to experience breakdown first. This results in a higher electric field being generated in the surrounding dielectric material upon breakdown, ultimately leading to device failure.

[0105] As will be discussed in detail below, the semiconductor device according to embodiments of the present invention can both shift the location where the peak electric field occurs and reduce the peak value of the electric field. Therefore, the semiconductor device according to embodiments of the present invention can have increased lifetime until dielectric breakdown and thus exhibit improved reliability.

[0106] Figure 4 This is a schematic cross-sectional view of a unit cell of a MOSFET 200 according to an embodiment of the present invention. Figure 4 As shown, the MOSFET 200 includes an n-type silicon carbide semiconductor substrate 210. The substrate 210 may include, for example, a single-crystal 4H silicon carbide semiconductor substrate heavily doped with n-type impurities (i.e., an n+ silicon carbide substrate). A lightly doped n-type (n-) silicon carbide drift layer 220 is formed on the substrate 210. The upper portion of the n-type silicon carbide drift layer 220 can be p-type doped by, for example, ion implantation to form a silicon carbide p-well 230. A heavily doped (n+) n-type silicon carbide region 240 can be formed in the upper portion of the silicon carbide p-well 230. The n-type region 240 can be formed by ion implantation. The heavily doped (n+) n-type silicon carbide region 240 serves as the source region of the device 200. The drift layer 220 and the substrate 210 together serve as the common drain region of the device 200. The n-type substrate 210, the n-type drift layer 220 formed therein, the p-well 230 and the n-type source region 240 can together constitute the semiconductor layer structure 250 of the device 200.

[0107] A gate dielectric layer 260 may be formed on the upper surface of the semiconductor layer structure 250. The gate dielectric layer 260 may include a stable dielectric material whose bandgap is approximately 2 eV (or more) larger than the underlying semiconductor. The gate dielectric layer 260 includes at least a base dielectric layer 262 and a capping dielectric layer 264. The base gate dielectric layer 262 may include, for example, a silicon oxide (SiO2) layer. The capping gate dielectric layer 264 may include a dielectric material having a dielectric constant higher than that of silicon oxide. For example, the capping gate dielectric layer 264 may include a variety of high dielectric constant materials, including tantalum-based, titanium-based, aluminum-based, zirconium-based, yttrium-based, and hafnium-based materials. In some embodiments, the capping gate dielectric layer 264 may include at least one of silicon, tantalum, titanium, aluminum, zirconium, yttrium, or hafnium, and at least one of oxygen or nitrogen. For example, silicon oxynitride hafnium may be used in an example embodiment. Other suitable materials for the capped gate dielectric layer 264 include silicates (Si... x Metal y O z The compound may be a silicon-metal nitride compound. Lanthanum or a lanthanide element may also be a metal in a silicate or nitride compound. Simple oxide compounds such as MgO or Al2O3 and simple nitrides such as AlN may be suitable. In some embodiments, the capped gate dielectric layer 264 may include silicon, a metal, and at least one of oxygen or nitrogen. In some embodiments, the capped gate dielectric layer 264 may include silicon, a metal, and both oxygen and nitrogen. It will be appreciated that the gate dielectric layer (including its sublayers) described herein is generally implemented as a patterned layer formed by blanket deposition of one or more dielectric layers and then patterning that layer(s).

[0108] While the exemplary embodiments of the invention discussed below focus primarily on examples where the base gate dielectric layer includes a silicon oxide layer, it will be appreciated that embodiments of the invention are not limited thereto. For example, the base gate dielectric layer may be formed of another dielectric material (e.g., silicon nitride, silicon oxynitride, etc.), or may comprise a multilayer structure (e.g., a silicon oxide layer and a silicon oxynitride layer). Similarly, the capped gate dielectric layer may be a multilayer structure (e.g., having two or three different high-dielectric-constant material layers or a combination of low and high-dielectric-constant layers) and / or more than one capped gate dielectric layer may be provided. References below Figure 11 Examples of devices having first and second capped gate dielectric layers are discussed.

[0109] A gate electrode 270 is formed on the gate dielectric layer 260 opposite to the semiconductor layer structure 250. The gate electrode 270 may include, for example, silicides (e.g., NiSi, TiSi, WSi, CoSi), doped polysilicon (poly-Si), and / or stable conductors. Other suitable materials for the gate electrode include various metals such as Ti, Ta, or W, or metal nitrides such as TiN, TaN, or WN. A channel region 232 is disposed in the upper portion of the p-well 230 between the source region 240 and the so-called "JFET" portion 224 of the drift layer 220, which is located directly below the gate dielectric layer 260.

[0110] A dielectric isolation pattern 280 is formed on the gate dielectric layer 260 and the gate electrode 270, and a source metallization 290 is formed on the dielectric isolation pattern 280 and on the exposed portion of the semiconductor layer structure 250. A drain contact (not shown) may be disposed on the lower surface of the substrate 210 opposite to the drift layer 220.

[0111] Figure 4 The semiconductor layer structure 250 is merely an example, and other configurations of the semiconductor layer structure 250 can be used without departing from the embodiments described herein. For example, the semiconductor layer structure 250 may include additional layers or regions, such as a more heavily doped current-spreading layer / region above the drift region 220 (e.g., in the JFET region 224). It should also be understood that the embodiments described herein can be used in any gated semiconductor device using a metal-oxide and / or metal-insulator interface, such as MISFETs, IGBT devices, and gated thyristors, to name just a few. Therefore, it will be understood that the semiconductor layer structure 250 can take many other forms without departing from the embodiments described herein.

[0112] It will be appreciated that the above description pertains to n-type MOSFETs. In p-type devices, the positions of the source and drain contacts can be reversed, and the conductivity types of other n-type and p-type regions can be interchanged. All embodiments disclosed herein can be implemented as either n-type or p-type devices.

[0113] As discussed above, the base gate dielectric layer can be substantially thicker than the cap gate dielectric layer. In example embodiments, the base gate dielectric layer can be substantially thicker than the cap gate dielectric layer, and the thickness can be at least two, three, four, or five times that of the cap gate dielectric layer. Conventional silicon carbide-based power semiconductor devices, such as power MOSFETs and IGBTs, have relatively thick silicon oxide gate dielectric layers. For example, a typical thickness can be approximately 35-60 nm. Power semiconductor devices according to embodiments of the present invention can have gate dielectric layers of similar thickness or possibly even thicker.

[0114] Generally, the equivalent electrooxide thickness of the gate dielectric layer in a power semiconductor device can be selected based on the desired performance criteria of the device. Therefore, if a conventional power semiconductor device is to be modified to have a multilayer gate dielectric layer according to an embodiment of the invention, then the multilayer gate dielectric layer can be designed such that its thickness-to-dielectric-constant ratio (T / Dk) is approximately the same as the T / Dk ratio of the modified power semiconductor device. Therefore, a portion of the silicon oxide gate dielectric layer in a conventional device can be omitted and replaced with a capped gate dielectric layer having a higher dielectric constant. The thickness of the capped gate dielectric layer can be greater than the thickness of the omitted portion of the conventional gate dielectric layer by a factor equal to the ratio of the dielectric constant of the high-dielectric-constant material used in the capped gate dielectric layer to the dielectric constant of silicon oxide (approximately 3.9).

[0115] For example, suppose a conventional power semiconductor device having a 36 nm thick silicon oxide gate dielectric layer is to be modified to have a multilayer gate dielectric layer according to an embodiment of the present invention. In this example, 5% of the silicon oxide gate dielectric layer is replaced with hafnium oxide. Therefore, 1.6 nm of the 36 nm silicon oxide gate dielectric layer in the conventional device is replaced by a hafnium oxide gate dielectric layer, leaving a 34.4 nm silicon oxide base gate dielectric layer. The dielectric constant of hafnium oxide is approximately 20, which is approximately five times the dielectric constant of silicon oxide (3.9). Therefore, an 8 nm hafnium oxide capping gate dielectric layer can be added to replace the omitted 1.6 nm of silicon oxide while (generally) maintaining the same electrical performance.

[0116] As clearly illustrated in the example above, the ratio of the thickness of the base gate dielectric layer to the thickness of the cap gate dielectric layer can depend on a comparison of the dielectric constant of the cap gate dielectric layer with that of the base gate dielectric layer (typically 3.9, since silicon oxide is commonly used). Therefore, this document will refer to the “equivalent thickness” of the base and cap gate dielectric layers, where “equivalent thickness” is the thickness of the layer divided by the dielectric constant of the material forming the layer. Thus, in the example above, the equivalent thickness of the base gate dielectric layer is 34.4 nm / 3.9 = 8.82 nm. Similarly, the equivalent thickness of the cap gate dielectric layer is 8 nm / 20 = 0.4 nm. Therefore, in this example, the ratio of the equivalent thickness of the base gate dielectric layer to the equivalent thickness of the cap gate dielectric layer is 22.05. In exemplary embodiments of the invention, the ratio of the equivalent thickness of the base gate dielectric layer to the equivalent thickness of the cap gate dielectric layer can be at least 5, at least 10, at least 15, at least 20, or at least 25.

[0117] Note that the "thickness" of the gate dielectric layer in this article refers to the range of the gate dielectric layer in the direction perpendicular to the lower surface on which the gate dielectric layer is formed. Therefore, in the above... Figure 4 In the example, the thickness is Figure 4 Measured in the vertical direction (i.e., in the direction perpendicular to the upper surface of the semiconductor layer structure 250). In power semiconductor devices with gate trenches, such as those described herein... Figure 10 and Figure 11 In power semiconductor devices, the thickness of the gate dielectric layer is measured in the vertical direction for the portion of the gate dielectric layer on the upper surface of the semiconductor layer structure, while the thickness of the portion of the gate dielectric layer on the sidewall of the trench is measured in the horizontal direction.

[0118] As described above, the capped gate dielectric layer 264 can be formed of a material with etch selectivity relative to silicon oxide. Therefore, the capped gate dielectric layer 264 can act as an etch stop pattern during the etch step used to pattern the gate electrode layer to form the gate electrode 270. Over-etching of the gate electrode of a power MOSFET, which leads to damage to the gate dielectric layer, is a significant cause of device failure in power MOSFETs.

[0119] The high-k dielectric capping gate dielectric layer 264 can be formed from a material that acts as an etch stop layer during the etching of the gate electrode layer to form the gate electrode 270 of the MOSFET 200. In particular, most high-k dielectric materials that can be used in the capping gate dielectric layer 264 are chemically very different from silicon, and therefore etchants that readily etch the polysilicon gate electrode layer without etching these high-k dielectric materials are readily available. Therefore, the multilayer gate dielectric layer 264 according to embodiments of the present invention can reduce or eliminate such over-etching and the resulting device failures.

[0120] While the multilayer gate dielectric layer 260 can prevent over-etching, a drawback of reducing the thickness of the silicon oxide base gate dielectric layer 262 (compared to the thickness of the silicon oxide gate dielectric layer 160 in a comparable conventional device) is that the reduced thickness generally increases the electric field value in the parallel plate region of the base gate dielectric layer 262 during on-state operation of the device. Therefore, due to the increased electric field in the gate dielectric layer 260, using a relatively thick capped gate dielectric layer 264—and thus a thinner silicon oxide base gate dielectric layer 262—may shorten the lifetime of the gate dielectric layer 260. Therefore, according to embodiments of the invention, a relatively thin capped gate dielectric layer 264 can be used to reduce or minimize the reduction in the thickness of the silicon oxide base gate dielectric layer 262, such that any increase in the electric field value will be small. Therefore, for example, in the specific embodiment discussed above, the conventional 36nm silicon oxide gate dielectric layer 160 is replaced by a 34.4nm silicon oxide base gate dielectric layer 262 (i.e., 1.6nm of silicon oxide is omitted) and replaced by an 8nm thick hafnium oxide capped gate dielectric layer 264. Here, the thickness of the base gate dielectric layer 262 is more than four times that of the capped gate dielectric layer 264. If a material with a dielectric constant higher than hafnium oxide is used for the capped gate dielectric layer 264, the thickness ratio can be reduced (because the capped gate dielectric layer 264 can be made thicker than 8nm), while if a material with a dielectric constant lower than hafnium oxide is used for the capped gate dielectric layer 264, the thickness ratio can be increased (because the capped gate dielectric layer 264 will need to be less than 8nm to maintain the same capacitor charge across the gate dielectric layer 260).

[0121] A significant advantage of multilayer gate dielectric layers according to embodiments of the invention, such as gate dielectric layer 260, is that due to the higher dielectric constant material used in capped gate dielectric layer 264, the electric field value in capped gate dielectric layer 264 will be lower than the corresponding electric field value present in silicon oxide gate dielectric layer. The higher dielectric constant of the material of capped gate dielectric layer 264 can significantly reduce the electric field crowding effect below the corner of gate electrode 270, thereby reducing or even almost eliminating gate edge field peaking that would otherwise occur. This can be referred to... Figures 5A-5C and Figures 6A-6C It can be seen. Especially, Figure 5A This is an enlarged cross-sectional view of part "A" of the conventional silicon carbide MOSFET 100 in Figure 2. Figure 5B and Figure 5C This indicates that during operation in the on state, along Figure 5A The simulated electric field intensity curves for lines 5B-5B (corner region) and 5C-5C (parallel plate region) are shown. Similarly, Figure 6A yes Figure 4An enlarged cross-sectional view of part "C" of a silicon carbide MOSFET 200 according to an embodiment of the present invention. Figure 6B and Figure 6C This indicates that during operation in the on state, along Figure 6A The simulated electric field intensity curves for lines 6B-6B (corner region) and 6C-6C (parallel plate region) are shown.

[0122] Figure 5A and Figure 6A The only difference between the devices is Figure 5A The top 1.6nm of the silicon oxide gate dielectric layer of the device Figure 6A The device was replaced with 8nm hafnium oxide. In the process of generating Figure 5b- Figure 5C and Figures 6B-6C In the simulation of the curve, the gate-source bias voltage is 15 volts.

[0123] For example, through comparison Figure 5B and Figure 6B As can be seen, the simulated peak electric field value in the hafnium oxide cap gate dielectric layer 264 is only about 2 x 10⁻⁶. 6 volts / cm ( Figure 6B The peak electric field strength in the silicon oxide gate dielectric layer 160 of a conventional device is approximately 6.5 x 10⁻⁶. 6 volts / cm ( Figure 5B Therefore, in the power semiconductor device according to an embodiment of the present invention, the peak electric field intensity appears in the corner region of the device at the top surface of the silicon oxide base gate dielectric layer 262. Figure 6B As shown, this peak electric field value is approximately 4.3 x 10⁻⁶. 6 volts / cm, compared to the peak electric field value in a conventional MOSFET 100 (6.5 x 10⁻⁶). 6 (V / cm) (See) Figure 5B The electric field peak is reduced by more than one-third. Therefore, the location of the peak electric field shifts downwards by a distance corresponding to the thickness of the cap gate dielectric layer 264, and the maximum value of the electric field can be significantly reduced. This can significantly enhance the device lifetime by delaying dielectric breakdown.

[0124] Figure 5C and Figure 6C The electric field values ​​in the parallel plate regions of MOSFETs 100 and 200 are shown respectively. As illustrated, in each case, the electric field intensity in the silicon oxide portion of the gate dielectric layer 160 / 262 is substantially constant with depth, with a value of approximately 4 x 10⁻⁶. 6 The electric field strength is approximately 1 volt / cm (i.e., the electric field strength is substantially the same in the parallel plate portions of the gate dielectric layer). In MOSFET200, the electric field strength in the hafnium oxide portion of the gate dielectric layer 264 is substantially constant with depth, with a value of approximately 1 x 10⁻⁶.6 The voltage per centimeter (V / cm) is approximately one-quarter of the field in the silicon oxide portion of the gate dielectric layer.

[0125] It is generally expected that the multilayer gate dielectric layers included in the power semiconductor device according to embodiments of the present invention exhibit similar resistance, thereby maintaining the on-state current level. Figure 7 This shows the conventional power MOSFET 100 for Figure 2 and the one for Figure 2. Figure 4 The simulated drain current versus gate voltage response curves for the power MOSFET 200 according to an embodiment of the present invention are shown. As can be seen, the drain current is substantially the same during on-state operation. This indicates that the techniques disclosed herein do not degrade other performance characteristics of the device.

[0126] Figure 8 This is a schematic cross-sectional view of a power MOSFET 300 according to another embodiment of the present invention. The power MOSFET 300 includes a substrate 210, a drift layer 220 (including a JFET region 224), a p-well 230 (including a channel region 232), a source region 240 (i.e., a semiconductor layer structure 250), a base-gate dielectric layer 262, and a source metallization 290, which may be identical to the elements with the same numbering in the MOSFET 200. Further description thereof will therefore be omitted. However, the MOSFET 300 includes a capped gate dielectric layer 364, a gate electrode 370, and a dielectric isolation pattern 380, which are different from their similarly numbered counterparts in the MOSFET 200.

[0127] In particular, such as Figure 8 As shown, the capped gate dielectric layer 364 is formed only on a portion of the base gate dielectric layer 262. In the depicted embodiment, the capped gate dielectric layer 364 is formed only above the source region 240, but embodiments of the invention are not limited thereto. Notably, the capped gate dielectric layer 364 is not formed above the JFET region 224. As a result, the effect of the capped gate dielectric layer 364 on the on-state resistance of the MOSFET 300 may be even smaller (compared to the MOSFET 200 discussed above), meaning that even thicker capped gate dielectric layers 364 can potentially be used, which could increase the effectiveness of the capped gate dielectric layer 364 as an etch stop layer during etching of the gate electrode layer. It also allows the use of materials in the capped gate dielectric layer 364 that might have an adverse effect on the channel region 232, since the capped gate dielectric layer 364 is not deployed above the channel region 232.

[0128] In some embodiments, the capped gate dielectric layer 364 may not extend over the portion of the p-well 230 adjacent to the JFET region 224 contacting the base gate dielectric layer 262 (i.e., the portion of the p-well 230 that acts as the channel region 232). Typically, if the thickness of the portion of the gate dielectric layer located between the gate electrode and the channel region is substantially constant, the performance of the vertical MOSFET can be improved. By forming the capped gate dielectric layer 364 only on the source region 240, the gate dielectric layer 360 can have a constant thickness over the channel region 232.

[0129] like Figure 8 As can be seen, since the capped gate dielectric layer 364 is formed only on a portion of the base gate dielectric layer 262, the gate dielectric layer 360 has a stepped upper surface. Specifically, the capped gate dielectric layer 364 is formed only on the exterior of the source region 240 and the p-well 230, and not on the upper surface of the JFET region 224 (i.e., the portion of the drift layer 220 that directly contacts the base gate dielectric layer 262) or above the channel region 232. Because the gate dielectric layer 360 has a stepped upper surface, the gate electrode 370 has a stepped lower surface. The steps in the lower surface of the gate electrode can cause the gate electrode 370 and the potential ground dielectric isolation pattern 380 to also have stepped upper surfaces, such as... Figure 8 As also shown in the figure, the opposite outer upper edge of the gate electrode 370 is further above the semiconductor layer structure 250 than the center portion of the upper surface of the gate electrode 370.

[0130] Since the capped gate dielectric layer 364 covers the portion of the base gate dielectric layer 262 that extends laterally beyond the gate electrode 370, it can serve as an etch stop layer to protect the base gate dielectric layer 262 from over-etching during the etch steps used to form the gate electrode 370. Furthermore, because the high-k dielectric capped gate dielectric layer 364 is located between the base gate dielectric layer 262 and the outer wall of the gate electrode 370, the peak electric field value in the gate dielectric layer 360 can be reduced. Since the capped gate dielectric layer 364 is not inserted between the gate electrode 370 and the channel region 232 and / or the JFET region 224, it can even reduce the impact on the performance of the power MOSFET 300.

[0131] Figures 9A to 9D The diagram is for manufacturing purposes. Figure 8 A schematic cross-sectional view of the process steps of the MOSFET 300.

[0132] refer to Figure 9A This can form a semiconductor layer structure 250. For example, providing heavily doped (n... +An n-type silicon carbide substrate 210 is prepared, and a lightly doped (n-type) silicon carbide substrate is formed on the substrate 210 via epitaxial growth. - A silicon carbide drift layer 220. Although not shown, in some embodiments, an n-type silicon carbide current distribution layer including the upper portion of the drift layer 220 may be formed. A silicon carbide p-well 230 is formed in the upper portion of the drift layer 220, for example, by ion implantation. Then, a heavily doped (n-type) silicon carbide p-well 230 is formed in the upper portion of the p-well 230, for example, by ion implantation. + n-type silicon carbide source / drain region 240. A base gate dielectric layer 261 is then formed on the device using a blanket method. The base gate dielectric layer 261 may include a silicon oxide layer.

[0133] A sacrificial mask 365 is then formed on the base gate dielectric layer 261 to cover a portion of the base gate dielectric layer 261 that will not form a capping gate dielectric layer 364. The sacrificial mask 365 may include, for example, a photoresist or a hard mask material. Figure 9A As shown, the sacrificial mask 365 may cover the portion of the base gate dielectric layer 261 above the JFET region 224 and the channel region 232. A capped gate dielectric layer 363 is then blanket-formed on the base gate dielectric layer 261 and the sacrificial mask 365. As shown, in some embodiments, the capped gate dielectric layer 363 may be thinner than the base gate dielectric layer 261. In example embodiments, the thickness of the base gate dielectric layer 261 may be at least two, three, four, or five times the thickness of the capped gate dielectric layer 363.

[0134] refer to Figure 9B An etch mask (not shown) can be formed covering the portion of the capped gate dielectric layer 363 that directly contacts the base gate dielectric layer 261, while the portion of the capped gate dielectric layer 363 that directly contacts the sacrificial mask 365 is exposed. An etching process can then be performed to remove the portion of the capped gate dielectric layer 363 that directly contacts the sacrificial mask 365, as well as the sacrificial mask 365 itself. As a result, the capped gate dielectric layer 363 remains only on the portion of the base gate dielectric layer 261 above the outside of the source region 240 and the p-well 230.

[0135] refer to Figure 9C The gate electrode layer (not shown) can be blanket-formed on the top surface of the device. The gate electrode layer can then be etched using standard techniques to form the gate electrode 370. (As...) Figure 9C As shown, the gate electrode 370 may have a stepped lower surface and a stepped upper surface because the outer portion of the gate electrode 370 extends onto the cap gate dielectric layer 363.

[0136] refer to Figure 9DA dielectric isolation layer (not shown) may be formed, which may include, for example, multiple or single dielectric layers. In an example embodiment, the dielectric isolation layer may include a multilayer structure comprising silicon oxide and phosphosilicate glass. The dielectric isolation layer is then patterned to expose source region 240 to form dielectric isolation pattern 380. Finally, source metallization 290 may be formed to cover dielectric isolation pattern 380 and contact source region 240 to provide MOSFET 300, as shown. Figure 8 As shown in the image.

[0137] Note that in some embodiments of the invention, the patterning of the gate dielectric layer can be separated from the patterning of the gate electrode. As a result, the gate dielectric layer can extend laterally beyond the sidewalls of the gate electrode. This can be advantageous because the gate dielectric layer can include a high-quality dielectric material compared to the dielectric isolation pattern used to cover the gate electrode. Therefore, extending the gate dielectric layer laterally beyond the sidewalls of the gate electrode ensures that the portion of the gate dielectric layer above the source region includes a high-quality dielectric material that is not easily broken down. In some embodiments, the gate dielectric layer can extend laterally beyond the sidewalls of the gate electrode by the same distance as the dielectric isolation pattern extends laterally beyond the sidewalls of the gate electrode.

[0138] Figure 10 This is a schematic cross-sectional view of a MOSFET 400 according to another embodiment of the present invention, the MOSFET 400 having a gate electrode formed in a trench in its semiconductor layer structure. MOSFETs with gate trenches are generally referred to as U-shaped MOSFET (UMOSFET) devices.

[0139] like Figure 10 As shown, the MOSFET 400 includes a semiconductor layer structure 450, which includes a heavily doped n-type silicon carbide semiconductor substrate 410, a lightly doped n-type (n-) silicon carbide drift layer 420, a silicon carbide p-type well 430, and a heavily doped (n+) n-type silicon carbide source region 440. A trench 422 is provided in the drift layer 420. In some embodiments, the bottom surface of the trench 422 may extend into the drift layer 420 located below the bottom surface of the well 430 and / or the source region 440. The substrate 410, drift layer 420, well 430, and source region 440 may be connected to... Figure 4 The corresponding regions / layers of MOSFET 200 are essentially the same, with two exceptions. First, as described above, trench 422 is provided in the upper surface of drift layer 420. Second, a p-type shielding region 436 can be formed in drift layer 420. Shielding region 436 helps protect the corners of the final gate dielectric layer 460 from high electric fields during reverse blocking operation. Therefore, further discussion of semiconductor layer structure 450 will be omitted.

[0140] like Figure 10 As further shown, a multilayer gate dielectric layer 460 is disposed on the bottom surface and sidewalls of the trench 422 and on the source region 440. The multilayer gate dielectric layer 460 includes a base gate dielectric layer 462 and a cap gate dielectric layer 464. The base gate dielectric layer 462 may include a silicon oxide layer, and the cap gate dielectric layer 464 may include a material having a dielectric constant higher than that of silicon oxide. Except that the multilayer gate dielectric layer 460 is not a planar layer but has portions extending along the sidewalls and bottom surface of the trench 422, the multilayer gate dielectric layer 460 may be identical to any of the described multilayer gate dielectric layers according to embodiments of the present invention.

[0141] A gate electrode 470 is formed within a trench 422, and a dielectric isolation pattern 480 covers the gate electrode 470. A source metallization 490 is formed on the semiconductor layer structure, the gate dielectric layer 460, and the dielectric isolation pattern 480 to complete the device.

[0142] As in the above embodiment, the capped gate dielectric layer 464 acts as an etch stop pattern, which can protect the underlying base gate dielectric layer from damage during the etching step performed to form the gate electrode 470. This can be important because the highest electric field may occur in a portion of the upper sidewall of the gate dielectric layer 460 adjacent to the trench 422.

[0143] During on-state operation, the highest electric field value in the gate dielectric layer 460 of the MOSFET 400 may occur at the "inner" corner of the gate dielectric layer 460, which corresponds to the upper corner of the trench 422 (i.e., the highest electric field occurs in the portion of the upper corner of the contact trench 422 of the gate dielectric layer 460). It is worth noting that the capped gate dielectric layer 464 is not present in this region of the gate dielectric layer, therefore a high electric field can occur in the silicon oxide-based gate dielectric layer 462. Figure 11 This is a schematic cross-sectional view of MOSFET 400', a modified version of MOSFET 400, which includes a gate dielectric layer 460' with a second capped gate dielectric layer 466, which helps to reduce the peak electric field at the inner corner of the adjacent gate dielectric layer 460'.

[0144] like Figure 11As shown, MOSFET 400' can be identical to MOSFET 400 except for providing three gate dielectric layers, including a silicon oxide base gate dielectric layer 462 and first and second high-dielectric-constant capped gate dielectric layers 464 and 466 formed on opposite surfaces of the base gate dielectric layer 462. Because the capped gate dielectric layer 466 is formed of a high-dielectric-constant material, the electric field in this layer will be smaller than the electric field present in the silicon oxide base gate dielectric layer 462 during on-state operation. Therefore, although electric field crowding effects may still exist in the gate dielectric layer 460' around the upper corner of trench 422, the electric field directly adjacent to the trench corner will be lower due to the higher dielectric constant of the capped gate dielectric layer 466. Thus, the same as the above-referenced MOSFET can be achieved in MOSFET 400'. Figure 6B The peak electric field values ​​of the same type discussed are reduced.

[0145] Figure 11 A potential challenge with the MOSFET 400' is that if the manufacturing process includes high-temperature processing steps after the formation of the gate dielectric layer 460', silicon oxide may grow at the interface between the silicon carbide semiconductor layer structure 450 and the gate dielectric layer 460'. Since any such silicon oxide layer would be very thin, it would have a very high electric field during device operation, making it highly susceptible to breakdown. Furthermore, the interface quality between many high-dielectric-constant materials and silicon carbide can be poor. Therefore, care must be taken in selecting the materials for the capping dielectric layer 466 and the temperature levels of subsequent processing steps to ensure that adding the capping gate dielectric layer 466 does not significantly negatively impact the performance of the MOSFET 400'.

[0146] According to another embodiment of the invention, a trench semiconductor device is provided including a trench with rounded corners. The lower corner and / or upper corner of the trench may be rounded. (See reference...) Figure 12 The invention also discusses techniques for rounding corners according to other embodiments of the invention. Figure 12 This is a schematic cross-sectional view of a trench according to an embodiment of the present invention.

[0147] like Figure 12 As shown, groove 422 has an upper corner 426 and a lower corner 428. These corners can be rounded using various techniques, such as... Figure 12As shown in the diagram. For example, after forming trench 422, post-processing annealing is performed in a hydrogen environment of etch-exposed silicon carbide. Since the top and side surfaces of each upper corner 426 are exposed to hydrogen, the upper corners are etched away at a faster rate than the other plane-exposed silicon carbide surfaces. Moreover, the upper surface and sidewalls of the trench comprise different planes of silicon carbide material (i.e., different atomic arrangements), and the bulk silicon carbide material can be oriented such that the sidewalls comprise planes that are etched faster in hydrogen than the upper surface. As a result, as Figure 12 As shown, the upper corner 426 can be significantly rounded, and the lower corner 428 will also be somewhat rounded. After hydrogen annealing / etching, the silicon carbide structure can be surface cleaned, and this cleaning can further round the upper and lower corners 426 and 428 of the trench 422.

[0148] like Figure 12 As further shown, the gate dielectric layer 460 can be conformally formed on the semiconductor layer structure. Consequently, the rounding of the corners 426, 428 of the trench 422 is replicated in different layers 462, 464, 466 of the gate dielectric layer 460. This rounding reduces electric field congestion, thus helping to reduce the peak electric field value in the gate dielectric layer 460 (or 460') during the device's on-state operation. The rounding of the portion of the lower corner 428 of the gate dielectric layers 460, 460' adjacent to the trench also helps to reduce the peak electric field during reverse blocking operation.

[0149] What will be recognized is that, Figure 10 and Figure 11 The trench MOSFETs 400, 400' can have rounded corners formed using the above-described technique. It will also be appreciated that any conventional trench semiconductor device can be improved by rounding the corners of the trench in the manner described above. Therefore, according to embodiments of the invention, the rounded corners can be used in conjunction with or separately from the multilayer gate dielectric layer.

[0150] It will be recognized that trench 422 extends through a region of the semiconductor device (e.g., into) Figure 12 (as shown in the view of the page), therefore, the upper corner 426 refers to the area where the opposite sidewalls of trench 422 meet or intersect with the top surface of semiconductor layer structure 450, while the lower corner 428 refers to the area where the opposite sidewalls of trench 422 meet or intersect with the bottom surface of trench 422. Therefore, it will be understood that corners 426 and 428 can refer to two-dimensional corners, rather than three-dimensional corners existing in, for example, a cube.

[0151] While embodiments of the invention have been discussed above primarily with respect to semiconductor devices including silicon gate electrodes, it will be appreciated that the embodiments of the invention are not limited thereto. Therefore, in other embodiments, other gate electrode materials may be used, including, for example, gate electrodes formed from other semiconductor materials, silicides, and / or metals. The oxidation and / or nitriding annealing techniques disclosed herein can be used to selectively convert selected portions of these other gate electrodes into dielectric materials.

[0152] This disclosure describes a method for improving interface protection in metal-oxide-semiconductor (MOS or MIS) devices. This can be particularly useful for improving the gate region in power transistors (e.g., MOSFETs, MISFETs, or IGBTs).

[0153] While the various embodiments discussed above illustrate the structure of a unit cell of an n-channel MOSFET, it will be appreciated that, according to further embodiments of the invention, the polarity of each semiconductor layer in each device can be reversed to provide a corresponding p-channel MOSFET.

[0154] The invention has been described above with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. It will be understood that when an element or layer is referred to as “on another element or layer,” “connected to another element or layer,” or “coupled to another element or layer,” it may be directly on another element or layer, directly connected to or coupled to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as “directly on another element or layer,” “directly connected to another element or layer,” or “directly coupled to another element or layer,” there are no intermediate elements or layers. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. The same reference numerals always refer to the same element.

[0155] It will be understood that while the terms "first" and "second" are used herein to describe various regions, layers, and / or elements, these regions, layers, and / or elements should not be limited by these terms. These terms are used only to distinguish one region, layer, or element from another. Therefore, the first region, layer, or element discussed below may be referred to as the second region, layer, or element, and similarly, the second region, layer, or element may be referred to as the first region, layer, or element without departing from the scope of the invention.

[0156] Relative terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship between one element and another element as shown in the figures. It will be understood that relative terms are intended to cover different orientations of the device other than those depicted in the figures. For example, if the device in the figures is flipped, then the element described as being “below” the other element will be oriented “above” the other element. Thus, the exemplary term “lower” can cover both “lower” and “upper” orientations, depending on the specific orientation of the figure. Similarly, if one of the devices in the figures is flipped, then the element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the exemplary term “below” or “under” can cover both above and below orientations.

[0157] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that, when used herein, the terms “comprising,” “including,” “containing,” and / or “comprising” specify the presence of the stated feature, element, and / or component, but do not exclude the presence or addition of one or more other features, elements, components, and / or groups thereof.

[0158] Embodiments of the invention are described herein with reference to cross-sectional views, which are schematic diagrams. Accordingly, variations in the illustrated shapes can be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be construed as limited to the specific shapes of the regions shown herein, but should include, for example, shape deviations caused by manufacturing processes. For instance, an injection region illustrated as rectangular will typically have rounded or curved features at its edges and / or an injection concentration gradient, rather than a binary change from an injection region to a non-injection region. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0159] It will be understood that the embodiments disclosed herein can be combined. Therefore, features depicted and / or described with respect to the first embodiment can also be included in the second embodiment, and vice versa.

[0160] While the embodiments described above have been referenced to specific accompanying drawings, it should be understood that some embodiments of the invention may include additional and / or intermediate layers, structures, or elements, and / or certain layers, structures, or elements may be removed. Although several exemplary embodiments of the invention have been described, those skilled in the art will readily recognize that many modifications may be made to the exemplary embodiments without materially departing from the novel teachings and advantages of the invention. Therefore, all such modifications are intended to be included within the scope of the invention as defined in the claims. Accordingly, it should be understood that the foregoing is illustrative of the invention and should not be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The invention is defined by the appended claims, which include equivalents of the claims.

Claims

1. A semiconductor device, comprising: The semiconductor layer structure includes silicon carbide and a drift layer having a first conductivity type; A gate dielectric layer on the semiconductor layer structure, the gate dielectric layer comprising a base gate dielectric layer on the semiconductor layer structure and a cap gate dielectric layer on the base gate dielectric layer opposite to the semiconductor layer structure; as well as A gate electrode is located on the gate dielectric layer opposite to the semiconductor layer structure. The base gate dielectric layer extends continuously below the gate electrode from a first side of the gate electrode to an opposite second side along the width direction of the gate electrode, wherein the width direction is perpendicular to the longitudinal direction of the gate electrode. Wherein, the dielectric constant of the cap gate dielectric layer is higher than the dielectric constant of the base gate dielectric layer, and In a direction intersecting the base gate dielectric layer and the cap gate dielectric layer and perpendicular to the semiconductor layer structure, the cap gate dielectric layer is thinner than the base gate dielectric layer. Wherein, the ratio of the thickness of the base gate dielectric layer divided by the dielectric constant of the material of the base gate dielectric layer to the thickness of the cap gate dielectric layer divided by the dielectric constant of the material of the cap gate dielectric layer is at least ten.

2. The semiconductor device according to claim 1, wherein, The base gate dielectric layer includes a silicon oxide layer.

3. The semiconductor device according to claim 2, wherein, The thickness of the base gate dielectric layer is at least five times that of the cap gate dielectric layer, and the dielectric constant of the cap gate dielectric layer is at least three times that of the base gate dielectric layer.

4. The semiconductor device according to claim 3, wherein, The gate electrode comprises silicon.

5. The semiconductor device according to claim 1, wherein, The semiconductor layer structure further includes a first well region and a second well region separated by a JFET region, wherein the cap gate dielectric layer is not above the upper surface of the JFET region in a direction perpendicular to the semiconductor layer structure.

6. The semiconductor device according to claim 5, wherein, The gate electrode has a stepped lower surface.

7. The semiconductor device according to claim 1, wherein, The opposite upper edge of the gate electrode is further above the semiconductor layer structure than the central portion of the upper surface of the gate electrode.

8. The semiconductor device according to claim 1, wherein, The cap gate dielectric layer exists only on a portion of the base gate dielectric layer.

9. The semiconductor device according to claim 1, wherein, The semiconductor layer structure includes a well of a second conductivity type located in the upper part of the drift layer and a source region of a first conductivity type located in the upper part of the well. The channel region is located in the well between the source region and the JFET region.

10. The semiconductor device according to claim 9, wherein, The capped gate dielectric layer is formed above the source region and is not formed above a portion of the drift layer that directly contacts the base gate dielectric layer in a direction perpendicular to the semiconductor layer structure.

11. The semiconductor device according to claim 1, wherein, The semiconductor device is configured such that during on-state operation, the peak electric field value in the gate dielectric layer will be substantially located at the upper surface of the base gate dielectric layer below the side edge of the gate electrode.

12. The semiconductor device according to claim 1, wherein, The semiconductor device is configured such that during on-state operation, the peak electric field value in the base gate dielectric layer is at least 50% greater than the peak electric field value in the cap gate dielectric layer.

13. The semiconductor device according to claim 1, wherein, The semiconductor device is a metal-insulator-semiconductor field-effect transistor ("MISFET") or an insulated-gate bipolar transistor ("IGBT").

14. The semiconductor device according to claim 1, wherein, The thickness of the gate dielectric layer is at least 25 nanometers.

15. The semiconductor device according to claim 1, wherein, The capped gate dielectric layer includes an etch stop layer relative to the gate electrode.

16. The semiconductor device according to claim 14, wherein, The thickness of the capped gate dielectric layer is between two nanometers and fifteen nanometers.

17. The semiconductor device according to claim 1, wherein, The semiconductor layer structure includes trenches in its upper surface, wherein the gate dielectric layer and the gate electrode are each at least partially located within the trenches.

18. The semiconductor device according to claim 17, wherein, At least some of the corners of the trench are rounded corners.

19. A semiconductor device, comprising: Including semiconductor layer structures of silicon carbide; A gate dielectric layer on the semiconductor layer structure; as well as The gate electrode on the gate dielectric layer, opposite to the semiconductor layer structure, The gate dielectric layer includes a base gate dielectric layer on the semiconductor layer structure and a cap gate dielectric layer on the base gate dielectric layer opposite to the semiconductor layer structure. Wherein, in a direction intersecting the base gate dielectric layer and the cap gate dielectric layer and perpendicular to the semiconductor layer structure, the cap gate dielectric layer is thinner than the base gate dielectric layer, and The semiconductor device is configured such that during on-state operation, the peak electric field in the gate dielectric layer is below the top surface of the gate dielectric layer. The semiconductor layer structure includes a drift layer having a first conductivity type, a first well and a second well each having a second conductivity type in the spaced-apart upper portion of the drift layer, a first source region and a second source region having a first conductivity type in the upper portion of the respective first well and second well, and a JFET region having a first conductivity type between the first well and the second well. Wherein, the opposite edge portions of the upper surface of the gate electrode are further above the semiconductor layer structure than the center portion of the upper surface of the gate electrode.

20. The semiconductor device of claim 19, wherein, The semiconductor device is configured such that during on-state operation, the peak electric field in the gate dielectric layer is in the base gate dielectric layer.

21. The semiconductor device according to claim 20, wherein, The semiconductor device is configured such that during on-state operation, the peak electric field value in the gate dielectric layer is substantially located at the upper surface of the base gate dielectric layer below the side edge of the gate electrode.

22. The semiconductor device according to claim 19, wherein, The semiconductor device is configured such that during on-state operation, the peak electric field in the gate dielectric layer is at least 2 nm below the top surface of the gate dielectric layer.

23. The semiconductor device according to claim 19, wherein, The base gate dielectric layer includes a silicon oxide layer and the gate electrode includes silicon.

24. The semiconductor device of claim 19, wherein, The thickness of the base gate dielectric layer is at least five times that of the cap gate dielectric layer, and the dielectric constant of the cap gate dielectric layer is at least three times that of the base gate dielectric layer.

25. The semiconductor device according to claim 24, wherein, The semiconductor layer structure further includes a first channel region and a second channel region disposed in a corresponding first well and a second well between the corresponding first source region and the second source region and the JFET region.

26. The semiconductor device of claim 25, wherein, The capped gate dielectric layer is not on the upper surface of the JFET region.

27. The semiconductor device according to claim 19, wherein, The gate electrode has a stepped lower surface.

28. The semiconductor device according to claim 19, wherein, The opposite upper edge of the gate electrode is further above the semiconductor layer structure than the central portion of the upper surface of the gate electrode.

29. The semiconductor device according to claim 19, wherein, The cap gate dielectric layer is formed only on a portion of the base gate dielectric layer.

30. The semiconductor device according to claim 19, wherein, The semiconductor device is configured such that during on-state operation, the peak electric field value in the gate dielectric layer will be substantially located at the upper surface of the base gate dielectric layer below the side edge of the gate electrode.

31. The semiconductor device according to claim 19, wherein, The semiconductor device is configured such that during on-state operation, the peak electric field value in the base gate dielectric layer is at least 50% greater than the peak electric field value in the cap gate dielectric layer.

32. The semiconductor device according to claim 19, wherein, The ratio of the thickness of the base gate dielectric layer divided by the dielectric constant of the material of the base gate dielectric layer to the thickness of the cap gate dielectric layer divided by the dielectric constant of the material of the cap gate dielectric layer is at least ten.

33. The semiconductor device according to claim 19, wherein, The ratio of the thickness of the base gate dielectric layer divided by the dielectric constant of the material of the base gate dielectric layer to the thickness of the cap gate dielectric layer divided by the dielectric constant of the material of the cap gate dielectric layer is at least fifteen.

34. The semiconductor device according to claim 19, wherein, The semiconductor layer structure includes trenches in its upper surface, wherein the gate dielectric layer and the gate electrode are each at least partially located within the trenches.

35. The semiconductor device according to claim 34, wherein, The upper corner of the trench is a rounded corner, and the gate dielectric layer is conformally disposed on the semiconductor layer structure and within the trench.

36. The semiconductor device according to claim 34 or 35, wherein, The lower corner of the trench is a rounded corner, and the gate dielectric layer is conformally disposed within the trench.

37. A semiconductor device, comprising: Semiconductor layer structure, including: A silicon carbide drift layer having a first conductivity type; Each of the upper portions of the drift layer has a first silicon carbide well and a second silicon carbide well of a second conductivity type. A first silicon carbide source region and a second silicon carbide source region having a first conductivity type in the upper part of the corresponding first well and second well; and A JFET region with a first conductivity type between the first well and the second well; A gate dielectric layer on the semiconductor layer structure, the gate dielectric layer comprising a silicon oxide base gate dielectric layer on the semiconductor layer structure and a capped gate dielectric layer on the base gate dielectric layer opposite to the semiconductor layer structure; and The silicon gate electrode on the gate dielectric layer, opposite to the semiconductor layer structure, The semiconductor device is configured such that, during on-state operation, the peak electric field value in the base gate dielectric layer is at least 50% greater than the peak electric field value in the cap gate dielectric layer. Wherein, the opposite edge portions of the upper surface of the gate electrode are further above the semiconductor layer structure than the center portion of the upper surface of the gate electrode.

38. The semiconductor device according to claim 37, wherein, The thickness of the base gate dielectric layer is at least five times that of the cap gate dielectric layer, and the dielectric constant of the cap gate dielectric layer is at least three times that of the base gate dielectric layer.

39. The semiconductor device according to claim 37 or 38, wherein, The semiconductor device is configured such that during on-state operation, the peak electric field in the gate dielectric layer is in the base gate dielectric layer.

40. The semiconductor device according to claim 37 or 38, wherein, The semiconductor device is configured such that during on-state operation, the peak electric field value in the gate dielectric layer is substantially located at the upper surface of the base gate dielectric layer below the side edge of the gate electrode.

41. The semiconductor device according to claim 37, wherein, The capped gate dielectric layer is not above the upper surface of the JFET region.

42. The semiconductor device of claim 37, wherein, The gate electrode has a stepped lower surface.

43. The semiconductor device according to claim 37, wherein, The cap gate dielectric layer is formed only on a portion of the base gate dielectric layer.

44. The semiconductor device of claim 37, wherein, The semiconductor layer structure includes trenches in its upper surface, wherein the gate dielectric layer and the silicon gate electrode are each at least partially located within the trenches.

45. The semiconductor device according to claim 37, wherein, The ratio of the thickness of the base gate dielectric layer divided by the dielectric constant of the material of the base gate dielectric layer to the thickness of the cap gate dielectric layer divided by the dielectric constant of the material of the cap gate dielectric layer is at least ten.

46. ​​A method of forming a semiconductor device, the method comprising: A semiconductor layer structure is formed, the semiconductor layer structure including a silicon carbide drift layer having a first conductivity type, a first silicon carbide well and a second silicon carbide well each having a second conductivity type in the respective upper part of the drift layer, a first silicon carbide source region and a second silicon carbide source region having a first conductivity type in the upper part of the respective first well and second well, and a JFET region having a first conductivity type between the first well and the second well. A base gate dielectric layer is formed on the semiconductor layer structure; A capped gate dielectric layer is formed on the base gate dielectric layer, the capped gate dielectric layer having a dielectric constant greater than that of the base gate dielectric layer; and A gate electrode comprising silicon is formed on the cap gate dielectric layer opposite to the semiconductor layer structure; as well as Remove portions of the base gate dielectric layer and the cap gate dielectric layer to form a base gate dielectric layer and a cap gate dielectric layer that together form at least a portion of the gate dielectric layer. Wherein, forming the cap gate dielectric layer on the base gate dielectric layer includes: A mask is formed on the semiconductor layer structure after the base gate dielectric layer is formed; The cap gate dielectric layer is formed on both the mask and the base gate dielectric layer; and Remove a portion of the cap gate dielectric layer and the mask to expose a portion of the base gate dielectric layer.

47. The method according to claim 46, wherein, The semiconductor device is configured such that during on-state operation, the peak electric field value in the base gate dielectric layer is at least 50% greater than the peak electric field value in the cap gate dielectric layer.

48. The method according to claim 46, wherein, The exposed portion of the base gate dielectric layer includes a portion of the base gate dielectric layer above the JFET region.

49. The method according to claim 46, wherein, The cap gate dielectric layer is thinner than the base gate dielectric layer.

50. The method of claim 46, wherein, The thickness of the base gate dielectric layer is at least five times that of the cap gate dielectric layer, and the dielectric constant of the cap gate dielectric layer is at least three times that of the base gate dielectric layer.

51. The method according to claim 46, wherein, Forming a gate electrode comprising silicon on the capped gate dielectric layer in contrast to the semiconductor layer structure involves blanket deposition of a gate electrode layer on the base gate dielectric layer and the capped gate dielectric layer, and then etching the gate electrode layer using the capped gate dielectric layer as an etch stop layer to form the gate electrode.

52. The method according to claim 46, wherein, The gate electrode has a stepped lower surface.

53. A semiconductor device, comprising: A semiconductor layer structure including silicon carbide, the semiconductor layer structure including trenches formed therein, wherein at least some corners of the trenches are rounded; On the semiconductor layer structure and within the trench, a gate dielectric layer includes a lower corner and an upper corner, wherein at least one of the lower corner and the upper corner includes a rounded corner; as well as The gate electrode on the gate dielectric layer, opposite to the semiconductor layer structure, The gate dielectric layer includes a silicon oxide base gate dielectric layer and a first cap gate dielectric layer and a second cap gate dielectric layer on the corresponding lower and upper surfaces of the base gate dielectric layer.

54. The semiconductor device according to claim 53, wherein, The semiconductor layer structure includes a drift layer having a first conductivity type, a well having a second conductivity type located above the drift layer, and a source region having a first conductivity type located above the well.

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