Performance optimization apparatus of memory system and operating method thereof

Abstract

Embodiments of the present disclosure relate to a performance optimization apparatus of a memory system and an operating method thereof. According to an embodiment of the present disclosure, there is provided a method for operating a performance optimization apparatus of a memory system, the method including determining N candidate performance parameter values for a performance parameter of the memory system, where N is a natural number, calculating N objective function results with respect to an objective function defined for the memory system, and determining an additional candidate performance parameter value for the performance parameter of the memory system based on the N candidate performance parameter values and the N objective function results.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0154794, filed on November 11, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] The various embodiments of this disclosure generally relate to a performance optimization apparatus for a memory system and a method of operating the same. Background Technology

[0004] Memory systems include data storage devices that store data based on requests from a host such as a computer, server, smartphone, tablet PC, or other electronic device. Examples of memory systems range from traditional disk-based hard disk drives (HDDs) to semiconductor-based data storage devices such as solid-state drives (SSDs), universal flash storage devices (UFS), or embedded MMC (eMMC) devices.

[0005] The memory system may further include a memory controller for controlling the memory devices. The memory controller can receive commands from a host and can execute those commands on the memory devices in the memory system based on the received commands, or control read / write / erase operations. The memory controller can be used to run firmware operations that perform logical operations controlling these operations.

[0006] The operational performance of a memory system can be determined by its performance parameters. Typically, engineers developing memory systems can manually determine the optimal values ​​for these parameters by directly analyzing the logical relationship between them and the system's operational performance. However, when engineers directly determine the optimal values, optimization can be time-consuming, and the degree of optimization may vary depending on the engineer. Summary of the Invention

[0007] Various embodiments of this disclosure relate to a performance optimization apparatus and operating method for a memory system capable of rapidly determining the optimal values ​​of performance parameters of the memory system.

[0008] Furthermore, various embodiments of this disclosure relate to a memory system performance optimization apparatus and its operating method that can minimize the degree of variation in the optimal values ​​of the performance parameters of the memory system.

[0009] On one hand, embodiments of this disclosure may provide a method for operating a performance optimization apparatus for a memory system, the method comprising: i) determining N candidate performance parameter values ​​for performance parameters of the memory system, where N is a natural number; ii) calculating N objective function results for an objective function defined for the memory system; and iii) determining additional candidate performance parameter values ​​for the performance parameters of the memory system based on the N candidate performance parameter values ​​and the N objective function results.

[0010] In this case, each of the N objective function results can be a result of an objective function measured when the corresponding candidate performance parameter value is applied to the memory system. The objective function can be a function of: i) the average of multiple latency times required for the memory system to process multiple commands received from external devices, and ii) the maximum value of the multiple latency times.

[0011] On the other hand, embodiments of this disclosure may provide a performance optimization apparatus for a memory system, the performance optimization apparatus comprising: i) a storage memory for storing N candidate performance parameter values ​​for the performance parameters of the memory system, wherein N is a natural number; and ii) a computation processor for calculating N objective function results for an objective function defined for the memory system, and determining additional candidate performance parameter values ​​for the performance parameters of the memory system based on the N candidate performance parameter values ​​and the N objective function results.

[0012] In this case, each of the N objective function results can be a result of an objective function measured when the corresponding candidate performance parameter value is applied to the memory system. The objective function can be a function of: i) the average of multiple latency times required for the memory system to process multiple commands received from external devices, and ii) the maximum value of the multiple latency times.

[0013] On the other hand, embodiments of this disclosure may provide a memory controller comprising: i) a working memory for storing N candidate performance parameter values ​​for performance parameters of a memory system including the memory controller, where N is a natural number; and ii) a processor for calculating N objective function results for an objective function defined for the memory system, and determining additional candidate performance parameter values ​​for the performance parameters of the memory system based on the N candidate performance parameter values ​​and the N objective function results.

[0014] In this case, each of the N objective function results can be a result of an objective function measured when the corresponding candidate performance parameter value is applied to the memory system. The objective function can be a function of: i) the average of multiple latency times required for the memory system to process multiple commands received from external devices, and ii) the maximum value of the multiple latency times.

[0015] According to embodiments of this disclosure, the optimal values ​​of performance parameters of a memory system can be determined quickly. Attached Figure Description

[0016] Figure 1 This is a schematic diagram illustrating the configuration of a memory system based on an embodiment of the present disclosure.

[0017] Figure 2 This is a block diagram schematically illustrating a memory device based on an embodiment of the present disclosure.

[0018] Figure 3 This is a diagram illustrating the structure of word lines and bit lines of a memory device based on an embodiment of the present disclosure.

[0019] Figure 4 This is a schematic diagram illustrating the structure of a performance optimization apparatus for a memory system based on an embodiment of the present disclosure.

[0020] Figure 5 This is a diagram illustrating candidate performance parameter values ​​and objective function results based on embodiments of the present disclosure.

[0021] Figure 6 This is a diagram illustrating the form of an objective function based on an embodiment of the present disclosure.

[0022] Figures 7 to 9 This is a diagram illustrating the values ​​of additional candidate performance parameters determined by a performance optimization apparatus for a memory system based on an embodiment of the present disclosure.

[0023] Figures 10 to 11 This is a diagram illustrating a performance optimization apparatus for a memory system based on an embodiment of the present disclosure, which determines the optimal values ​​of the performance parameters of the memory system.

[0024] Figure 12 This is a diagram illustrating a method for optimizing the operation of a memory system based on an embodiment of the present disclosure.

[0025] Figure 13 This is a diagram illustrating the configuration of a computing system based on an embodiment of the present disclosure. Detailed Implementation

[0026] In the following, embodiments of the present disclosure are described in detail with reference to the accompanying drawings. Throughout the specification, references to "embodiment," "another embodiment," etc., are not necessarily limited to only one embodiment, and different references to any such phrases are not necessarily limited to the same embodiment. When used herein, the term "embodiment" does not necessarily refer to all embodiments.

[0027] Various embodiments of the present disclosure are described in more detail below with reference to the accompanying drawings. However, we note that the invention can be embodied in different forms and variations and should not be construed as limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in the various figures and embodiments.

[0028] The methods, processes, and / or operations described herein can be executed by code or instructions that will be run by a computer, processor, controller, or other signal processing device. This computer, processor, controller, or other signal processing device can be the computer, processor, controller, or other signal processing device described herein, or an element other than those described herein. Because the algorithms underlying the methods or operations of the computer, processor, controller, or other signal processing device are described in detail, the code or instructions for implementing the operations of the method embodiments can convert the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods herein.

[0029] When implemented at least in part as software, controllers, processors, devices, modules, units, multiplexers, generators, logic devices, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing, for example, code or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device.

[0030] Figure 1 This is a diagram illustrating a schematic configuration of a memory system 100 based on an embodiment of the present disclosure.

[0031] In some embodiments, memory system 100 may include memory device 110 configured to store data and memory controller 120 configured to control memory device 110.

[0032] Memory device 110 may include multiple memory blocks, each memory block including multiple memory cells for storing data. Memory device 110 may be configured to operate in response to control signals received from memory controller 120. For example, operation of memory device 110 may include read operations, programming operations (also referred to as "write operations"), erase operations, etc.

[0033] The memory cells in memory device 110 are used to store data and can be arranged as an array of memory cells. The array of memory cells can be divided into blocks of memory cells, and each block includes different pages of memory cells. In a typical implementation of a NAND flash memory device, a page of a memory cell is the smallest unit of memory that can be programmed or written, and the data stored in the memory cell can be erased at the block level.

[0034] In some implementations, the memory device 110 can be implemented as various types, such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Generation 4 Low Power Double Data Rate (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND Flash Memory, Vertical NAND Flash Memory, NOR Flash Memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin-Transfer Torque Random Access Memory (STT-RAM).

[0035] The memory device 110 can be implemented in a three-dimensional array structure. Embodiments of this disclosure are applicable to any type of flash memory device having a charge storage layer. In one embodiment, the charge storage layer can be formed of a conductive material, and such a charge storage layer can be referred to as a floating gate. In another embodiment, the charge storage layer can be formed of an insulating material, and such a flash memory device can be referred to as charge fetch flash (CTF).

[0036] The memory device 110 can be configured to receive commands and addresses from the memory controller 120 for accessing a region of the memory cell array selected using that address. In other words, the memory device 110 can perform operations corresponding to the received commands on a memory region of the memory device having a physical address corresponding to the address received from the memory controller 120.

[0037] In some implementations, the memory device 110 can perform programming operations, reading operations, erasing operations, etc. During a programming operation, the memory device 110 can write data to an address-selected region. During a reading operation, the memory device 110 can read data from an address-selected memory region. During an erasing operation, the memory device 110 can erase data stored in an address-selected memory region.

[0038] The memory controller 120 can control write (programming) operations, read operations, erase operations, and background operations performed on the memory device 110. Background operations may include, for example, operations implemented to optimize the overall performance of the memory device 110, such as garbage collection (GC) operations, wear leveling (WL) operations, and bad block management (BBM) operations.

[0039] The memory controller 120 can control the operation of the memory device 110 upon request from the host. Optionally, when the memory controller 120 performs these background operations of the memory device, the memory controller 120 can control the operation of the memory device 110 even without a request from the host.

[0040] The memory controller 120 and the host may be separate devices. In some embodiments, the memory controller 120 and the host may be integrated and implemented as a single device. In the following description, by way of example, the memory controller 120 and the host will be discussed as separate devices.

[0041] Reference Figure 1 The memory controller 120 may include a memory interface 122, a control circuit 123, and a host interface (I / F) 121.

[0042] Host interface 121 can be configured to provide an interface for communicating with a host.

[0043] When a command is received from the host, the control circuit 123 can receive the command through the host interface 121 and can perform operations to process the received command.

[0044] The memory interface 122 can be directly or indirectly connected to the memory device 110 to provide an interface for communicating with the memory device 110. That is, the memory interface 122 can be configured to provide an interface to the memory device 110 and the memory controller 120 so that the memory controller 120 can perform memory operations on the memory device 110 based on control signals and instructions from the control circuit 123.

[0045] The control circuit 123 can be configured to control the operation of the memory device 110 via the memory controller 120. For example, the control circuit 123 may include a processor 124 and a working memory 125. The control circuit 123 may further include an error detection / correction circuit (ECC circuit) 126, etc.

[0046] Processor 124 can control the overall operation of memory controller 120. Processor 124 can perform logical operations. Processor 124 can communicate with host via host interface 121. Processor 124 can communicate with memory device 110 via memory interface 122.

[0047] Processor 124 can be used to perform operations associated with the Flash Translation Layer (FTL) to efficiently manage memory operations performed on memory system 100. Processor 124 can translate logical block addresses (LBAs) provided by the host into physical block addresses (PBAs) via the FTL. The FTL can receive an LBA and translate it into a PBA using a mapping table.

[0048] Based on the mapping unit, there are various address mapping methods that FTL can use. Typical address mapping methods can include page mapping, block mapping, and hybrid mapping.

[0049] Processor 124 can be configured to randomize data received from the host and write the randomized data to the memory cell array. For example, processor 124 can randomize data received from the host by using a randomizing seed. The randomized data is provided to memory device 110 and written to the memory cell array.

[0050] Processor 124 can be configured to derandomize data received from memory device 110 during a read operation. For example, processor 124 can derandomize data received from memory device 110 by using a derandomization seed. The derandomized data can then be output to the host.

[0051] Processor 124 can run firmware (FW) to control the operation of memory controller 120. Processor 124 can control the overall operation of memory controller 120, and in order to perform logical operations, processor 124 can run (drive) the firmware loaded into working memory 125 during startup.

[0052] Firmware refers to a program or software stored on some kind of non-volatile memory and running inside the memory system 100.

[0053] In some implementations, the firmware may include various functional layers. For example, the firmware may include at least one of the following: a flash translation layer (FTL) configured to translate a logical address in a host request into a physical address of the memory device 110; a host interface layer (HIL) configured to interpret commands issued by the host to a data storage device such as the memory system 100 and pass the commands to the FTL; and a flash interface layer (FIL) configured to pass commands issued by the FTL to the memory device 110.

[0054] For example, firmware can be stored in memory device 110 and then loaded into working memory 125.

[0055] The working memory 125 may store firmware, program code, commands, or multiple data required to operate the memory controller 120. For example, the working memory 125 may include at least one of static RAM (SRAM), dynamic RAM (DRAM), and synchronous RAM (SDRAM) as volatile memory.

[0056] Error detection / correction circuit 126 can be configured to detect and correct one or more error bits in data using error detection and correction codes. In some embodiments, the data undergoing error detection and correction may include data stored in working memory 125 and data retrieved from memory device 110.

[0057] Error detection / correction circuit 126 can be implemented to decode data using error correction codes. Error detection / correction circuit 126 can be implemented using various decoding schemes. For example, a decoder performing non-system code decoding or a decoder performing system code decoding can be used.

[0058] In some implementations, the error detection / correction circuit 126 can detect one or more error bits based on sectors. That is, each data entry in the read data can include multiple sectors. In this disclosure, a sector can refer to a data unit smaller than a read unit of flash memory (e.g., a page). The sectors constituting each data entry in the read data can be mapped based on addresses.

[0059] In some implementations, the error detection / correction circuit 126 can calculate the bit error rate (BER) sector by sector and determine whether the number of erroneous bits in the data is within the error correction capability. For example, if the BER is higher than a reference value, the error detection / correction circuit 126 can determine that the erroneous bits in the corresponding sector are uncorrectable and the corresponding sector is marked as "failed". If the BER is lower than or equal to the reference value, the error detection / correction circuit 126 can determine that the corresponding sector is correctable or the corresponding sector can be marked as "passed".

[0060] Error detection / correction circuit 126 can continuously perform error detection and correction operations on all read data. When a sector in the read data is correctable, error detection / correction circuit 126 can move to the next sector to check if error correction is needed for that sector. In completing error detection and correction operations on all read data in this way, error detection / correction circuit 126 can obtain information about which sector in the read data is considered uncorrectable. Error detection / correction circuit 126 can provide this information (e.g., the address of the uncorrectable bit) to processor 124.

[0061] The memory system 100 may also include a bus 127 for providing a channel between the constituent elements 121, 122, 124, 125, and 126 of the memory controller 120. For example, bus 127 may include a control bus for transmitting various types of control signals and commands and a data bus for transmitting various types of data.

[0062] For example, Figure 1 The aforementioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 are shown. Note that some of the constituent elements shown may be omitted, or some of the aforementioned constituent elements 121, 122, 124, 125, and 126 of the memory controller 120 may be integrated into a single element. Additionally, in some embodiments, one or more other constituent elements may be added to the aforementioned constituent elements of the memory controller 120.

[0063] Figure 2 This is a block diagram schematically illustrating a memory device 110 based on an embodiment of the present disclosure.

[0064] In some implementations, the memory device 110 based on embodiments of the present disclosure may include a memory cell array 210, an address decoder 220, a read / write circuit 230, control logic 240, and a voltage generation circuit 250.

[0065] The memory cell array 210 may include multiple memory blocks BLK1-BLKz, where z is a natural number equal to or greater than 2.

[0066] In multiple memory blocks BLK1-BLKz, multiple word lines WL and multiple bit lines BL can be set by row and column, and multiple memory cells MC can be arranged.

[0067] Multiple memory blocks BLK1-BLKz can be connected to the address decoder 220 via multiple word lines WL. Multiple memory blocks BLK1-BLKz can be connected to the read / write circuitry 230 via multiple bit lines BL.

[0068] Each of the multiple memory blocks BLK1-BLKz may include multiple memory cells. For example, the multiple memory cells are non-volatile memory cells. In some embodiments, these non-volatile memory cells may be arranged in a vertical channel configuration.

[0069] The memory cell array 210 can be configured as a memory cell array with a two-dimensional structure. In some embodiments, the memory cell array 210 can be arranged in a three-dimensional structure.

[0070] Each of the plurality of memory cells included in the memory cell array 210 can store at least one bit of data. For example, each of the plurality of memory cells included in the memory cell array 210 can be a single-level cell (SLC) configured to store one bit of data. Another example is that each of the plurality of memory cells included in the memory cell array 210 can be a multi-level cell (MLC) configured to store two bits of data per memory cell. Yet another example is that each of the plurality of memory cells included in the memory cell array 210 can be a three-level cell (TLC) configured to store three bits of data per memory cell. Yet another example is that each of the plurality of memory cells included in the memory cell array 210 can be a four-level cell (QLC) configured to store four bits of data per memory cell. Furthermore, the memory cell array 210 can include a plurality of memory cells, each of which can be configured to store at least five bits of data per memory cell.

[0071] Reference Figure 2 The address decoder 220, read / write circuit 230, control logic 240, and voltage generation circuit 250 can operate as peripheral circuitry configured to drive the memory cell array 210.

[0072] Address decoder 220 can be connected to memory cell array 210 via multiple word lines WL.

[0073] Address decoder 220 can be configured to operate in response to commands and control signals from control logic 240.

[0074] Address decoder 220 can receive addresses through input / output buffers within memory device 110. Address decoder 220 can be configured to decode block addresses among the received addresses. Address decoder 220 can select at least one memory block based on the decoded block address.

[0075] Address decoder 220 can receive read voltage Vread and pass voltage Vpass from voltage generation circuit 250.

[0076] During a read operation, the address decoder 220 can apply a read voltage Vread to the selected word line WL within the selected memory block and a pass voltage Vpass to the remaining unselected word lines WL.

[0077] During the programming verification operation, the address decoder 220 can apply the verification voltage generated by the voltage generation circuit 250 to the selected word line WL inside the selected memory block, and can apply the pass voltage Vpass to the remaining unselected word lines WL.

[0078] Address decoder 220 can be configured to decode column addresses from received addresses. Address decoder 220 can then transmit the decoded column addresses to read / write circuitry 230.

[0079] The memory device 110 can perform read and program operations page by page. The address received when requesting a read or program operation may include at least one of a block address, a row address, and a column address.

[0080] Address decoder 220 can select a memory block and a word line based on the block address and row address. Column address can be decoded by address decoder 220 and provided to read / write circuitry 230.

[0081] Address decoder 220 may include at least one of block decoder, row decoder, column decoder and address buffer.

[0082] The read / write circuit 230 may include multiple page buffers PB. The read / write circuit 230 can operate as a "read circuit" when the memory cell array 210 performs a read operation, and can operate as a "write circuit" when the memory cell array 210 performs a write operation.

[0083] The aforementioned read / write circuit 230 is also referred to as a page buffer circuit including multiple page buffers PB, or as a data register circuit. The read / write circuit 230 may include data buffers involved in data processing functions, and in some embodiments, the read / write circuit 230 may further include cache buffers for data caching.

[0084] Multiple page buffers PB can be connected to the memory cell array 210 via multiple bit lines BL. In order to detect or sense the threshold voltage Vth of the memory cell during read operations and program verification operations, the multiple page buffers PB can continuously supply sensing current to the bit lines BL connected to the memory cell to detect changes in current proportional to the amount of current that changes according to the programming state of the corresponding memory cell at the sensing node, and the corresponding voltage can be stored or latched as sensing data.

[0085] The read / write circuit 230 can operate in response to a page buffer control signal output from the control logic 240.

[0086] During a read operation, the read / write circuit 230 senses the voltage value of the memory cell and reads the voltage value as data. The read / write circuit 230 temporarily stores the acquired data and outputs the data DATA to the input / output buffer of the memory device 110. In an embodiment, in addition to the page buffer PB or page register, the read / write circuit 230 may also include column select circuitry.

[0087] Control logic 240 can be connected to address decoder 220, read / write circuit 230, and voltage generation circuit 250. Control logic 240 can receive commands CMD and control signals CTRL through the input / output buffer of memory device 110.

[0088] Control logic 240 can be configured to control the overall operation of memory device 110 in response to control signal CTRL. Control logic 240 can output control signals to adjust the voltage levels of the sensing nodes of multiple page buffers PB to precharge voltage levels.

[0089] Control logic 240 can control read / write circuit 230 to perform read operations in memory cell array 210. Voltage generation circuit 250 can generate read voltage Vread and pass voltage Vpass used during read operations in response to voltage generation circuit control signals output from control logic 240.

[0090] The memory block BLK included in the memory device 110 may include multiple pages PG. In some embodiments, multiple memory cells arranged in columns form a memory cell string, while multiple memory cells arranged in rows form a memory block. Each of the multiple pages PG is connected to one of the word lines WL, and each of the memory cell string STR is connected to one of the bit lines BL.

[0091] Within a storage block BLK, multiple word lines (WL) and multiple bit lines (BL) can be arranged in rows and columns. For example, each of the multiple word lines (WL) can be arranged along the row direction, while each of the multiple bit lines (BL) can be arranged along the column direction. Alternatively, each of the multiple word lines (WL) can be arranged along the column direction, while each of the multiple bit lines (BL) can be arranged along the row direction.

[0092] In some implementations, multiple word lines (WL) and multiple bit lines (BL) may intersect each other to address individual memory cells in an array of multiple memory cells (MC). In some implementations, each memory cell (MC) may include a transistor (TR) comprising a layer of material capable of retaining charge.

[0093] For example, a transistor TR arranged in each memory cell MC may include a drain, a source, and a gate. The drain (or source) of transistor TR may be connected directly or via another transistor TR to the corresponding bit line BL. The source (or drain) of transistor TR may be connected directly or via another transistor TR to a source line (which may be ground). The gate of transistor TR may include a control gate (CG) and a floating gate (FG) surrounded by an insulator, with a gate voltage applied from word line WL to the control gate (CG).

[0094] In each of the multiple memory blocks BLK1-BLKz, a first select line (also referred to as a source select line or drain select line) may be additionally arranged on the outside of the first outermost word line of the read / write circuit 230, and a second select line (also referred to as a drain select line or source select line) may be additionally arranged on the outside of the other second outermost word line.

[0095] In some implementations, at least one dummy word line may be additionally arranged between the first outermost word line and the first select line. Additionally, at least one dummy word line may be additionally arranged between the second outermost word line and the second select line.

[0096] Read and program operations (write operations) on storage blocks can be performed page by page, and erase operations can be performed block by block.

[0097] Figure 3 This is a diagram illustrating the structure of the word line WL and bit line BL of a memory device 110 based on an embodiment of the present disclosure.

[0098] Reference Figure 3 The memory device 110 has a core region where memory cells MC are arranged and an auxiliary region (the remaining region other than the core region) including circuitry for performing operations on the memory cell array 210.

[0099] In the core area, a certain number of memory cells arranged in one direction can be called a "page" PG, while a certain number of memory cells connected in series can be called a "memory cell string" STR.

[0100] Word lines WL1-WL9 can be connected to row decoder 310. Bit line BL can be connected to column decoder 320. (Corresponding to...) Figure 2 The data register 330 of the read / write circuit 230 can be located between multiple bit lines BL and the column decoder 320.

[0101] Multiple word lines WL1-WL9 can correspond to multiple pages PG.

[0102] For example, each of the multiple word lines WL1-WL9 can correspond to, for example, Figure 3 The diagram shows a page PG. When each of the multiple word lines WL1-WL9 has a large size, each of the multiple word lines WL1-WL9 can correspond to at least two (e.g., two or four) page PGs. Each page PG is the smallest unit in programming and reading operations, and all memory cells MC within the same page PG can be operated simultaneously during programming and reading operations.

[0103] Multiple bit lines BL can be connected to column decoder 320. In some implementations, the multiple bit lines BL can be divided into odd bit lines BL and even bit lines BL, such that a pair of odd bit lines BL and even bit lines BL are connected together to column decoder 320.

[0104] When accessing a memory cell MC, row decoder 310 and column decoder 320 are used to locate the desired memory cell based on its address.

[0105] In some implementations, the data register 330 plays a crucial role because all data processing performed by the memory device 110, including programming and reading operations, occurs via the data register 330. If data processing performed by the data register 330 is delayed, all other areas must wait until the data register 330 completes its data processing, thereby reducing the overall performance of the memory device 110.

[0106] Reference Figure 3 In the example shown, within a memory cell string STR, multiple transistors TR1-TR9 can be connected to multiple word lines WL1-WL9, respectively. In some implementations, the multiple transistors TR1-TR9 correspond to memory cells MC. In this example, the multiple transistors TR1-TR9 include a control gate CG and a floating gate FG.

[0107] Multiple word lines WL1-WL9 include two outermost word lines, WL1 and WL9. A first select line DSL can be additionally arranged outside the first outermost word line WL1. Compared to the other outermost word line WL9, the first outermost word line WL1 is closer to the data register 330 and has a shorter signal path. A second select line SSL can be additionally arranged outside the other second outermost word line WL9.

[0108] The first selection transistor D-TR, controlled by the first selection line DSL, has a gate electrode connected to the first selection line DSL, but does not include a floating gate FG. The second selection transistor S-TR, controlled by the second selection line SSL, has a gate electrode connected to the second selection line SSL, but does not include a floating gate FG.

[0109] The first selection transistor D-TR serves as a switching circuit to connect the corresponding memory cell string STR to the data register 330. The second selection transistor S-TR serves as a switching circuit to connect the corresponding memory cell string STR to the source line SL. That is, the first selection transistor D-TR and the second selection transistor S-TR can be used to enable or disable the corresponding memory cell string STR.

[0110] In some embodiments, the memory system 100 applies a predetermined turn-on voltage Vcc to the gate electrode of the first selection transistor D-TR, thereby turning on the first selection transistor D-TR, and applies a predetermined cut-off voltage (e.g., 0V) to the gate electrode of the second selection transistor S-TR, thereby turning off the second selection transistor S-TR.

[0111] During a read or verify operation, memory system 100 turns on both the first selection transistor D-TR and the second selection transistor S-TR. Therefore, during a read or verify operation, current can flow through the corresponding memory cell string STR and drain to the source line SL corresponding to ground, allowing the voltage level of the bit line BL to be measured. However, during a read operation, there may be a time difference in the turn-on / turn-off timing between the first selection transistor D-TR and the second selection transistor S-TR.

[0112] During the erase operation, the memory system 100 can apply a predetermined voltage (e.g., +20V) to the substrate via the source line SL. During the erase operation, the memory system 100 applies a voltage sufficient to allow both the first selection transistor D-TR and the second selection transistor S-TR to float. Therefore, the applied erase voltage can remove charge from the floating gate FG of the selected memory cell.

[0113] Figure 4This is a schematic diagram illustrating the structure of a performance optimization device 10 for a memory system 100 based on an embodiment of the present disclosure.

[0114] Reference Figure 4 The performance optimization device 10 of the memory system 100 may include a storage memory 11 and a computing processor 12.

[0115] The storage memory 11 can store N candidate performance parameter values ​​X1, X2, ..., XN-1, XN for the performance parameter X of the memory system 100, where N is a natural number. The storage memory 11 can be volatile memory (e.g., SRAM, DRAM, SDRAM) or non-volatile memory (e.g., NAND flash memory).

[0116] At this point, N candidate performance parameter values ​​X1, X2, ..., XN-1, XN can be randomly selected from the range of possible values ​​for the performance parameter X of the memory system 100.

[0117] The computing processor 12 can compute N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), and OBJ_FUNC(XN) for an objective function OBJ_FUNC(X) defined for the memory system. To this end, the computing processor 12 can repeatedly measure the operational performance of the memory system 100 after setting the performance parameter X of the memory system 100 to one of the aforementioned N candidate performance parameter values ​​X1, X2, ..., XN-1, XN.

[0118] Each of the N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN) is the result of the objective function OBJ_FUNC(X) when the memory system 100 is used to measure the memory system 100 by applying the corresponding candidate performance parameter values ​​X1, X2, ..., XN-1, XN. The computing processor 12 can load the candidate performance parameter values ​​X1, X2, ..., XN-1, XN from the storage memory 11 to compute the N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN).

[0119] The computing processor 12 can determine the additional candidate performance parameter value XN+1 of the performance parameter X of the memory system 100 based on N candidate performance parameter values ​​X1, X2, ..., XN-1, XN and N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN).

[0120] In this way, the performance optimization device 10 of the memory system 100 can automatically determine the additional candidate performance parameter value XN+1 for the performance parameter X of the memory system 100 based on N candidate performance parameter values ​​X1, X2, ..., XN-1, XN and the N measured objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN). Therefore, compared to engineers manually analyzing the performance of the memory system 100, the performance optimization device 10 of the memory system 100 can quickly determine the optimal value of the performance parameter X and prevent deviations from the optimal value of the performance parameter.

[0121] For example, the performance optimization device 10 of the memory system 100 can be implemented as a separate computing device (e.g., PC, smartphone, tablet) connected to the memory system.

[0122] However, as another example, the memory controller 120 of the memory system 100 can operate as a performance optimization device 10 of the memory system 100. In this case, the storage memory 11 can be the working memory 125 of the memory system 100, and the computing processor 12 can be the processor 124 of the memory system 100.

[0123] The performance parameter X of the memory system 100 can be one of various parameters whose value can affect the operational performance of the memory system 100.

[0124] For example, the performance parameter X could be a ratio between the utilization rate of the write buffer included in the memory system 100 and the operating characteristics of the memory system 100 (e.g., the delay for outputting a completion signal for a command received from the host). The memory system 100 can temporarily store data (not shown) using a write buffer before it is stored in the memory device 110. For example, the write buffer could be located in a specific area within the working memory 125 included in the memory system 100.

[0125] The memory system 100 can adjust its operating characteristics (performance parameters) to prevent the size of the free space in the write buffer from decreasing when the write buffer utilization rate increases. In this case, the relationship OP = X * WBU can be established for the write buffer utilization rate WBU, the operating characteristics OP of the memory system 100, and the performance parameter X.

[0126] As another example, the performance parameter X can be the speed of the operating clock input to the components included in the memory system 100.

[0127] As another example, the performance parameter X can be the generation cycle of a status read message, which the memory system 100 generates to check the results of internal operations (e.g., read / write operations).

[0128] Figure 5 The diagram illustrates the candidate performance parameter values ​​X1, X2, ..., XN-1, XN and the objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN) based on embodiments of the present disclosure.

[0129] Reference Figure 5 The objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN) for the candidate performance parameter values ​​X1, X2, ..., XN-1, XN can be obtained from... Figure 4 The computational processor 12 described herein is used for calculation. The objective function result for each of the candidate performance parameter values ​​X1, X2, ..., XN-1, XN can be calculated by measuring the operational performance of the memory system 100 after setting the performance parameter X of the memory system 100 to the corresponding candidate performance parameter value.

[0130] In embodiments of this disclosure, the performance optimization apparatus 10 of the memory system 100 can use an objective function OBJ_FUNC(X) to determine, as accurately as possible, the correlation between the performance parameter X of the memory system 100 and the operational performance of the memory system 100. Therefore, depending on how the objective function OBJ_FUNC(X) is set, the performance optimization apparatus 10 of the memory system 100 can determine the optimal value of the performance parameter X of the memory system 100 in different ways.

[0131] Figure 6 This is a diagram illustrating the form of the objective function OBJ_FUNC(X) based on an embodiment of this disclosure.

[0132] The memory system 100 can receive M commands CMD_1, ..., CMD_M from an external device (e.g., a host) within a set time period (e.g., 1 second), where M is a natural number greater than or equal to 2. At this time, the memory system 100 can measure the waiting time for processing each of the M commands CMD_1, ..., CMD_M. In the following description, as an example, the case where the external device transmitting the M commands CMD_1, ..., CMD_M to the memory system 100 is a host will be described; however, the external device is not limited to a host.

[0133] The command waiting time can be defined as the difference between the following two items: i) the time when the host transmits the command to the memory system 100 and ii) the time when the memory system 100 transmits the processing completion response to the host for the command. For example, if the host transmits the command to the memory system 100 100µs after the reference time, and the memory system 100 transmits the processing completion response to the command to the host 180µs after the reference time, then the command waiting time is 180µs – 100µs = 80µs.

[0134] The objective function OBJ_FUNC(X) can be a function f(AVG_LATENCY,MAX_LATENCY) of i) the average value of multiple latency (CMD_1), ..., latency (CMD_M) AVG_LATENCY and ii) the maximum value of multiple latency (CMD_1), ..., latency (CMD_M) MAX_LATENCY.

[0135] The average value AVG_LATENCY of multiple latency (CMD_1), ..., latency (CMD_M) can be determined as (latency(CMD_1) + ... + latency(CMD_M)) / M. For example, if M = 1,000,000, then the average value AVG_LATENCY of multiple latency (CMD_1), ..., latency (CMD_M) could be the average value of the latency of 1,000,000 commands.

[0136] The maximum value of multiple latency (CMD_1), ..., latency (CMD_M), MAX_LATENCY, can be determined as max(latency(CMD_1), ..., latency(CMD_M)). For example, if M = 1,000,000, then the maximum value of multiple latency (CMD_1), ..., latency (CMD_M), MAX_LATENCY, can be the maximum value among the latency of 1,000,000 commands.

[0137] The reason why the objective function OBJ_FUNC(X) is defined as i) the average value of multiple latency (CMD_1), ..., latency (CMD_M) AVG_LATENCY and ii) the maximum value of multiple latency (CMD_1), ..., latency (CMD_M) MAX_LATENCY is as follows.

[0138] Key metrics used to determine the operational performance of memory system 100 include latency and throughput. Latency can be defined as the time required for memory system 100 to complete processing of a command received from the host. Throughput can be defined as the performance of memory system 100 in processing commands received from the host.

[0139] In this context, a trade-off can be established between latency and throughput. For example, when memory system 100 receives a read command from the host, memory system 100 can internally pause the erase operation to reduce latency.

[0140] In this scenario, the memory system 100 can process read commands received from the host more quickly, thereby reducing latency. However, this may delay the processing of erase operations, thus the memory system 100 may not be able to secure enough free storage blocks, and consequently, the throughput of the memory system 100 may decrease.

[0141] Therefore, the performance optimization device 10 of the memory system 100 needs to consider both latency and throughput in order to determine the optimal value of the performance parameter X of the memory system 100.

[0142] At this time, the performance optimization device 10 of the memory system 100 can define the latency based on the maximum value MAX_LATENCY of multiple latency (CMD_1), ..., latency (CMD_M).

[0143] Furthermore, the performance optimization device 10 of the memory system 100 can define throughput based on the average value AVG_LATENCY of the multiple latency times (CMD_1), ..., latency (CMD_M). For example, throughput can be defined as a value that is inversely proportional to the average value AVG_LATENCY of the multiple latency times (CMD_1), ..., latency (CMD_M).

[0144] Therefore, in order to determine the optimal performance parameters that can reduce latency and increase throughput at the same time, the objective function can be defined as a function that considers both i) the average value of multiple latency (CMD_1), ..., latency (CMD_M) AVG_LATENCY and ii) the maximum value of multiple latency (CMD_1), ..., latency (CMD_M) MAX_LATENCY.

[0145] Similarly, the performance optimization apparatus 10 of the memory system 100 can optimize the performance parameter X of the memory system 100 by taking into account two conflicting metrics. For example, for the two conflicting metrics 1) fault detection accuracy and 2) fault detection time, the performance optimization apparatus 10 of the memory system 100 can optimize the performance parameter of the memory system 100 by defining the objective function OBJ_FUNC(X) as a function of the reciprocals of 1) fault detection accuracy and 2) fault detection time.

[0146] Furthermore, the specific form of the above objective function OBJ_FUNC(X) can be determined differently.

[0147] For example, the objective function OBJ_FUNC(X) can be defined as the sum of i) the value obtained by multiplying the average value AVG_LATENCY of multiple latency (CMD_1), ..., latency (CMD_M) by a first weight W1, and ii) the value obtained by multiplying the maximum value of multiple latency (CMD_1), ..., latency (CMD_M) by a second weight W2. In other words, the objective function OBJ_FUNC(X) can be a function of the following form.

[0148] OBJ_FUNC(X)=(W1)*(AVG_LATENCY)+(W2)*(MAX_LATENC Y)

[0149] In this case, the values ​​of the first weight W1 and the second weight W2 can be determined, for example, to satisfy W1 + W2 = 1 (e.g., W1 = 0.4 / W2 = 0.6, W1 = 0.5 / W2 = 0.5).

[0150] Figures 7 to 9 This is a schematic diagram illustrating the performance optimization apparatus 10 of a memory system 100 based on an embodiment of the present disclosure determining the value of an additional candidate performance parameter value XN+1.

[0151] Reference Figure 7 The performance optimization device 10 of the memory system 100 can set a surrogate function SURR_FUNC(X) and an acquisition function ACQ_FUNC(X) required to determine the value of the additional candidate performance parameter XN+1.

[0152] The surrogate function SURR_FUNC(X) is estimated based on the aforementioned N candidate performance parameter values ​​X1, X2, ..., XN-1, XN and the N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN). The surrogate function SURR_FUNC(X) is similar to the objective function OBJ_FUNC(X), but may not perfectly match the objective function OBJ_FUNC(X).

[0153] In this case, one of various probability models can be used to define the surrogate function SURR_FUNC(X). For example, the surrogate function SURR_FUNC(X) can be defined as a function that follows a probability model known as a Gaussian process.

[0154] A Gaussian process function is a function that outputs a normally distributed random variable for any input. A Gaussian process function can be defined by: 1) the mean function, which represents the average of the output values ​​for a given input, and 2) the kernel function, which represents the relation and covariance matrix of a given sample used to estimate the surrogate function SURR_FUNC(X).

[0155] The probability distribution of any performance parameter of memory system 100 can be derived by using the proxy function SURR_FUNC(X).

[0156] The acquisition function ACQ_FUNC(X) can be determined based on the surrogate function SURR_FUNC(X). The acquisition function ACQ_FUNC(X) is used to determine the value of the performance parameter of the memory system 100 based on the probability distribution of the surrogate function SURR_FUNC(X). The value of this performance parameter can further optimize the objective function result better than N candidate performance parameter values ​​X1, X2, ..., XN-1, XN.

[0157] The function ACQ_FUNC(X) can be determined to be a function that considers the following two criteria: 1) the exploitation criterion, which is that the optimal performance parameter value may exist near the N candidate performance parameter values ​​X1, X2, ..., XN-1, XN that have been searched; and 2) the exploration criterion, which is that the optimal performance parameter value may be far away from the N candidate performance parameter values ​​X1, X2, ..., XN-1, XN.

[0158] Different methods can be used to determine the acquisition function ACQ_FUNC(X) by taking into account the two criteria mentioned above. For example, the method for determining the acquisition function ACQ_FUNC(X) could be PI (probability improvement) or EI (expectation improvement).

[0159] In embodiments of this disclosure, the additional candidate performance parameter value XN+1 can be determined by the performance parameter that minimizes the value of the acquisition function ACQ_FUNC(X). This will be described in detail below.

[0160] Reference Figure 8 The function ACQ_FUNC(X) can be determined as a function of: i) the result of inputting performance parameters into the surrogate function SURR_FUNC(X), and ii) the variance VARIANCE(X) of the result of inputting performance parameters into the surrogate function SURR_FUNC(X). As mentioned above, since the surrogate function SURR_FUNC(X) is defined as a function following a probabilistic model, the result of inputting performance parameter values ​​into the surrogate function SURR_FUNC(X) will not be a fixed single value, but rather represented as a probability distribution. Therefore, the variance VARIANCE(X) of the result of inputting performance parameter values ​​into the surrogate function SURR_FUNC(X) can be derived.

[0161] For performance parameter values ​​near N candidate performance parameter values ​​X1, X2, ..., XN-1, XN, the result of the surrogate function SURR_FUNC(X) can be similar to the results of the N already calculated objective functions OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN). Therefore, the variance VARIANCE(X) of the result of the surrogate function SURR_FUNC(X) for performance parameter values ​​near N candidate performance parameter values ​​X1, X2, ..., XN-1, XN is relatively small.

[0162] However, for performance parameter values ​​that are far removed from the N candidate performance parameter values ​​X1, X2, ..., XN-1, XN, the result of the surrogate function SURR_FUNC(X) may differ significantly from the result of the objective function OBJ_FUNC(X) when the performance parameter values ​​are input into the objective function. Therefore, the variance VARIANCE(X) of the result of the surrogate function SURR_FUNC(X) for performance parameter values ​​far removed from the N candidate performance parameter values ​​X1, X2, ..., XN-1, XN is relatively large.

[0163] Based on the above description, the function ACQ_FUNC(X) can be determined, for example, as follows.

[0164] ACQ_FUNC(X)=SURR_FUNC(X)–b*(VARIANCE(X))

[0165] In this case, b can be a predetermined weight value.

[0166] Therefore, based on the variance VARIANCE(X) of the result of the proxy function SURR_FUNC(X), the value of the function ACQ_FUNC(X) for obtaining performance parameter values ​​far away from the N candidate performance parameter values ​​X1, X2, ..., XN-1, XN can be less than the value of the function ACQ_FUNC(X) for obtaining performance parameter values ​​near the N candidate performance parameter values ​​X1, X2, ..., XN-1, XN.

[0167] Reference Figure 9 If the acquisition function ACQ_FUNC(X) is determined, the performance optimization device 10 of the memory system 100 can determine the performance parameter X that minimizes the value of the acquisition function ACQ_FUNC(X). The performance optimization device 10 of the memory system 100 can determine the value of the performance parameter X as an additional candidate performance parameter value XN+1.

[0168] Figure 10 and Figure 11 This is a diagram illustrating how the performance optimization apparatus 10 of a memory system 100, based on an embodiment of the present disclosure, determines optimal values ​​for the performance parameters of the memory system 100.

[0169] Reference Figure 10The computing processor 12 included in the performance optimization device 10 of the memory system 100 can determine the optimal value of the performance parameter of the memory system 100 from the candidate performance parameter values ​​X1, X2, ..., XN-1, XN and the additional candidate performance parameter value XN+1 based on i) N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN) and ii) the objective function result OBJ_FUNC(XN+1) for the additional candidate performance parameter value XN+1.

[0170] When determining the optimal value of the performance parameter X of the memory system 100 from the candidate performance parameter values ​​X1, X2, ..., XN-1, XN and the additional candidate performance parameter value XN+1, the computing processor 12 can determine the optimal value of the performance parameter X of the memory system 100 from the candidate performance parameter values ​​X1, X2, ..., XN-1, XN and the additional candidate performance parameter value XN+1 as the value corresponding to the smallest one among the N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN) and the objective function result OBJ_FUNC(XN+1).

[0171] On the other hand, in order to determine the optimal value of the performance parameter X of the memory system 100, the computing processor 12 can search for a separate candidate performance parameter value XN+2 in addition to the candidate performance parameter values ​​X1, X2, ..., XN-1, XN and the additional candidate performance parameter value XN+1.

[0172] In the following text, reference will be made to Figure 11 Here is an example to describe the operation of the computing processor 12 described above.

[0173] Reference Figure 11 The computing processor 12 can determine whether N is equal to or greater than a preset threshold (S1110).

[0174] When N is equal to or greater than the threshold (S1110 - Yes), the computation processor 12 can determine the optimal value of the performance parameter X of the memory system 100 from the candidate performance parameter values ​​X1, X2, ..., XN-1, XN and the additional candidate performance parameter value XN+1 based on the objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN) and the additional candidate performance parameter value XN+1 (S1120).

[0175] On the other hand, when N is less than the threshold (S1110-No), the computation processor 12 can determine whether there is a value equal to or less than a preset reference value among the N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN) and the additional candidate performance parameter value XN+1 (S1130).

[0176] When a value equal to or less than a preset reference value exists (S1130 - Yes), the computing processor 12 can determine the optimal value of the performance parameter of the memory system 100 from the candidate performance parameter values ​​X1, X2, ..., XN-1, XN and the additional candidate performance parameter value XN+1 based on the objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN) and the additional candidate performance parameter value XN+1 (S1120).

[0177] Furthermore, when there is no value equal to or less than the preset reference value (S1130 - No), in order to determine the optimal value of the performance parameter of the memory system 100, the computing processor 12 may search for a separate candidate performance parameter value XN+2 in addition to the candidate performance parameter values ​​X1, X2, ..., XN-1, XN and the additional candidate performance parameter value XN+1 (S1140).

[0178] Figure 12 A diagram illustrating a method for operating a performance optimization apparatus 10 for a memory system 100 based on an embodiment of the present disclosure.

[0179] Reference Figure 12 The method for the performance optimization apparatus 10 for operating the memory system 100 may include determining N candidate performance parameter values ​​X1, X2, ..., XN-1, XN for the performance parameter X of the memory system 100, where N is a natural number (S1210).

[0180] For example, performance parameter X is the ratio by which the operational performance of memory system 100 changes based on the utilization rate of write buffers included in memory system 100.

[0181] Furthermore, the method for the performance optimization apparatus 10 for operating the memory system 100 may include: calculating N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(X) (S1220) for an objective function OBJ_FUNC(X) defined for the memory system 100. In this case, each of the N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(X) is the result of the objective function OBJ_FUNC(X) when the memory system 100 is measured by applying a corresponding candidate performance parameter value X1, X2, ..., XN-1, XN to the memory system 100.

[0182] The objective function OBJ_FUNC(X) can be a function of: i) the average of the multiple wait times required for the memory system 100 to process multiple commands received from an external device (e.g., a host), AVG_LATENCY, and i) the maximum of the multiple wait times, MAX_LATENCY.

[0183] For example, the objective function OBJ_FUNC(X) could be a function representing the sum of the following: i) the value obtained by multiplying the average of multiple waiting times AVG_LATENCY by a first weight W1, and ii) the value obtained by multiplying the maximum of multiple waiting times MAX_LATENCY by a second weight W2.

[0184] The method of the performance optimization apparatus 10 for operating the memory system 100 may include: determining an additional candidate performance parameter value XN+1 for the performance parameter X of the memory system 100 based on N candidate performance parameter values ​​X1, X2, ..., XN-1, XN and N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(X) (S1230).

[0185] For example, regarding the acquisition function ACQ_FUNC(X) based on the surrogate function SURR_FUNC(X), the additional candidate performance parameter value XN+1 can be determined using the performance parameter X that minimizes the value of the acquisition function ACQ_FUNC(X), where the surrogate function SURR_FUNC(X) is estimated based on N candidate performance parameter values ​​X1, X2, ..., XN-1, XN and N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN). In this case, the acquisition function ACQ_FUNC(X) can be a function of: i) the result of inputting the performance parameter X into the surrogate function SURR_FUNC(X), and ii) the variance VARIANCE(X) of the result of inputting the performance parameter X into the surrogate function SURR_FUNC(X).

[0186] The method for the performance optimization apparatus 10 for operating the memory system 100 may further include: determining the optimal value of the performance parameter X of the memory system 100 from among the candidate performance parameter values ​​X1, X2, ..., XN-1, XN and the additional candidate performance parameter value XN+1, based on i) the objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN) and ii) the objective function result OBJ_FUNC(XN+1) with an additional candidate performance parameter value XN+1.

[0187] The method of the performance optimization apparatus 10 for operating the memory system 100 can determine the optimal value of the performance parameter from among the candidate performance parameter values ​​X1, X2, ..., XN-1, XN and the additional candidate performance parameter value XN+1 when i) N is equal to or greater than a preset threshold or ii) there is a value equal to or less than a preset reference value among the N objective function results OBJ_FUNC(X1), OBJ_FUNC(X2), ..., OBJ_FUNC(XN-1), OBJ_FUNC(XN) and the additional candidate performance parameter value XN+1.

[0188] Figure 13 This is a diagram illustrating the configuration of a computing system 1300 based on an embodiment of the present disclosure.

[0189] Reference Figure 13The computing system 1300 based on embodiments of the present disclosure may include: a memory system 100 electrically connected to a system bus 1360; a CPU 1310 configured to control the overall operation of the computing system 1300; RAM 1320 configured to store data and information related to the operation of the computing system 1300; a user interface / user experience (UI / UX) module 1330 configured to provide a user environment to a user; a communication module 1340 configured to communicate with external devices in a wired and / or wireless manner; and a power management module 1350 configured to manage the power used by the computing system 1300.

[0190] The computing system 1300 may be a personal computer (PC) or a mobile terminal that may include a smartphone, tablet computer or various electronic devices.

[0191] The computing system 1300 may further include a battery for supplying operating voltage, and may further include an application chipset, a graphics-related module, a camera image processor, and DRAM. Other components will be apparent to those skilled in the art.

[0192] The memory system 100 may include not only devices configured to store data in a disk such as a hard disk drive (HDD), but also devices configured to store data in non-volatile memory such as a solid-state drive (SSD), general-purpose flash memory, or embedded MMC (eMMC) device. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Furthermore, the memory system 100 can be implemented as various types of storage devices and can be installed inside various electronic devices.

[0193] Based on the embodiments of this disclosure described above, the operational latency of a memory system can be advantageously reduced or minimized. Furthermore, based on the embodiments of this disclosure, the overhead incurred during the calling of a specific function can be advantageously reduced or minimized. Although various embodiments of this disclosure have been described with specific details and different nuances for illustrative purposes, those skilled in the art will appreciate that various modifications, additions, and substitutions can be made based on the content disclosed or described herein without departing from the spirit and scope of the invention as defined in the appended claims. Moreover, embodiments can be combined to form additional embodiments.

Claims

1. A method for optimizing the performance of an operating memory system, the method comprising: N candidate performance parameter values ​​are determined for the performance parameters of the memory system, where N is a natural number. ； Calculate N objective function results for an objective function defined for the memory system; Based on the N candidate performance parameter values ​​and the N objective function results, additional candidate performance parameter values ​​are determined for the performance parameters of the memory system; as well as Based on the N objective function results and the objective function results corresponding to the additional candidate performance parameter values, the optimal value of the performance parameter of the memory system is determined from the candidate performance parameter values ​​and the additional candidate performance parameter values. Each of the N objective function results is a result of the objective function, which is measured when the corresponding one of the N candidate performance parameter values ​​is applied to the memory system, and The objective function is a function of the following: the average of the multiple waiting times required for the memory system to process multiple commands received from an external device, and the maximum value of the multiple waiting times.

2. The method of claim 1, wherein the performance parameter of the memory system is a ratio of the operational performance of the memory system to the utilization rate of the write buffers included in the memory system.

3. The method of claim 1, wherein the objective function is a function representing the sum of the following: a value obtained by multiplying the average of the plurality of waiting times by a first weight, and a value obtained by multiplying the maximum of the plurality of waiting times by a second weight.

4. The method of claim 1, wherein the additional candidate performance parameter value is determined by a value of the performance parameter that minimizes the value of the acquisition function obtained based on the surrogate function, the surrogate function being estimated based on the N candidate performance parameter values ​​and the N objective function results.

5. The method of claim 4, wherein the acquisition function is a function of: the result of inputting the performance parameter into the proxy function, and the variance of the result of inputting the performance parameter into the proxy function.

6. The method according to claim 1, wherein when N is equal to or greater than a preset threshold or when there is a value equal to or less than a preset reference value among the N objective function results and the objective function results corresponding to the additional candidate performance parameter value, the optimal value of the performance parameter is determined from the candidate performance parameter value and the additional candidate performance parameter value.

7. A performance optimization apparatus for a memory system, comprising: The storage memory stores N candidate performance parameter values ​​for the performance parameters of the memory system, where N is a natural number; as well as A computing processor computes N objective function results for an objective function defined for the memory system, and determines additional candidate performance parameter values ​​for the performance parameters of the memory system based on the N candidate performance parameter values ​​and the N objective function results. The computational processor determines the optimal value of the performance parameter of the memory system from among the candidate performance parameter values ​​and the additional candidate performance parameter values, based on the N objective function results and the objective function results corresponding to the additional candidate performance parameter values. Each of the N objective function results is a result of the objective function, which is measured when the corresponding one of the N candidate performance parameter values ​​is applied to the memory system, and The objective function is a function of the following: the average of the multiple waiting times required for the memory system to process multiple commands received from an external device, and the maximum value of the multiple waiting times.

8. The performance optimization apparatus for a memory system according to claim 7, wherein the performance parameter of the memory system is a ratio of the change in the operating performance of the memory system based on the utilization rate of the write buffers included in the memory system.

9. The performance optimization apparatus for a memory system according to claim 7, wherein the objective function is a function representing the sum of the following: a value obtained by multiplying the average of the plurality of latency times by a first weight, and a value obtained by multiplying the maximum value of the plurality of latency times by a second weight.

10. The performance optimization apparatus for a memory system according to claim 7, wherein the additional candidate performance parameter values ​​are determined by minimizing the value of an acquisition function obtained based on a surrogate function, the surrogate function being estimated based on the N candidate performance parameter values ​​and the N objective function results.

11. The performance optimization apparatus for a memory system according to claim 10, wherein the acquisition function is a function of: the result of inputting the performance parameters into the proxy function, and the variance of the result of inputting the performance parameters into the proxy function.

12. The performance optimization apparatus for a memory system according to claim 7, wherein when N is equal to or greater than a preset threshold or when there is a value equal to or less than a preset reference value among the N objective function results and the objective function results corresponding to the additional candidate performance parameter value, the computational processor determines the optimal value of the performance parameter from the candidate performance parameter value and the additional candidate performance parameter value.

13. A memory controller, comprising: The working memory stores N candidate performance parameter values ​​for the performance parameters of the memory system including the memory controller, where N is a natural number; as well as The processor computes N objective function results for an objective function defined for the memory system; and based on the N candidate performance parameter values ​​and the N objective function results, determines additional candidate performance parameter values ​​for the performance parameters of the memory system. The processor determines the optimal value of the performance parameter of the memory system from the candidate performance parameter values ​​and the additional candidate performance parameter values ​​based on the N objective function results and the objective function results corresponding to the additional candidate performance parameter values. Each of the N objective function results is a result of the objective function, which is measured when the corresponding one of the N candidate performance parameter values ​​is applied to the memory system, and The objective function is a function of the following: the average of the multiple wait times required for the memory system to process multiple commands received from an external device, and the maximum value of the multiple wait times.

14. A method for optimizing a system, the method comprising: The objective function of the system is modeled based on the measured results and the selected parameter values. The objective function is expressed as the following equation, and the measured results are obtained by measuring the performance of the system set to each selected value. Equation OBJ_FUNC(X) = W1 THROUGHPUT+W2 MAX_LATENCY, Where "OBJ_FUNC()" represents the objective function, "X" represents the parameter, "W1" and "W2" represent the predetermined weights, "THROUGHPUT" represents the throughput of the system and is inversely proportional to the average waiting time of a predetermined number of commands provided to the system, and "MAX_LATENCY" represents the maximum of the waiting times. The probability distribution of the parameters is obtained by applying a probability model to the objective function; The acquisition function is determined based on the probability distribution; The additional value of the parameter is estimated using the acquisition function; as well as Based on the measured results and additional results obtained by measuring the performance of the system set to the additional value, the optimal value of the system parameter is determined from the selected value and the additional value.

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