Risc-v processor and method with dynamically modifiable coprocessor instruction immediate number field

Abstract

The RISC-V processor and method for dynamically modifying the immediate number field of the coprocessor instruction of the application, by providing a processor software and hardware architecture, only one arithmetic operation instruction is needed, and an override bit is added in the coprocessor, so that the coprocessor instruction coding field can be dynamically modified by the previous instruction. Compared with the original multiple instructions and the use limitation of the immediate number, the application greatly improves the programming efficiency and use flexibility of the coprocessor instruction.

Description

Technical Field

[0001] This invention relates to the field of computers, and in particular to a RISC-V processor and method for dynamically modifying the immediate digital field of coprocessor instructions. Background Technology

[0002] With the rapid development of information technology, semiconductor chips are widely used in all sectors of society. Large integrated packet processing devices, such as network processors, can include multiple smaller dedicated processors. In recent years, due to the open-source nature of RISC-V, these dedicated processors have seen increasing applications. Each of these smaller processors is specifically adapted and designed for dedicated programming to perform specific types of packet processing. To improve processing performance and efficiency, the chip often integrates a large number of dedicated hardware acceleration coprocessing components, such as route lookup, hash, checksum, and atomic operations. These hardware acceleration coprocessing components are configured and executed through RISC-V coprocessing instructions.

[0003] Generally, when the aforementioned coprocessor executes, it requires a dedicated processor to pre-configure or transfer some information. Some instruction sets also provide user-defined instructions that can be used to extend the instructions of such coprocessors. For example, the RISC-V processor provides a basic instruction format (taking a 32-bit instruction set as an example). Funct7 represents how many different instruction functions you can implement, rd, rs1, rs2 represent the destination register and source register 1, source register 2, respectively. opcode represents the type of this instruction, such as custom0~custom3 corresponding to the coprocessors.

[0004] For coprocessor instructions, rd generally represents the destination register to be written back after the coprocessor finishes execution. rs1 and rs2 are generally used to read some parameter information needed by the coprocessor from the register. For some memory-oriented coprocessor instructions, rs1 and rs2 generally store memory addresses. This means that some information must be carried directly in the instruction. This information carried directly in the instruction code must be a definite value at compile time and cannot be a variable. This limitation has a significant impact on coding efficiency.

[0005] For example, if the `funct3` field is used to represent different coprocessors, the value of the `funct3` field needs to be determined before issuing the coprocessor instruction. Assuming multiple different coprocessor instructions need to be issued, in the worst case, multiple instructions are required to construct a single coprocessor instruction. As another example, if a partial field in the instruction is used to represent the length of data that the coprocessor (such as DMA) needs to process, such as the `funct7` field, the limitation is that the length of data to be processed must be explicitly specified (immediate value) when issuing the coprocessor instruction. This reduces programming efficiency and also results in poor flexibility. In the worst case, multiple instructions are still required to construct a single coprocessor instruction.

[0006] Therefore, existing methods, in addition to reading data from the source register, also suffer from limitations in coprocessor usage and programming efficiency due to the requirement that other bits in the instruction field must be constants at compile time. Furthermore, they present problems such as the need to construct multiple instructions and the requirement that they must be immediate values. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a RISC-V processor that can dynamically modify the immediate digital field of the coprocessor instruction, so as to solve the above-mentioned technical problems in the prior art.

[0008] To achieve the above and other related objectives, this invention provides a RISC-V processor capable of dynamically modifying the immediate digital field of coprocessor instructions. The processor includes an instruction memory, physical registers, and a pipelined architecture. The pipelined architecture connects the instruction memory and the physical registers, and is used to sequentially fetch arithmetic operation instructions whose destination register is a constant 0 register, as well as specified instructions with field overriding information, from the instruction memory. When an arithmetic operation instruction is fetched, the instruction is decoded, operands are extracted, and the decoded arithmetic operation instruction is executed to obtain the operation result, which cannot be written back to the physical register. When a specified instruction with field overriding information is fetched, the specified instruction is decoded, operands are extracted, and it is determined whether the obtained instruction encoding field with field overriding information can be dynamically modified by the operation result of the arithmetic operation instruction fetched from the specified instruction corresponding to that instruction encoding field. The corresponding coprocessor instruction is then output for distribution to the corresponding coprocessor.

[0009] In one embodiment of the present invention, the pipeline structure includes: an instruction fetch module, a decoding and operand acquisition module, an arithmetic operation execution module, an execution result write-back module, a coprocessor instruction concatenation module, and a coprocessor instruction dispatch module; wherein, the instruction fetch module is used to sequentially fetch arithmetic operation instructions whose corresponding destination register is a constant 0 register and a specified instruction with field overriding information from the instruction memory; the decoding and operand acquisition module, connected to the instruction fetch module, is used to decode the arithmetic operation instructions and the specified instruction, and after reading the operands, dispatch the obtained decoded arithmetic operation instructions to the arithmetic operation execution module or dispatch the obtained instruction encoding field with field overriding information to the coprocessor instruction execution module. The coprocessor instruction concatenation module; the arithmetic operation execution module, connected to the decoding and operand acquisition module and the execution result write-back module, is used to execute the decoded arithmetic operation instructions to obtain the operation execution result, and send the obtained operation execution result to the execution result write-back module; the coprocessor instruction concatenation module, connected to the decoding and operand acquisition module and the arithmetic operation execution module, is used to determine whether the obtained instruction encoding field with field coverage information can be dynamically modified by the operation execution result of an arithmetic operation instruction retrieved from the specified instruction corresponding to the instruction encoding field, and output the corresponding coprocessor instruction for the coprocessor instruction distribution module to distribute to the corresponding coprocessor.

[0010] In one embodiment of the present invention, determining whether the obtained instruction encoding field with field coverage information can be dynamically modified by the execution result of the arithmetic operation instruction retrieved from the previous specified instruction corresponding to the instruction encoding field, and outputting the corresponding coprocessor instruction includes: using the field coverage information corresponding to the instruction encoding field to determine whether the instruction encoding field can be dynamically modified by the execution result of the previous retrieved arithmetic operation instruction; if yes, then overwriting the field corresponding to the overwritten field position in the field coverage information in the execution result of the arithmetic operation instruction with the field corresponding to the overwritten field position in the instruction encoding field, and outputting the corresponding coprocessor instruction according to the overwritten instruction encoding field; if no, then outputting the corresponding coprocessor instruction according to the instruction encoding field.

[0011] In one embodiment of the present invention, the specified instruction includes: specified coprocessor information, field length information, and field coverage information.

[0012] In one embodiment of the present invention, the field coverage information includes: the location of the covered field.

[0013] In one embodiment of the present invention, the number of coverage bits corresponding to the coverage field position can be expanded.

[0014] In one embodiment of the present invention, the decoding and operand acquisition module includes: a decoding module, used to parse the arithmetic operation instruction and the instruction type and source register address of the specified instruction, and issue a corresponding source operand read instruction; and an operand acquisition module, connected to the decoding module, used to acquire source operands based on the source operand read instruction, and dispatch the obtained decoded arithmetic operation instruction to the arithmetic operation execution module or dispatch the obtained instruction encoding field with field overlay information to the coprocessor instruction splicing module.

[0015] In one embodiment of the present invention, the application installation module includes: the specified instruction is a 32-bit RISC-V instruction.

[0016] To achieve the above and other related objectives, this invention provides a method for dynamically modifying the immediate digital field of a coprocessor instruction. The method utilizes a RISC-V processor, which includes an instruction memory, physical registers, and a pipelined architecture. The method comprises: sequentially retrieving arithmetic operation instructions whose destination register is a constant 0 register, and a specified instruction with field overriding information from the instruction memory; when an arithmetic operation instruction is retrieved, the instruction is decoded and operands are extracted, and the decoded arithmetic operation instruction is executed to obtain the operation result, wherein, since the destination register of the arithmetic operation instruction is the constant 0 register, the operation result does not change the value of the constant 0 register; when a specified instruction with field overriding information is retrieved, the specified instruction is decoded and operands are extracted, and it is determined whether the obtained instruction encoding field with field overriding information can be dynamically modified by the operation result of the arithmetic operation instruction retrieved above the specified instruction corresponding to that instruction encoding field, and the corresponding coprocessor instruction is output for distribution to the corresponding coprocessor.

[0017] In one embodiment of the present invention, determining whether the obtained instruction encoding field with field coverage information can be dynamically modified by the execution result of the arithmetic operation instruction retrieved from the previous specified instruction corresponding to the instruction encoding field, and outputting the corresponding coprocessor instruction includes: using the field coverage information corresponding to the instruction encoding field to determine whether the instruction encoding field can be dynamically modified by the execution result of the previous retrieved arithmetic operation instruction; if yes, then overwriting the field in the execution result of the arithmetic operation instruction corresponding to the overwritten field position marked by the field coverage information with the field of the instruction encoding field corresponding to the overwritten field position, and outputting the corresponding coprocessor instruction according to the overwritten instruction encoding field; if no, then outputting the corresponding coprocessor instruction according to the instruction encoding field.

[0018] As described above, the RISC-V processor of the present invention, which can dynamically modify the immediate digital field of the coprocessor instruction, has the following beneficial effects: The present invention provides a processor hardware and software architecture that only requires one arithmetic operation instruction and adds an override bit in the coprocessor, so that the coprocessor instruction encoding field can be dynamically modified by the previous instruction. Compared with the original multiple instructions and the restriction that the usage must be an immediate value, the present invention greatly improves the efficiency and flexibility of coprocessor instruction programming. Attached Figure Description

[0019] Figure 1 The diagram shown is a schematic representation of a RISC-V processor with dynamically modifiable immediate digital fields of coprocessor instructions, according to an embodiment of the present invention.

[0020] Figure 2 The diagram shown is a schematic representation of the assembly line structure in one embodiment of the present invention.

[0021] Figure 3 This is a schematic diagram showing the instruction encoding field coverage in one embodiment of the present invention.

[0022] Figure 4 The diagram shown is a schematic representation of the processor hardware pipeline structure in one embodiment of the present invention.

[0023] Figure 5 The diagram shown is a flowchart illustrating a method for dynamically modifying the immediate digital field of a coprocessor instruction according to an embodiment of the present invention. Detailed Implementation

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0025] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the invention. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of the invention. The following detailed description should not be considered limiting, and the scope of the embodiments of the invention is defined only by the claims of the published patents. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0026] Throughout this specification, when it is said that a part is "connected" to another part, this includes not only "direct connection" but also "indirect connection" by placing other elements in between. Furthermore, when it is said that a part "includes" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather means that other constituent elements may also be included.

[0027] The terms "first," "second," and "third," etc., used herein are for the purpose of describing various parts, components, regions, layers, and / or segments, but are not limiting. These terms are used only to distinguish one part, component, region, layer, or segment from others. Therefore, the "first part," "component," "region," "layer," or "segment" described below may refer to a "second part," "component," "region," "layer," or "segment" without departing from the scope of this invention.

[0028] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition arise only when combinations of elements, functions, or operations are inherently mutually exclusive in some manner.

[0029] This invention provides a RISC-V processor that can dynamically modify the immediate data field of coprocessor instructions. By providing a processor hardware and software architecture, only one arithmetic operation instruction is needed, and an override bit is added to the coprocessor. This allows the coprocessor instruction encoding field to be dynamically modified by the previous instruction. Compared with the original multiple instructions and the restriction that the usage must be an immediate value, this invention greatly improves the efficiency and flexibility of coprocessor instruction programming.

[0030] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0031] like Figure 1 The diagram shows a schematic representation of the structure of a RISC-V processor with dynamically modifiable immediate digital fields of coprocessor instructions in an embodiment of the present invention.

[0032] The processor includes: an instruction memory 11, physical registers 12, and a pipeline structure 13;

[0033] The pipeline structure 13 connects the instruction memory 11 and the physical register 12, and is used for...

[0034] Arithmetic operation instructions whose destination register is a constant 0 register and specified instructions with field overriding information are retrieved from the instruction memory in turn; specifically, an arithmetic operation instruction whose destination register is a constant 0 register is retrieved first, followed by a specified instruction with field overriding information.

[0035] When an arithmetic operation instruction is retrieved, the arithmetic operation instruction is decoded and the operands are extracted. The decoded arithmetic operation instruction is then executed to obtain the operation result. Since the destination register of the arithmetic operation instruction is the constant 0 register, the operation result does not change the value of the constant 0 register. It should be noted that the operation result is an instruction encoding field.

[0036] When the retrieved instruction is a specified instruction with field coverage information, the arithmetic operation instruction is decoded and the operands are extracted. It is then determined whether the obtained instruction encoding field with field coverage information can be dynamically modified by the operation result of the arithmetic operation instruction retrieved above the specified instruction corresponding to the instruction encoding field. The corresponding coprocessor instruction is then output for distribution to the corresponding coprocessor.

[0037] In one embodiment, such as Figure 2As shown, the pipeline structure 13 includes: an instruction fetch module 131, a decoding and operand acquisition module 132, an arithmetic operation execution module 133, an execution result write-back module 134, a coprocessor instruction splicing module 135, and a coprocessor instruction distribution module 136.

[0038] The instruction fetch module 131 is used to retrieve arithmetic operation instructions whose destination register is a constant 0 register and specified instructions with field overriding information from the instruction memory in turn.

[0039] The decoding and operand acquisition module 132 is connected to the instruction fetching module 131 and is used to decode the arithmetic operation instruction and the specified instruction, and after reading the operand, dispatch the obtained decoded arithmetic operation instruction to the arithmetic operation execution module 133 or dispatch the obtained instruction encoding field with field overlay information to the coprocessor instruction splicing module 134.

[0040] The arithmetic operation execution module 133 is connected to the decoding and operand acquisition module 132 and the execution result write-back module 134. It is used to execute the decoded arithmetic operation instructions to obtain the operation execution result and send the obtained operation execution result to the execution result write-back module 134. Due to the characteristics of the RISC-V constant 0 register, the constant 0 register is used as the destination register of the previous arithmetic operation result. Therefore, the operation execution result does not change the value of the constant 0 register, so that the modification of the present invention will not affect the function of the original program.

[0041] The coprocessor instruction splicing module 135, connected to the decoding and operand acquisition module 132 and the arithmetic operation execution module 133, is used to determine whether the obtained instruction encoding field with field coverage information can be dynamically modified by the operation execution result of an arithmetic operation instruction retrieved from the specified instruction corresponding to the instruction encoding field, and output the corresponding coprocessor instruction for the coprocessor instruction distribution module 136 to distribute to the corresponding coprocessor.

[0042] In this embodiment, the decoding and operand acquisition module 132 includes:

[0043] The decoding module 1321 is used to parse the arithmetic operation instruction and the instruction type and source register address of the specified instruction, and issue the corresponding source operand read instruction;

[0044] The operand acquisition module 1322 is connected to the decoding module 1321 and is used to acquire the source operand based on the source operand read instruction, and dispatch the obtained decoded arithmetic operation instruction to the arithmetic operation execution module 133 or dispatch the obtained instruction encoding field with field overlay information to the coprocessor instruction splicing module 135.

[0045] In one embodiment, determining whether the obtained instruction encoding field with field coverage information can be dynamically modified by the execution result of an arithmetic operation instruction retrieved from the specified instruction corresponding to the instruction encoding field, and outputting the corresponding coprocessor instruction includes:

[0046] The field coverage information corresponding to the instruction encoding field is used to determine whether the instruction encoding field can be dynamically modified by the execution result of the previous arithmetic operation instruction fetched by the instruction fetching module. Specifically, if the field coverage information has one or more overriding field positions, it can be dynamically modified by the execution result of the previous arithmetic operation instruction; otherwise, it cannot be modified.

[0047] If so, then the field corresponding to the covered field position in the field coverage information in the execution result of the arithmetic operation instruction will be overwritten by the field corresponding to the covered field position in the instruction encoding field, and the corresponding coprocessor instruction will be output according to the overwritten instruction encoding field; such as Figure 3 As shown, if the overriding field position is the funct3 field, then the funct3 field of the operation execution result is overwritten onto the funct3 field position corresponding to the instruction encoding field; if the overriding field position is the funct7 field, then the funct7 field of the operation execution result is overwritten onto the funct7 field position corresponding to the instruction encoding field.

[0048] If not, the corresponding coprocessor instruction is output according to the instruction encoding field.

[0049] In one embodiment, the arithmetic operation instruction can be any type of arithmetic instruction, such as...

[0050] Addi, X0, R1, R2; / / Execute an arithmetic operation instruction with X0 as the destination register. In the RISC-V architecture, X0 is a constant 0 register. Therefore, the result of the arithmetic operation instruction does not change the value of the X0 register and has no effect on the program execution result.

[0051] In one embodiment, the specified instruction includes: specifying coprocessor information, field length information, and field coverage information. For example,

[0052] Coprocessor type0, length, override; / / where override indicates whether the execution result of the previous instruction should be used to overwrite the relevant fields of the coprocessor, such as type (indicating which coprocessor to send to), and length indicates the length.

[0053] As can be seen from the above pseudo-instructions, only one arithmetic operation instruction is needed, and an override bit is added to the coprocessor to achieve dynamic modification of the coprocessor instruction encoding field. Compared with the original multiple instructions and the restriction that the usage must be an immediate value, the present invention greatly improves the efficiency and flexibility of coprocessor instructions.

[0054] In one embodiment, the field coverage information includes: the location of the covered field.

[0055] In one embodiment, the number of bits corresponding to the override bit position can be expanded. By expanding the bit width of the override bit, more sources and selection methods for coprocessor instruction encoding can be provided.

[0056] In one embodiment, the specified instruction is a 32-bit RISC-V instruction. Of course, for non-RISC-V instruction set kernels, a register can also be specified to perform the above function; therefore, this invention is not limited to RISC-V instruction set kernels.

[0057] To better illustrate the aforementioned RISC-V processor with dynamically modifiable immediate digital fields of coprocessor instructions, the present invention provides the following specific embodiments.

[0058] Example 1: A processor hardware pipeline structure. Figure 4 This is a schematic diagram of the processor hardware pipeline structure.

[0059] The structure includes: an instruction fetch module, a decoding module, an operand acquisition module, an arithmetic operation execution module, an execution result write-back module, a coprocessor instruction concatenation module, and a coprocessor instruction distribution module;

[0060] Taking the 32-bit RISC-V instruction set as an example, the processor core is divided into 5 pipeline stages. The first stage is the instruction fetch module, which fetches 32-bit instructions (pseudo-instructions) from the instruction memory. The second stage is the decoding module, which decodes the instructions, parses the instruction type and source register address based on the instruction fields, and issues a source operand read instruction. The third stage is the operand fetch module, which fetches the source operand. The fourth stage is the arithmetic operation execution module, which executes arithmetic operation instructions (or coprocessor instruction concatenation). The fifth stage is write-back (or coprocessor instruction dispatch).

[0061] The pseudo-instructions are as follows:

[0062] Addi, X0, R1, R2; / / Execute an arithmetic operation instruction, with X0 as the destination register. In the RISC-V architecture, X0 is a constant 0 register.

[0063] Coprocessor type0, length, override; / / where override indicates whether the execution result of the previous instruction should be used to overwrite the relevant fields of the coprocessor, such as type (indicating which coprocessor to send to), and length indicates the length.

[0064] These two instructions are fetched sequentially by the instruction fetch module. During the coprocessor instruction concatenation pipeline stage, the override bit encoded in the instruction by the compiler can be used to select whether some parameters come directly from the instruction encoding or from the execution result of the arithmetic operation instruction during the fourth-level coprocessor instruction concatenation stage.

[0065] Furthermore, by utilizing the characteristics of the RISC-V constant 0 register, this constant 0 register is used as the destination register for the result of the previous arithmetic operation, so that the modification of this invention will not affect the functionality of the original program.

[0066] The following specific embodiments are provided in conjunction with the accompanying drawings:

[0067] like Figure 5 This is a flowchart illustrating a method for dynamically modifying the immediate digital field of a coprocessor instruction according to an embodiment of the present invention.

[0068] The method employs a RISC-V processor, the processor including: instruction memory, physical registers, and a pipelined architecture, and includes:

[0069] Step S51: In turn, retrieve arithmetic operation instructions whose destination register is a constant 0 register and specified instructions with field overriding information from the instruction memory.

[0070] Step S52: When the retrieved instruction is an arithmetic operation instruction, the arithmetic operation instruction is decoded and the operands are extracted. The decoded arithmetic operation instruction is then executed to obtain the operation result. Since the destination register of the arithmetic operation instruction is the constant 0 register, the operation result does not change the value of the constant 0 register.

[0071] Step S53: When the retrieved instruction is a specified instruction with field coverage information, the specified instruction is decoded and operands are extracted. It is determined whether the obtained instruction encoding field with field coverage information can be dynamically modified by the execution result of the arithmetic operation instruction retrieved above the specified instruction corresponding to the instruction encoding field. The corresponding coprocessor instruction is then output for distribution to the corresponding coprocessor.

[0072] In one embodiment, determining whether the obtained instruction encoding field with field coverage information can be dynamically modified by the execution result of the arithmetic operation instruction retrieved from the previous instruction corresponding to the specified instruction, and outputting the corresponding coprocessor instruction includes:

[0073] The field coverage information corresponding to the instruction encoding field is used to determine whether the instruction encoding field can be dynamically modified by the execution result of the previously retrieved arithmetic operation instruction;

[0074] If so, the field in the execution result of the arithmetic operation instruction that corresponds to the covered field position marked by the field covered information will be overwritten with the field in the instruction encoding field that corresponds to the covered field position, and the corresponding coprocessor instruction will be output according to the overwritten instruction encoding field.

[0075] If not, the corresponding coprocessor instruction is output according to the instruction encoding field.

[0076] In one embodiment, the specified instructions include: specifying coprocessor information, field length information, and field coverage information.

[0077] In one embodiment, the field coverage information includes: the location of the covered field.

[0078] In one embodiment, the number of coverage bits corresponding to the coverage field position can be expanded.

[0079] In one embodiment, the pipeline structure includes: an instruction fetch module, a decoding and operand acquisition module, an arithmetic operation execution module, an execution result write-back module, a coprocessor instruction concatenation module, and a coprocessor instruction dispatch module; wherein, the instruction fetch module is used to sequentially fetch arithmetic operation instructions whose destination register is a constant 0 register and specified instructions with field overriding information from the instruction memory; the decoding and operand acquisition module, connected to the instruction fetch module, is used to decode the arithmetic operation instructions and specified instructions, and after reading the operands, dispatch the obtained decoded arithmetic operation instructions to the arithmetic operation execution module or dispatch the obtained instruction encoding field with field overriding information to the coprocessor instruction execution module. The processor instruction concatenation module; the arithmetic operation execution module, connected to the decoding and operand acquisition module and the execution result write-back module, is used to execute the decoded arithmetic operation instructions to obtain the operation execution result, and send the obtained operation execution result to the execution result write-back module; the coprocessor instruction concatenation module, connected to the decoding and operand acquisition module and the arithmetic operation execution module, is used to determine whether the obtained instruction encoding field with field coverage information can be dynamically modified by the operation execution result of an arithmetic operation instruction retrieved from the specified instruction corresponding to the instruction encoding field, and output the corresponding coprocessor instruction for the coprocessor instruction distribution module to distribute to the corresponding coprocessor.

[0080] In one embodiment, the decoding and operand acquisition module includes: a decoding module, used to parse the arithmetic operation instruction and the instruction type and source register address of the specified instruction, and issue the corresponding source operand read instruction; and an operand acquisition module, connected to the decoding module, used to acquire the source operand based on the source operand read instruction, and dispatch the obtained decoded arithmetic operation instruction to the arithmetic operation execution module or dispatch the obtained instruction encoding field with field overlay information to the coprocessor instruction splicing module.

[0081] In summary, this invention provides a RISC-V processor and method for dynamically modifying the immediate numeric field of coprocessor instructions. By offering a processor hardware and software architecture that requires only one arithmetic operation instruction and adds an override bit to the coprocessor, the coprocessor instruction encoding field can be dynamically modified by the previous instruction. Compared to the original multiple instructions and the limitation of requiring immediate values, this invention significantly improves the efficiency and flexibility of coprocessor instruction programming. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0082] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A RISC-V processor capable of dynamically modifying the immediate digital field of coprocessor instructions, characterized in that, The processor includes: an instruction memory, physical registers, and a pipeline structure; The pipeline structure, connecting the instruction memory and physical registers, is used to sequentially fetch arithmetic operation instructions whose destination register is a constant 0 register and specified instructions with field overriding information from the instruction memory. The specified instructions also include specified coprocessor information. When an arithmetic operation instruction is fetched, the instruction is decoded and operands are extracted. The decoded arithmetic operation instruction is then executed to obtain the operation result. Since the destination register of the arithmetic operation instruction is the constant 0 register, the operation result does not change the value of the constant 0 register. When a specified instruction with field overriding information is fetched, the instruction is decoded and operands are extracted. It is determined whether the instruction encoding field with field overriding information can be dynamically modified by the operation result of the arithmetic operation instruction fetched before the specified instruction corresponding to the instruction encoding field. The corresponding coprocessor instruction is then output for distribution to the coprocessor indicated by the specified coprocessor information.

2. The RISC-V processor with dynamically modifiable immediate digital field of coprocessor instructions as described in claim 1, characterized in that, The pipeline structure includes: an instruction fetch module, a decoding and operand acquisition module, an arithmetic operation execution module, an execution result write-back module, a coprocessor instruction concatenation module, and a coprocessor instruction distribution module; The instruction fetch module is used to retrieve arithmetic operation instructions whose destination register is a constant 0 register and specified instructions with field overriding information from the instruction memory in turn. The decoding and operand acquisition module, connected to the instruction fetching module, is used to decode the arithmetic operation instruction and the specified instruction, and after reading the operand, dispatch the obtained decoded arithmetic operation instruction to the arithmetic operation execution module or dispatch the obtained instruction encoding field with field overlay information to the coprocessor instruction splicing module. The arithmetic operation execution module is connected to the decoding and operand acquisition module and the execution result write-back module. It is used to execute the decoded arithmetic operation instructions to obtain the operation execution result, and send the obtained operation execution result to the execution result write-back module so that the operation execution result cannot be written back to the physical register. The coprocessor instruction concatenation module, connected to the decoding and operand acquisition module and the arithmetic operation execution module, is used to determine whether the obtained instruction encoding field with field coverage information can be dynamically modified by the operation result of an arithmetic operation instruction retrieved from the specified instruction corresponding to the instruction encoding field, and output the corresponding coprocessor instruction for the coprocessor instruction distribution module to distribute to the coprocessor indicated by the specified coprocessor information.

3. The RISC-V processor with dynamically modifiable immediate digital field of coprocessor instructions according to claim 1 or 2, characterized in that, The process of determining whether the obtained instruction encoding field with field coverage information can be dynamically modified by the execution result of an arithmetic operation instruction retrieved from the specified instruction corresponding to that instruction encoding field, and outputting the corresponding coprocessor instruction, includes: The field coverage information corresponding to the instruction encoding field is used to determine whether the instruction encoding field can be dynamically modified by the execution result of the previously retrieved arithmetic operation instruction; If so, the field corresponding to the covered field position in the field covered information in the execution result of the arithmetic operation instruction will be overwritten by the field corresponding to the covered field position in the instruction encoding field, and the corresponding coprocessor instruction will be output according to the overwritten instruction encoding field. If not, the corresponding coprocessor instruction is output according to the instruction encoding field.

4. The RISC-V processor with dynamically modifiable immediate digital field of coprocessor instructions as described in claim 1, characterized in that, The specified instruction also includes field length information.

5. The RISC-V processor with dynamically modifiable immediate digital field of coprocessor instructions as described in claim 1, characterized in that, The field coverage information includes: the location of the covered field.

6. The RISC-V processor with dynamically modifiable immediate digital field of coprocessor instructions according to claim 5, characterized in that, The number of bits corresponding to the coverage field position can be expanded.

7. The RISC-V processor with dynamically modifiable immediate digital field of coprocessor instructions according to claim 2, characterized in that, The decoding and operand acquisition module includes: The decoding module is used to parse the arithmetic operation instructions, the instruction type of the specified instruction, and the source register address, and issue the corresponding source operand read instruction; The operand acquisition module, connected to the decoding module, is used to acquire the source operand based on the source operand read instruction, and dispatch the obtained decoded arithmetic operation instruction to the arithmetic operation execution module or dispatch the obtained instruction encoding field with field overlay information to the coprocessor instruction splicing module.

8. The RISC-V processor with dynamically modifiable immediate digital field of coprocessor instructions as described in claim 1, characterized in that, The specified instruction is a 32-bit RISC-V instruction.

9. A method for dynamically modifying the immediate numeric field of a coprocessor instruction, characterized in that, Applied to a RISC-V processor, the processor including: instruction memory, physical registers, and a pipelined architecture, the method includes: The instruction memory is used to retrieve arithmetic operation instructions whose destination register is a constant 0 register, as well as specified instructions with field overriding information. The specified instructions also include specified coprocessor information. When the retrieved instruction is an arithmetic operation instruction, the instruction is decoded and the operands are extracted. The decoded instruction is then executed to obtain the result. Since the destination register of the instruction is the constant 0 register, the result does not change the value of the constant 0 register. When the retrieved instruction is a specified instruction with field overriding information, the specified instruction is decoded and operands are extracted. It is then determined whether the obtained instruction encoding field with field overriding information can be dynamically modified by the execution result of the arithmetic operation instruction retrieved above the specified instruction corresponding to the instruction encoding field. The corresponding coprocessor instruction is then output for distribution to the coprocessor indicated by the specified coprocessor information.

10. The method according to claim 9, characterized in that, The process of determining whether the obtained instruction encoding field with field coverage information can be dynamically modified by the execution result of the arithmetic operation instruction retrieved from the previous instruction corresponding to the specified instruction, and outputting the corresponding coprocessor instruction, includes: The field coverage information corresponding to the instruction encoding field is used to determine whether the instruction encoding field can be dynamically modified by the execution result of the previously retrieved arithmetic operation instruction; If so, the field in the execution result of the arithmetic operation instruction that corresponds to the covered field position marked by the field covered information will be overwritten with the field in the instruction encoding field that corresponds to the covered field position, and the corresponding coprocessor instruction will be output according to the overwritten instruction encoding field. If not, the corresponding coprocessor instruction is output according to the instruction encoding field.

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