A method and system for starting a D1-H application processor

Abstract

The application provides a starting method and system of D1-H application processor, the method comprises the following steps: running internal solidification boot program; running SPL program in on-chip SDRAM; running application program in DDR, thus the starting of D1-H is completed. 48 KB from 0 address in D1-H chip is ROM, which is the boot program BROM of solidification chip; after power-on reset of D1-H, the first instruction is acquired from address 0x0 in the internal mechanism of the chip, the starting is run, the state of firmware exchange starting pin FEL is detected, if the FEL pin is low level, the forced programming mode is entered, which is used for program download; if the FEL pin is high level, the program SPL to be run in the next stage is found in which external nonvolatile memory, and is loaded to address 0x20000 for running, i.e. in on-chip SDRAM. The method improves the starting speed of D1-H chip, and ensures the starting safety.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a boot method and system for a D1-H application processor. Background Technology

[0002] The D1-H application processor chip has been launched and is in mass production. It is the world's first mass-produced application processor equipped with the Pingtouge XuanTie 906 RISC-V architecture, providing a new key intelligent chip for the AIoT era. The D1 chip integrates a self-developed on-chip high-speed interconnect bus (NSI) and rich application interfaces, providing high-performance heterogeneous multi-core computing processing and excellent graphics acceleration capabilities. The D1-H is a RISC-V architecture processor, and this product can be widely used in smart cars, smart home appliances, smart cities, smart commercial displays, smart offices, and many other fields.

[0003] Currently, the original version of the D1-H chip has a slightly slow boot speed, and there is still room for further optimization in terms of boot speed and security. Summary of the Invention

[0004] In view of this, the purpose of this application is to propose a boot method and system for the D1-H application processor, which can specifically solve the existing problems.

[0005] To achieve the above objectives, this application proposes a startup method for a D1-H application processor, comprising:

[0006] Run the internal hardened bootloader;

[0007] Run the SPL program in the on-chip SDRAM;

[0008] Run the application in DDR; D1-H boot is now complete.

[0009] Furthermore, the running of the internally embedded bootloader includes:

[0010] The D1-H chip has 48KB of ROM starting from address 0, which stores the chip's boot program BROM.

[0011] After power-on reset, the chip's internal mechanism retrieves the first instruction from address 0x0 and begins execution. It then checks the status of the firmware exchange start pin FEL. If the FEL pin is low, it enters the forced programming mode for program download. If the FEL pin is high, it searches for the external non-volatile memory where the next program SPL to be run is located and loads it to address 0x20000, i.e., the on-chip SDRAM.

[0012] Furthermore, the external non-volatile memory includes: dMMC / SD card, Nand Flash, and Nor Flash.

[0013] Furthermore, if the next stage is not found, the program enters forced programming mode, and the idle level of the FEL pin is high.

[0014] Furthermore, the execution of the SPL program in the on-chip SDRAM includes:

[0015] Initialize the clock to 1GHz, initialize serial port 0 for the program in DDR to use the serial port to output debugging information, initialize DDR, and then copy the application program in non-volatile memory to address 0x40000000 in DDR memory.

[0016] Furthermore, the first 48 bytes of the SPL program constitute the boot header, wherein the checksum field is filled by a checksum tool, which accumulates the checksum every 4 bytes according to the bin file of the SPL program, and the initial value of the checksum field is 0x5F0A6C39; the SPL code length field information is obtained through the linker script;

[0017] The method for setting the boot header is as follows: first, set the boot header according to the preset information at the beginning of the startup file; second, link the startup file to the beginning of the linker file; and finally, use a checksum tool in the Makefile file to complete the checksum field filling.

[0018] Furthermore, the BROM verifies the checksum field in the boot header. After the verification passes, it copies the SPL program of the corresponding size to the chip's internal SDRAM according to the SPL code length field in the boot header, and then runs the SPL program.

[0019] To achieve the above objectives, this application also proposes a boot system for a D1-H application processor, comprising:

[0020] The firmware boot module is used to run the internal firmware boot program;

[0021] The SPL module is used to run the SPL program in the on-chip SDRAM.

[0022] The application module is used to run the application in DDR, and the D1-H boot process is now complete.

[0023] In summary, the advantages of this application and the user experience it brings are as follows: compared with the original version of the D1-H chip boot program, the method of this application improves the boot speed of the D1-H chip and ensures boot security. Attached Figure Description

[0024] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0025] Figure 1 A flowchart illustrating a startup method for the D1-H application processor according to an embodiment of this application is shown.

[0026] Figure 2 A flowchart illustrating the D1-H interrupt response according to an embodiment of this application is shown.

[0027] Figure 3 A configuration diagram of the boot system of the D1-H application processor according to an embodiment of this application is shown.

[0028] Figure 4 A schematic diagram of the structure of an electronic device provided in one embodiment of this application is shown.

[0029] Figure 5 A schematic diagram of a storage medium provided in one embodiment of this application is shown. Detailed Implementation

[0030] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0031] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] Figure 1 A flowchart illustrating the startup method of the D1-H application processor according to an embodiment of this application is shown. The startup process of the D1-H application processor differs from that of a typical microcontroller and can be divided into three stages: running the internal firmware boot program, running the SPL program in the on-chip SDRAM, and running the application program in DDR.

[0033] like Figure 1 As shown, the startup method of the D1-H application processor includes:

[0034] The first stage involves running the internally firmware bootloader. The D1-H chip's internal 48KB ROM, starting from address 0, stores the chip's bootloader BROM. After power-on reset, the D1-H's internal mechanism fetches the first instruction from address 0x0 and begins execution. This program, called the first-stage program, checks the status of the Fireware Exchange Launch (FEL) pin. If the FEL pin is low, it enters forced programming mode for program download. If the FEL pin is high, it searches for the external non-volatile memory containing the program to be run in the second stage and loads it at address 0x20000, i.e., the on-chip SDRAM. If the second stage program is not found, it also enters forced programming mode, with the FEL pin high when idle. The D1-H supports four types of non-volatile memory: SPI Nor Flash, SPI Nand Flash, SD card, and eMMC.

[0035] The second stage involves running the SPL program in the on-chip SDRAM. Although the Secondary Program Loader (SPL) is not the user's application program, it still needs to be implemented by the user. It prepares the runtime environment for the application program, and is responsible for initializing the clock to 1GHz, initializing serial port 0 for the program in DDR to use to output debugging information, initializing DDR, and then copying the application program in non-volatile memory to address 0x40000000 in DDR memory.

[0036] The third stage involves running the application in DDR, at which point the D1-H boot process is complete. This process can be done using... Figure 1 Briefly stated.

[0037] The process of loading the SPL program from external non-volatile memory to on-chip SDRAM is not user-controlled, but the copying of the SPL program can be accomplished by correctly configuring its structure. The first 48 bytes of the SPL program constitute the boot header, detailed in Table 1. The "Checksum" field can be filled using a checksum tool, which accumulates the checksum every 4 bytes based on the SPL program's bin file. The initial value of the "Checksum" field is 0x5F0A6C39. The "SPL Code Length" field information will be obtained through the linker script.

[0038] The BROM verifies the "checksum" field in the boot header. If the verification passes, it copies the corresponding size of the SPL program to the chip's internal SDRAM according to the "SPL code length" field in the boot header, and then runs the SPL program.

[0039]

[0040] The specific method for setting the boot header is as follows: First, set the boot header at the beginning of the startup file according to the information in Table 1; second, link the startup file to the very beginning of the linker file; and finally, use a checksum tool in the Makefile file to fill in the "checksum" field.

[0041] As can be seen from the D1-H startup process, the SPL program and the application program together constitute the minimum NOS software system of D1-H. The SPL program is mainly responsible for booting the application program, determining whether the application program can run successfully. The application program is where the user actually programs and where the interrupt system runs. The following will elaborate on three aspects: SPL program design, interrupt system establishment, and linker implementation.

[0042] To simplify the design, the SPL program and the application program share a single linker file and startup file. During linking, they are all linked to the DDR, so users can treat the SPL program as if it does not exist when programming.

[0043] 1. SPL Programming

[0044] Since both the SPL and the application program are linked to DDR, and the SPL program runs in on-chip SDRAM, the execution address and link address of the SPL program are inconsistent. For the SPL program to run, it must be position-independent code (PIC). Simply put, position-independent code refers to binary code whose execution is unaffected by its location in memory; it can run without relying on an absolute memory address, and all memory-related parts of the code use relative addresses. The general principle for writing assembly code for PIC is that when referencing symbols in the same position-independent segment or another position-independent segment with a fixed relative position, it must be a PC-based symbol reference, using an offset relative to the current PC to implement jumps or constant accesses. In C language code, it is important to avoid using global and static variables, using only local variables and avoiding calls to external libraries. The implementation of the SPL program is based on these principles.

[0045] 1) Serial port and clock initialization

[0046] The D1-H has six UARTs, designated UART0 through UART5. The SPL program initializes the serial port using UART0 with a baud rate of 115200. This serial port initialization is for DDR initialization. After DDR initialization, relevant debugging information will be printed via the serial port to determine if the DDR initialization was successful.

[0047] The importance of a clock to a chip is self-evident; it's the pulse of an embedded system. Clock initialization is to determine the system clock and bus clock, providing the clock frequency input required for the subsequent operation of various system modules. The clock configuration of D1-H is determined by the Clock Controller Unit (CCU), which controls the Phase-Locked Loop (PLL) configuration and most clock generation, division, synchronization, and gating. Clock initialization mainly involves initializing the chip's main frequency to 1GHz, initializing the Advanced High Performance Bus (AHB), and initializing the Advanced Peripheral Bus (APB).

[0048] The serial port and clock initialization are encapsulated into two independent function blocks, as shown in Table 2.

[0049]

[0050] 2) DDR Initialization

[0051] The D1-H has a relatively small on-chip SDRAM, typically used to run small SPL programs. The SPL program then copies the larger application code to DDR and runs it there. The H5TQ4G63EFR-RDC DDR3 is selected, with a single-chip capacity of 512MB.

[0052] It is possible to construct a closed-source binary environment and use embedded machine code to run DDR initialization code at a specified address.

[0053] Since the SPL program code length needs to be calculated, the machine code of the DDR initialization code is stored in a specific section. In the GNU environment, this can be achieved using the "attribute" keyword, as follows:

[0054]

[0055] The “.ddr.bin” segment is an allocated segment. This operation involves storing the machine code array ddr_bin, which contains the DDR initialization code, in the “.ddr.bin” segment.

[0056] The DDR initialization code runs at address 0x00030000. Therefore, before initializing DDR, the `memcpy` function is used to copy the DDR initialization binary code to address 0x00030000, and then the DDR initialization is completed using the statement "((void(*)(void))((void*)0x00030000))()". Since the SPL program is implemented using position-independent code, the `memcpy` function needs to be implemented manually and cannot be called from the C library.

[0057] 3) Application copying and running

[0058] The choice of external non-volatile memory is related to the copying of application programs. The D1-H supports four types of non-volatile memory: SPI Nor Flash, Spinand Flash, SD card, and eMMC. Compared to SD card and eMMC, SPI Nor Flash and Spinand Flash have the advantages of small size and simple interface. Therefore, SPI Nor Flash and SPI Nand Flash can be selected as the external memory of the D1-H.

[0059] The application copying process involves copying a certain amount of code from a specified address in Flash to address 0x40000000 in DDR memory. Since program downloading and burning involves downloading machine code to address zero in Flash, the SPL program and application are copied together into DDR to facilitate application copying. Based on the application loading requirements and the programming characteristics of Flash, the functionalities shown in Table 3 are designed. The type of external memory used is determined by the function `spl_get_bootdevice`; the code sizes of the SPL program and application can be obtained from the linker file.

[0060]

[0061] The application runs by setting the PC pointer. Since the chip's operating environment is in internal SDRAM while the application runs in DDR, the PC pointer needs to be incremented by a certain offset. This offset is obtained by the difference between the link start address and the running start address. The specific implementation is as follows:

[0062]

[0063] Among them, "_image_start" is related to the link start address, and its value is the link start address, which is the starting address of DDR 0x40000000; "start" is related to the running start address, which is the starting address of the chip's internal SDRAM 0x20000; "_main" is the application entry address.

[0064] 2. Establishment of the interrupt system

[0065] RISC-V specifies that when a CPU interrupt occurs, a new program is executed from the PC address defined in the mtvec register. This program is typically an interrupt service routine (ISR), and can further jump to a more specific ISR by querying the Interrupt and number fields in the mcause register. After interrupt handling is complete, the MERT instruction is used to exit the ISR and return to the main program. Furthermore, since the RISC-V architecture does not provide automatic hardware saving and restoring of the interrupt entry and exit mechanism, software must explicitly use instructions to save and restore the context. Based on this mechanism, the specific implementation of the D1-H interrupt system is as follows:

[0066]

[0067] The vectors function is the total entry address of the interrupt service routine. The four-byte alignment is to set the MODE field of the mtvec register to 0, that is, when all interrupts are responded to, the CPU jumps to the address indicated by the BASE field of the mtvec register. The context refers to the CPU's internal registers, namely the 31 general-purpose registers x1 to x31. The handle_trap function reads the value of the mcause register to determine the type of interrupt and then enters the different interrupt service routines.

[0068] Therefore, the interrupt service routines corresponding to each interrupt and exception need to be implemented by the user and called in the `handle_trap` function, which defaults to an infinite loop. For external interrupts, i.e., interrupts generated by external devices such as UART and GPIO, it is necessary to further determine which external device caused the interrupt to jump to the corresponding interrupt service routine. Machine mode, user mode, and management mode all have corresponding external interrupts. By default, interrupts occurring in any mode will switch to machine mode for response; therefore, this mainly focuses on external interrupts in machine mode.

[0069] D1-H implements a Platform Level Interrupt Controller (PLIC) for priority arbitration and dispatch of multiple external interrupt sources. The interrupt source number and information can be viewed by reading the relevant PLIC registers. After determining the interrupt source number, the corresponding interrupt service routine must be called based on that number. The specific implementation is as follows:

[0070] Similar to the design of vectored interrupts, the interrupt vector table uses function pointers to place interrupt service routines into a global array, such as `irqTable`, in order of interrupt number. When an external interrupt occurs, the program calls the corresponding interrupt service routine in `irqTable` based on the interrupt number. The default interrupt service routine is an infinite loop. In actual programming, users need to register external interrupt service routines themselves, i.e., replace the default external interrupt handling routine. At this point, the D1-H interrupt system is initially established, but to successfully trigger external interrupts, PLIC initialization is also required. RISC-V specifies that the interrupt source priority must be higher than the interrupt target threshold and greater than 0; otherwise, no final interrupt notification will be generated. Therefore, PLIC initialization mainly sets the priority and threshold of each interrupt source. By default, the priority of all interrupt sources is set to 1, and the threshold is set to 0. Based on the above analysis, following the componentization approach, the processing related to external interrupts is encapsulated into independent functional functions, as shown in Table 4.

[0071]

[0072] Based on the established D1-H interrupt system, when an interrupt occurs, the response process is as follows: Figure 2 As shown.

[0073] 3. Implementation of Linked Files

[0074] The linker file specifies how segments from the input intermediate files are mapped to the final object file, and controls the address allocation of each part within the object file. Commands such as MEMORY and SECTIONS control the mapping of segments from the input intermediate files to the final object file and the address allocation of each part within the object file. It typically includes the following segments:

[0075] (1) text section. Used to store program code.

[0076] (2) data segment. It is usually used to store global variables and static variables that are not initialized to 0.

[0077] (3) BSS segment. It is usually used to store global variables and static variables that are initialized to 0 or are not initialized.

[0078] (4) Heap segment. Used for dynamically allocated memory, its size is not fixed and can be dynamically expanded or shrunk. It is generally allocated and released by the programmer.

[0079] (5) stack segment. Automatically allocated and released by the compiler, storing function parameters, local variables, etc.

[0080] Based on the composition and syntax of the link file, complete the design of the link file. Part of the content is shown in the code below.

[0081]

[0082] The following points should be noted regarding this linked file:

[0083] (1) The linker specifies that the output executable file is a 64-bit RISC-V instruction set in little-endian format, the platform of the output executable file is RISC-V, the entry address of the program is start, and the stack size is 61440 bytes. The stack size can be set by the user within the RAM size range.

[0084] (2) The starting address of the link is 0x40000000, and the area size is 512MB.

[0085] (3) Since the text segment contains both the SPL program and the application code, to facilitate the calculation of the SPL program's code size, it is necessary to explicitly indicate in the text segment which files belong to the SPL program, i.e., obj / start.o (.text*) and obj / mymemcpy.o (.text*) in the code above. At the same time, to ensure the correctness of the boot header information, the startup file should be linked at the very beginning.

[0086] (4) Obtain the program code size by adding "tags" to the linker file. "Tags" are similar to variables in C language. In the linker file, they can be used to record the address of the current description location. For example, to calculate the size of the SPL program code, define two tags "__spl_start" and "__spl_end" to record the start and end addresses of the SPL program, respectively. The difference between the two is the size of the SPL program code.

[0087] The application provides a boot system for a D1-H application processor, which is used to execute the boot method for the D1-H application processor described in the above embodiments, such as... Figure 3 As shown, the system includes:

[0088] The firmware boot module 301 is used to run the internal firmware boot program;

[0089] SPL module 302 is used to run the SPL program in the on-chip SDRAM;

[0090] Application module 303 is used to run the application in DDR, at which point the D1-H boot process is complete.

[0091] The boot system for the D1-H application processor provided in the above embodiments of this application and the boot method for the D1-H application processor provided in the embodiments of this application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the applications stored therein.

[0092] This application also provides an electronic device corresponding to the boot method of the D1-H application processor provided in the foregoing embodiments, for executing the boot method of the D1-H application processor. This application does not limit the scope of the embodiments.

[0093] Please refer to Figure 4 This illustrates a schematic diagram of an electronic device provided by some embodiments of this application. For example... Figure 4 As shown, the electronic device 20 includes: a processor 200, a memory 201, a bus 202, and a communication interface 203. The processor 200, the communication interface 203, and the memory 201 are connected via the bus 202. The memory 201 stores a computer program that can run on the processor 200. When the processor 200 runs the computer program, it executes the startup method of the D1-H application processor provided in any of the foregoing embodiments of this application.

[0094] The memory 201 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Communication between this system network element and at least one other network element is achieved through at least one communication interface 203 (which can be wired or wireless), such as the Internet, wide area network, local area network, or metropolitan area network.

[0095] Bus 202 can be an ISA bus, PCI bus, or EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. The memory 201 is used to store programs. After receiving an execution instruction, the processor 200 executes the program. The startup method of the D1-H application processor disclosed in any of the foregoing embodiments of this application can be applied to the processor 200, or implemented by the processor 200.

[0096] The processor 200 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 200 or by instructions in software form. The processor 200 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 201. The processor 200 reads the information in memory 201 and, in conjunction with its hardware, completes the steps of the above method.

[0097] The electronic device provided in this application embodiment and the startup method of the D1-H application processor provided in this application embodiment are based on the same inventive concept and have the same beneficial effects as the methods they adopt, run or implement.

[0098] This application also provides a computer-readable storage medium corresponding to the boot method of the D1-H application processor provided in the foregoing embodiments. Please refer to [link / reference]. Figure 5 The computer-readable storage medium shown is an optical disc 30, on which a computer program (i.e., a program product) is stored. When the computer program is run by a processor, it executes the startup method of the D1-H application processor provided in any of the foregoing embodiments.

[0099] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be elaborated here.

[0100] The computer-readable storage medium provided in the above embodiments of this application and the startup method of the D1-H application processor provided in the embodiments of this application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the application programs stored therein.

[0101] It should be noted that:

[0102] The algorithms and displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems can also be used in conjunction with the teachings herein. The required structure for constructing such systems is apparent from the above description. Furthermore, this application is not directed to any particular programming language. It should be understood that the content of this application described herein can be implemented using various programming languages, and the above description of specific languages ​​is for the purpose of disclosing the best mode of implementation of this application.

[0103] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0104] Similarly, it should be understood that, in order to simplify this application and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of this application, various features of this application are sometimes grouped together into a single embodiment, figure, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0105] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0106] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0107] The various component embodiments of this application can be implemented in hardware, or as software modules running on one or more processors, or a combination thereof. Those skilled in the art will understand that microprocessors or digital signal processors (DSPs) can be used in practice to implement some or all of the functions of some or all of the components in the virtual machine creation system according to the embodiments of this application. This application can also be implemented as a device or system program (e.g., a computer program and computer program product) for performing part or all of the methods described herein. Such an implementation of this application can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, provided on a carrier signal, or provided in any other form.

[0108] It should be noted that the above embodiments are illustrative of this application and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. This application can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several systems, several of these systems may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0109] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A boot method for a D1-H application processor, characterized in that, include: Run the internal hardened bootloader; Run the SPL program in the on-chip SDRAM; Run the application in DDR; D1-H boot is now complete. The operation of the internally embedded bootloader includes: The D1-H chip has 48KB of ROM starting from address 0, which stores the chip's boot program BROM. After power-on reset, the internal mechanism of the D1-H chip retrieves the first instruction from address 0x0 and begins execution. It starts by detecting the status of the firmware exchange start pin FEL. If the FEL pin is low, it enters the forced burning mode for program download. If the FEL pin is high, it searches for the external non-volatile memory where the next stage program SPL is located and loads it into address 0x20000, i.e., the on-chip SDRAM. The SPL program running in the on-chip SDRAM includes: Initialize the clock to 1GHz, initialize serial port 0 for the program in DDR to use the serial port to output debugging information, initialize DDR, and then copy the application program in non-volatile memory to address 0x40000000 in DDR memory; The first 48 bytes of the SPL program are the boot header. The checksum field is filled by a checksum tool, which accumulates the checksum every 4 bytes according to the bin file of the SPL program. The initial value of the checksum field is 0x5F0A6C39. The SPL code length field information is obtained through the linker script. The boot header is set as follows: First, set the boot header at the beginning of the startup file according to the preset information; second, link the startup file to the beginning of the linker file; finally, use a checksum tool in the Makefile file to complete the checksum field filling.

2. The method according to claim 1, characterized in that, The external non-volatile memory includes: dMMC / SD card, Nand Flash, and Nor Flash.

3. The method according to claim 1, characterized in that, If the next stage is not found, the program will enter forced programming mode, and the idle level of the FEL pin will be high.

4. The method according to claim 1, characterized in that, The BROM verifies the checksum field in the boot header. After the verification is successful, it copies the corresponding size of the SPL program to the chip's internal SDRAM according to the SPL code length field in the boot header, and then runs the SPL program.

5. A boot system for a D1-H application processor, using the method described in any one of claims 1-4, characterized in that, include: The firmware boot module is used to run the internal firmware boot program; The SPL module is used to run the SPL program in the on-chip SDRAM. The application module is used to run the application in DDR, and the D1-H boot process is now complete.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, The processor executes the computer program to implement the method as described in any one of claims 1-4.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by a processor to implement the method as described in any one of claims 1-4.

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