An emulation test platform and an automatic generation method thereof

Abstract

The application provides a simulation test platform automatic generation method, which is based on modularization technology, uses XML files to configure and store attribute data, executes the configured data to automatically generate a test platform, and finally loads the test platform into a full-digital simulation system VTest to run. The modularization driving mechanism is adopted to realize a requirement and module matching method, and the ability of automatically generating a simulation test platform based on modules is solved.

Description

Technical Field

[0001] This invention relates to a method for automatically generating a simulation test platform, belonging to the field of simulation. Background Technology

[0002] Embedded simulation systems use software to realistically simulate the physical environment in which embedded software runs, even without the target hardware. Embedded software that originally ran on real hardware can run in the simulation system without any modification, exhibiting the same dynamic characteristics as on the real hardware. Running embedded software on a simulation system involves not only processor simulation but also, and more importantly, simulation of peripheral devices communicating with the embedded software and the processing of communication data. Because the peripheral devices and communication data used by each embedded software differ depending on the requirements and environment, the functional simulation of these peripheral devices and the functional processing of communication data need to be developed separately when building a simulation test platform. Furthermore, each embedded software's corresponding simulation test platform needs to be developed independently. This results in a simulation test platform that is only applicable to a specific embedded software, failing to achieve a universal effect. Each development process is time-consuming, labor-intensive, and requires a high level of technical skill from the developers. However, as software becomes increasingly productized and complex, the current model for building simulation test platforms struggles to meet the design requirements of high efficiency, high reusability, and automation.

[0003] To reduce code modifications or secondary development caused by design inconsistencies in simulation test platforms due to different software functions and data communication methods, ensure the universality of simulation test platform functions, meet the requirements of high efficiency, high quality, and high reusability in platform generation, lower the threshold for simulation test platform generation, and ensure the correctness of simulation test platform testing software, it is necessary to study a new solution for automatic generation of simulation test platforms. Summary of the Invention

[0004] The technical problem solved by this invention is to address the shortcomings of existing simulation test platform construction technologies, which cannot meet the requirements of high efficiency, high reusability, and high quality. This invention provides a simulation test platform and its automatic generation method, realizing the transformation from demand-customized platform development to demand-configurable platform generation.

[0005] The technical solution adopted in this invention is: a simulation test platform, comprising: an instruction execution system module, a memory address operation module, a performance statistics module, a chip simulation module, a data control module, an interrupt triggering module, a log information recording module, and a data parsing module; The instruction execution system module loads, parses, sends, receives, and forwards instructions during the operation of the simulation test platform. It receives instruction data streams sent from outside, loads instruction files, and outputs the converted instruction data to the designated module, driving the corresponding module to perform instruction parsing and execution functions. The memory address operation module controls and processes memory address read and write operations, and records the addresses and data of the operations in real time; the memory address operation module receives instruction data from the instruction execution system module and outputs the data stream generated by the address operation to the log information recording module; The performance statistics module performs interval statistics on the execution time of functional items, supporting point-to-point time statistics and same-point time statistics; when the simulation test platform finishes running, it records the performance-related data to the log file; The chip simulation module performs software simulation of the logic functions, characteristics and timing of the chip. Different independent chip simulation libraries are developed for different chips. The data control module receives and sends protocol data streams. The data control module integrates and controls the timing of all data protocol transmissions, protocol structure judgment, protocol correctness judgment, protocol verification and processing, protocol response control, and command parsing and execution. The interrupt triggering module integrates all interrupt triggering controls and triggering methods. The interrupt triggering module receives the instruction data that triggers the interrupt from the instruction execution system module, parses the instruction, and executes it. The log information recording module records the input and output data of other modules during the operation, forming log information; The data parsing module analyzes the entire packet data of the protocol and displays it in a graphical visualization. The data parsing results support both pure data display and the display of text after data translation. The data parsing module records the results of parsing data packets in real time and sends log data to the log information recording module.

[0006] Furthermore, the memory address operation module monitors one or more addresses within a certain range, and when the software operates on an address, it records the data at the operated address to a file in real time.

[0007] Furthermore, the performance statistics module configures performance statistics attributes according to the instructions of the instruction execution system module, including start address, end address, address operation mode, data start value, data end value, and performance time valid range; wherein when the start address and end address are the same, it indicates that the time interval for statistically analyzing the data operation at the same address is calculated. After the software finishes running, the performance statistics module automatically calculates the maximum and minimum values ​​of the performance data and outputs the start time of the maximum and minimum values; it automatically determines whether the statistical time is within the valid range and gives an out-of-range warning prompt, and saves the data to the specified txt file.

[0008] Furthermore, the chip simulation module receives the data stream sent by the data control module through the port, parses and identifies the data stream, and processes the data through the chip control logic; the chip simulation module sends data to the data control module through the port, and the data control module parses and processes the data stream. The structure, transmission process, and input data of the sent data are the same.

[0009] Furthermore, the data control module receives instruction data and protocol data streams through the instruction execution system module, and outputs the processed data to the corresponding chip simulation module; the protocol data received by the chip simulation module is processed and output to the log information recording module.

[0010] The data control module receives instruction data from the instruction execution system module and output data from the chip simulation module. The instruction execution system module determines the data transmission structure, the chip simulation module determines the output data transmission structure, and the data control module sequentially receives, parses, and processes the data. The data control module sends input stream data to the chip simulation module, unpacks source data to the data parsing module, and sends input and output data to the log information recording module for recording.

[0011] Furthermore, the data parsing rules in the data parsing module are configured through XML files, and different protocols and parsing methods are configured through configuration files.

[0012] A method for generating a simulation test platform, comprising: Loading configuration file: The configuration file adopts an XML file structure; Obtain project information: Based on the loaded configuration file XML, obtain the basic information, processor information, general function library information, and chip simulation library module of the corresponding project information, and store and manage the above data, and provide interface functions for obtaining configuration file information data; Obtain functional module relationship data: Based on the loaded functional library configuration information XML, obtain information such as the attributes, pins, data interfaces, relationships and linking methods between functional libraries, and store and manage the data; Data processing based on configuration files: Analyze the input requirements based on the information obtained from the configuration files, obtain processor information, project name, memory usage, interrupt usage, functional interfaces and other functional interfaces, and generate corresponding platform files; Generate basic project and processor information: Based on the data obtained from the configuration file and the requirements project, automatically generate project information, memory data, processor information data and the file under test; Generate basic project files: Create project files based on the generated project information data. The files include processor, memory, source file under test, object code file, and project attribute data. Retrieve function libraries from the container: Based on the analysis and matching of configuration file information and requirement items, obtain the required function libraries, automatically extract the required function libraries and corresponding files from the container, and store them in the specified directory of the project file; Generate function libraries: The function libraries obtained from the container are placed in the specified directory of the project file. Function library information is added to the project file, including library file path, name, attribute data, communication port and supported pin information; The association between the corresponding library and other libraries is obtained by configuring data through the configuration file and link data is automatically generated, including port communication links between function libraries, pin links, function library and processor interrupt pin links and attribute configuration data values. Generate test instructions: The test instruction generator loads the completed project file and uses the function library IDs in the project file and the instruction IDs and names in the instruction file to generate an instruction description file and a test instruction-ID mapping file. Project file loading and execution: After the test platform project file is generated, it is loaded and executed through the fully digital simulation system VTest, and the instruction-driven mechanism is notified to carry out software testing.

[0013] Furthermore, the configuration file includes project information, processor information, general function library information, chip simulation library, and data control module. The XML file also supports configuring the attributes, pins, data interfaces, relationships between libraries, and linking methods of each function library.

[0014] Furthermore, the functional library modules simulate the corresponding chip logic and timing, including instruction execution system modules, memory address operation modules, performance statistics modules, chip simulation modules, data control modules, interrupt triggering modules, log information recording modules, and data parsing modules.

[0015] Furthermore, the loading and running of the project files also includes: instruction-driven support for loading instruction files and scripts, as well as support for test instructions sent by the general automated dynamic testing platform DTP.

[0016] The advantages of this invention compared to the prior art are: This invention proposes a simulation test platform and its automatic generation method. The method is based on modular technology, which matches requirements with modules, encapsulates test instructions in a modular manner, uses XML files to configure and store attribute data, executes the configured data to automatically generate the test platform, and finally loads it into the all-digital simulation system VTest for operation, realizing the transformation from demand-customized platform development to demand-configurable platform generation. Attached Figure Description

[0017] Figure 1 This is a framework diagram of the simulation test platform of the present invention; Figure 2 This is a flowchart illustrating the process of generating the simulation test platform of the present invention. Detailed Implementation

[0018] The invention will now be further described with reference to the accompanying drawings.

[0019] I. Platform Components Based on a modular platform, an execution mechanism between modules was designed and implemented, resulting in a simulation test platform comprising: an instruction execution system module, a memory address operation module, a performance statistics module, a chip simulation module, a data control module, an interrupt triggering module, a log information recording module, and a data parsing module.

[0020] (1) Instruction Execution System Module This module provides unified management of functions such as loading, parsing, sending, receiving, and forwarding instructions during the operation of the simulation test platform. It is essential to exist in every project. The attribute and structure information of this library are described through configuration files. When a project creates other function libraries, it automatically checks whether it can communicate with the instruction system library. If communication is possible, it automatically establishes a communication connection. The specific connection method is obtained through configuration files.

[0021] The instruction execution system module receives instruction data streams sent from outside (network or port) and loads the instruction file.

[0022] The instruction file format is as follows: Time command: Keyword in the instruction file; Test end time: Keyword for test end time; EndTime: Sets the runtime end time; The instruction file contains a set of multiple instructions. Each instruction is formatted as: #time;instruction name;parameter1;parameter2;parameter3 ..., where time is the execution time of the instruction, and parameters are the data content of the instruction. Multiple parameters are supported. The instruction is to set a single AD result data when the software runs for 33.2 seconds. It is accompanied by four parameters with values ​​of 0, 12, 0x00, and 0xFFF.

[0023] The instruction execution system module receives instruction data via a network interface or other ports. The data format is: instruction name; parameter1; parameter2; parameter3..., which lacks the timestamps compared to the instruction format in the data file. The instruction execution system module executes the instruction immediately upon receiving the instruction data.

[0024] The instruction execution system module outputs instruction data after conversion based on the input data. During platform operation, the converted instruction data is sent to a designated module to drive that module to perform instruction parsing and execution functions.

[0025] The converted instruction data structure is as follows: nTpye: Instruction data type, currently a script instruction; nID: Instruction ID number. The instruction module generates the corresponding instruction ID based on the execution name. Each module identifies the instruction by the instruction ID number. The ID identification formula is: (Instruction ID - Module ID * 10000) < 10000. szPara: Parameters for the instruction data; (2) Memory address operation module Memory address operations are functions that control and process read and write operations on memory addresses, while simultaneously logging the addresses and data of the operations in real time.

[0026] The memory address operation module receives instruction data from the instruction execution system module and outputs the data stream generated by the address operation to the log information recording module.

[0027] The memory address manipulation module controls the timing and content of data input through instructions, supporting the following instructions: 1> Set address data Parameter 1: Starting address, hexadecimal Parameter 2: Data or file, file type includes txt and bin, txt format Note: Supports 8-bit, 16-bit, and 32-bit address type settings. 2> Set address bit data Parameter 1: Address, 0x indicates hexadecimal, otherwise decimal. Parameter 2: Data, 0x indicates hexadecimal, otherwise decimal. Parameter 3: Mask, 0x indicates hexadecimal, otherwise decimal. Note: Supports 8-bit, 16-bit, and 32-bit address type settings, and sets single or multiple bit values ​​through a mask; The memory address operation module monitors one or more addresses within a certain range. When the software operates on an address, it records the data at the operated address to a file in real time.

[0028] Address monitoring method: SetWatchOnMemory(DWORD dwBeginAddr, DWORD dwEndAddr, DWORD dwMemType, VTTACCESS vtAccess, VTTMEMORYCALLBACK vttCallBack), parameters include start address, end address, address type, callback function (this function is executed when operating on addresses within the monitoring range); File type: Record files support TXT; File format: time address operation mode address data value, such as: 10.5 read 0x5000 0x12, when the software runs for 10.5 seconds, the data read from address 0x5000 is 0x12; (3) Performance Statistics Module Performance statistics are interval statistics of the execution time of a certain function item, supporting point-to-point time statistics and same-point time statistics; when the simulation test platform finishes running, the performance-related data is recorded to the log file.

[0029] The performance statistics module configures performance statistics attributes according to the instructions of the instruction execution system module, including start address, end address, address operation mode (read / write), data start value, data end value, and performance time validity range (if the range is exceeded, an alarm will be triggered or other operations will be performed); when the start address and end address are the same, it indicates that the time interval for statistically analyzing the data operation status of the same address is statistically set.

[0030] After the software finishes running, the performance statistics module automatically calculates the maximum and minimum performance data and outputs the start time of the maximum and minimum values. It automatically checks whether the statistical time is within a valid range and issues an out-of-range warning. The data is saved to a specified txt file, with the following content: .

[0031] (4) Chip emulation module The chip simulation module mainly performs software simulation of the logic functions, characteristics and timing of the chip, and develops different independent chip simulation libraries for different chips.

[0032] The chip emulation module receives and sends protocol data streams through the data control module.

[0033] The chip simulation module receives the data stream sent by the data control module through the port, parses and identifies the data stream, and processes the data through the chip control logic.

[0034] The data transmission structure is as follows: lpbuf: Data stream storage buffer; nLen: Length of the data stream, in bytes; nResverse: Reserved parameter; dReceiveBeginTime: The start time of data transmission, in seconds; The chip simulation module sends data to the data control module through the port. The data control module parses and processes the data stream. The structure, transmission process, and input data are the same.

[0035] (5) Data control module The data control module integrates and controls all data protocol transmission timing, protocol structure judgment, protocol correctness judgment, protocol verification and processing, protocol response control, and command parsing and execution.

[0036] The data control module receives instruction data and protocol data streams through the instruction execution system module, and outputs the processed data to the corresponding chip simulation module; the protocol data received by the chip simulation module is processed and output to the log information recording module.

[0037] The data control module receives instruction data from the instruction execution system module and output data from the chip simulation module. The instruction execution system module determines the data transmission structure, and the chip simulation module determines the output data transmission structure. The data control module then sequentially receives, parses, and processes the data. The data transmission structure and method are detailed in the instruction module and chip simulation module.

[0038] The data control module sends input stream data to the chip simulation module, unpacked source data to the data parsing module, and input / output data to the log information recording module for recording. The data transmission structure and method are detailed in the chip simulation module, data parsing module, and log information recording module.

[0039] (6) Interrupt Trigger Module The interrupt triggering module integrates all interrupt triggering controls and triggering methods, enabling unified control and management of interrupt triggering.

[0040] The interrupt triggering module receives the instruction data that triggers the interrupt from the instruction execution system module, parses the instruction, and executes it.

[0041] The interrupt trigger module receives interrupt trigger command data, and supports the following commands: 1> Trigger an external interrupt Parameter 1: Interrupt number: 0~15 Parameter 2: Trigger level mode: HIGH: rising edge; LOW: falling edge Parameter 3: Loop time, in seconds. If less than or equal to 0, trigger once or stop triggering. Note: Currently, 16 external interrupt numbers are supported, and they can be triggered in a cyclic manner. 2> Trigger internal interrupt Parameter 1: Interrupt number: 0~9 Parameter 2: Trigger level mode: HIGH: rising edge; LOW: falling edge Parameter 3: Loop time, in seconds. If less than or equal to 0, trigger once or stop triggering. Note: Currently, the number of internal interrupt numbers supported is 10, which can be triggered in a cyclic manner; (7) Log information recording module The log information recording module records the input and output data of all modules, forming a complete and unified log information system. The log files support txt text files, bin files, and databases, realizing unified management of log data recording and improving the efficiency of data information recording.

[0042] The log information recording module receives data from other modules via an interface. The data format and type are as follows: nTpye: Data type, currently the file name; nID: The ID number corresponding to the file. Each file in the system has a unique ID. szPara: Stores the file name and its contents; nTpye: Data type, currently set to print and save a data file; nID: The ID number corresponding to the printed file; szPara: The specific content of the printed data; (8) Data parsing module The data parsing module analyzes the entire packet data of the protocol and presents it in a graphical visualization. The data parsing results support both pure data display and the display of text after data translation. The data parsing rules are configured through XML files. Different protocols and different parsing methods can be configured through configuration files to achieve flexible application and rapid adaptation of data parsing.

[0043] a) XML file structure: GRID: A set of data start markers, with attributes Name: data protocol name, Row: number of rows displayed in the interface, Col: number of columns displayed in the interface, and Flag: data ID identifier used for protocol matching ID; DATA: Data item under GRID, Offset: Data item offset, Length: Data length, Name: Data name, ValueType: Data type, Order: Data order, Vector: Equivalent value, CodeType: Encoding method, FloatType: Floating-point data type; DATASELECT: Data item configuration and transformation configuration; BIT: Configurable in bit mode within DATA, supporting offset position, length, and name equivalent configuration; BITSELECT: Bit data item conversion configuration; The data parsing module receives data from the data control module, and the data transmission structure is as follows: nFlag: Data packet identifier, which is matched with the flag in the parsing cabinet configuration file. If the match is successful, the corresponding rule data is parsed. pBuf: Data packet storage area; nBufLen: Number of bytes in the data packet; The data parsing module records the results of parsing data packets in real time and sends the log data to the log information recording module. Supported file types include txt and excel.

[0044] II. Platform Generation Method Based on the configuration information and test requirements, corresponding functional modules are added. Through the configuration information and relationships of the functional modules, the simulation test platform project and test platform files are automatically generated. The platform files include the VTE file, software object code file, software source code file, function library module file, test instruction set, and instruction file.

[0045] The platform generation process is as follows: 1) Load the configuration file XML The configuration file is designed using an XML file structure. The configuration file content includes project information, processor information, general function library information, chip simulation library and data control module, etc. At the same time, the XML file supports configuring the attributes, pins, data interfaces, associations and linking methods between various function libraries.

[0046] 2) Obtaining project information Based on the loaded configuration file XML, the system retrieves basic information, processor information, general function library information, chip simulation library modules, and other data related to the corresponding project information, stores and manages this data, and provides interface functions for retrieving configuration file information data.

[0047] 3) Obtain functional module relationship data Based on the loaded function library configuration information XML, obtain information such as the function library's attributes, pins, data interfaces, relationships between function libraries, and linking methods, and store and manage the data.

[0048] 4) Process data according to the configuration file. The input requirements are analyzed based on the information obtained from the configuration file. Processor information (processor type, clock speed), project name, memory usage, interrupt usage, function interfaces (obtain function library) and other function interfaces are extracted from the requirements, and finally the corresponding platform file is generated.

[0049] 5) Generation of basic engineering and processor information Based on the data obtained from the configuration file and the required project, the system automatically generates project information (project name, version, attribute configuration), memory data, processor information (processor type, clock speed, interrupt status), and the file under test (file storage path and target code file).

[0050] 6) Generation of basic engineering documents Based on the generated project information data, a project file is created, which includes processor, memory, source file under test, object code file, and project attribute data.

[0051] 7) Retrieve function libraries from the container The function library module simulates the logic and timing functions of the corresponding chip. The function library has a unified standard interface and communication protocol. All function libraries are collected into a container for unified management. The types include instruction execution system module, memory address operation module, performance statistics module, chip simulation module, data control module, interrupt triggering module, log information recording module, and data parsing module.

[0052] Based on the analysis and matching of configuration file information and requirements, the required function libraries are obtained, and the required function libraries and corresponding files are automatically extracted from the container and stored in the specified directory of the project file.

[0053] 8) Function library generation The function libraries obtained from the container are placed in the specified directory of the project file. The function library information is added to the project file, including the library file path, name, attribute data, communication port and supported pin information.

[0054] By configuring data in the configuration file, the association between the corresponding library and other libraries can be obtained and the link data can be automatically generated, including port communication links between function libraries, pin links, interrupt pin links between function libraries and processors, and attribute configuration data values.

[0055] 9) Test instruction generation The test instructions are generated after the project information and function libraries are generated. Finally, the test instruction generation program is executed. This program automatically generates the supported test instructions and usage instructions based on the currently selected processor, function libraries, and other information. The test instruction file format supports txt and json files.

[0056] The test instruction generator loads the completed project file and uses the function library ID and instruction ID and name information in the instruction file to generate an instruction description file and a test instruction and ID correspondence file. The formula for calculating the generated instruction ID is: function library ID * 10000 + instruction ID in instruction file.

[0057] 10) Load and run the project file After the test platform project files are generated, they are loaded and executed through the fully digital simulation system VTest, which then notifies the instruction-driven mechanism to perform software testing. The instruction-driven mechanism supports loading instruction files and scripts, as well as test instructions sent by the general automated dynamic testing platform DTP.

[0058] Example: This invention defines an automatic generation method for simulation test platforms. Based on modular technology, it utilizes XML files for configuring and storing attribute data, automatically generates the test platform using the configured data, and finally loads it into the all-digital simulation system VTest for execution. By employing a modular-driven mechanism to match requirements with modules, it solves the problem of automatically generating simulation test platforms based on modules.

[0059] like Figure 1 As shown, the simulation test platform includes: (1) Instruction Execution System Module This module is mainly responsible for loading, parsing, sending, receiving, and forwarding instructions during the operation of the simulation test platform.

[0060] Command loading: Load the command file to be executed through the interface or port, read the command content in the file and save it; Instruction parsing: The read instructions are parsed to understand their format, including execution time, instruction name, and instruction parameters; instruction names can be transmitted using instruction IDs. Command transmission: Based on the command time, when the simulation platform reaches that time, the command is broadcast through the communication port. The transmitted content includes the command name and parameters. Command reception: Receives commands from other modules, parses them, and then sends them out. Command forwarding: Receive commands from other modules and send them out directly without parsing them; (2) Memory address operation module This module handles the control of memory address read and write operations, including single address, multiple address, and contiguous address blocks. Memory address control methods include real-time monitoring, periodic operation, and conditional control, while simultaneously recording real-time data for monitored address operations. Configurable settings are available for address type, monitoring method, and data log file name. (3) Performance Statistics Module This module performs interval statistics on the execution time of functional items, mainly using point-to-point time statistics and same-point time statistics. Specific statistical functions support address read / write operation statistics, signal change time statistics, and code segment execution time statistics. It also satisfies conditional judgment statistical functions, such as the time interval between consecutive writes to address 0x1000 being 0. After the simulation test platform finishes running, the module automatically calculates the maximum and minimum values ​​of performance data and records them to the log file.

[0061] (4) Chip emulation module This module primarily focuses on developing software simulation capabilities for the logic functions, characteristics, and timing of chips based on their datasheets. This includes simulation of register functions, memory processing, interrupt control, timing control, and logical judgment functions. During operation, it monitors register and memory operations in real time, acquires different input data, and drives the logic processing of the chip simulation functions based on this input data, further triggering operations such as data transmission and interrupt triggering. It provides an independent instruction set for each chip simulation, controlling data transmission and reception, fault setting, and other functions through this instruction set. After receiving data from the chip library, it saves all data generated during the process to a file and exits.

[0062] (5) Data control module Data protocol transmission timing: Controlling the data transmission time ensures the correctness of data timing and transmission process, and prevents data overflow and data loss.

[0063] Protocol structure judgment: The overall structure of the transmitted data is identified for correctness. If erroneous data is found, transmission will be stopped. The judgment is based on the rule configuration file.

[0064] Protocol correctness assessment: This assesses the correctness of the transmitted data content, including frame headers and frame counts. If erroneous data is detected, transmission will be stopped. The assessment criteria are configured through the rule configuration file.

[0065] Protocol checksum processing: Verification and automatic calculation of transmitted data. If the calculation has been completed, the automatic calculation function is turned off.

[0066] Protocol response control: Automatically identify protocols with response data, obtain the response data content, and send the data; data identification rules, data content, and response time control can be configured through configuration files.

[0067] (6) Interrupt Trigger Module This module integrates all interrupt trigger control and triggering methods, supporting single triggering, random triggering, periodic triggering, low-level triggering, high-level triggering, and level edge triggering. It also allows setting the level recovery time and level hold time; and provides corresponding instructions to drive interrupt triggering.

[0068] (7) Log information recording module This module saves data in TXT files, uniformly recording all communication data between modules. The timing, format, and filename of file recording are controlled by each module. This module provides file writing functionality and a data receiving port; each module sends data to the log information recording module through the data receiving port.

[0069] The data transmission communication type recorded in the log information: Serial Number type illustrate 1 EN_LOGFILE_NAME Set the log file name, passing parameters including the file name and file ID. 2 EN_LOG_PRINT Log file data is printed, and the parameters passed include the file name and the data content, which is formatted. 3 EN_LOG_ISSAVE Log file storage switch, the parameters passed include the file name and the switch flag, 0 for disabling file recording, 1 for enabling file recording. (8) Data parsing module This module receives data packets via a port or network, finds the parsing rules for parsing the data packets based on the ID identifier in the data packets, then unpacks the data packets and displays the converted data in a graphical visualization according to the parsing rules. The displayed results support both pure data display and the display of text after data conversion.

[0070] Data parsing rules are configured via XML files and automatically loaded during initialization. Configuration for different protocols and parsing methods is completed through configuration files, enabling flexible application and rapid adaptation of data parsing.

[0071] The XML file configuration structure elements are shown in the table below: Serial Number element illustrate 1 GRID Start of a set of number analysis 2 Name Data item name settings 3 FLAG A set of data identifiers, unique 4 DATA A set of data item configuration flags 5 Offset Data item offset 6 ValueType Data item display method 7 CodeType Data item encoding type 8 Length Data item byte length 9 DATASELECT Data item optional configuration 10 Bit Data item configuration 11 BITSELECT Data item bit optional configuration 12 Vector Equivalent value of data item 13 Value Data item data value 14 FloatType Data items are configured for floating-point number types. The platform generation process is as follows: The platform generation mainly includes four functions: function library configuration file XML, project file generation, function library generation, and instruction set generation. The flowchart for platform generation is as follows: Figure 2 As shown.

[0072] The function library configuration file (XML) mainly configures relevant library information data such as basic project information, processor information, instruction system library information, chip simulation library information, and memory address operation library information. It also supports configuring the instruction templates, default data settings, and default association settings of the function library.

[0073] The XML configuration elements for basic project information are shown in the table below: Serial Number element illustrate 1 DefaultVal Default settings 2 Name Name settings 3 Value Data values, supports list configuration 4 KeyID The ID value of an element is fixed and immutable. 5 ELE Starting mark for element configuration The processor information XML configuration elements are shown in the table below: Serial Number element illustrate 1 CHIP Starting mark for element configuration 2 Name Name settings 3 ScriptFile Command Template Configuration 4 KeyID The ID value of an element is fixed and immutable. 5 FilePath Processor storage path configuration, supports relative paths 6 Source Processor other attribute configuration file settings 7 ATTRUBUTE Processor attribute configuration flags 8 PIN Processor pin configuration flags 9 VPORT Processor communication port configuration 10 MEMTYPE Memory attribute configuration The XML configuration elements for the functional module library information are shown in the table below: Serial Number element illustrate 1 CHIP Starting mark for element configuration 2 DRIVER Function library configuration flags 3 DATA Data processing library configuration flags 4 Name Name settings 5 ScriptFile Command Template Configuration 6 KeyID The ID value of an element is fixed and immutable. 7 FilePath Processor storage path configuration, supports relative paths 8 Source Processor other attribute configuration file settings 9 ATTRUBUTE Functional module library attribute configuration flags 10 PIN Functional module library pin configuration flags 11 VPORT Functional module library communication port configuration The project file generation function mainly obtains the basic configuration data, functional module configuration information and parameters of the platform requirements, and then generates project files based on the functional module configuration files (XML). The file content includes project name, processor type, memory usage range, functional module name, relationship between functional modules, interrupt trigger settings, and settings for object code file and source code file.

[0074] The function library is generated by automatically finding the function library that meets the requirements based on the function library configuration data of the platform requirements and the function module configuration file XML information, and generating the library in the specified project directory. At the same time, the attribute data configuration parameters of the library are saved, and the association between function libraries is automatically set.

[0075] Instruction set generation mainly involves automatically finding the instruction templates supported by the generated function library, and automatically generating corresponding instruction description files and instruction ID association tables based on the instruction templates and function library IDs. Instruction names are associated with function library configuration names, and different function library names can generate different instruction names.

[0076] The instruction template content format is as follows: Serial Number project illustrate 1 Command Name Command name definition, supports wildcard settings 2 Command ID The ID value of a module is unique. 3 Parameter 1 Command parameter settings are defined by the module developer. 4 Parameter N There are no restrictions on the parameter format; it should be determined based on the actual situation. The command name associations are as follows: Serial Number project illustrate 1 Command Name Instruction name definition, generated based on functional module name 2 ID A unique ID value generated based on the ID value of the functional module is used to identify this project. The parts of this invention not described in detail are well-known to those skilled in the art.

Claims

1. A simulation testing platform, characterized in that, include: The module includes an instruction execution system module, a memory address operation module, a performance statistics module, a chip simulation module, a data control module, an interrupt triggering module, a log information recording module, and a data parsing module. The instruction execution system module loads, parses, sends, receives, and forwards instructions during the operation of the simulation test platform. It receives instruction data streams sent from outside, loads instruction files, and outputs the converted instruction data to the designated module, driving the corresponding module to perform instruction parsing and execution functions. The memory address operation module controls and processes memory address read and write operations, and records the addresses and data of the operations in real time; the memory address operation module receives instruction data from the instruction execution system module and outputs the data stream generated by the address operation to the log information recording module; The performance statistics module performs interval statistics on the execution time of functional items, supporting point-to-point time statistics and same-point time statistics; When the simulation test platform finishes running, it will record performance-related data to a log file. The chip simulation module performs software simulation of the logic functions, characteristics and timing of the chip. Different independent chip simulation libraries are developed for different chips. The data control module receives and sends protocol data streams. The data control module integrates and controls the timing of all data protocol transmissions, protocol structure judgment, protocol correctness judgment, protocol verification and processing, protocol response control, and command parsing and execution. The interrupt triggering module integrates all interrupt triggering controls and triggering methods. The interrupt triggering module receives the instruction data that triggers the interrupt from the instruction execution system module, parses the instruction, and executes it. The log information recording module records the input and output data of other modules during the operation, forming log information; The data parsing module analyzes the entire packet data of the protocol and displays it in a graphical visualization. The data parsing results support both pure data display and the display of text after data translation. The data parsing module records the results of parsing data packets in real time and sends the log data to the log information recording module. The method for generating the simulation test platform includes: Loading configuration file: The configuration file adopts an XML file structure; Obtain project information: Based on the loaded configuration file XML, obtain the basic information, processor information, general function library information, and chip simulation library module of the corresponding project information, and store and manage the above data, and provide interface functions for obtaining configuration file information data; Obtain functional module relationship data: Based on the loaded functional library configuration information XML, obtain the attribute, pin, data interface, relationship and linking method information between functional libraries, and store and manage the data; Data processing based on configuration files: Analyze the input requirements based on the information obtained from the configuration files, obtain processor information, project name, memory usage, interrupt usage, functional interfaces and other functional interfaces, and generate corresponding platform files; Generate basic project and processor information: Based on the data obtained from the configuration file and the requirements project, automatically generate project information, memory data, processor information data and the file under test; Generate basic project files: Create project files based on the generated project information data. The files include processor, memory, source file under test, object code file, and project attribute data. Retrieve function libraries from the container: Based on the analysis and matching of configuration file information and requirement items, obtain the required function libraries, automatically extract the required function libraries and corresponding files from the container, and store them in the specified directory of the project file; Generate function libraries: The function libraries obtained from the container are placed in the specified directory of the project file. Function library information is added to the project file, including library file path, name, attribute data, communication port and supported pin information; The association between the corresponding library and other libraries is obtained by configuring data through the configuration file and link data is automatically generated, including port communication links between function libraries, pin links, function library and processor interrupt pin links and attribute configuration data values. Generate test instructions: The test instruction generator loads the project file and uses the function library IDs in the project file and the instruction IDs and names in the instruction file to generate an instruction description file and a file that maps test instructions to their IDs. Project file loading and execution: After the test platform project file is generated, it is loaded and executed through the fully digital simulation system VTest, and the instruction-driven mechanism is notified to carry out software testing.

2. The simulation testing platform according to claim 1, characterized in that, The memory address operation module monitors one or more addresses within a certain range. When the software operates on an address, it records the data at the operated address to a file in real time.

3. The simulation testing platform according to claim 1, characterized in that, The performance statistics module configures performance statistics attributes according to the instructions of the instruction execution system module, including start address, end address, address operation mode, data start value, data end value, and performance time valid range; where the start address and end address are the same, it indicates that the time interval for statistically analyzing the data operation of the same address is being recorded. After the software finishes running, the performance statistics module automatically calculates the maximum and minimum values ​​of the performance data and outputs the start time of the maximum and minimum values; it automatically determines whether the statistical time is within the valid range and gives an out-of-range warning prompt, and saves the data to the specified txt file.

4. The simulation testing platform according to claim 1, characterized in that, The chip simulation module receives the data stream sent by the data control module through the port, parses and identifies the data stream, and processes the data through the chip control logic; the chip simulation module sends data to the data control module through the port, and the data control module parses and processes the data stream. The structure, transmission process and input data of the sent data are the same.

5. The simulation testing platform according to claim 1, characterized in that, The data control module receives instruction data and protocol data streams through the instruction execution system module, and outputs the processed data to the corresponding chip simulation module. The protocol data received by the chip emulation module is processed and output to the log information recording module; The data control module receives instruction data from the instruction execution system module and output data from the chip simulation module. The instruction execution system module determines the data transmission structure, the chip simulation module determines the output data transmission structure, and the data control module sequentially receives, parses, and processes the data. The data control module sends input stream data to the chip simulation module, unpacks source data to the data parsing module, and sends input and output data to the log information recording module for recording.

6. The simulation testing platform according to claim 1, characterized in that, In the data parsing module, data parsing rules are configured through XML files, and different protocols and parsing methods are configured through configuration files.

7. The simulation testing platform according to claim 1, characterized in that, The configuration file includes project information, processor information, general function library information, chip simulation library and data control module. The XML file also supports configuring the attributes, pins, data interfaces, relationships and linking methods between the various function libraries.

8. The simulation testing platform according to claim 1, characterized in that, The functional library simulates the logic and timing of the corresponding chips, including modules such as instruction execution system, memory address operation, performance statistics, chip simulation, data control, interrupt triggering, log information recording, and data parsing.

9. A simulation testing platform according to claim 1, characterized in that, The loading and running of the project files also includes: instruction-driven support for loading instruction files and scripts, as well as support for test instructions sent by the general automated dynamic testing platform DTP.

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