A multi-chip fusion-based external bus expansion control method and device

Abstract

The application provides a multi-chip fusion-based external bus expansion control method, comprising a host chip, a plurality of slave chips, a master-slave control selection module and an external expansion control bus, wherein the host chip and the plurality of slave chips are connected with the external expansion control bus through the master-slave control selection module; the host chip and the plurality of slave chips are obtained based on multi-chip fusion cutting; the working mode of the host chip is set as a host mode and the working mode of the slave chip is set as a slave mode by outputting a master-slave control signal through the external expansion control bus; and the host chip controls an internal circuit and an external device connected with the slave chip.

Description

Technical Field

[0001] This invention relates to the field of chip control technology, and in particular to an external bus expansion control method and apparatus based on multi-chip fusion. Background Technology

[0002] Generally, one MCU is chosen for each application, and high performance isn't necessary; a mid-to-low-end MCU is sufficient. However, sometimes a single MCU isn't enough, such as insufficient I / O ports, insufficient computing power, or insufficient analog sampling ports. Engineers are accustomed to using a particular MCU, and replacing it with a larger-specification MCU would result in significant costs and time expenditure in development, mass production quality, and product certification cycles. Because of customer needs, manufacturers have a responsibility to develop products that meet those needs. Therefore, how to meet diverse customer requirements efficiently and cost-effectively has become a pressing issue. Summary of the Invention

[0003] To solve the above problems, the present invention is implemented through the following technology:

[0004] On one hand, the present invention provides an external bus expansion control method based on multi-chip fusion, comprising: a host chip, multiple slave chips, a master-slave control selection module and an external expansion control bus, wherein the host chip and the multiple slave chips are connected to the external expansion control bus through the master-slave control selection module;

[0005] The host chip and multiple slave chips are obtained by multi-chip fusion and cutting.

[0006] The external extended control bus outputs master-slave control signals to set the operating mode of the master chip to master mode and the operating mode of the slave chip to slave mode.

[0007] The host chip controls the internal circuitry and the external devices connected to the slave chip.

[0008] In some embodiments, it also includes:

[0009] The addresses of the external devices connected to the slave chip are mapped into the address space of the master chip, so that the master chip can control the external devices connected to the slave chip.

[0010] In some embodiments, controlling the external device connected to the slave chip via the host chip includes:

[0011] The host chip synchronously controls multiple slave chips and external devices with the same function as the slave chips.

[0012] In some embodiments, controlling the external device connected to the slave chip via the host chip includes:

[0013] The host chip can control an external device of one of the slave chips at the same time.

[0014] In some embodiments, it also includes:

[0015] The host chip performs address reading and read / write control on the external devices connected to the slave chip through the external expansion control bus.

[0016] In some embodiments, an external bus expansion control device based on multi-chip fusion includes: a host chip, multiple slave chips, a master-slave control selection module, and an external expansion control bus, wherein the host chip and the multiple slave chips are connected to the external expansion control bus through the master-slave control selection module;

[0017] The cutting module is used to cut a host chip and multiple slave chips based on multi-chip fusion.

[0018] The external expansion control bus is used to output master-slave control signals to set the working mode of the master chip to master mode and the working mode of the slave chip to slave mode;

[0019] The host chip is used to control the internal circuitry and the external devices connected to the slave chip.

[0020] In some embodiments, the external expansion control bus further includes: a mapping module, used for:

[0021] The addresses of the external devices connected to the slave chip are mapped into the address space of the master chip, so that the master chip can control the external devices connected to the slave chip.

[0022] In some embodiments, the host chip is used for:

[0023] The host chip synchronously controls multiple slave chips and external devices with the same function as the slave chips.

[0024] In some embodiments, the host chip is used for:

[0025] The host chip can control an external device of one of the slave chips at the same time.

[0026] In some embodiments, the system further includes: the host chip, configured to perform address reading and read / write control on external devices connected to the slave chip via the external expansion control bus.

[0027] The external bus expansion control method and device based on multi-chip fusion provided by the present invention has at least the following beneficial effects: by expanding the external control bus, the host CPU controls the various functional modules of the slave device, realizing the most difficult synchronization function of multi-chip. It can not only expand various functions, but also realize multi-chip parallel computing, and even high-level security applications such as lockstep computing. Attached Figure Description

[0028] The preferred embodiments will be described below in a clear and easy-to-understand manner, with reference to the accompanying drawings, to further explain the above-mentioned characteristics, technical features, advantages, and implementation methods of an external bus expansion control method and device based on multi-chip fusion.

[0029] Figure 1 This is a schematic diagram of an embodiment of an external bus expansion control method based on multi-chip fusion in this invention;

[0030] Figure 2 This is a schematic diagram of the MCU architecture with an external expansion control bus in this invention;

[0031] Figure 3 This is a schematic diagram of chip cutting using MCU fusion design technology in this invention;

[0032] Figure 4 This is a diagram of the external control bus architecture in this invention;

[0033] Figure 5 This is an equivalent diagram of the multiple chips in this invention after being connected to an external expansion control bus;

[0034] Figure 6 This is an architecture diagram of the extended multiple LCD displays implemented through external bus expansion technology in this invention;

[0035] Figure 7 This is an architecture diagram of the extended multi-motor drive implemented through external bus extension technology in this invention;

[0036] Figure 8 This is an architecture diagram of the extended multi-functional combination expansion achieved through external bus expansion technology in this invention;

[0037] Figure 9 This is a schematic diagram of a multi-chip design with only signal synchronization functionality;

[0038] Figure 10 It is a general MCU architecture, where the CPU can only control the current MCU's bus architecture via the bus. Detailed Implementation

[0039] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0040] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or sets.

[0041] To keep the drawings concise, only the parts relevant to the invention are shown schematically in each figure, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, only one of components with the same structure or function is shown schematically, or only one is labeled. In this document, "one" can mean not only "only one" but also "more than one".

[0042] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0043] Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0045] It should be noted that:

[0046] like Figure 9 , 10 As shown, multi-chip fusion using the technology of this invention can design cost-effective MCUs and MCUs with more functions, that is, using a single chip with digital signal interconnection and analog signal interconnection technology. It can be cut into 8 dies and packaged into 8 low-end MCU products; it can also be cut into 4 dies and packaged into 4 mid-range MCU products; or it can be cut into 2 dies and packaged into 2 high-end MCU products.

[0047] Chips A, B, C, D, E, F, G, and H can be packaged into 8 high-performance products.

[0048] Chips A, B, C, D, E, F, G, and H can be packaged into a high-end product consisting of four chips.

[0049] Chips A, B, E, F and chips C, D, G, H can be packaged into two high-end products;

[0050] In this way, single-core MCU products or multi-core MCU products can be implemented on the same product, or even on the same wafer, while the chip design cost, mask illumination cost, testing cost, and production cost are almost the same.

[0051] In one embodiment, such as Figure 1 As shown, the present invention provides an external bus expansion control method based on multi-chip fusion, including: a host chip, multiple slave chips, a master-slave control selection module, and an external expansion control bus, wherein the host chip and the multiple slave chips are connected to the external expansion control bus through the master-slave control selection module;

[0052] The S101 is based on multi-chip fusion and cutting to obtain a master chip and multiple slave chips.

[0053] Specifically, such as Figure 3 As shown, the final step in multi-chip fusion technology is product finalization during the dicing process. During dicing, the signal lines of the chip's external expansion control bus are cut along the dicing chute, thus completely severing the physical connection of the signals. Finally, packaging is performed. Because of multi-chip fusion technology, the chips that haven't been diced, whether it's a single die or a complete chip with multiple dies, rely on the external expansion control bus for control connections.

[0054] S102 outputs master-slave control signals through the external extended control bus to set the working mode of the master chip to master mode and the working mode of the slave chip to slave mode.

[0055] Specifically, such as Figure 2 As shown, the most crucial element in multi-chip fusion technology is the external expansion control bus. When one MCU selects master MCU mode, all MCUs (this MCU and the others) are controlled by this CPU. In master MCU mode, the CPU controls internal circuits via the internal bus and can also control other MCUs via the external expansion control bus. When other MCUs select slave mode, they relinquish control of their own CPUs and instead use the external expansion control bus to control their own circuits.

[0056] All peripherals of the slave MCU are removed from the control of the slave MCU's CPU, releasing control to the CPU of the master MCU. At this time, all peripherals of the slave MCU are remapped into the address space of the master MCU. Thus, the master MCU controls the peripherals of the slave MCU just as the master MCU controls its own peripherals.

[0057] In the table below, the APB0 address is the peripheral address of the main MCU0, which the CPU can operate on.

[0058] APB1 and APB2 are the peripheral addresses of MCU1 and MCU2, respectively. When MCU1 and MCU2 are set as slave devices, the CPUs of MCU1 and MCU2 lose control of their peripherals. However, the master MCU0 can control the peripherals of MCU1 and MCU2 through different peripheral addresses, just like operating the peripherals of MCU0.

[0059]

[0060]

[0061] S103 controls the internal circuitry and external devices connected to the slave chip via the host chip. The current MCU architecture has remained largely unchanged: the CPU controls the functions of various modules within the MCU to achieve a specific function. This is because older MCUs, such as 8-bit and 16-bit MCUs, lacked sufficient computing power to control additional functional modules. From now on, 32-bit MCUs have become increasingly common, with a growth rate exceeding the combined growth of 8-bit and 16-bit MCUs. In a few more years, the total number of 32-bit MCUs may even surpass the combined total of 8-bit and 16-bit MCUs. Simultaneously, the powerful CPU computing power of 32-bit MCUs, through multi-chip fusion technology and external expansion control buses, greatly increases the possibility of controlling another slave MCU, or even multiple slave MCUs, via the CPU.

[0062] The application environments faced by 32-bit MCUs have also greatly increased. The possibility of a single MCU satisfying all applications will decrease. Without increasing design costs, mask costs, or application development complexity, the opportunity to create a new MCU by cutting and packaging two or more dies will be greatly enhanced. This allows for meeting customer needs in the low-end, mid-range, and high-end markets simultaneously at the lowest cost, thus strengthening the MCU's competitiveness. However, there will not be an unlimited increase in multi-die cutting and packaging, because when two or even four dies are insufficient for an application, a more advanced MCU / MPU will still be chosen for application development.

[0063] In this embodiment, through an external expansion control bus, the host CPU can control the various functional modules of the slave device, realizing the most difficult synchronization function of multi-chips. It can not only expand various functions, but also realize multi-chip parallel computing, and even high-level security applications such as lockstep computing.

[0064] In one embodiment, it also includes:

[0065] The addresses of the external devices connected to the slave chip are mapped into the address space of the master chip, so that the master chip can control the external devices connected to the slave chip.

[0066] In one embodiment, controlling the external device connected to the slave chip via the host chip includes:

[0067] The host chip synchronously controls multiple slave chips and external devices with the same function as the slave chips.

[0068] In one embodiment, controlling the external device connected to the slave chip via the host chip includes:

[0069] The host chip can control an external device of one of the slave chips at the same time.

[0070] In one embodiment, it also includes:

[0071] The host chip performs address reading and read / write control on the external devices connected to the slave chip through the external expansion control bus.

[0072] Specifically, such as Figure 4 The diagram shown is of an external expansion control bus, which includes an address bus (10-bit address, capable of addressing a total of 1024 registers), a data bus (8 / 16 / 32-bit data width), a read / write control module (read / write control), and a master-slave control module (CPU-controlled bus / external expansion control bus-controlled bus).

[0073] The external expansion control bus follows the same design philosophy and control rules as the CPU's internal bus. For example, the external expansion control bus must conform to the AMBA bus rules. Therefore, for slave devices, the external expansion control bus is equivalent to another CPU and can be seamlessly connected. For customer development, the addresses of each functional module are completely identical. The master / slave control can select different slave devices and can be configured to control multiple slave devices simultaneously, writing the same functional modules to different slave devices simultaneously, such as simultaneously starting the timer count of all slave modules or simultaneously controlling the port output of different slave devices to output the same value. It can also be configured so that the master can only control one slave's functional module at a time, similar to single-threaded control of its own functional module. Functional expansion can be achieved through single-MCU packaging, two-MCU packaging, or even multi-core MCU packaging.

[0074] In one embodiment, an external bus expansion control device based on multi-chip fusion includes: a host chip, multiple slave chips, a master-slave control selection module, and an external expansion control bus, wherein the host chip and the multiple slave chips are connected to the external expansion control bus through the master-slave control selection module;

[0075] The cutting module is used to cut a host chip and multiple slave chips based on multi-chip fusion.

[0076] The external expansion control bus is used to output master-slave control signals to set the working mode of the master chip to master mode and the working mode of the slave chip to slave mode.

[0077] The host chip is used to control the internal circuitry and the external devices connected to the slave chip.

[0078] Specifically, MCU architectures with external expansion control buses, such as Figure 2 As shown, Figure 5 The diagram shown represents the equivalent of multiple chips connected via an external expansion control bus. The most crucial element in multi-chip fusion technology is the external expansion control bus. When one MCU selects master mode, all MCUs (this MCU and the others) are controlled by this CPU. In master mode, the CPU controls internal circuits via the internal bus and can also control other MCUs via the external expansion control bus. When other MCUs select slave mode, they relinquish control of their own CPUs and instead use the external expansion control bus to control their own circuits.

[0079] All peripherals of the slave MCU are removed from the control of the slave MCU's CPU, releasing control to the CPU of the master MCU. At this time, all peripherals of the slave MCU are remapped into the address space of the master MCU. Thus, the master MCU controls the peripherals of the slave MCU just as the master MCU controls its own peripherals.

[0080] The current MCU architecture has remained unchanged: the CPU controls the functions of various modules within the MCU to achieve a specific purpose. This is because older MCUs, such as 8-bit and 16-bit MCUs, lacked sufficient computing power to control additional functional modules. However, 32-bit MCUs have emerged, with a growth rate exceeding the combined growth of 8-bit and 16-bit MCUs. In the next few years, the total number of 32-bit MCUs may even surpass the combined total of 8-bit and 16-bit MCUs. Furthermore, the powerful CPU computing power of 32-bit MCUs, coupled with external expansion control buses through multi-chip fusion technology, greatly increases the possibility of controlling another slave MCU, or even multiple slave MCUs, directly from the CPU.

[0081] The application environments faced by 32-bit MCUs have also greatly increased. The possibility of a single MCU satisfying all applications will decrease. Without increasing design costs, mask costs, or application development complexity, the opportunity to create a new MCU by cutting and packaging two or more dies will be greatly enhanced. This allows for meeting customer needs in the low-end, mid-range, and high-end markets simultaneously at the lowest cost, thus strengthening the MCU's competitiveness. However, there will not be an unlimited increase in multi-die cutting and packaging, because when two or even four dies are insufficient for an application, a more advanced MCU / MPU will still be chosen for application development.

[0082] In this embodiment, through an external expansion control bus, the host CPU can control the various functional modules of the slave device, realizing the most difficult synchronization function of multi-chips. It can not only expand various functions, but also realize multi-chip parallel computing, and even high-level security applications such as lockstep computing.

[0083] For example, such as Figure 6The diagram illustrates an architecture for expanding multiple LCD displays using external bus expansion technology. Generally, the LCD driver integrated into an MCU has a fixed number of SEG / COM displays. If a larger number of LCDs is needed, a larger MCU with more pins is typically required, resulting in a larger and more expensive MCU. This not only incurs high chip costs but also necessitates redevelopment for different MCU manufacturers, which is prohibitively expensive. Developing an LCD exceeding the specified specifications using only the same type of MCU requires two MCUs, and synchronization between the chips is necessary, increasing the complexity of MCU application development. Furthermore, achieving synchronized display with two MCUs on one LCD is quite costly. There are three common methods in the industry for implementing this expanded LCD application. The first method involves directly replacing the MCU with another one that has a larger display capacity. Generally, this MCU has higher specifications, meaning the die cost is higher. Expanding the LCD display also requires more pins, significantly increasing the cost of the accompanying MCU packaging. For applications requiring high-capacity displays, especially those using MCUs from different manufacturers, development time and costs increase significantly. The second approach in the industry, using two MCUs of the same type to extend LCD driving technology, is also mature. However, using two conventional MCUs means two dies in two separate packages, increasing MCU costs. The third approach, using two MCU dies in a single package, is also mature and results in a single package, leading to lower costs. However, the two MCUs lack inter-chip connectivity, essentially functioning as two independent MCUs, resulting in higher development time and costs for users.

[0084] In this embodiment, the present invention employs multi-chip fusion technology, using a single die-packaged MCU and bonding wires for signal interconnection. This solves the problem of customers using a single MCU for development, enabling the expansion of LCD displays. The MCU is designed with synchronous interconnection in mind, and the LCD display module is reused, reducing overall cost, development difficulty, and development time.

[0085] The biggest design challenge in multi-chip fusion technology is synchronization. Whether it's the reuse of digital circuits or analog circuits, synchronization is essential. Take lockstep technology in automotive-grade MCUs, for example; it essentially involves multiple cores performing parallel computation, followed by a decision-making core to ensure functional safety.

[0086] In this LCD extension application, to reduce power consumption and peripheral device costs, the LCD bias voltage does not need to be generated by two MCUs simultaneously. If the LCD bias voltage generated by the first MCU is inconsistent with that generated by the second MCU, current backflow will occur, resulting in a large current. Therefore, the LCD bias voltage is generated by the first MCU, and the second MCU only receives the LCD bias voltage generated by the first MCU.

[0087] Because the content is displayed on the same LCD screen, the COM signals of the two MCUs must be synchronized, and their operating frequencies must also be the same; otherwise, the content displayed on the LCD screen will be out of sync. Therefore, the SEG signal, LCD frequency signal, and system clock are provided by the first MCU, while the second MCU passively receives them. Thus, the multiplexing relationship between digital and analog signals must be clearly considered from the initial design stage. The most important aspects are the synchronization relationship of reset, clock, and other signals. These can be generated entirely by one MCU as the master chip, with the others received by slave chips. Alternatively, multiple independent MCUs can be used, with a multi-MCU synchronization handshake mechanism used for synchronization when needed.

[0088] This embodiment solves the problem of producing both high-performance, cost-effective MCUs and high-end MCUs from a single mask. It allows for individual packaging of a single die, packaging of two dies, or even multi-die packaging. This satisfies customer demands in the low-end, mid-range, and high-end markets simultaneously at the lowest cost, enhancing the competitiveness of the MCU.

[0089] For example, such as Figure 7 The diagram shows an architecture for expanding multi-motor drive through external bus expansion technology.

[0090] Generally speaking, a single MCU for driving a single motor doesn't need to be very powerful; a mid-to-low-end MCU is sufficient. However, for driving dual motors, the MCU's performance needs to be significantly improved. This is because the MCU is still single-threaded, and when faced with parallel computing, its time-sharing computing power is clearly insufficient. The required computing power of the MCU needs to be increased not only by doubling, but even by several levels to meet the demands of parallel processing of multiple motors.

[0091] Developing dual-motor applications using only the same type of MCU requires two MCUs and synchronization between them, increasing the complexity of MCU application development. Furthermore, driving two motors simultaneously with two MCUs is quite expensive. There are three common methods in the industry to achieve this multi-motor expansion. The first method involves replacing the MCU with a higher-specification one. Generally, this MCU has higher specifications, meaning the die cost is higher. Expanding the motor driver requires more pins, significantly increasing the cost of the accompanying MCU package. Using a high-capacity display MCU, or even one from a different manufacturer, further increases development time and costs. The second method, using two MCUs of the same type for multi-motor expansion, is now mature. However, using two standard MCUs means two dies in two packages, increasing MCU cost. The third method involves combining two MCU dies into a single package, a mature technology that results in a single package and lower cost. However, the two MCUs lack interconnection between chips, making them similar to two independent MCUs. This results in a relatively high development cycle and cost for users.

[0092] In this embodiment, chip fusion technology refers to the ability to package using a single chip or multiple chips, with synchronous interconnection signals and analog multiplexing technology designed between the multiple chips.

[0093] The biggest design challenge in multi-chip fusion technology is synchronization. Whether it's the reuse of digital circuits or analog circuits, synchronization is essential. Take lockstep technology in automotive-grade MCUs, for example; it essentially involves multiple cores performing parallel computation, followed by a decision-making core to ensure functional safety.

[0094] In the multi-motor drive application of this embodiment, such as a 4-wheel drive toy car model, one motor drives the front wheel and one motor drives the rear wheel. If the two motors cannot be synchronized, with one rotating faster and the other slower, then straight-line movement and turning will be uncontrollable.

[0095] For example, electric vehicles currently use battery packs for power, and the output current is fixed. If the specified output current is exceeded, the battery pack will be damaged, and even the battery life will be severely affected. Therefore, multiple motors need to be driven, strictly adhering to time-sharing requirements. That is, when motor A is working, motor B cannot be driven, and vice versa. This provides overcurrent protection for the battery while ensuring the safe operation of the system. Therefore, the multiplexing relationship between digital and analog signals must be clearly considered from the initial design stage. The most important aspect is the synchronization relationship of reset, clock, and other signals. This can be entirely generated by one chip as the master chip, with the others receiving signals from slave chips. Alternatively, multiple independent MCUs can be used, with a multi-MCU synchronization handshake mechanism used for synchronization when needed.

[0096] This invention utilizes multi-chip fusion technology, solving the problem of enabling customers to expand multi-motor drive capabilities using a single MCU for development. The MCU is designed with synchronous interconnection in mind, and multi-motor drive modules can be reused, reducing overall cost, development difficulty, and development time.

[0097] For example, such as Figure 8 The diagram shows an architecture for expanding multi-functional combinations through external bus expansion technology.

[0098] Generally, one MCU is chosen for each application, and high performance isn't necessary; a mid-to-low-end MCU is sufficient. However, sometimes a single MCU isn't enough, such as insufficient I / O ports, insufficient computing power, or insufficient analog sampling ports. Engineers may be accustomed to using a particular MCU, and replacing it with a larger MCU would significantly increase development time, product mass production quality, and product certification cycles, resulting in substantial costs and time expenditure. Therefore, manufacturers have a responsibility to develop products that meet customer needs.

[0099] Developing functionality beyond the specifications using only one type of MCU requires two MCUs and synchronization between them, increasing the complexity of MCU application development. Furthermore, using two MCUs for expanded functionality is quite expensive. There are three common methods in the industry to achieve this functional expansion. The first method involves directly replacing the MCU with one that has a high-capacity display. Generally, this MCU has higher specifications, meaning the die cost is higher. Expanding the LCD display requires more pins, significantly increasing the cost of the accompanying MCU package. Using an MCU with a high-capacity display, especially from a different manufacturer, further increases the development cycle and costs. For example, if an MCU drives a motor, especially one with a built-in OPA (operational amplifier), each OPA uses three ports. The motor uses three OPAs for current sampling, plus six ports for a three-phase motor, consuming 15 ports. This consumes some of the LCD display ports, preventing customers from observing motor speed and other information on the LCD while the motor is running. So, if a customer needs to both drive the motor and monitor its speed and other status via an LCD, a higher-specification MCU is necessary. The second approach in the industry is to use two MCUs of the same type for application development: one for motor driving and the other for LCD display. This technology is also the most mature. However, using two standard MCUs means two dies in two packages, increasing the MCU cost. The third approach is to use two identical MCU dies in a single package. This technology is also mature, and there's only one package, resulting in lower costs. However, the two MCUs lack inter-chip interconnection, making them essentially two independent MCUs. This increases the development time and costs for users.

[0100] In this embodiment, the biggest design challenge of multi-chip fusion technology is synchronization. Whether it's the reuse of digital circuits or analog circuits, synchronization is essential. Similar to lockstep technology in automotive-grade MCUs, it essentially involves multiple cores performing parallel computation, followed by a decision-making core to ensure functional safety.

[0101] This patent's multi-chip fusion technology enables functional expansion by employing a multi-chip design approach, combined with subsequent cutting, packaging, and testing, to realize single-MCU and multi-MCU products. Within multi-MCU products, functional expansion is achieved at a lower cost. Therefore, the multiplexing relationship between digital and analog signals must be clearly considered from the initial design stage. The most crucial aspect is the synchronization relationship of reset, clock, and other signals. These can be generated entirely by one chip as the master chip, with the others receiving signals from slave chips. Alternatively, multiple independent MCUs can be used, with a multi-MCU synchronization handshake mechanism used for synchronization when needed.

[0102] There are two ways to implement master-slave synchronization, such as... Figure 2 As shown:

[0103] The first master-slave synchronization method: Before the chips are diced from the wafer, we know how many chips need to be diced together. Based on different configurations, we download different bootloaders. For example, chip A downloads the master bootloader, and chip B downloads the slave bootloader. After the system powers on, only chip A's CPU starts; chip B's CPU does not. Simultaneously, chip B's peripheral circuits, such as ADC, GPIO, LCD, and motor drivers, are not controlled by chip B's CPU; they act solely as slave devices of chip A and are controlled only by chip A's CPU. Chip B's clock is connected to chip A's clock, its reset signal is connected to chip A's reset signal, and read / write control is connected to chip A, achieving complete master-slave synchronization. Note that in this method, chip B's CPU never functions; chip A's CPU directly controls chip B's peripheral circuits.

[0104] The second master-slave synchronization method: Although chips A and B are packaged together, they can operate independently. Before master-slave configuration, the peripheral circuits of chip A are controlled by the CPU of chip A, and the peripheral circuits of chip B are controlled by the CPU of chip B. Chips A and B operate independently, and there is no master-slave relationship. When chips A and B are controlled by a user program, they can be configured into a master-slave relationship, for example, configuring chip A as the master and chip B as the slave. Their master-slave synchronization relationship needs to be synchronized by a handshake protocol. For example, if chip A controls the LCD circuit of chip B, chip A will send a request signal. This will cause chip B's CPU to stop controlling the LCD circuit of chip B. At the same time, B will send an ack feedback signal to chip A. After receiving the ack signal, chip A will... Figure 2The external control expansion bus consists of address lines, data lines, read / write control, request control, release control, and ack feedback signals. Therefore, the CPU of chip A can directly control the LCD peripheral circuit of chip B. When the CPU of chip A is reading / writing the LCD peripheral control register of chip B, the CPU of chip B cannot control the LCD peripheral control register of chip B. If the CPU of chip B forcibly accesses the LCD circuit, the hardware will return a bus error signal. After the CPU of chip A configures the LCD circuit of chip B, chip A will send a release control signal to chip B. Upon receiving this release signal, chip B will restore bus control of its LCD circuit to chip B's control and simultaneously return an ack feedback signal to chip A, informing chip A that it has lost control of chip B. At this point, the master-slave relationship is terminated.

[0105] In this embodiment, functional expansion can be achieved through port expansion, computing power expansion, analog sampling expansion, or communication port expansion—in short, any function on the chip can be extended. This can even enable advanced applications such as multi-core lockstep computation and multi-core parallel computation.

[0106] In one embodiment, the external expansion control bus further includes: a mapping module, used for:

[0107] The addresses of the external devices connected to the slave chip are mapped into the address space of the master chip, so that the master chip can control the external devices connected to the slave chip.

[0108] In one embodiment, the host chip is used for:

[0109] The host chip synchronously controls multiple slave chips and external devices with the same function as the slave chips.

[0110] In one embodiment, the host chip is used for:

[0111] The host chip can control an external device of one of the slave chips at the same time.

[0112] In one embodiment, the system further includes: the host chip, configured to perform address reading and read / write control on external devices connected to the slave chip via the external expansion control bus.

[0113] Based on the above embodiments, the parts that are the same as those in the above embodiments will not be described again in this embodiment.

[0114] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of program modules is merely an example. In practical applications, the above functions can be assigned to different program modules as needed, that is, the internal structure of the device can be divided into different program units or modules to complete all or part of the functions described above. The program modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software program unit. Furthermore, the specific names of the program modules are only for easy differentiation and are not intended to limit the scope of protection of this application.

[0115] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0116] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0117] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; the division of modules or units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interface; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0118] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0119] Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The integrated unit described above can be implemented in hardware or as a software functional unit.

[0120] It should be noted that the above embodiments can be freely combined as needed. The above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An external bus expansion control method based on multi-chip fusion, characterized in that, include: The system comprises a master chip, multiple slave chips, a master-slave control selection module, and an external expansion control bus. The master chip and the multiple slave chips are connected to the external expansion control bus via the master-slave control selection module. The external expansion control bus includes a master-slave control module, an address bus, a data bus, and a read / write control module. The host chip and multiple slave chips are obtained by multi-chip fusion and cutting. The external extended control bus outputs master-slave control signals to set the operating mode of the master chip to master mode and the operating mode of the slave chip to slave mode. The addresses of the external devices connected to the slave chip are mapped into the address space of the master chip, so that the master chip can control the external devices connected to the slave chip. The host chip controls the internal circuitry and the external devices connected to the slave chip. The host chip performs address reading and read / write control on the external devices connected to the slave chip through the external expansion control bus.

2. The external bus expansion control method based on multi-chip fusion according to claim 1, characterized in that, The method of controlling the external device connected to the slave chip through the host chip includes: The host chip synchronously controls multiple slave chips and external devices with the same function as the slave chips.

3. The external bus expansion control method based on multi-chip fusion according to claim 1, characterized in that, The method of controlling the external device connected to the slave chip through the host chip includes: The host chip can control an external device of one of the slave chips at the same time.

4. An external bus expansion control device based on multi-chip fusion, characterized in that, include: The system includes a master chip, multiple slave chips, a master-slave control selection module, and an external expansion control bus. The master chip and the multiple slave chips are connected to the external expansion control bus through the master-slave control selection module. The cutting module is used to cut a host chip and multiple slave chips based on multi-chip fusion. The mapping module is used to map the address of the external device connected to the slave chip to the address space of the master chip, so that the master chip can control the external device connected to the slave chip. The external expansion control bus is used to output master-slave control signals to set the working mode of the master chip to master mode and the working mode of the slave chip to slave mode; The host chip is used to control the internal circuitry and the external devices connected to the slave chip; The host chip is also used to perform address reading and read / write control on the external devices connected to the slave chip via the external expansion control bus.

5. The external bus expansion control device based on multi-chip fusion according to claim 4, characterized in that, The host chip is used for: The host chip synchronously controls multiple slave chips and external devices with the same function as the slave chips.

6. The external bus expansion control device based on multi-chip fusion according to claim 4, characterized in that, The host chip is used for: The host chip can control an external device of one of the slave chips at the same time.

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