A layout wiring method of a resistance string in a chip and the chip

Abstract

A chip resistor string layout wiring method and chip, characterized in that, the method comprises the following steps: step 1, obtain the resistance parameter of the DAC module in the chip design circuit, and generate the resistance matching mode in the resistance string based on the resistance parameter; step 2, based on the resistance matching mode, obtain the layout position of the through hole between the first metal layer and the second metal layer in the layout, and the number of the first metal line; step 3, according to the layout size of the DAC module resistance string area in the chip, the number of the first metal line and the manufacturing process of the chip, the selection of the first metal line width is realized, and the corresponding number and width of the first metal line is arranged in the form of transverse through above the resistance. The present application is effective and reliable, greatly improves the high-precision chip pass rate in the chip production and manufacturing process, generally improves the output precision of the chip, and does not need to increase the additional cost, and will not change the existing layout design of the chip, low cost, small cost.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more specifically, to a layout routing method for resistor strings in a chip and the chip thereof. Background Technology

[0002] Currently, the layout and routing of chips significantly impact their actual performance. In some high-precision chips, the layout and routing method severely affects the chip's output performance. This is especially true for chips with a large number of resistors. When the voltage divider of the resistor taps in the resistor string is connected to other modules in the chip circuit, the metal wires connecting the voltage divider may generate significant resistance, greatly affecting the actual tap voltage of the resistor string, and thus further impacting the overall output performance of the chip.

[0003] On the other hand, the output characteristics of the chip are also affected by the well edge effect (WPE), the thermal and stress gradients at different locations in the chip, and various uncontrollable factors during the manufacturing process, which result in various output deviations in the actual mass-produced chips.

[0004] However, for high-precision chips, output accuracy is crucial. For example, in chips containing digital-to-analog converters (DACs), resistor strings are used extensively, and some chips require the DAC output voltage accuracy to be maintained within ±0.4%. When various influencing factors arise, it becomes difficult to mass-produce high-precision chips containing DAC modules.

[0005] To address this problem, there is an urgent need for a layout routing method for resistor strings in chips. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a layout routing method for resistor strings in a chip. By obtaining the resistor parameters in the chip and generating a resistor matching mode, the width and number of the first metal lines are calculated to generate a high-precision resistor string layout routing mode.

[0007] The present invention adopts the following technical solution.

[0008] The first aspect of the present invention relates to a layout routing method for resistor strings in a chip, the method comprising the following steps: Step 1, obtaining the resistance parameters of the DAC module in the chip design circuit, and generating a resistance matching mode in the resistor string based on the resistance parameters; Step 2, obtaining the placement position of the via between the first metal layer and the second metal layer in the layout, and the number of first metal lines in the first metal layer based on the resistance matching mode; Step 3, selecting the width of the first metal lines according to the layout size of the resistor string area of ​​the DAC module in the chip, the number of first metal lines, and the chip manufacturing process, and laying out a corresponding number and width of metal lines for laying the first metal lines in a horizontally penetrating manner above the resistors.

[0009] Preferably, the resistance parameters include the number of resistors in the chip, the resistance length of each resistor, and the width.

[0010] Preferably, the resistor matching method includes the first and last positions of each resistor in the resistor string.

[0011] Preferably, the metal lines in the first metal layer are horizontal metal lines, which are perpendicular to the direction of the poly resistors in the resistor string; the metal lines in the second metal layer are vertical metal lines, which are parallel to the direction of the poly resistors in the resistor string.

[0012] Preferably, the beginning and end of each first metal line in the first metal layer are located on a through hole; the beginning of each second metal line in the second metal layer is led out from the beginning of the resistor string corresponding to the second metal line, and the end is located on a through hole to achieve connection with the first metal line.

[0013] Preferably, the shortest spacing between two adjacent first metal lines is determined based on the chip manufacturing process; and the width of the first metal line is calculated based on the shortest spacing, the layout size of the resistor string region, and the number of first metal lines.

[0014] Preferably, the layout of each first metal line in the first metal layer is arranged such that the spacing between each first metal line is equal and they run parallel through the resistor string region.

[0015] Preferably, the resistor string region includes the region where each resistor in the resistor string is located, excluding the portion where the first and second connections between each resistor are made.

[0016] A second aspect of the present invention relates to a chip including a DAC module, wherein the resistor string in the DAC module is implemented using the layout routing method for resistor strings in a chip according to the first aspect of the present invention to implement the routing of the first metal line.

[0017] The beneficial effects of this invention are that, compared with the prior art, the layout routing method for resistor strings in a chip according to this invention obtains the resistance parameters of the DAC module in the chip, generates a resistance matching mode, and then calculates the width and number of the first metal lines to generate a high-precision resistor string layout routing mode. This invention is effective and reliable, significantly improving the high-precision chip yield rate in the chip manufacturing process, generally improving the output accuracy of chips, and requiring no additional cost, without changing the existing layout design of the chip, thus being low-cost and inexpensive. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the resistor string portion in a chip containing a DAC module in the prior art;

[0019] Figure 2 This is a diagram of the chip output voltage in a chip containing a DAC module in the prior art.

[0020] Figure 3 This is a schematic diagram of the layout routing method for resistor strings in a chip according to the present invention.

[0021] Figure 4 This is a chip output voltage curve diagram in the layout routing method of resistor strings in a chip according to the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of this invention. The embodiments described in this application are merely some embodiments of this invention, and not all embodiments. Based on the spirit of this invention, other embodiments obtained by those skilled in the art without creative effort are all within the protection scope of this invention.

[0023] Figure 1 This is a schematic diagram of the resistor string portion in a chip containing a DAC module, based on existing technology. Figure 1 As shown, this invention uses a chip containing a DAC module as an example to illustrate the improvement of the layout of the resistor string portion in the chip in the method of this invention.

[0024] first, Figure 1 This includes multiple resistors arranged at equal intervals horizontally but vertically as a whole, ranging from R0 to R31. These resistors are connected end-to-end. Additionally, depending on the actual requirements of the chip... Figure 1The existing technology uses a first and second metal wire design to implement resistor taps, thus providing resistors of various resistance values ​​for the chip design circuit. A drawback of the existing technology is that the metal wires are not precisely calculated and are simply connected using the thinnest possible metal wires. Furthermore, the metal distribution on each resistor is uneven, and the stress gradient has varying effects on the resistance value.

[0025] Specifically, in this diagram, there are seven first metal lines, indicated by horizontal red lines, all of which can be implemented within the first metal layer. Additionally, multiple vertical metal lines can be implemented within the second metal layer, their actual positions arranged between multiple resistor strings, with their starting ends connected to the starting ends of individual resistor strings.

[0026] The first metal wire and the second metal wire can be connected through a through hole.

[0027] Figure 1 The wiring method described herein can actually be implemented based on the resistor matching method in the prior art. Since it does not involve the specific improvements in this invention, this invention will not discuss the specific resistor matching method in detail.

[0028] Figure 2 This is a graph showing the chip output voltage of a chip containing a DAC module in the prior art. Figure 1 In the embodiment shown, the output voltage curve of the chip was acquired. The output voltage stabilized at 1.0574V after the chip was powered on, and the chip's accuracy deviation was 0.1325%.

[0029] The accuracy deviation of the chip in this invention is obtained based on the deviation between the simulated value and the theoretical value, and the theoretical output voltage of the chip is 1.056V. Additionally, the resistance R = ρL / S. Here, ρ represents the resistivity of the resistor, which is determined by its inherent properties; L represents the length of the resistor; and S represents the cross-sectional area of ​​the resistor. All of these can be used to design the starting and ending positions of the first and second metal lines, as well as the positions of vias, in the layout design.

[0030] To improve the output accuracy of this chip, the present invention provides the following technical solution.

[0031] Figure 3 This is a schematic diagram of the layout routing method for resistor strings in a chip according to the present invention. Figure 3 As shown, the first aspect of the present invention relates to a layout routing method for resistor strings in a chip, the method comprising steps 1 to 3.

[0032] Step 1: Obtain the resistor parameters of the DAC module in the chip design circuit, and generate the resistor matching method in the resistor string based on the resistor parameters.

[0033] It is understood that the present invention can refer to methods in the prior art to implement specific resistance matching methods in the resistor string region.

[0034] Specifically, resistor parameters include the number of resistors in the chip, the length and width of each resistor. Resistor matching methods include the beginning and end positions of each resistor in the resistor string.

[0035] Based on existing methods, and considering the effects of stress and temperature at different locations within the resistor string region, as well as the influence of edge and center positions on resistance values, this invention designs the actual position of each resistor within the resistor string region by determining the number of resistors required for the chip and the resistance value of each resistor. Using this actual position, this invention can determine the connection and arrangement of each metal wire.

[0036] Step 2: Based on the resistance matching method, obtain the layout position of the vias between the first metal layer and the second metal layer in the layout, as well as the number of the first metal lines.

[0037] Preferably, the metal lines in the first metal layer are horizontal metal lines, which are perpendicular to the direction of the poly resistors in the resistor string; the metal lines in the second metal layer are vertical metal lines, which are parallel to the direction of the poly resistors in the resistor string.

[0038] Preferably, the beginning and end of each first metal line in the first metal layer are located on a through hole; the beginning of each second metal line in the second metal layer is led out from the beginning of the resistor string corresponding to the second metal line, and the end is located on a through hole, so as to achieve connection with the first metal line.

[0039] In this invention, each resistor is connected to other components of the chip in a standardized manner, and this connection is achieved through a first metal line and a second metal line. The first and second metal lines are connected through vias between the first and second metal layers, respectively. Furthermore, the first metal line is arranged horizontally, and the second metal line is arranged vertically, with its ends connected to the vias or the beginning of the resistor. This design makes the metal layer layout standardized and clear, and this invention further improves upon this design by refining the metal lines.

[0040] Understandably, because resistor matching requires that the actual start and end positions of each resistor be different, the lengths of the metal wires connecting to the start and end of the resistors will also differ. If the metal wires are too thin, it may cause significant errors in the resistance values ​​of the resistors actually connected to other components on the chip. Conversely, if the metal wires are designed to be too wide, it may result in an unsightly layout or make the layout impossible to implement.

[0041] To address the aforementioned problems, the present invention calculates the number of wires that need to be routed above the resistors based on the resistor matching order and the number of resistors. Then, based on the resistor size and the required number of wires, the width of the first metal wire is calculated, and the metal wire is widened to the maximum extent possible, thereby achieving the goal of reducing the wire resistance.

[0042] Step 3: Select the width of the first metal line according to the layout size of the resistor string area of ​​the DAC module in the chip, the number of the first metal lines and the chip manufacturing process, and lay out the corresponding number and width of the first metal lines in a horizontal through-line manner above the resistor.

[0043] In this invention, the shortest interval between two adjacent first metal lines is determined based on the chip manufacturing process; and the width of the first metal line is calculated based on the shortest interval, the layout size of the resistor string region, and the number of first metal lines.

[0044] Specifically, this invention can first measure the dimensions of the resistor string region, such as its longitudinal width. To ensure process implementation, this invention requires that the spacing between two adjacent first metal lines exceed the minimum requirements of the process manufacturing design. For example, if the process requires 0.23µm, the shortest spacing used in actual layout drawing is 0.38µm.

[0045] By using the shortest distance as the interval between any two adjacent metal lines and the longitudinal width of the resistor string region as the maximum width, the width of the metal lines can be calculated. This method ensures that the width of each first metal line is maximized without compromising existing manufacturing requirements, minimizing the impact of the metal lines on the resistance value of the resistor string and improving the chip's output accuracy.

[0046] Preferably, the layout of each first metal line in the first metal layer is arranged such that the spacing between each first metal line is equal and they run parallel through the resistor string region.

[0047] Meanwhile, the present invention extends the line above the resistor from left to right through the entire resistor, which ensures that the stress on each resistor is the same and the overall layout looks very aesthetically pleasing. This not only ensures the matching of resistors, but also reduces the impact of different stresses on the resistance value.

[0048] Preferably, the resistor string region includes the region where each resistor in the resistor string is located, excluding the portion where the first and second connections between each resistor are made.

[0049] As shown in the figure, in order to prevent interference, the position of the first metal wire in this invention will not exceed the position where the resistor string is connected end to end.

[0050] Figure 4 This is a diagram showing the chip output voltage curve in the layout routing method for resistor strings in a chip according to the present invention. Figure 4 As shown, the experimental output of the chip after this wiring scheme is 1.05688V with an accuracy of 0.0833%. Although both wiring schemes meet the requirements, the second wiring scheme is more accurate.

[0051] Specifically, since the chip's output accuracy is affected by reliability testing, temperature testing, and aging testing, the lower the proportion of post-layout simulation accuracy, the more margin is left for other modules and tests in the system. Therefore, the proportion of chip output accuracy in this part of the calculation process in this invention should be reduced as much as possible, that is, the lower the accuracy, the better.

[0052] Furthermore, if some chips require a small number of resistors and have short resistor lengths, the overall size of the resistor string region may be too small. This results in insufficient width of multiple metal lines. In this case, a staggered routing method between the metal lines in the first metal layer and the metal lines in the third metal layer can also be considered to reduce line resistance. The third metal layer can be an additional metal layer in the chip, distinct from the first and second metal layers, used to share the routing burden of the first or second metal layers.

[0053] As the digital-to-analog conversion bit depth of a DAC chip increases, the number of resistors required in the chip typically increases. However, the size of the resistor string area may not necessarily increase accordingly, but it does place higher demands on the chip's output accuracy. In this case, this staggered routing method can be considered, making the routing advantages more apparent.

[0054] A second aspect of the present invention relates to a chip including a DAC module, wherein the resistor string in the DAC module is implemented using the layout routing method for resistor strings in a chip according to the first aspect of the present invention to implement the routing of the first metal line.

[0055] The beneficial effects of this invention are that, compared with the prior art, the layout routing method for resistor strings in a chip according to this invention obtains the resistance parameters in the chip, generates a resistance matching mode, and then calculates the width and number of the first metal lines to generate a high-precision resistor string layout routing mode. This invention is effective and reliable, significantly improving the high-precision chip yield rate in the chip manufacturing process, generally improving the output accuracy of chips, and requiring no additional cost, without changing the existing chip layout design; it is low-cost and inexpensive.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A layout routing method for resistor strings in a chip, characterized in that, The method includes the following steps: Step 1: Obtain the resistance parameters of the DAC module in the chip design circuit, and generate the resistance matching mode in the resistor string based on the resistance parameters; Step 2: Based on the resistance matching method, obtain the layout position of the via between the first metal layer and the second metal layer in the layout, and the number of first metal lines in the first metal layer; The metal wires in the first metal layer are horizontal metal wires, which are perpendicular to the direction of the poly resistors in the resistor string; the metal wires in the second metal layer are vertical metal wires, which are parallel to the direction of the poly resistors in the resistor string; the beginning and end of each first metal wire in the first metal layer are located on the via; the beginning of each second metal wire in the second metal layer is led out from the beginning of the resistor string corresponding to the second metal wire, and the end is located on the via, so as to achieve connection with the first metal wire; Step 3: Select the width of the first metal line according to the layout size of the resistor string area of ​​the DAC module in the chip, the number of the first metal lines and the manufacturing process of the chip, and lay out the corresponding number and width of metal lines for laying the first metal lines in a horizontal through-type manner above the resistor.

2. The layout routing method for resistor strings in a chip according to claim 1, characterized in that: The resistance parameters include the number of resistors in the chip, the length of each resistor, and its width.

3. The layout routing method for resistor strings in a chip according to claim 2, characterized in that: The resistor matching method includes the first and last positions of each resistor in the resistor string.

4. The layout routing method for resistor strings in a chip according to claim 1, characterized in that: The shortest interval between two adjacent first metal lines is determined based on the chip's manufacturing process. The width of the first metal line is calculated based on the shortest interval distance, the layout size of the resistor string region, and the number of the first metal lines.

5. The layout routing method for resistor strings in a chip according to claim 4, characterized in that: The first metal layer has a layout in which the spacing between each first metal line is equal and they run parallel through the resistor string region.

6. The layout routing method for resistor strings in a chip according to claim 5, characterized in that: The resistor string region includes the region where each resistor in the resistor string is located, excluding the portion where the first and second resistors are connected.

7. A chip, characterized in that: The chip includes a DAC module, and the resistor string in the DAC module is routed using a layout routing method for resistor strings in a chip as described in any one of claims 1-6 to route the first metal line.

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