Storage system and method for multi-cell mapping

Abstract

A memory system is provided having a memory having memory cells that can store a number of states that is not a power of two. A mapping is used to allocate data bits in the memory. The mapping can be a modified version of a quadrature amplitude modulation (QAM) mapping. The mapping can be done by a controller in the memory system or by the memory die. Performing the mapping in the memory die can reduce data communication between the controller and the memory die, which can improve performance and power consumption.

Description

Background Technology

[0001] As more and more digital data is generated in daily life, there is a need to increase the storage capacity of memory in storage systems. One way to increase storage capacity is by increasing the number of physical memory cells per given region on the memory die (“physical scaling”). Another way is by increasing the number of states or levels that can be stored in a memory cell (“logical scaling”). Logical scaling, which increases the total number of information bits per memory cell, can be accomplished by combining physical scaling with logical scaling. Attached Figure Description

[0002] Figure 1A This is a block diagram of a non-volatile storage system implementation plan.

[0003] Figure 1B This is a block diagram illustrating a storage module in one implementation scheme.

[0004] Figure 1C This is a block diagram illustrating a hierarchical storage system implementation.

[0005] Figure 2A This illustrates an implementation scheme. Figure 1A The diagram shows a block diagram of the components of the controller for a non-volatile memory system.

[0006] Figure 2B This illustrates an implementation scheme. Figure 1A The diagram shows the components of a non-volatile memory system.

[0007] Figure 3 This is a block diagram of the host and storage system of an implementation scheme.

[0008] Figure 4 This is a diagram illustrating an example implementation of the bit depth and window noise ratio for each cell.

[0009] Figure 5 It is a diagram of the quadrature amplitude modulation (QAM) mapping of an implementation scheme.

[0010] Figure 6A and Figure 6B This is a diagram illustrating the process of modifying the QAM mapping to perform a non-power-of-two mapping.

[0011] Figure 7 This is a graph of the modified QAM mapping used for implementations of non-power-of-2 mappings.

[0012] Figure 8A and Figure 8B This is a diagram of a modified QAM mapping for an implementation scheme of alternating state shaping.

[0013] Figure 9A This is a block diagram of an implementation where the mapper and demapper are located in the controller of the storage system.

[0014] Figure 9B This is a block diagram of an implementation scheme where the mapper and demapper are located in the memory die of the storage system. Detailed Implementation

[0015] The following embodiments generally relate to memory systems and methods for multi-cell mapping. In one embodiment, a memory system is presented, including a memory die and a controller configured to provide data to the memory die for storage. The memory die includes a plurality of memory cells, each memory cell configured to store a state number that is not a power of 2. The memory die is further configured to determine the location for storing data in the plurality of memory cells using a non-power-of-2 mapping; and to write the data into the plurality of memory cells determined by the mapping. In another embodiment, a method is provided, comprising receiving a plurality of data bits to be stored in a memory die; mapping the plurality of data bits to the plurality of memory cells using a non-power-of-2 mapping; and storing the plurality of data bits in the plurality of memory cells in the memory die according to the mapping. In yet another embodiment, a memory system is provided, including a memory die and means for mapping a plurality of data bits to a plurality of memory cells using a non-power-of-2 mapping, the memory die including a plurality of memory cells, each memory cell configured to store a state number that is not a power of 2. Other implementation schemes are provided, and these implementation schemes can be used individually or in combination.

[0016] Now turn to the attached image. Figures 1A-1C Storage systems suitable for implementing these implementation schemes are shown. Figure 1A This is a block diagram illustrating a non-volatile storage system 100 (sometimes referred to herein as a storage device or simply a device) according to one embodiment of the subject matter described herein. Reference Figure 1A The nonvolatile memory system 100 includes a controller 102 and nonvolatile memory that may be composed of one or more nonvolatile memory dies 104. As described herein, the term die refers to a collection of nonvolatile memory cells formed on a single semiconductor substrate, and the associated circuitry for managing the physical operations of those nonvolatile memory cells. The controller 102 interacts with a host system and transmits sequences of commands for read, program, and erase operations to the nonvolatile memory die 104.

[0017] Controller 102 (which may be a non-volatile memory controller (e.g., flash memory, resistive random access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random access memory (MRAM) controller)) may take the form of, for example, processing circuitry, a microprocessor or processor, and a computer-readable medium storing computer-readable program code (e.g., firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Controller 102 may be configured with hardware and / or firmware to perform the various functions described below and shown in the flowcharts. Additionally, some components shown as internal to the controller may also be stored external to the controller, and other components may be used. Furthermore, the phrase "operationally communicating with..." may mean communicating directly or indirectly (wired or wirelessly) with one or more components, or communicating through one or more components, which may or may not be shown herein.

[0018] As used herein, a nonvolatile memory controller is a device that manages data stored on nonvolatile memory and communicates with a host device such as a computer or electronic device. In addition to the specific functions described herein, a nonvolatile memory controller can have various functions. For example, a nonvolatile memory controller can format the nonvolatile memory to ensure that the memory is operating correctly, identify bad nonvolatile memory cells, and allocate spare cells to replace future failed cells. Some portions of the spare cells can be used to house firmware to operate the nonvolatile memory controller and implement other features. In operation, when the host needs to read data from or write data to the nonvolatile memory, it can communicate with the nonvolatile memory controller. If the host provides a logical address to read / write data, the nonvolatile memory controller can translate the logical address received from the host into a physical address in the nonvolatile memory. (Alternatively, the host may provide a physical address.) The non-volatile memory controller may also perform various memory management functions, such as, but not limited to, wear-leveling (allocating writes to specific blocks of memory cells to avoid wear that would otherwise be repeatedly written to) and garbage collection (moving only valid data pages to a new block after a block is full, so that the entire block can be erased and reused). Additionally, the structure used for the “means” described in the claims may include some or all of the structures of the controller described herein, such that these structures are appropriately programmed or manufactured such that the controller operates to perform the functions described herein.

[0019] The non-volatile memory die 104 may include any suitable non-volatile memory medium, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells. The memory cells may be in the form of solid-state (e.g., flash) memory cells and may be programmable once, programmable multiple times, or programmable many times. The memory cells may also be single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), or other memory cell-level technologies known now or developed thereafter. Furthermore, the memory cells may be manufactured in a two-dimensional or three-dimensional manner.

[0020] The interface located between the controller 102 and the non-volatile memory die 104 can be any suitable flash memory interface, such as switching modes 200, 400, or 800. In one embodiment, the storage system 100 can be a card-based system, such as a Secure Digital Card (SD) or a Micro Secure Digital (Micro SD) card (or USB, SSD, etc.). In an alternative embodiment, the storage system 100 can be part of an embedded storage system.

[0021] Although Figure 1A In the example shown, the non-volatile memory system 100 (sometimes referred to herein as a memory module) includes a single channel between the controller 102 and the non-volatile memory die 104; however, the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures (such as...) Figure 1B and Figure 1C As shown in the architecture, there can be two, four, eight, or more memory channels between the controller and the memory device, depending on the controller's capabilities. In any of the embodiments described herein, even if a single channel is shown in the figures, there can be more than one single channel between the controller and the memory die.

[0022] Figure 1B A storage module 200 comprising multiple non-volatile storage systems 100 is illustrated. Similarly, the storage module 200 may include a storage controller 202 that interacts with a host and a storage system 204 comprising the multiple non-volatile storage systems 100. The interface between the storage controller 202 and the non-volatile storage systems 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA), a Peripheral Component Rapid Interconnect (PCIe) interface, or a Double Data Rate (DDR) interface. In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), such as those found in server PCs or portable computing devices such as laptops and tablets.

[0023] Figure 1CThis is a block diagram illustrating a hierarchical storage system. The hierarchical storage system 250 includes a plurality of storage controllers 202, each of which controls a corresponding storage system 204. A host system 252 can access memory within the storage system via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Fast (NVMe) or Fibre Channel Ethernet (FCoE) interface. In one embodiment, Figure 1C The system shown can be a rack-mountable mass storage system that can be accessed by multiple host computers, such as in a data center or other locations where mass storage is required.

[0024] Figure 2A This is a block diagram illustrating exemplary components of controller 102 in more detail. Controller 102 includes a front-end module 108 that interacts with a host, a back-end module 110 that interacts with one or more non-volatile memory dies 104, and various other modules that perform the functions now described in detail. Modules may take the form of, for example, packaged functional hardware units designed for use in conjunction with other components, portions of program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry that typically performs a specific function of the associated functionality, or stand-alone hardware or software components that interact with a larger system. Controller 102 may sometimes be referred to herein as a NAND controller or flash memory controller, but it should be understood that controller 102 can be used with any suitable memory technology, some of which are exemplified below.

[0025] Referring again to the module of controller 102, the buffer management / bus controller 114 manages the buffers in random access memory (RAM) 116 and controls the internal bus arbitration of controller 102. Read-only memory (ROM) 118 stores the system boot code. Although Figure 2A The RAM 116 and ROM 118 are shown positioned separately from the controller 102, but in other embodiments, one or both of them may be located within the controller. In yet another embodiment, portions of the RAM and ROM may be located both inside and outside the controller 102.

[0026] Front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provides an electrical interface to the host or next-level storage controller. The type of host interface 120 may be selected depending on the type of memory used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, Serial Attached Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. Host interface 120 is typically used for transmitting data, control signals, and timing signals.

[0027] Back-end module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and error-corrects data bytes read from non-volatile memory. Command sequencer 126 generates command sequences, such as programming and erasing command sequences, to be transmitted to non-volatile memory die 104. RAID (Redundant Array of Independent Drives) module 128 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to memory device 104. In some cases, RAID module 128 may be part of ECC engine 124. Memory interface 130 provides command sequences to and receives status information from non-volatile memory die 104. In one embodiment, memory interface 130 may be a double data rate (DDR) interface, such as a switching mode 200, 400, or 800 interface. Flash control layer 132 controls the overall operation of back-end module 110.

[0028] Storage system 100 also includes other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interact with controller 102. In alternative embodiments, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller 114 are optional components that are not required in controller 102.

[0029] Figure 2B This is a block diagram showing the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells for storing data. The non-volatile memory cells can be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 also includes a data cache 156 for caching data. The peripheral circuitry 141 includes a state machine 152 that provides status information to the controller 102.

[0030] Return again Figure 2AThe flash control layer 132 (which will be referred to herein as the flash translation layer (FTL), or more generally as the "media management layer," since the memory may not be flash) handles flash errors and interacts with the host. Specifically, the FTL (which may be an algorithm in the firmware) is responsible for the internal memory management and translates writes from the host into writes to the memory die 104. An FTL may be necessary because the memory die 104 may have limited endurance, may only have a few pages written, and / or may not have any writes (unless it is erased as a block of memory cells). The FTL understands these potential limitations of the memory die 104, which may not be visible to the host. Therefore, the FTL attempts to translate writes from the host into writes to the memory die 104.

[0031] The FTL may include a logical-to-physical address (L2P) mapping (sometimes referred to herein as a table or data structure) and allocated cache memory. In this way, the FTL translates logical block addresses (“LBAs”) from the host into physical addresses in memory die 104. The FTL may include other features such as, but not limited to, power-down recovery (enabling the FTL’s data structures to recover in the event of a sudden power loss) and wear leveling (ensuring wear is evenly distributed across memory blocks to prevent some blocks from becoming excessively worn, which would lead to a greater chance of failure).

[0032] Please refer to the attached diagram again. Figure 3 This is a block diagram of a host 300 and a storage system (sometimes referred to herein as a device) 100 according to one embodiment. The host 300 may take any suitable form, including but not limited to a computer, mobile phone, digital camera, tablet computer, wearable device, digital video recorder, surveillance system, etc. The host 300 includes a processor 330 configured to send data (e.g., initially stored in the host's memory 340 (e.g., DRAM)) to the storage system 100 for storage in the storage system's memory die 104 (e.g., a non-volatile memory die). While the host 300 and storage system 100 are... Figure 3 The memory system 100 is shown as a separate box, but it should be noted that the storage system 100 may be integrated into the host 300, the storage system 100 may be removably connected to the host 300, and the storage system 100 and the host 300 may communicate over a network. It should also be noted that the memory die 104 may be integrated into the storage system 100 or removably connected to the storage system 100.

[0033] As mentioned above, with the increasing generation of digital data in daily life, there is a need to increase the storage capacity of memory in storage systems. One way to increase storage capacity is by increasing the number of physical memory cells per given region on the memory die (“physical scaling”). Another way is by increasing the number of states or levels that can be stored in a memory cell (“logical scaling”). Logical scaling, which increases the total number of information bits per memory cell, can be accomplished by combining physical scaling with logical scaling.

[0034] Current X4 memory uses four physical bits per cell, 16 voltage levels, and even with additional bits for error correction code (ECC) parity checking, achieves fewer than four information bits per cell. However, from an information theory perspective, given the window noise ratio (W / N) of achievable memory dies, higher logic densities between four and five information bits per cell are possible, requiring more than four physical bits per cell. This is in... Figure 4 As shown in the image.

[0035] One approach to increasing logic scaling is to provide X5 memory with five physical bits and 32 voltage levels per cell. However, using 32 levels can significantly reduce programming speed, and the amount of communication to the memory die can be much higher, leading to reduced performance and increased power consumption. A better approach could be to use X4.5 with 23 voltage levels, which is equivalent to 4.52 physical bits per cell. However, mapping programming data to 23 voltage levels presents a new challenge.

[0036] The following implementations can be used to map data to adjacent (or non-adjacent) memory cells with voltage level numbers that are not powers of 2. The example below uses 2^3 as a non-power of 2 number, but it should be understood that this is merely an example and other non-powers of 2 numbers can be used. As will be discussed in more detail below, these implementations support non-powers of 2 number of states, which keeps the mapper / demapper simple and easy to implement while maintaining ECC properties that minimize logical errors caused by any physical faults. Additionally, these implementations provide the desired state shaping properties that reduce the use of high-voltage states, thus reducing wear and interference effects in memory die 104. These techniques can be performed in controller 102 or in memory die 104. When these techniques are performed in memory die 104, CMOS bonded array (CbA) technology can be used. In CbA technology, a control die (sometimes called a CMOS logic unit) is integrated into the memory die and performs control functions related to the data stored on that memory die, so that the data stored on that memory die does not need to be passed to the main memory controller die for manipulation or updating, and then transferred back to the memory die. Using memory die 104 to perform mapping can significantly improve the performance of the memory system 100 by reducing controller-memory die communication (e.g., in one embodiment, an improvement of approximately 11% because 4.5 bits are transferred per cell before mapping, and 5 bits are transferred per cell after mapping).

[0037] In one example implementation, controller 102 or memory die 104 uses a two-dimensional mapping method with a series of powers other than 2 to map each vector of input bits to two physical memory cells. The mapping used in this example minimizes the amount of logical errors caused by the most common physical errors (i.e., reading states adjacent to programmed states) and has a relatively simple implementation that reduces power consumption.

[0038] The mapping used in this example is a modified version of the quadrature amplitude modulation (QAM) mapping. Figure 5 This is an illustration of an example of a QAM mapping that can be used to map voltage levels to powers of 2. In one implementation, the QAM mapping is modified to be used with non-powers of 2 state numbers by performing various reflections and transformations on the basic, smaller QAM mapping.

[0039] More specifically, such as Figure 6A and Figure 6BAs shown, in one implementation, a smaller QAM map is modified to reflect half of it on its edges to obtain a new, larger constellation. The outer symbols are then removed and moved to the top right corner. The constellation is increased by reflection and balanced by folding the outer symbols to construct a non-power-of-two map. The resulting modified QAM map ensures that physical errors of adjacent symbols result in a single logical (bit) error (e.g., QAM modulation is a two-dimensional version of Gray code) and also ensures a reduction in the number of errors when physical errors occur at the boundaries between maps. Figure 7 The diagram shows a 23×23 mapping table created through the modifications described above. Each symbol represents nine bits, and each cell is programmed to be one of 23 voltage levels. The last row and last column of the mapping that requires the 24th voltage level are mapped to the unused symbol in the upper right corner. This allocation can be chosen to minimize logical errors caused by physical errors in adjacent states.

[0040] Symbol assignment can also be used for state shaping. That is, assigning 2 9 =512 input vectors provide 23×23=529 symbols, which gives some degrees of freedom for state shaping (529-512=17 unused symbols). That is, retaining the unused symbols in the top right corner avoids the highest stress voltage level and achieves shaping gain by reducing wear on memory die 104 and by reducing interference effects caused by higher voltage levels. In addition, the ECC decoder can achieve additional coding gain to improve decoding by taking into account the unused symbols in the mapping scheme. Furthermore, alternative high-voltage schemes can be beneficial in reducing interference effects. For example, alternative mappings can be used by adjacent cells in word lines (e.g., even / odd cell pairs) or for adjacent word lines (even / odd number lines). An example of such alternative state shaping is in Figure 8A and Figure 8B As shown in the image.

[0041] As described above, it can be implemented in controller 102 (see...) Figure 9A ) or memory die 104 (see Figure 9B The mapping / demapping operation is performed in the memory chip 104. When implemented in controller 102, five bits / cell can be sent to memory die 104 to describe the voltage level of each cell. However, when implemented in memory die 104, controller 102 may only need to send user data (and ECC parity), which in the example above is only 4.5 bits / cell. This equates to a 10% reduction in communication on the memory bus, which is significant for both performance and power reduction. When implemented in memory die 104, CbA technology can be used.

[0042] These implementations offer several advantages. For example, compared to the X4 implementation, these implementations allow for increased logic scaling, which can be important because it allows for significant cost reductions. Furthermore, if current NAND technology only allows between 4 and 5 information bits per cell, the X5 implementation with five physical bits per cell would be wasteful. 32 voltage levels would significantly reduce programming speed, increase susceptibility to interference, and significantly increase communication with the memory die 104. Moreover, as mentioned above, utilizing the mapper / demapper in the memory die 104 to transmit only 4.5 bits per cell instead of 5 bits per cell reduces communication by approximately 10% and has a related impact on performance and power consumption. Furthermore, as NAND technology density continues to scale, increased logic scaling may become crucial.

[0043] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices such as ReRAM, electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and MRAM, as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0044] The memory device can be formed from passive and / or active components in any combination. As a non-limiting example, a passive semiconductor memory element includes a ReRAM device element, which in some embodiments includes resistivity-switching storage elements such as antifuse, phase-change materials, etc., and optionally includes guiding elements such as diodes. As a further non-limiting example, an active semiconductor memory element includes EEPROM and flash memory device elements, which in some embodiments include elements having charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0045] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND memory array can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements sharing a single bit line and being accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, for example, in a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0046] Semiconductor memory elements located within and / or on a substrate can be arranged in two or three dimensions, such as two-dimensional (2D) memory structures or three-dimensional (3D) memory structures.

[0047] In a 2D memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a 2D memory structure, the memory elements are arranged in a plane (e.g., in an xz plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of the memory elements are formed, or it may be a carrier substrate attached to the memory elements after they have been formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0048] Memory elements can be arranged in a single memory device level in an ordered array, such as in multiple rows and / or columns. However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0049] Arrange a 3D memory array such that the memory elements occupy multiple planes or multiple memory device levels to form a three-dimensional structure (i.e., in the x, y and z directions, where the y direction is substantially perpendicular to the main surface of the substrate and the x and z directions are substantially parallel to the main surface of the substrate).

[0050] As a non-limiting example, a 3D memory structure can be vertically arranged as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), wherein each column has multiple memory elements. These columns can be arranged in a 2D configuration, for example, in the xz plane, thereby producing a 3D arrangement structure of memory elements, wherein the elements are located on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a 3D memory array.

[0051] In a non-limiting example, in a 3D NAND memory array, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other 3D configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The 3D memory array can also be designed in both NOR and ReRAM configurations.

[0052] Typically, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory layers located at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic 3D array, the layer constituting each memory device level of the array is typically formed on the layer of the lower memory device level of the array. However, the layers of adjacent memory device levels in a monolithic 3D memory array may be shared between memory device levels or there may be intermediate layers between memory device levels.

[0053] Two-dimensional arrays can then be formed individually and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic 3D memory array. Furthermore, multiple 2D or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0054] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0055] Those skilled in the art will recognize that the present invention is not limited to the described 2D and 3D structures, but encompasses all relevant memory structures as described herein and as understood by those skilled in the art within the spirit and scope of the invention.

[0056] The foregoing detailed description is intended to be understood as an illustration of the selected forms in which the invention may take place, and not as a definition of the invention. The scope of the claimed invention is intended to be defined only by the following claims (including all equivalents). Finally, it should be noted that any aspect of any embodiment described herein may be used alone or in combination with each other.

Claims

1. A storage system for multi-cell mapping, the storage system comprising: A memory die, the memory die comprising a plurality of memory cells, each memory cell being configured to store a number of states of voltage levels that are not powers of 2; and A controller configured to provide data to the memory die for storage; The memory die is configured as follows: The data is mapped to the plurality of memory cells having a number of voltage levels that are not powers of 2 using a modified quadrature amplitude modulation (QAM) mapping. as well as The data is written into the plurality of memory cells determined by the modified QAM mapping. The modified QAM mapping mentioned above is created in the following way: The right and left halves of the basic QAM map are reflected on the right and top edges of the basic QAM map, which are smaller than the modified QAM map, respectively. The symbols reflected in the right end of the portion on the right edge and the symbols reflected in the upper end of the portion on the upper edge are moved to the upper right of the basic QAM map.

2. The storage system of claim 1, wherein the data is written into an adjacent memory cell.

3. The storage system according to claim 1 further includes performing state shaping on the modified QAM mapping.

4. The storage system of claim 1, wherein the mapping is performed by a control die coupled to the memory die.

5. The storage system according to claim 1, wherein a power other than 2 is 2^3.

6. The storage system according to claim 1, wherein the memory die comprises a three-dimensional memory.

7. A method for multi-cell mapping in a memory system having a memory die comprising a plurality of memory cells, each memory cell being configured to store a number of states whose voltage levels are not powers of 2, the method comprising: The modified quadrature amplitude modulation (QAM) mapping is used to map the plurality of memory cells to a number of voltage levels that are not powers of 2. as well as The data is written into the plurality of memory cells determined by the modified QAM mapping. The modified QAM mapping mentioned above is created in the following way: The right and left halves of the basic QAM map are reflected on the right and top edges of the basic QAM map, which are smaller than the modified QAM map, respectively. The symbols reflected in the right end of the portion on the right edge and the symbols reflected in the upper end of the portion on the upper edge are moved to the upper right of the basic QAM map.

8. The method of claim 7, wherein the data is written into an adjacent memory cell.

9. The method of claim 7 further includes shaping the modified QAM mapping state.

10. The method of claim 7, wherein the mapping is performed by one of: the controller of the storage system, the memory die, or a control die coupled to the memory die.

11. The method of claim 7, further comprising performing a demapping operation.

12. The method of claim 11, wherein the demapping operation is performed by one of: the controller of the memory system, the memory die, or a control die coupled to the memory die.

13. The method of claim 7, wherein the power of non-2 is 23.

14. A storage system, the storage system comprising: A memory die, the memory die comprising a plurality of memory cells, each memory cell being configured to store a number of states of voltage levels that are not powers of 2; A means for mapping the plurality of memory cells to a number of voltage levels that are not powers of 2 using a modified quadrature amplitude modulation (QAM) mapping; as well as A means for writing data into the plurality of memory cells determined by the modified QAM mapping. The modified QAM mapping mentioned above is created in the following way: The right and left halves of the basic QAM map are reflected on the right and top edges of the basic QAM map, which are smaller than the modified QAM map, respectively. The symbols reflected in the right end of the portion on the right edge and the symbols reflected in the upper end of the portion on the upper edge are moved to the upper right of the basic QAM map.

Images