A GaN HEMT device with improved threshold voltage stability and gate breakdown voltage, and its fabrication method.
By fabricating a doped n-type SnO2 layer on a p-type SnO layer and employing a low-temperature deposition process, the problems of threshold voltage instability and low gate breakdown voltage in p-type SnO GaN HEMT devices were solved, achieving high stability and high breakdown voltage performance of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2022-12-14
- Publication Date
- 2026-06-19
Smart Images
Figure CN116110786B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and more specifically to a GaN HEMT device and its fabrication method that improves threshold voltage stability and gate breakdown voltage. Background Technology
[0002] GaN, as a typical representative of third-generation semiconductor materials, possesses a series of advantages, including a large bandgap, high breakdown field strength, high polarization coefficient, high electron mobility, and high electron saturation drift velocity. Furthermore, when formed into a heterojunction with AlGaN, it generates a high-concentration, high-mobility two-dimensional electron gas. These advantages make GaN a preferred material for fabricating next-generation high-performance high-frequency power switching devices. Currently, HEMT power devices based on GaN can be divided into two main categories: depletion-mode devices and enhancement-mode devices. However, depletion-mode GaN HEMT devices suffer from high power loss due to inherent negative gate voltage turn-off, limiting their application. In practical applications, enhancement-mode GaN HEMT devices, with zero gate voltage turn-off and fail-safe features, are more widely used and favored by the market compared to depletion-mode GaN HEMT devices. Their excellent performance makes them promising for applications in consumer electronics, rail transportation, industrial equipment, and communication base stations.
[0003] The main technologies for realizing enhancement-mode GaN HEMT devices include p-type GaN capping, thin barrier structures, grooved gate structures, and under-gate F ion implantation. Among these, enhancement-mode devices achieved using p-type GaN capping have been successfully deployed in the market. However, p-type GaN capping still faces some insurmountable challenges, such as low threshold voltage, poor etching uniformity in the non-gate region, and the introduction of high-density surface defects on the AlGaN surface during etching. Therefore, researchers have proposed using p-type metal oxides (such as tin oxide and nickel oxide) that can be synthesized at low temperatures and used only for lift-off operations to replace the p-type GaN capping, thereby solving the aforementioned problems while reducing processing costs.
[0004] However, to date, publicly disclosed GaN HEMT devices fabricated using p-type metal oxide cap layers (mainly nickel oxide and cuprous oxide) either exhibit a weak positive threshold voltage drift effect, remaining depletion-type devices, or their implemented threshold voltages are low (less than 1V), lacking significant application potential. Among p-type metal oxides, p-type tin oxide (p-type SnO) can achieve a p-type concentration as high as 10⁻⁶ without doping. 19 cm -3 The bandgap can reach 3.9 eV, and low-temperature deposition can be achieved using a variety of thin film processes.
[0005] However, p-type SnO GaN HEMT devices also face the following problems: (1) p-type SnO material itself is in a metastable state. Its metastable characteristics are mainly manifested in its easy reaction with hydrogen ions in external water molecules to form complexes. At the same time, under the high temperature process of device manufacturing, more stable n-type tin oxide (SnO2) will be generated, but it will lose p-type conductivity. Therefore, GaN HEMT devices using p-type SnO as the gate cap layer face the problem of unstable threshold voltage. (2) When p-type SnO is in contact with the gate metal, the peak electric field at the metallurgical junction is too large and the peak electric field is not uniform, which causes the device to break down prematurely, resulting in a low gate breakdown voltage of the device. Summary of the Invention
[0006] To address the aforementioned problems in the prior art, this invention provides a GaN HEMT device and its fabrication method that improve threshold voltage stability and gate breakdown voltage. The technical problem to be solved by this invention is achieved through the following technical solution:
[0007] One embodiment of the present invention provides a method for fabricating a GaN HEMT device that improves threshold voltage stability and gate breakdown voltage. The method for fabricating the GaN HEMT device includes:
[0008] Pre-treatment of the substrate layer;
[0009] A buffer layer is prepared on the substrate layer;
[0010] A channel layer is fabricated on the buffer layer;
[0011] A barrier layer is fabricated on the channel layer;
[0012] At a first temperature, a first passivation layer is prepared on the barrier layer;
[0013] A source and a drain are fabricated on both ends of the barrier layer, and the sides of the source and the drain are in contact with the sides of the first passivation layer.
[0014] The first passivation layer in the middle portion is etched away to expose part of the barrier layer, and a p-type SnO layer is prepared on the exposed barrier layer, wherein the upper portions of both ends of the p-type SnO layer are located on a portion of the upper surface of the first passivation layer.
[0015] An n-type SnO2 layer doped with a predetermined element is prepared on the p-type SnO layer, wherein the predetermined element is one of Sb, Pd, Ce, and F atoms;
[0016] At a second temperature, a second passivation layer is prepared on the remaining exposed first passivation layer and the Sb-doped n-type SnO2 layer using an ICPCVD process, wherein the second temperature is lower than the first temperature.
[0017] The second passivation layer in the middle portion is etched away to expose a portion of the n-type SnO2 layer, and a gate is fabricated on the exposed n-type SnO2 layer.
[0018] In one embodiment of the present invention, the pretreatment of the substrate layer includes:
[0019] The substrate was ultrasonically cleaned sequentially using acetone, anhydrous ethanol solution, and deionized water, then dried with nitrogen gas, and finally heat-treated in a hydrogen atmosphere.
[0020] In one embodiment of the present invention, the step of fabricating a buffer layer on the substrate layer includes:
[0021] Under the first process conditions, the buffer layer is deposited on the substrate using MOCVD process;
[0022] The process of fabricating a channel layer on the buffer layer includes:
[0023] Under the first process conditions, the channel layer is prepared on the buffer layer using MOCVD process;
[0024] The first process conditions are: the reaction chamber pressure in the MOCVD is 10-100 Torr, the Ga source flow rate is 50-100 μmol / min, the ammonia flow rate is 3000-6000 sccm, the hydrogen flow rate is 1000-2000 sccm, and the temperature is 900℃.
[0025] In one embodiment of the present invention, the step of fabricating a barrier layer on the channel layer includes:
[0026] Under the second process conditions, the barrier layer is prepared on the channel layer using MOCVD process;
[0027] The second process conditions are as follows: the reaction chamber pressure in the MOCVD is 10-100 Torr, the Al source flow rate is 10-30 μmol / min, the Ga source flow rate is 30-90 μmol / min, the ammonia flow rate is 3000-6000 sccm, the hydrogen flow rate is 1000-2000 sccm, and the temperature is 900℃.
[0028] In one embodiment of the present invention, the step of fabricating a first passivation layer on the barrier layer includes:
[0029] Under the third process conditions, the first passivation layer of silicon nitride material is prepared on the barrier layer using the PECVD process.
[0030] The third process conditions are: the reaction chamber pressure in the PECVD is 0.5-30 Pa, the first temperature is 200-350 °C, and silane and nitrous oxide gas or silane and ammonia gas are simultaneously introduced into the reaction chamber.
[0031] In one embodiment of the present invention, the fabrication of the source and drain electrodes on both ends of the barrier layer includes:
[0032] The first passivation layer at both ends is etched away to expose the upper surfaces at both ends of the barrier layer;
[0033] After photolithography and development, masks for the source and drain are fabricated on the first passivation layer. Then, the source and drain are deposited on the upper surfaces at both ends of the barrier layer using electron beam evaporation and annealing.
[0034] In one embodiment of the present invention, the etching away of the middle portion of the first passivation layer to expose a portion of the barrier layer, and the fabrication of a p-type SnO layer on the exposed barrier layer, wherein the upper portions of both ends of the p-type SnO layer are located on a portion of the upper surface of the first passivation layer, includes:
[0035] The first passivation layer in the middle part is etched away;
[0036] After photolithography and development, a mask for preparing the SnO layer is fabricated on the first passivation layer. Then, the epitaxial wafer is pretreated with argon gas to remove residual photoresist.
[0037] Under vacuum conditions, the surface of the epitaxial wafer is pre-sputtered using radio frequency magnetron sputtering. After pre-sputtering, a p-type SnO film is first sputtered and grown on the exposed barrier layer and the first passivation layer. Then, acetone and ethanol are used sequentially for ultrasonic exfoliation to obtain the desired p-type SnO pattern. Finally, the p-type SnO layer is prepared by annealing in air.
[0038] In one embodiment of the present invention, the step of preparing an n-type SnO2 layer covered by a predetermined doped element on the p-type SnO layer includes:
[0039] After photolithography and development, a mask for preparing the SnO2 layer is fabricated on the first passivation layer. Then, the epitaxial wafer is pretreated with argon gas to remove residual photoresist.
[0040] Under vacuum conditions, the surface of the epitaxial wafer is pre-sputtered using radio frequency magnetron sputtering. After pre-sputtering, an n-type SnO2 film doped with a preset element is first sputtered on the first passivation layer and the p-type SnO layer. Then, the n-type SnO2 layer is prepared by ultrasonic exfoliation using acetone and ethanol in sequence.
[0041] In one embodiment of the present invention, the fabrication of a second passivation layer on the remaining exposed first passivation layer and the n-type SnO2 layer using the ICPCVD process includes:
[0042] Under the fourth process conditions, the second passivation layer of silicon nitride material is prepared on the remaining exposed first passivation layer and the n-type SnO2 layer using the ICPCVD process;
[0043] The fourth process conditions are: the reaction chamber pressure in the ICPCVD is 5-10 mTorr, the second temperature is 120-150℃, and silane and nitrogen gas or silane and ammonia gas are simultaneously introduced into the reaction chamber.
[0044] An embodiment of the present invention also provides a GaN HEMT device with improved threshold voltage stability and gate breakdown voltage, which is fabricated using any of the above-described fabrication methods, the GaN HEMT device comprising:
[0045] Substrate layer;
[0046] A buffer layer is located on the substrate layer;
[0047] A channel layer is located on the buffer layer;
[0048] A barrier layer is located on the channel layer;
[0049] Two first passivation layers, both of which are located above the barrier layer;
[0050] The source and drain are located on the upper surfaces at both ends of the barrier layer, respectively;
[0051] A p-type SnO layer is located on the barrier layer exposed between the two portions of the first passivation layer;
[0052] An n-type SnO2 layer doped with a predetermined element, wherein the n-type SnO2 layer covers the p-type SnO layer, and the predetermined element is one of Sb, Pd, Ce, and F atoms;
[0053] Two portions of the second passivation layer are respectively located on the two portions of the first passivation layer and a portion of the n-type SnO2 layer;
[0054] The gate is located on the exposed n-type SnO2 layer between the two portions of the second passivation layer.
[0055] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0056] This invention successfully alleviates the threshold voltage instability and low gate breakdown issues faced by p-type SnO GaN HEMT devices through the combined effect of multiple factors. The n-type SnO2 layer mitigates the reaction between the p-type SnO layer and hydrogen ions from external water molecules, improving the stability of the GaN HEMT device's threshold voltage. Furthermore, the use of a low-temperature deposition process avoids oxidation of the p-type SnO layer during passivation due to high temperatures, further enhancing the device's threshold voltage stability. The formation of a pn junction between the n-type SnO2 layer and the p-type SnO layer prevents electric field spikes that could lead to premature gate breakdown, reducing the peak electric field at the metallurgical junction in the GaN HEMT device and thus improving the device's gate breakdown voltage.
[0057] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0058] Figure 1 This is a schematic flowchart of a method for fabricating a GaN HEMT device that improves threshold voltage stability and gate withstand voltage according to an embodiment of the present invention.
[0059] Figures 2a-2i A process flow diagram of a method for fabricating a GaN HEMT device that improves threshold voltage stability and gate breakdown voltage, provided in an embodiment of the present invention;
[0060] Figure 3 This is a schematic diagram of the structure of a GaN HEMT device that improves threshold voltage stability and gate withstand voltage according to an embodiment of the present invention;
[0061] Figure 4 These are schematic diagrams of the formation of a traditional p-type SnO layer and a metal gate depletion region (left figure) and the formation of a p-type SnO layer and an Sb-doped n-type SnO2 layer depletion region (right figure) provided in embodiments of the present invention.
[0062] Symbol explanation:
[0063] 1-Substrate layer, 2-Buffer layer, 3-Channel layer, 4-Barrier layer, 5-First passivation layer, 61-Source, 62-Drain, 7-p-type SnO layer, 8-n-type SnO2 layer, 9-Second passivation layer, 10-Gate. Detailed Implementation
[0064] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0065] It should be noted that, in this embodiment, "up," "down," "left," and "right" refer to the positional relationship of the GaN HEMT device when it is in the illustrated state, "width" refers to the lateral dimension of the GaN HEMT device when it is in the illustrated state, and "thickness" refers to the longitudinal dimension of the GaN HEMT device when it is in the illustrated state.
[0066] Example 1
[0067] Please see Figure 1 and Figures 2a-2i , Figure 1 This is a schematic flowchart of a method for fabricating a GaN HEMT device that improves threshold voltage stability and gate withstand voltage according to an embodiment of the present invention. Figures 2a-2i This is a process flow diagram illustrating a method for fabricating a GaN HEMT device with improved threshold voltage stability and gate breakdown voltage, provided by an embodiment of the present invention. The present invention provides a method for fabricating a GaN HEMT device with improved threshold voltage stability and gate breakdown voltage, the method comprising:
[0068] Step 1: Pre-treat the substrate layer 1.
[0069] Specifically, the substrate layer 1 is ultrasonically cleaned sequentially using acetone, anhydrous ethanol solution and deionized water, then dried with nitrogen gas, and finally heat-treated in a hydrogen atmosphere.
[0070] In this embodiment, the specific heat treatment steps are as follows: heat treatment of substrate layer 1 at 1050°C for 10 minutes in a hydrogen atmosphere.
[0071] Optionally, the substrate 1 is made of one of sapphire, silicon carbide, silicon, or gallium nitride.
[0072] Step 2, as follows Figure 2a As shown, a buffer layer 2 is prepared on the substrate layer 1.
[0073] Specifically, under the first process conditions, a buffer layer 2 is deposited on the substrate layer 1 using MOCVD (metal-organic chemical vapor deposition) process.
[0074] The first process conditions are as follows: the reaction chamber pressure in MOCVD is 10-100 Torr, the Ga source flow rate is 50-100 μmol / min, the ammonia flow rate is 3000-6000 sccm, the hydrogen flow rate is 1000-2000 sccm, and the temperature is 900℃.
[0075] Optionally, the material of buffer layer 2 is gallium nitride, and the thickness of buffer layer 2 is 1-5 μm.
[0076] Step 3, as follows Figure 2bAs shown, a channel layer 3 is prepared on the buffer layer 2.
[0077] Specifically, under the first process conditions, the channel layer 3 is prepared on the buffer layer 2 using the MOCVD process.
[0078] Optionally, the material of the channel layer 3 is gallium nitride, and the thickness of the channel layer 3 is 30-60nm.
[0079] Step 4, as follows Figure 2c As shown, a barrier layer 4 is prepared on the channel layer 3.
[0080] Specifically, under the second process conditions, a barrier layer 4 is prepared on the channel layer 3 using the MOCVD process.
[0081] The second process conditions are as follows: the reaction chamber pressure in MOCVD is 10-100 Torr, the Al source flow rate is 10-30 μmol / min, the Ga source flow rate is 30-90 μmol / min, the ammonia flow rate is 3000-6000 sccm, the hydrogen flow rate is 1000-2000 sccm, and the temperature is 900℃.
[0082] Optionally, barrier layer 4 is Al x Ga (1-x) The N-type barrier layer has an Al composition of 0.1-0.25.
[0083] Optionally, the thickness of barrier layer 4 is 10-40 nm.
[0084] Step 5, as follows Figure 2d As shown, a first passivation layer 5 is prepared on the barrier layer 4 at a first temperature.
[0085] Specifically, under the third process conditions, a first passivation layer 5 of silicon nitride material is prepared on the barrier layer 4 using PECVD (plasma-enhanced chemical vapor deposition) process.
[0086] The third process conditions are: the reaction chamber pressure in the PECVD is 0.5-30 Pa, the reaction chamber temperature (i.e., the first temperature) is 200-350 °C, and silane and nitrous oxide gas or silane and ammonia gas are simultaneously introduced into the reaction chamber.
[0087] Optionally, the thickness of the first passivation layer 5 is 50-400 nm.
[0088] Optionally, the material of the first passivation layer 5 can also be silicon dioxide.
[0089] Step 6, as follows Figure 2e As shown, a source electrode 61 and a drain electrode 62 are fabricated on both ends of the barrier layer 4, and the sides of the source electrode 61 and the drain electrode 62 are in contact with the sides of the first passivation layer 5.
[0090] Step 6.1: Etch away the first passivation layer 5 at both ends to expose the upper surfaces at both ends of the barrier layer 4.
[0091] Step 6.2: After photolithography and development, a mask for preparing source electrode 61 and drain electrode 62 is fabricated on the first passivation layer 5. Then, source electrode 61 and drain electrode 62 are deposited on the upper surface of both ends of barrier layer 4 using electron beam evaporation process, and annealing is performed.
[0092] Specifically, source electrode 61 and drain electrode 62 are deposited using electron beam evaporation and annealed at 860°C for 30 seconds under a nitrogen atmosphere.
[0093] Optionally, the source 61 and drain 62 are made of a Ti / Al / Ni / Au combination, wherein the thickness of Ti is 20-100nm, the thickness of Al is 100-300nm, the thickness of Ni is 20-200nm, and the thickness of Au is 20-200nm.
[0094] Step 7, as follows Figure 2f As shown, the first passivation layer 5 in the middle is etched away to expose part of the barrier layer 4, and a p-type SnO layer 7 is prepared on the exposed barrier layer 4, with the upper portions of both ends of the p-type SnO layer 7 located on part of the upper surface of the first passivation layer 5.
[0095] Step 7.1: Etch away the first passivation layer 5 in the middle part.
[0096] Step 7.2: After photolithography and development, a mask for preparing the SnO layer is fabricated on the first passivation layer 5. Then, the epitaxial wafer is pretreated with argon gas to remove the photoresist residue on the surface due to incomplete development.
[0097] Step 7.3: Under vacuum conditions, pre-sputter the surface of the epitaxial wafer using radio frequency magnetron sputtering. After pre-sputtering, p-type SnO thin films are first sputtered and grown on the exposed barrier layer 4 and the first passivation layer 5. Then, acetone and ethanol are used sequentially for ultrasonic exfoliation to obtain the desired p-type SnO pattern. Finally, annealing is performed in air to prepare the p-type SnO layer 7.
[0098] Specifically, a vacuum pump is used to evacuate the growth chamber to a vacuum level of 8 × 10⁻⁶. -4 After the target surface was pre-sputtered for 5 minutes at a pressure below Pa, impurities were removed. After pre-sputtering, a p-type SnO film was grown by formal sputtering. The sputtered p-type SnO film was then ultrasonically exfoliated with acetone and ethanol to obtain the desired p-type SnO pattern. Finally, it was annealed at 225°C in air to obtain the p-type SnO layer 7 that met the requirements.
[0099] Optionally, the thickness of the p-type SnO layer 7 is 70-150 nm.
[0100] Optionally, the sputtering process conditions are as follows: pure Sn target material is selected, and the RF magnetron sputtering process conditions are: in a mixed atmosphere of oxygen and argon, the distance between the target and the substrate is 66mm, the RF power is set to 50W and the growth pressure is 5.7mTorr.
[0101] In this embodiment, argon gas is used for pretreatment before sputtering the p-type SnO layer instead of oxygen gas. This avoids the oxidation of the p-type SnO layer by oxygen during the pretreatment process and further improves the stability of the device threshold voltage.
[0102] Step 8, as follows Figure 2g As shown, an n-type SnO2 layer 8 covered by a predetermined element is prepared on a p-type SnO layer 7. The predetermined element is one of Sb, Pd, Ce, and F atoms.
[0103] Step 8.1: After photolithography and development, a mask for preparing the SnO2 layer is fabricated on the first passivation layer 5. Then, the epitaxial wafer is pretreated with argon gas to remove residual photoresist.
[0104] Step 8.2: Under vacuum conditions, pre-sputter the surface of the epitaxial wafer using radio frequency magnetron sputtering. After pre-sputtering, firstly, an n-type SnO2 film doped with a preset element is sputtered on the first passivation layer 5 and the p-type SnO layer 7. Then, ultrasonic exfoliation is performed sequentially using acetone and ethanol to prepare the n-type SnO2 layer 8.
[0105] Specifically, a vacuum pump is used to evacuate the growth chamber to a vacuum level of 8 × 10⁻⁶. -4 After the target surface is below Pa, pre-sputtering is performed for 5 minutes to remove impurities. After pre-sputtering, an n-type SnO2 film doped with the preset elements is then grown by formal sputtering. The sputtered n-type SnO2 film doped with the preset elements is then ultrasonically exfoliated using acetone and ethanol in sequence to obtain the required n-type SnO2 layer 8.
[0106] Optionally, the thickness of the n-type SnO2 layer 8 is 10-30 nm.
[0107] SnO2, as a binary conductive oxide and an intrinsic n-type wide bandgap oxide material, can have its n-type carrier concentration increased by doping it with appropriate concentrations of doping elements in this embodiment. In particular, the addition of element Sb can achieve an n-type carrier concentration of up to 10. 19 cm -3Meanwhile, its bandgap is between 3.5 and 4.0 eV. Furthermore, SnO2 is very stable to air and heat, insoluble in water, and sparingly soluble in acid or alkali solutions, thus exhibiting good electrical conductivity and thermochemical stability. In this embodiment, to address the issue of unstable threshold voltage in the fabricated GaN HEMT device, an n-type SnO2 layer 8 doped with Sb, Pd, Ce, or F atoms is grown above the p-type SnO layer 7. The n-type SnO2 layer 8 has good chemical stability. Thus, the n-type SnO2 layer 8 grown on it acts as an isolation layer between the p-type SnO layer 7 and external water molecules, preventing direct contact between external water molecules and the p-type SnO layer, mitigating the reaction between SnO and hydrogen ions in external water molecules, thereby improving the stability of the threshold voltage of the GaN HEMT device.
[0108] Step 9, as follows Figure 2h As shown, at a second temperature, a second passivation layer 9 is prepared on the remaining exposed first passivation layer 5 and n-type SnO2 layer 8 using an ICPCVD process. The second temperature is lower than the first temperature.
[0109] Specifically, under the fourth process conditions, a second passivation layer 9 of silicon nitride material is prepared on the remaining exposed first passivation layer 5 and n-type SnO2 layer 8 using ICPCVD (inductively coupled plasma chemical vapor deposition) process.
[0110] The fourth process conditions are: the reaction chamber pressure in ICPCVD is 5-10 mTorr, the reaction chamber temperature (i.e., the second temperature) is 120-150℃, and silane and nitrogen gas or silane and ammonia gas are simultaneously introduced into the reaction chamber.
[0111] Optionally, the thickness of the second passivation layer 9 is 50-500 nm.
[0112] Optionally, the material of the second passivation layer 9 can also be silicon dioxide.
[0113] In this embodiment, the second passivation layer is prepared by ICPCVD low-temperature deposition process, thereby avoiding oxidation of the p-type SnO layer 7 due to high temperature during the passivation process and preserving the conductivity of the p-type SnO layer 7, which can further improve the stability of the device threshold voltage.
[0114] Step 10, as follows Figure 2i As shown, the second passivation layer (9) in the middle part is etched away to expose part of the n-type SnO2 layer 8, and a gate 10 is fabricated on the exposed n-type SnO2 layer 8.
[0115] Specifically, the second passivation layer 9 in the middle part is etched away. After photolithography and development, a mask for preparing the gate metal is fabricated on the n-type SnO2 layer 8. Before depositing the gate metal, the epitaxial wafer is pretreated with argon gas to remove residual photoresist on the surface due to incomplete development. Then, the gate 10 is deposited using electron beam evaporation and annealed in a nitrogen atmosphere at a temperature of 225°C for 30 seconds.
[0116] Optionally, the metal of the gate 10 is a Ni / Au combination, wherein the thickness of Ni is 20-100nm and the thickness of Au is 50-500nm.
[0117] In this embodiment, the gate 10 is fabricated on the n-type SnO2 layer 8, making the n-type SnO2 layer 8 a contact layer with the gate 10. This avoids the p-type SnO layer 7 from directly contacting the gate 10 to form a metallurgical junction. Instead, by forming a pn junction between the n-type SnO2 layer 8 and the p-type SnO layer 7, the occurrence of electric field spikes that could lead to premature gate breakdown is avoided. This reduces the peak electric field at the metallurgical junction in the GaN HEMT device, thereby improving the gate breakdown voltage of the device.
[0118] It should be noted that the epitaxial wafer in this invention refers to all materials grown up to the corresponding step. Additionally, the photoresist can be removed using gases such as nitrogen or helium that do not oxidize p-type SnO.
[0119] This invention utilizes p-type SnO as the gate cap layer to fabricate an enhanced GaN HEMT device, successfully achieving a threshold voltage greater than 1V and a gate breakdown voltage greater than 4V without optimization. Furthermore, theoretical simulations show that the threshold voltage of this device can exceed 4V, and the gate breakdown voltage can exceed 7V, demonstrating great application potential.
[0120] This invention successfully alleviates the threshold voltage instability and low gate breakdown voltage issues faced by p-type SnO GaN HEMT devices through the combined effects of multiple factors. Specifically, this invention grows a chemically stable n-type SnO2 layer doped with a predetermined element on top of the p-type SnO layer as an isolation layer between the p-type SnO layer and external water molecules. This prevents direct contact between external water molecules and the p-type SnO layer, mitigating the reaction between the p-type SnO layer and hydrogen ions in external water molecules, thus improving the stability of the GaNHEMT device's threshold voltage. Furthermore, during the passivation process for preparing the second passivation layer, a low-temperature deposition process such as ICP-CVD is used to grow the second passivation layer, avoiding oxidation of the p-type SnO layer due to high temperatures during passivation, further improving the stability of the device's threshold voltage. Moreover, argon gas pretreatment, rather than oxygen pretreatment, is used before sputtering the p-type SnO layer to avoid oxidation of the p-type SnO layer by oxygen during the pretreatment process, further improving the stability of the device's threshold voltage. Furthermore, the n-type SnO2 layer doped with preset elements serves as a contact layer with the gate metal, avoiding direct contact between the p-type SnO layer and the gate metal to form a metallurgical junction. Instead, by forming a pn junction between the n-type SnO2 layer and the p-type SnO layer, the occurrence of electric field spikes is avoided, which could lead to premature gate breakdown. This reduces the peak electric field at the metallurgical junction in the GaN HEMT device, thereby improving the gate breakdown voltage of the device.
[0121] Example 2
[0122] Based on Embodiment 1, this invention also provides a GaNHEMT device with improved threshold voltage stability and gate breakdown voltage. This GaN HEMT device is fabricated using the method described in Embodiment 1. Please refer to [link to Embodiment 1]. Figure 3 The GaNHEMT device includes:
[0123] Substrate 1;
[0124] Buffer layer 2 is located on substrate layer 1;
[0125] Channel layer 3 is located on buffer layer 2;
[0126] Barrier layer 4 is located above channel layer 3;
[0127] The first passivation layer 5 consists of two parts, both of which are located above the barrier layer 4.
[0128] The source 61 and drain 62 are located on the upper surfaces at both ends of the barrier layer 4, respectively;
[0129] p-type SnO layer 7 is located on the barrier layer 4 exposed between the two parts of the first passivation layer 5;
[0130] An n-type SnO2 layer 8 is doped with a preset element, and the n-type SnO2 layer (8) covers a p-type SnO layer 7. The preset element is one of Sb, Pd, Ce and F atoms.
[0131] The two parts of the second passivation layer 9 are located on the two parts of the first passivation layer 5 and the part of the n-type SnO2 layer 8, respectively;
[0132] Gate 10 is located on the exposed n-type SnO2 layer 8 between the two portions of the second passivation layer 9.
[0133] Please see Figure 4 , Figure 4 The diagram shows the formation of the depletion region of a traditional p-type SnO layer with a metal gate (left image) and the formation of the depletion region of a p-type SnO layer with an Sb-doped n-type SnO2 layer (right image). Figure 4 As can be seen, the depletion region formed by the traditional p-type SnO layer and the metal gate is relatively narrow. However, in the right-hand diagram, the depletion region is wider than in the left-hand diagram because n-type SnO2 and p-type SnO form a pn junction. Furthermore, the peak electric field of the depletion region is inversely related to its width. Therefore, this invention improves the gate breakdown voltage by forming a pn junction between n-type SnO2 and p-type SnO, thereby expanding the depletion region width and reducing the peak electric field of the gate.
[0134] In practical applications, enhancement-mode GaN HEMTs with zero gate voltage turn-off and fail-safe features have greater potential for application in high-efficiency, high-power electronic devices compared to depletion-mode GaN HEMTs, and are bound to be more popular in the market. For this invention, the threshold voltage stability and gate breakdown voltage of p-type SnO GaN HEMTs are improved by depositing an Sb-doped n-type SnO2 layer on a p-type SnO cap layer, giving it greater application potential in power electronics fields requiring high power and high reliability. In summary, this invention has a very broad prospect for applications in consumer electronics (mobile phone chargers), aerospace, industrial equipment, and communication base stations.
[0135] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0136] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0137] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, disclosure, and appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.
[0138] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, any modifications made without departing from the inventive concept should be considered within the scope of protection of the present invention.
Claims
1. A method for fabricating a GaN HEMT device with improved threshold voltage stability and gate breakdown voltage, characterized in that, The fabrication method of the GaN HEMT device includes: The substrate layer (1) is pretreated; A buffer layer (2) of gallium nitride material is prepared on the substrate layer (1); A channel layer (3) of gallium nitride material is prepared on the buffer layer (2); A barrier layer (4) is prepared on the channel layer (3); A first passivation layer (5) is prepared on the barrier layer (4) at a first temperature of 200-350 °C. A source electrode (61) and a drain electrode (62) are prepared on both ends of the barrier layer (4), and the sides of the source electrode (61) and the drain electrode (62) are in contact with the sides of the first passivation layer (5). The first passivation layer (5) in the middle is etched away to expose part of the barrier layer (4), and a p-type SnO layer (7) is prepared on the exposed barrier layer (4), with the upper portions of both ends of the p-type SnO layer (7) located on part of the upper surface of the first passivation layer (5); specifically, the process includes: etching away the first passivation layer (5) in the middle; after photolithography and development, a mask for preparing the SnO layer is prepared on the first passivation layer (5), and then the epitaxial wafer is pretreated with argon gas to remove residual photoresist; under vacuum conditions, the surface of the epitaxial wafer is pre-sputtered using radio frequency magnetron sputtering; after pre-sputtering, a p-type SnO thin film is first sputtered and grown on the exposed barrier layer (4) and the first passivation layer (5), and then ultrasonically peeled off with acetone and ethanol in sequence to obtain the desired p-type SnO pattern, and finally annealed in air to prepare the p-type SnO layer (7); An n-type SnO2 layer (8) doped with a predetermined element, Sb, is prepared on the p-type SnO layer (7). Specifically, the preparation includes: a mask for preparing the SnO2 layer is fabricated on the first passivation layer (5) after photolithography and development operations; then, the epitaxial wafer is pretreated with argon gas to remove residual photoresist; the surface of the epitaxial wafer is pre-sputtered using radio frequency magnetron sputtering under vacuum conditions; after pre-sputtering, an n-type SnO2 thin film doped with a predetermined element is first sputtered on the first passivation layer (5) and the p-type SnO layer (7); then, the n-type SnO2 layer (8) is prepared by ultrasonic peeling with acetone and ethanol in sequence. At a second temperature, a second passivation layer (9) is prepared on the remaining exposed first passivation layer (5) and Sb-doped n-type SnO2 layer (8) using the ICPCVD process. The second temperature is lower than the first temperature, and the second temperature is 120-150 °C. The second passivation layer (9) in the middle portion is etched away to expose part of the n-type SnO2 layer (8), and a gate (10) is fabricated on the exposed n-type SnO2 layer (8). Specifically, this includes: etching away the second passivation layer (9) in the middle portion, and fabricating a mask for preparing the gate metal on the n-type SnO2 layer (8) through photolithography and development operations. Then, before depositing the gate metal, the epitaxial wafer is pretreated with argon gas, and the gate (10) is deposited using an electron beam evaporation process.
2. The method of fabricating a GaN HEMT device of claim 1, wherein, The pretreatment of the substrate layer (1) includes: The substrate (1) was ultrasonically cleaned sequentially with acetone, anhydrous ethanol solution and deionized water, then dried with nitrogen and heat-treated in a hydrogen atmosphere.
3. The method of fabricating a GaN HEMT device of claim 1, wherein, The preparation of the buffer layer (2) on the substrate layer (1) includes: Under the first process conditions, the buffer layer (2) is deposited on the substrate layer (1) using the MOCVD process; The preparation of the channel layer (3) on the buffer layer (2) includes: Under the first process conditions, the channel layer (3) is prepared on the buffer layer (2) using MOCVD process; The first process conditions are as follows: the reaction chamber pressure in the MOCVD is 10-100 Torr, the Ga source flow rate is 50-100 μmol / min, the ammonia flow rate is 3000-6000 sccm, the hydrogen flow rate is 1000-2000 sccm, and the temperature is 900 ℃.
4. The method for fabricating a GaN HEMT device according to claim 1, characterized in that, The fabrication of the barrier layer (4) on the channel layer (3) includes: Under the second process conditions, the barrier layer (4) is prepared on the channel layer (3) using MOCVD process; The second process conditions are as follows: the reaction chamber pressure in the MOCVD is 10-100 Torr, the Al source flow rate is 10-30 μmol / min, the Ga source flow rate is 30-90 μmol / min, the ammonia flow rate is 3000-6000 sccm, the hydrogen flow rate is 1000-2000 sccm, and the temperature is 900 ℃.
5. The method for fabricating a GaN HEMT device according to claim 1, characterized in that, The fabrication of the first passivation layer (5) on the barrier layer (4) includes: Under the third process conditions, the first passivation layer (5) of silicon nitride material is prepared on the barrier layer (4) using the PECVD process; The third process conditions are as follows: the reaction chamber pressure in the PECVD is 0.5-30 Pa, the first temperature is 200-350℃, and silane and nitrous oxide gas or silane and ammonia gas are simultaneously introduced into the reaction chamber.
6. The method for fabricating a GaN HEMT device according to claim 1, characterized in that, The fabrication of source (61) and drain (62) on both ends of the barrier layer (4) includes: The first passivation layer (5) at both ends is etched away to expose the upper surfaces at both ends of the barrier layer (4); After photolithography and development, a mask for the source electrode (61) and the drain electrode (62) is fabricated on the first passivation layer (5). Then, the source electrode (61) and the drain electrode (62) are deposited on the upper surface of both ends of the barrier layer (4) using electron beam evaporation and annealing.
7. The method for fabricating a GaN HEMT device according to claim 1, characterized in that, The fabrication of a second passivation layer (9) on the remaining exposed first passivation layer (5) and the n-type SnO2 layer (8) using the ICPCVD process includes: Under the fourth process conditions, the second passivation layer (9) of silicon nitride material is prepared on the remaining exposed first passivation layer (5) and the n-type SnO2 layer (8) using the ICPCVD process; The fourth process conditions are: the reaction chamber pressure in the ICPCVD is 5-10 mTorr, the second temperature is 120-150℃, and silane and nitrogen gas or silane and ammonia gas are simultaneously introduced into the reaction chamber.
8. A GaN HEMT device with improved threshold voltage stability and gate resistance, characterized in that, The GaN HEMT device, prepared using the preparation method according to any one of claims 1 to 7, comprises: Substrate (1); A buffer layer (2) is located on the substrate layer (1); The channel layer (3) is located on the buffer layer (2); A barrier layer (4) is located on the channel layer (3); Two first passivation layers (5) are located on the barrier layer (4); The source (61) and drain (62) are located on the upper surfaces at both ends of the barrier layer (4); A p-type SnO layer (7) is located on the barrier layer (4) exposed between the two portions of the first passivation layer (5); An n-type SnO2 layer (8) doped with a preset element, wherein the n-type SnO2 layer (8) covers the p-type SnO layer (7), and the preset element is Sb; Two portions of the second passivation layer (9) are located on the two portions of the first passivation layer (5) and a portion of the n-type SnO2 layer (8), respectively. The gate (10) is located on the n-type SnO2 layer (8) exposed between the two portions of the second passivation layer (9).